TPS737-Q1 [TI]
具有反向电流保护和使能功能的汽车类 1A 超低压降稳压器;
| 型号： | TPS737-Q1 |
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TEXAS INSTRUMENTS |
| 描述： | 具有反向电流保护和使能功能的汽车类 1A 超低压降稳压器 电源电路 线性稳压器IC |
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TPS73719-Q1
TPS73733-Q1
www.ti.com ........................................................................................................................................................................................... SBVS123–DECEMBER 2008
1-A LOW-DROPOUT REGULATOR
WITH REVERSE CURRENT PROTECTION
1
FEATURES
2
•
Qualified for Automotive Applications
•
•
Thermal Shutdown and Current Limit for Fault
Protection
•
Stable with 1.0-µF or Larger Ceramic Output
Capacitor
Available in Multiple Output Voltage Versions
•
•
•
Input Voltage Range: 2.2 V to 5.5 V
–
–
Adjustable Output: 1.20 V to 5.5 V
Ultra-Low Dropout Voltage: 130 mV typ at 1 A
Custom Outputs Available Using Factory
Package-Level Programming
Excellent Load Transient Response, Even With
Only 1.0-µF Output Capacitor
APPLICATIONS
•
NMOS Topology Delivers Low Reverse
Leakage Current
•
Point of Load Regulation for DSPs, FPGAs,
ASICs, and Microprocessors
•
•
1.0% Initial Accuracy
•
•
Post-Regulation for Switching Supplies
Portable/Battery-Powered Equipment
3% Overall Accuracy Over Line, Load, and
Temperature
•
Less Than 20-nA (Typ) Quiescent Current in
Shutdown Mode
DESCRIPTION/ORDERING INFORMATION
The TPS737xx family of linear low-dropout (LDO) voltage regulators uses an NMOS pass element in a
voltage-follower configuration. This topology is relatively insensitive to output capacitor value and ESR, allowing
a wide variety of load configurations. Load transient response is excellent, even with a small 1.0-µF ceramic
output capacitor. The NMOS topology also allows very low dropout.
The TPS737xx family uses an advanced BiCMOS process to yield high precision while delivering very low
dropout voltages and low ground pin current. Current consumption, when not enabled, is under 20 nA and ideal
for portable applications. These devices are protected by thermal shutdown and foldback current limit.
Optional
DRB PACKAGE
(TOP VIEW)
VIN
VOUT
1.0 µF
IN
OUT
FB
OUT
NC
1
2
3
4
8
7
6
5
IN
TPS737xx
NC
NC
EN
EN
GND
NR/FB
GND
ON
OFF
NC – No internal connection
Typical Application Circuit
ORDERING INFORMATION(1)
TA
VOUT (TYP)
3.3 V
PACKAGE(2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
TPS73733QDRBRQ1
TPS73719QDRBRQ1
TPS73701QDRBRQ1
733Q
–40°C to 125°C
1.9 V
SON – DRB
Reel of 3000
719Q
Adjustable
PREVIEW
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
TPS73719-Q1
TPS73733-Q1
SBVS123–DECEMBER 2008........................................................................................................................................................................................... www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
VIN range
–0.3 V to 6.0 V
–0.3 V to 6.0 V
–0.3 V to 5.5 V
–0.3 V to 6.0 V
Internally limited
Indefinite
VEN range
VOUT range
VNR, VFB range
Peak output current
Output short-circuit duration
Continuous total power dissipation
Junction temperature range, TJ
Storage temperature range
ESD rating, HBM
See Dissipation Ratings Table
–55°C to 150°C
–65°C to 150°C
2000 V
ESD rating, CDM
500 V
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
DISSIPATION RATINGS(1)
DERATING FACTOR
ABOVE TA = 25°C
T
A ≤ 25°C
TA = 70°C
TA = 85°C
BOARD
PACKAGE
RθJC
RθJA
POWER RATING POWER RATING POWER RATING
High-K(2)(3)
DRB
1.2°C/W
40°C/W
25.0 mW/°C
2.50 W 1.38 W 1.0 W
(1) See Power Dissipation in the Applications section for more information related to thermal design.
(2) The JEDEC High-K (2s2p) board design used to derive this data was a 3-inch x 3-inch, multilayer board with 1-ounce internal power and
ground planes and 2-ounce copper traces on the top and bottom of the board.
(3) Based on preliminary thermal simulations.
2
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TPS73719-Q1
TPS73733-Q1
www.ti.com ........................................................................................................................................................................................... SBVS123–DECEMBER 2008
ELECTRICAL CHARACTERISTICS
over operating temperature range (TJ = –40°C to 125°C), VIN = (VOUT(nom) + 1.0 V)(1), IOUT = 10 mA, VEN = 2.2 V, COUT = 2.2 µF
(unless otherwise noted). Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
2.2
TYP
MAX
5.5
UNIT
VIN
Input voltage range(1),(2)
Internal reference (TPS73701)
Output voltage range (TPS73701)(3)
Nominal
V
V
V
VFB
TJ = 25°C
TJ = 25°C
1.192
VFB
1.2
1.216
5.5 – VDO
+1.0
–1.0
5.36 V < VIN < 5.5 V, VOUT = 5.08 V,
10 mA < IOUT < 800 mA,
–40°C < TJ < 85°C, TPS73701
–2.0
–3.0
+2.0
+3.0
VOUT
Accuracy(1),(4)
%
Over VIN
IOUT, and
temperature
,
VOUT + 0.5 V ≤ VIN ≤ 5.5 V,
10 mA ≤ IOUT ≤ 1 A
±0.5
0.01
ΔVOUT%/
ΔVIN
Line regulation(1)
VOUT(nom) + 0.5 V ≤ VIN ≤ 5.5 V
%/V
%/mA
mV
1 mA ≤ IOUT ≤ 1 A
10 mA ≤ IOUT ≤ 1 A
0.002
ΔVOUT%/
ΔIOUT
Load regulation
0.0005
Dropout voltage(5)
VDO
IOUT = 1 A
130
500
2.2
(VIN = VOUT(nom) – 0.1 V)
Output impedance in dropout
Output current limit
ZO(DO)
ICL
2.2 V ≤ VIN ≤ VOUT + VDO
VOUT = 0.9 × VOUT(nom)
VOUT = 0 V
0.25
1.6
450
0.1
400
1300
20
Ω
A
1.05
ISC
Short-circuit current
Reverse leakage current(6) (–IIN
mA
µA
IREV
)
VEN ≤ 0.5 V, 0 V ≤ VIN ≤ VOUT
IOUT = 10 mA (IQ)
IOUT = 1 A
IGND
GND pin current
µA
ISHDN
IFB
Shutdown current (IGND
)
VEN ≤ 0.5 V, VOUT ≤ VIN ≤ 5.5 V
nA
FB pin current (TPS73701)
0.1
58
0.6
µA
f = 100 Hz, IOUT = 1 A
f = 10 kHz, IOUT = 1 A
Power-supply rejection ratio (ripple
rejection)
PSRR
VN
dB
37
Output noise voltage
BW = 10 Hz to 100 kHz
COUT = 10 µF
27 × VOUT
600
µVRMS
tSTR
Startup time
VOUT = 3 V, RL = 30 Ω, COUT = 1 µF
µs
V
VEN(HI)
VEN(LO)
IEN(HI)
EN pin high (enabled)
EN pin low (shutdown)
EN pin current (enabled)
1.7
0
VIN
0.5
V
VEN = 5.5 V
20
160
140
nA
Shutdown, temperature increasing
Reset, temperature decreasing
TSD
TJ
Thermal shutdown temperature
Operating junction temperature
°C
°C
–40
125
(1) Minimum VIN = VOUT + VDO or 2.2V, whichever is greater.
(2) For VOUT(nom) < 1.6 V, when VIN ≤ 1.6 V, the output will lock to VIN and may result in an overvoltage condition on the output. To avoid
this situation, disable the device before powering down VIN
.
(3) TPS73701 is tested at VOUT = 1.2 V.
(4) Tolerance of external resistors not included in this specification.
(5) VDO is not measured for fixed output versions with VOUT(nom) < 2.3 V, because minimum VIN = 2.2 V.
(6) Fixed-voltage versions only; see the Applications section for more information.
Copyright © 2008, Texas Instruments Incorporated
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TPS73733-Q1
SBVS123–DECEMBER 2008........................................................................................................................................................................................... www.ti.com
FUNCTIONAL BLOCK DIAGRAMS
IN
4-MHz
Charge Pump
EN
Thermal
Protection
Ref
Servo
27 kW
Bandgap
Error
Amp
Current
Limit
OUT
8 kW
GND
R1
R2
R1 + R2 = 80 kW
NR
Figure 1. Fixed Voltage Version
IN
Standard 1% Resistor Values for
Common Output Voltages
V
O
R
1
R
2
4-MHz
1.2 V
1.5 V
1.8 V
2.5 V
2.8 V
3.0 V
3.3 V
Short
Open
Charge Pump
23.2 kW
28.0 kW
39.2 kW
44.2 kW
46.4 kW
52.3 kW
95.3 kW
56.2 kW
36.5 kW
33.2 kW
30.9 kW
30.1 kW
EN
Thermal
Protection
Ref
Servo
27 kW
Bandgap
Error
Amp
NOTE: V
= (R + R )/R × 1.204;
1 2 2
OUT
OUT
FB
Current
Limit
R1 || R2 ≅19 kW for best accuracy.
GND
80 kW
8 kW
R1
R2
Figure 2. Adjustable Voltage Version
4
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TPS73719-Q1
TPS73733-Q1
www.ti.com ........................................................................................................................................................................................... SBVS123–DECEMBER 2008
DRB PACKAGE
3mm x 3mm SON
(TOP VIEW)
OUT
NC
1
2
3
4
8
7
6
5
IN
NC
NC
EN
NR/FB
GND
NC – No internal connection
Table 1. Terminal Functions
DESCRIPTION
TERMINAL
NAME
NO.
8
IN
Unregulated input supply
GND
4, Pad
Ground
Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdown
mode. Refer to the Shutdown section under Applications Information for more details. EN must not be left
floating and can be connected to IN if not used.
EN
5
Fixed voltage versions only. Connecting an external capacitor to this pin bypasses noise generated by the
internal bandgap, reducing output noise to very low levels.
NR
FB
3
3
Adjustable voltage version only. This is the input to the control loop error amplifier, and it is used to set the
output voltage of the device.
OUT
NC
1
Regulator output. A 1.0-µF or larger capacitor of any type is required for stability.
2, 6, 7
No internal connection
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TPS73733-Q1
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TYPICAL CHARACTERISTICS
TJ = 25°C, VIN = (VOUT(nom) + 1.0 V), IOUT = 10 mA, VEN = 2.2 V, COUT = 2.2 µF (unless otherwise noted)
LOAD REGULATION
LINE REGULATION
0.5
0.4
0.20
0.15
0.10
0.05
0
Referred to IOUT = 10mA
Referred to VIN = VOUT + 1.0V at IOUT = 10mA
-40°C
+25°C
+125°C
0.3
0.2
+25°C
+125°C
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.05
-0.10
-0.15
-0.20
-40°C
0
100 200 300 400 500 600 700 800 900 1000
IOUT (mA)
0
0.5
1.0
1.5
2.0
2.5
3.0 3.5
4.0
4.5
V
IN - VOUT (V)
Figure 3.
Figure 4.
DROPOUT VOLTAGE vs TEMPERATURE
DROPOUT VOLTAGE vs OUTPUT CURRENT
200
180
160
140
120
100
80
200
180
160
140
120
100
80
VOUT = 2.5V
+125°C
+25°C
60
60
-40°C
40
40
20
20
0
0
0
100 200 300 400 500 600 700 800 900 1000
IOUT (mA)
-50
-25
0
25
50
75
100
125
150
Temperature (°C)
Figure 5.
OUTPUT VOLTAGE HISTOGRAM
IOUT = 10mA
Figure 6.
DROPOUT VOLTAGE DRIFT HISTOGRAM
30
25
20
15
10
5
18
16
14
12
10
8
IOUT = 10mA
6
4
2
0
0
VOUT Error (%)
Worst Case dVOUT/dT (ppm/°C)
Figure 7.
Figure 8.
6
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TYPICAL CHARACTERISTICS (continued)
TJ = 25°C, VIN = (VOUT(nom) + 1.0 V), IOUT = 10 mA, VEN = 2.2 V, COUT = 2.2 µF (unless otherwise noted)
GROUND PIN CURRENT vs OUTPUT CURRENT
GROUND PIN CURRENT vs TEMPERATURE
3000
2500
2000
1500
1000
500
2500
2000
1500
1000
500
IOUT = 1A
VIN = 5.0V
VIN = 5.0V
VIN = 3.3V
VIN = 3.3V
VIN = 2.2V
VIN = 2.2V
0
0
-50
-25
0
25
50
75
100
125
0
200
400
600
800
1000
Temperature (°C)
IOUT (mA)
Figure 9.
Figure 10.
GROUND PIN CURRENT IN SHUTDOWN
vs TEMPERATURE
CURRENT LIMIT vs VOUT (FOLDBACK)
1
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
VENABLE = 0.5V
VIN = VOUT + 0.5V
ICL
0.1
ISC
VOUT = 3.3V
0.5
0.01
-50
-25
0
25
50
75
100
125
0
1.0
1.5
2.0
2.5
3.0
3.5
Temperature (°C)
VOUT (V)
Figure 11.
Figure 12.
CURRENT LIMIT vs TEMPERATURE
CURRENT LIMIT vs VIN
2.0
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
VOUT = 1.2V
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-50
-25
0
25
50
75
100
125
VIN (V)
Temperature (°C)
Figure 13.
Figure 14.
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TYPICAL CHARACTERISTICS (continued)
TJ = 25°C, VIN = (VOUT(nom) + 1.0 V), IOUT = 10 mA, VEN = 2.2 V, COUT = 2.2 µF (unless otherwise noted)
PSRR (RIPPLE REJECTION) vs
PSRR (RIPPLE REJECTION) vs FREQUENCY
VIN – VOUT
90
80
70
60
50
40
30
20
10
0
40
35
30
25
20
15
10
5
IOUT = 100mA
COUT = Any
IOUT = 1mA
COUT = 1mF
IOUT = 1mA
COUT = 10mF
IO = 100mA
CO = 1mF
IOUT = 1mA
COUT = Any
Frequency = 10kHz
COUT = 10mF
IOUT = 100mA
COUT = 10mF
VOUT = 2.5V
IOUT = 100mA
0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
10
100
1k
10k
100k
1M
10M
V
IN - VOUT (V)
Frequency (Hz)
Figure 15.
Figure 16.
TPS73701
RMS NOISE VOLTAGE vs CFB
NOISE SPECTRAL DENSITY
1
60
55
50
45
40
35
30
25
20
COUT = 1mF
0.1
COUT = 10mF
VOUT = 2.5V
COUT = 0mF
R1 = 39.2kW
IOUT = 150mA
10Hz < Frequency < 100kHz
0.01
10
100
1k
10k
100k
10p
100p
1n
10n
CFB (F)
Frequency (Hz)
Figure 17.
Figure 18.
RMS NOISE VOLTAGE vs CNR
RMS NOISE VOLTAGE vs COUT
60
50
40
30
20
10
0
140
120
100
80
VOUT = 5.0V
VOUT = 5.0V
VOUT = 3.3V
VOUT = 3.3V
VOUT = 1.5V
60
40
VOUT = 1.5V
20
CNR = 0.01mF
COUT = 0mF
10Hz < Frequency < 100kHz
10Hz < Frequency < 100kHz
0
0.1
1
10
1p
10p
100p
1n
10n
COUT (mF)
CNR (F)
Figure 19.
Figure 20.
8
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TYPICAL CHARACTERISTICS (continued)
TJ = 25°C, VIN = (VOUT(nom) + 1.0 V), IOUT = 10 mA, VEN = 2.2 V, COUT = 2.2 µF (unless otherwise noted)
TPS73733
LOAD TRANSIENT RESPONSE
TPS73733
LINE TRANSIENT RESPONSE
CNR = 10nF
CNR = 10nF
COUT = 10mF
VOUT
200mV/div
COUT = 10mF
100mV/div
VOUT
1A
5.3V
10mA
4.3V
IOUT
VIN
10ms/div
10ms/div
Figure 21.
Figure 22.
TPS73701
TURN-ON RESPONSE
TPS73701
TURN-OFF RESPONSE
RL = 20W
COUT = 10mF
VOUT
RL = 20W
RL = 20W
COUT = 1mF
1V/div
1V/div
COUT = 1mF
RL = 20W
COUT = 10mF
VOUT
2V
2V
VEN
1V/div
1V/div
0V
0V
VEN
100ms/div
100ms/div
Figure 23.
Figure 24.
TPS73701, VOUT = 3.3V
POWER-UP/POWER-DOWN
IENABLE vs TEMPERATURE
6
5
10
1
VIN
4
VOUT
3
2
1
0.1
0.01
0
-1
-2
50ms/div
-50
-25
0
25
50
75
100
125
Temperature (°C)
Figure 25.
Figure 26.
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TYPICAL CHARACTERISTICS (continued)
TJ = 25°C, VIN = (VOUT(nom) + 1.0 V), IOUT = 10 mA, VEN = 2.2 V, COUT = 2.2 µF (unless otherwise noted)
TPS73701
IFB vs TEMPERATURE
TPS73701
IFB vs TEMPERATURE
160
140
120
100
80
160
140
120
100
80
60
60
40
40
20
20
0
0
-50
-25
0
25
50
75
100
125
−
50
−
25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
Figure 27.
Figure 28.
TPS73701
TPS73701
LOAD TRANSIENT, ADJUSTABLE VERSION
LINE TRANSIENT, ADJUSTABLE VERSION
VOUT = 2.5V
CFB = 10nF
CFB = 10nF
R1 = 39.2kW
COUT = 10mF
COUT = 10mF
VOUT
VOUT
100mV/div
100mV/div
4.5V
250mA
3.5V
IOUT
VIN
10mA
10ms/div
5ms/div
Figure 29.
Figure 30.
10
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APPLICATION INFORMATION
The TPS737xx belongs to a family of new generation LDO regulators that use an NMOS pass transistor to
achieve ultra-low-dropout performance, reverse current blockage, and freedom from output capacitor constraints.
These features combined with an enable input make the TPS737xx ideal for portable applications. This regulator
family offers a wide selection of fixed output voltage versions and an adjustable output version. All versions have
thermal and over-current protection, including foldback current limit.
Figure 31 shows the basic circuit connections for the fixed voltage models. Figure 32 gives the connections for
the adjustable output version (TPS73701).
VIN
VOUT
IN
OUT
TPS737xx
EN
GND
ON
OFF
Figure 31. Typical Application Circuit for Fixed-Voltage Versions
Optional input capacitor.
May improve source
impedance, noise, or PSRR.
Optional output capacitor.
May improve load transient,
noise, or PSRR.
VIN
VOUT
IN
OUT
TPS73701
R1
CFB
EN
GND
FB
ON
R2
OFF
Optional capacitor
reduces output noise
and improves
(R1 + R2)
R2
VOUT
=
x 1.204
transient response.
Figure 32. Typical Application Circuit for Adjustable-Voltage Version
R1 and R2 can be calculated for any output voltage using the formula shown in Figure 32. Sample resistor values
for common output voltages are shown in Figure 2.
For best accuracy, make the parallel combination of R1 and R2 approximately equal to 19 kΩ. This 19 kΩ, in
addition to the internal 8-kΩ resistor, presents the same impedance to the error amp as the 27-kΩ bandgap
reference output. This impedance helps compensate for leakages into the error amp terminals.
Input and Output Capacitor Requirements
Although an input capacitor is not required for stability if input impedance is very low, it is good analog design
practice to connect a 0.1-µF to 1-µF low equivalent series resistance (ESR) capacitor across the input supply
near the regulator. This capacitor counteracts reactive input sources and improves transient response, noise
rejection, and ripple rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients
are anticipated or the device is located several inches from the power source.
The TPS737xx requires a 1.0-µF output capacitor for stability. It is designed to be stable for all available types
and values of capacitors. In applications where multiple low ESR capacitors are in parallel, ringing may occur
when the product of COUT and total ESR drops below 50 nΩF. Total ESR includes all parasitic resistances,
including capacitor ESR and board, socket, and solder joint resistance. In most applications, the sum of capacitor
ESR and trace resistance will meet this requirement.
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Output Noise
A precision bandgap reference is used to generate the internal reference voltage, VREF. This reference is the
dominant noise source within the TPS737xx and it generates approximately 32 µVRMS (10 Hz to 100 kHz) at the
reference output (NR). The regulator control loop gains up the reference noise with the same gain as the
reference voltage, so that the noise voltage of the regulator is approximately given by:
(
)
VOUT
VREF
R1 ) R2
VN + 32mVRMS
+ 32mVRMS
R2
(1)
Since the value of VREF is 1.2V, this relationship reduces to:
mVRMS
V
ǒ
Ǔ
+ 27ǒ Ǔ
( )
V
VN mVRMS
VOUT
(2)
for the case of no CNR
.
An internal 27kΩ resistor in series with the noise reduction pin (NR) forms a low-pass filter for the voltage
reference when an external noise reduction capacitor, CNR, is connected from NR to ground. For CNR = 10 nF,
the total noise in the 10-Hz to 100-kHz bandwidth is reduced by a factor of ~3.2, giving the approximate
relationship in Equation 3 for CNR = 10 nF.
mVRMS
VN(mVRMS) = 8.5
x VOUT(V)
V
(3)
This noise reduction effect is shown as RMS Noise Voltage vs CNR in the Typical Characteristics section.
The TPS73701 adjustable version does not have the NR pin available. However, connecting a feedback
capacitor, CFB, from the output to the feedback pin (FB) reduces output noise and improve load transient
performance. This capacitor should be limited to 0.1 µF.
The TPS737xx uses an internal charge pump to develop an internal supply voltage sufficient to drive the gate of
the NMOS pass element above VOUT. The charge pump generates ~250 µV of switching noise at ~4 MHz;
however, charge-pump noise contribution is negligible at the output of the regulator for most values of IOUT and
COUT
.
Board Layout Recommendation to Improve PSRR and Noise Performance
To improve ac performance such as PSRR, output noise, and transient response, it is recommended that the
printed circuit board (PCB) be designed with separate ground planes for VIN and VOUT, with each ground plane
connected only at the GND pin of the device. In addition, the ground connection for the bypass capacitor should
connect directly to the GND pin of the device.
Internal Current Limit
The TPS737xx internal current limit helps protect the regulator during fault conditions. Foldback current limit
helps to protect the regulator from damage during output short-circuit conditions by reducing current limit when
VOUT drops below 0.5 V. See Figure 12 in the Typical Characteristicssection.
Enable Pin and Shutdown
The enable pin (EN) is active high and is compatible with standard TTL-CMOS levels. A VEN below 0.5 V (max)
turns the regulator off and drops the GND pin current to approximately 10 nA. When EN is used to shutdown the
regulator, all charge is removed from the pass transistor gate, and the output ramps back up to a regulated VOUT
(see Figure 23).
When shutdown capability is not required, EN can be connected to VIN. However, the pass gate may not be
discharged using this configuration, and the pass transistor may be left on (enhanced) for a significant time after
VIN has been removed. This scenario can result in reverse current flow (if the IN pin is low impedance) and faster
ramp times upon power-up. In addition, for VIN ramp times slower than a few milliseconds, the output may
overshoot upon power-up.
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TPS73719-Q1
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Dropout Voltage
The TPS737xx uses an NMOS pass transistor to achieve extremely low dropout. When (VIN – VOUT) is less than
the dropout voltage (VDO), the NMOS pass device is in its linear region of operation and the input-to-output
resistance is the RDS, ON of the NMOS pass element.
For large step changes in load current, the TPS737xx requires a larger voltage drop from VIN to VOUT to avoid
degraded transient response. The boundary of this transient dropout region is approximately twice the dc
dropout. Values of VIN – VOUT above this line ensure normal transient response.
Operating in the transient dropout region can cause an increase in recovery time. The time required to recover
from a load transient is a function of the magnitude of the change in load current rate, the rate of change in load
current, and the available headroom (VIN to VOUT voltage drop). Under worst-case conditions [full-scale
instantaneous load change with (VIN – VOUT) close to dc dropout levels], the TPS737xx can take a couple of
hundred microseconds to return to the specified regulation accuracy.
Transient Response
The low open-loop output impedance provided by the NMOS pass element in a voltage follower configuration
allows operation without a 1.0-µF output capacitor. As with any regulator, the addition of additional capacitance
from the OUT pin to ground reduces undershoot magnitude but increases its duration. In the adjustable version,
the addition of a capacitor, CFB, from the OUT pin to the FB pin will also improve the transient response.
The TPS737xx does not have active pulldown when the output is overvoltage. This architecture allows
applications that connect higher voltage sources, such as alternate power supplies, to the output. This
architecture also results in an output overshoot of several percent if the load current quickly drops to zero when a
capacitor is connected to the output. The duration of overshoot can be reduced by adding a load resistor. The
overshoot decays at a rate determined by output capacitor COUT and the internal/external load resistance. The
rate of decay is given by Equation 4 and Equation 5.
(Fixed voltage version)
VOUT
dV
dT
+
COUT 80kW ø RLOAD
(4)
(5)
(Adjustable voltage version)
VOUT
dV
dT
+
(
)
COUT 80kW ø R1 ) R2 ø RLOAD
Reverse Current
The NMOS pass element of the TPS737xx provides inherent protection against current flow from the output of
the regulator to the input when the gate of the pass device is pulled low. To ensure that all charge is removed
from the gate of the pass element, the EN pin must be driven low before the input voltage is removed. If this is
not done, the pass element may be left on because of stored charge on the gate.
After the EN pin is driven low, no bias voltage is needed on any pin for reverse current blocking. Note that
reverse current is specified as the current flowing out of the IN pin because of voltage applied on the OUT pin.
There will be additional current flowing into the OUT pin as a result of the 80-kΩ internal resistor divider to
ground (see Figure 1 and Figure 2).
For the TPS73701, reverse current may flow when VFB is more than 1.0V above VIN.
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Thermal Protection
Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the
device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is again
enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection
circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage due to
overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heatsink. For reliable operation, junction temperature should be limited to 125°C maximum. To estimate the
margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal
protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should
trigger at least 35°C above the maximum expected ambient condition of your application. This produces a
worst-case junction temperature of 125°C at the highest expected ambient temperature and worst-case load.
The internal protection circuitry of the TPS737xx has been designed to protect against overload conditions. It
was not intended to replace proper heatsinking. Continuously running the TPS737xx into thermal shutdown
degrades device reliability.
Power Dissipation
The ability to remove heat from the die is different for each package type, presenting different considerations in
the PCB layout. The PCB area around the device that is free of other components moves the heat from the
device to the ambient air. Performance data for JEDEC low- and high-K boards are shown in the Power
Dissipation Ratings table. Using heavier copper will increase the effectiveness in removing heat from the device.
The addition of plated through-holes to heat-dissipating layers also improves the heatsink effectiveness.
Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of
the output current times the voltage drop across the output pass element (VIN to VOUT):
ǒ
Ǔ
PD + VIN * VOUT IOUT
(6)
Power dissipation can be minimized by using the lowest possible input voltage necessary to assure the required
output voltage.
Package Mounting
Solder pad footprint recommendations for the TPS737xx are presented in Application Bulletin Solder Pad
Recommendations for Surface-Mount Devices (SBFA015), available from the Texas Instruments web site at
www.ti.com.
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PACKAGE OPTION ADDENDUM
www.ti.com
6-Apr-2009
PACKAGING INFORMATION
Orderable Device
TPS73719QDRBRQ1
TPS73733QDRBRQ1
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SON
DRB
8
3000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
SON
DRB
8
3000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS73733-Q1 :
Catalog: TPS73733
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 1
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