TPS73701DRVR [TI]

1A Low-Dropout Regulator with Reverse Current Protection; 1A低压降稳压器具有反向电流保护


型号：	TPS73701DRVR
厂家：	TEXAS INSTRUMENTS
描述：	1A Low-Dropout Regulator with Reverse Current Protection 1A低压降稳压器具有反向电流保护线性稳压器IC 调节器电源电路光电二极管输出元件信息通信管理
文件：	总31页 (文件大小：1298K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS737xx

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SBVS067O –JANUARY 2006–REVISED JUNE 2012

1A Low-Dropout Regulator

with Reverse Current Protection

FEATURES

DESCRIPTION

The TPS737xx family of linear low-dropout (LDO)

voltage regulators uses an NMOS pass element in a

voltage-follower configuration. This topology is

relatively insensitive to output capacitor value and

ESR, allowing a wide variety of load configurations.

Load transient response is excellent, even with a

small 1.0μF ceramic output capacitor. The NMOS

topology also allows very low dropout.

•

Stable with 1.0μF or Larger Ceramic Output

Capacitor

•

Input Voltage Range: 2.2V to 5.5V

Ultra-Low Dropout Voltage: 130mV typ at 1A

Excellent Load Transient Response—Even

With Only 1.0μF Output Capacitor

•

NMOS Topology Delivers Low Reverse

Leakage Current

The TPS737xx family uses an advanced BiCMOS

process to yield high precision while delivering very

low dropout voltages and low ground pin current.

Current consumption, when not enabled, is under

20nA and ideal for portable applications. These

devices are protected by thermal shutdown and

foldback current limit.

•

1.0% Initial Accuracy

3% Overall Accuracy Over Line, Load, and

Temperature

•

Less Than 20nA typical I_Qin Shutdown Mode

Thermal Shutdown and Current Limit for Fault

Protection

DRB PACKAGE

3mm x 3mm SON

(TOP VIEW)

•

Available in Multiple Output Voltage Versions

–

Adjustable Output: 1.20V to 5.5V

OUT

N/C

Custom Outputs Available Using Factory

Package-Level Programming

N/C

NR/FB

GND

APPLICATIONS

•

Point of Load Regulation for DSPs, FPGAs,

ASICs, and Microprocessors

DCQ PACKAGE

SOT223

•

Post-Regulation for Switching Supplies

Portable/Battery-Powered Equipment

(TOP VIEW)

DRV PACKAGE⁽¹⁾

2mm x 2mm SON

(TOP VIEW)

TAB IS GND

Optional

OUT

NR/FB

GND

V_IN

V_OUT

1.0mF

OUT

N/C

TPS737xx

GND

OFF

OUT NR/FB

(1) Power dissipation may limit operating

range. Check Thermal Information table.

Typical Application Circuit

space

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS737xx

SBVS067O –JANUARY 2006–REVISED JUNE 2012

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION⁽¹⁾

(2)

PRODUCT

V_OUT

TPS737xx yy yz

XX is nominal output voltage (for example, 25 = 2.5V, 01 = Adjustable⁽³⁾).

YYY is package designator.

Z is package quantity.

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the

device product folder at www.ti.com.

(2) Most output voltages of 1.25V and 1.3V to 5.0V in 100mV increments are available on a quick-turn basis using innovative factory

package-level programming. Minimum order quantities apply; contact factory for details and availability.

(3) For fixed 1.20V operation, tie FB to OUT.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

Over operating free-air temperature range unless otherwise noted.

PARAMETER

TPS737xx

–0.3 to +6.0

–0.3 to +5.5

–0.3 to +6.0

Internally limited

Indefinite

UNIT

V_INrange

V_ENrange

V_OUTrange

V_NR, V_FBrange

Peak output current

Output short-circuit duration

Continuous total power dissipation

Junction temperature range, T_J

Storage temperature range

ESD rating, HBM

See Thermal Information table

–55 to +150

°C

–65 to +150

ESD rating, CDM

500

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics

is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.

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SBVS067O –JANUARY 2006–REVISED JUNE 2012

THERMAL INFORMATION

TPS737xx⁽²⁾

THERMAL METRIC⁽¹⁾

DRB

8 PINS

49.5

58.9

25.1

1.7

DCQ

6 PINS

53.1

35.2

7.8

DRV⁽³⁾

6 PINS

67.2

87.6

36.8

1.8

UNITS

θ_JA

Junction-to-ambient thermal resistance⁽⁴⁾

Junction-to-case (top) thermal resistance⁽⁵⁾

Junction-to-board thermal resistance⁽⁶⁾

Junction-to-top characterization parameter⁽⁷⁾

Junction-to-board characterization parameter⁽⁸⁾

Junction-to-case (bottom) thermal resistance⁽⁹⁾

θ_JCtop

θ_JB

°C/W

ψ_JT

2.9

ψ_JB

25.2

8.6

7.7

37.2

7.7

θ_JCbot

N/A

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A.

(2) Thermal data for the DRB, DCQ, and DRV packages are derived by thermal simulations based on JEDEC-standard methodology as

specified in the JESD51 series. The following assumptions are used in the simulations:

(a) i. DRB: The exposed pad is connected to the PCB ground layer through

ii. DCQ: The exposed pad is connected to the PCB ground layer through

2x2 thermal via array.

a 3x2 thermal via array.

. iii. DRV: The exposed pad is connected to the PCB ground layer through a 2x2 thermal via array. Due to size limitation of thermal

pad, 0.8-mm pitch array is used which is off the JEDEC standard.

(b) The top copper layer has a detailed copper trace pattern. The bottom copper layer is assumed to have a 20% thermal conductivity of

copper, representing a 20% copper coverage.

(c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area. To

understand the effects of the copper area on thermal performance, see the Power Dissipation and Estimating Junction Temperature

sections of this data sheet.

(3) Power dissipation may limit operating range.

(4) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(5) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(6) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(7) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data to obtain θ_JAusing a procedure described in JESD51-2a (sections 6 and 7).

(8) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data to obtain θ_JAusing a procedure described in JESD51-2a (sections 6 and 7).

(9) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

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ELECTRICAL CHARACTERISTICS

Over operating temperature range (T_J= –40°C to +125°C), V_IN= V_OUT(nom)+ 1.0V⁽¹⁾, I_OUT= 10mA, V_EN= 2.2V, and

C_OUT= 2.2μF, unless otherwise noted. Typical values are at T_J= +25°C.

TPS737xx

PARAMETER

Input voltage range⁽¹⁾⁽²⁾

TEST CONDITIONS

MIN

TYP

MAX

5.5

UNIT

V_IN

2.2

Internal reference

(DCQ package)

T_J= +25°C

1.198

1.192

1.2

1.210

1.216

V_FB

Internal reference

(DRB and DRV packages)

T_J= +25°C

Output voltage range

(TPS73701)⁽³⁾

V_FB

5.5 – V_DO

+1.0

Nominal

T_J= +25°C

–1.0

5.36V < V_IN< 5.5V, V_OUT= 5.08V,

10mA < I_OUT< 800mA,

–40C < T_J< +85°C, TPS73701DCQ

V_OUT

Accuracy^{(1) ,}

–2.0

–3.0

+2.0

+3.0

(4)

over V_IN, I_OUT

and T

V_OUT+ 0.5V ≤ V_IN≤ 5.5V;

10mA ≤ I_OUT≤ 1A

±0.5

ΔV_OUT%/ΔV_IN

ΔV_OUT%/ΔI_OUT

Line regulation⁽¹⁾

V_OUT(nom)+ 0.5V ≤ V_IN≤ 5.5V

1mA ≤ I_OUT≤ 1A

0.01

0.002

%/V

Load regulation

%/mA

10mA ≤ I_OUT≤ 1A

0.0005

Dropout voltage⁽⁵⁾

(V_IN= V_OUT(nom)– 0.1V)

V_DO

I_OUT= 1A

130

500

2.2

Z_O(DO)

I_CL

Output impedance in dropout

Output current limit

2.2V ≤ V_IN≤ V_OUT+ V_DO

V_OUT= 0.9 × V_OUT(nom)

V_OUT= 0V

0.25

1.6

450

0.1

400

1300

Ω

1.05

I_SC

Short-circuit current

Reverse leakage current⁽⁶⁾(–I_IN

μA

I_REV

)

V_EN≤ 0.5V, 0V ≤ V_IN≤ V_OUT

I_OUT= 10mA (I_Q)

I_OUT= 1A

I_GND

GND pin current

μA

I_SHDN

I_FB

Shutdown current (I_GND

)

V_EN≤ 0.5V, V_OUT≤ V_IN≤ 5.5

FB pin current (TPS73701)

0.1

0.6

μA

f = 100Hz, I_OUT= 1A

f = 10kHz, I_OUT= 1A

Power-supply rejection ratio

(ripple rejection)

PSRR

V_N

Output noise voltage

BW = 10Hz to 100kHz

C_OUT= 10μF

27 × V_OUT

600

μV_RMS

t_STR

Startup time

V_OUT= 3V, R_L= 30Ω, C_OUT= 1μF

μs

V_EN(HI)

V_EN(LO)

I_EN(HI)

EN pin high (enabled)

EN pin low (shutdown)

EN pin current (enabled)

1.7

V_IN

0.5

V_EN= 5.5V

+160

+140

Shutdown, temperature increasing

Reset, temperature decreasing

T_SD

T_J

Thermal shutdown temperature

Operating junction temperature

°C

–40

+125

(1) Minimum V_IN= V_OUT+ V_DOor 2.2V, whichever is greater.

(2) For V_OUT(nom)< 1.6V, when V_IN≤ 1.6V, the output will lock to V_INand may result in an over-voltage condition on the output. To avoid this

situation, disable the device before powering down V_IN

(3) TPS73701 is tested at V_OUT= 1.2V.

(4) Tolerance of external resistors not included in this specification.

(5) V_DOis not measured for fixed output versions with V_OUT(nom)< 2.3V since minimum V_IN= 2.2V.

(6) Fixed-voltage versions only; refer to the Applications section for more information.

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SBVS067O –JANUARY 2006–REVISED JUNE 2012

FUNCTIONAL BLOCK DIAGRAMS

4MHz

Charge Pump

Thermal

Protection

Ref

Servo

Ω

27k

Bandgap

Error

Amp

Current

Limit

OUT

Ω

GND

R₁

Ω

R₁+ R₂= 80k

R₂

Figure 1. Fixed Voltage Version

Table 1. Standard 1%

Resistor Values for

Common Output Voltages

4MHz

1.2V

1.5V

1.8V

2.5V

2.8V

3.0V

3.3V

Short

Open

Charge Pump

23.2kΩ

28.0kΩ

39.2kΩ

44.2kΩ

46.4kΩ

52.3kΩ

95.3kΩ

56.2kΩ

36.5kΩ

33.2kΩ

30.9kΩ

30.1kΩ

Thermal

Protection

Ref

Servo

Ω

27k

Bandgap

Error

Amp

NOTE: V

= (R + R )/R × 1.204;

1 2 2

OUT

Current

Limit

19kΩ for best

accuracy.

GND

Ω

80k

Ω

R₁

R₂

Figure 2. Adjustable Voltage Version

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PIN CONFIGURATIONS

DCQ PACKAGE

SOT223-6

(TOP VIEW)

DRB PACKAGE

3mm x 3mm SON

(TOP VIEW)

TAB IS GND

OUT

N/C

NR/FB

GND

OUT NR/FB

DRV PACKAGE⁽¹⁾

2mm x 2mm SON

(TOP VIEW)

OUT

NR/FB

GND

N/C

(1) Power dissipation may limit operating range. Check Thermal Information table.

Table 1. Pin Descriptions

SOT223

(DCQ)

3×3 SON

(DRB)

2×2 SON

(DRV)

NAME

PIN NO.

DESCRIPTION

Unregulated input supply

Ground

GND

3, 6

4, Pad

3, Pad

Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts

the regulator into shutdown mode. Refer to the Shutdown section under

Applications Information for more details. EN must not be left floating and can

be connected to IN if not used.

Fixed voltage versions only—connecting an external capacitor to this pin

bypasses noise generated by the internal bandgap, reducing output noise to

very low levels.

Adjustable voltage version only—this is the input to the control loop error

amplifier, and is used to set the output voltage of the device.

OUT

Regulator output. A 1.0μF or larger capacitor of any type is required for stability.

—

2, 6, 7

Not connected

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TYPICAL CHARACTERISTICS

For all voltage versions at T_J= +25°C, V_IN= V_OUT(nom)+ 1.0V, I_OUT= 10mA, V_EN= 2.2V, and C_OUT= 2.2μF, unless otherwise

noted.

LOAD REGULATION

LINE REGULATION

0.5

0.4

0.20

0.15

0.10

0.05

Referred to I_OUT= 10mA

Referred to V_IN= V_OUT+ 1.0V at I_OUT= 10mA

-40°C

+25°C

+125°C

0.3

0.2

+25°C

+125°C

0.1

-0.1

-0.2

-0.3

-0.4

-0.5

-0.05

-0.10

-0.15

-0.20

-40°C

100 200 300 400 500 600 700 800 900 1000

I_OUT(mA)

0.5

1.0

1.5

2.0

2.5

3.0 3.5

4.0

4.5

_IN- V_OUT(V)

Figure 3.

Figure 4.

DROPOUT VOLTAGE vs OUTPUT CURRENT

DROPOUT VOLTAGE vs TEMPERATURE

200

180

160

140

120

100

200

180

160

140

120

100

V_OUT= 2.5V

+125°C

+25°C

-40°C

100 200 300 400 500 600 700 800 900 1000

I_OUT(mA)

-50

-25

100

125

150

Temperature (°C)

Figure 5.

Figure 6.

OUTPUT VOLTAGE HISTOGRAM

OUTPUT VOLTAGE DRIFT HISTOGRAM

I_OUT= 10mA

V_OUTError (%)

Worst Case dV_OUT/dT (ppm/°C)

Figure 7.

Figure 8.

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TYPICAL CHARACTERISTICS (continued)

For all voltage versions at T_J= +25°C, V_IN= V_OUT(nom)+ 1.0V, I_OUT= 10mA, V_EN= 2.2V, and C_OUT= 2.2μF, unless otherwise

noted.

GROUND PIN CURRENT vs OUTPUT CURRENT

GROUND PIN CURRENT vs TEMPERATURE

3000

2500

2000

1500

1000

500

2500

2000

1500

1000

500

I_OUT= 1A

V_IN= 5.0V

V_IN= 3.3V

V_IN= 2.2V

-50

-25

100

125

200

400

600

800

1000

Temperature (°C)

I_OUT(mA)

Figure 9.

Figure 10.

GROUND PIN CURRENT IN SHUTDOWN

vs TEMPERATURE

CURRENT LIMIT vs V_OUT(FOLDBACK)

2.00

1.80

1.60

1.40

1.20

1.00

0.80

0.60

0.40

0.20

V_ENABLE= 0.5V

V_IN= V_OUT+ 0.5V

I_CL

0.1

I_SC

V_OUT= 3.3V

0.01

-0.5

0.5

1.0

1.5

2.0

2.5

3.0

3.5

-50

-25

100

125

Output Voltage (V)

Temperature (°C)

Figure 11.

Figure 12.

CURRENT LIMIT vs V_IN

CURRENT LIMIT vs TEMPERATURE

2.0

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0

V_OUT= 1.2V

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

-50

-25

100

125

V_IN(V)

Temperature (°C)

Figure 13.

Figure 14.

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TYPICAL CHARACTERISTICS (continued)

For all voltage versions at T_J= +25°C, V_IN= V_OUT(nom)+ 1.0V, I_OUT= 10mA, V_EN= 2.2V, and C_OUT= 2.2μF, unless otherwise

noted.

PSRR (RIPPLE REJECTION) vs FREQUENCY

PSRR (RIPPLE REJECTION) vs V_IN– V_OUT

I_OUT= 100mA

C_OUT= Any

I_OUT= 1mA

C_OUT= 1mF

I_OUT= 1mA

C_OUT= 10mF

I_O= 100mA

C_O= 1mF

I_OUT= 1mA

C_OUT= Any

Frequency = 10kHz

C_OUT= 10mF

I_OUT= 100mA

C_OUT= 10mF

V_OUT= 2.5V

I_OUT= 100mA

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

100

10k

100k

10M

V_IN- V_OUT(V)

Frequency (Hz)

Figure 15.

Figure 16.

TPS73701

NOISE SPECTRAL DENSITY

RMS NOISE VOLTAGE vs C_FB

C_OUT= 1mF

0.1

C_OUT= 10mF

V_OUT= 2.5V

C_OUT= 0mF

R₁= 39.2kW

I_OUT= 150mA

10Hz < Frequency < 100kHz

0.01

100

10k

100k

10p

100p

10n

C_FB(F)

Frequency (Hz)

Figure 17.

Figure 18.

RMS NOISE VOLTAGE vs C_NR

RMS NOISE VOLTAGE vs C_OUT

140

120

100

V_OUT= 5.0V

V_OUT= 3.3V

V_OUT= 1.5V

C_NR= 0.01mF

C_OUT= 0mF

10Hz < Frequency < 100kHz

0.1

10p

100p

10n

C_OUT(mF)

C_NR(F)

Figure 19.

Figure 20.

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TYPICAL CHARACTERISTICS (continued)

For all voltage versions at T_J= +25°C, V_IN= V_OUT(nom)+ 1.0V, I_OUT= 10mA, V_EN= 2.2V, and C_OUT= 2.2μF, unless otherwise

noted.

TPS73733

LOAD TRANSIENT RESPONSE

LINE TRANSIENT RESPONSE

C_NR= 10nF

C_OUT= 10mF

V_OUT

200mV/div

C_OUT= 10mF

100mV/div

V_OUT

5.3V

10mA

4.3V

I_OUT

V_IN

10ms/div

Figure 21.

Figure 22.

TPS73701

TURN-ON RESPONSE

TURN-OFF RESPONSE

R_L= 20W

C_OUT= 10mF

V_OUT

R_L= 20W

C_OUT= 1mF

1V/div

C_OUT= 1mF

R_L= 20W

C_OUT= 10mF

V_OUT

V_EN

1V/div

V_EN

100ms/div

Figure 23.

Figure 24.

TPS73701, V_OUT= 3.3V

POWER-UP/POWER-DOWN

I_ENABLEvs TEMPERATURE

V_IN

V_OUT

0.1

0.01

-1

-2

50ms/div

-50

-25

100

125

Temperature (°C)

Figure 25.

Figure 26.

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TYPICAL CHARACTERISTICS (continued)

For all voltage versions at T_J= +25°C, V_IN= V_OUT(nom)+ 1.0V, I_OUT= 10mA, V_EN= 2.2V, and C_OUT= 2.2μF, unless otherwise

noted.

TPS73701

RMS NOISE VOLTAGE vs C_FB

I_FBvs TEMPERATURE

160

140

120

100

V_OUT= 2.5V

C_OUT= 0mF

R₁= 39.2kW

10Hz < Frequency < 100kHz

-50

-25

100

125

10p

100p

10n

Temperature (°C)

C_FB(F)

Figure 27.

Figure 28.

TPS73701

LOAD TRANSIENT, ADJUSTABLE VERSION

LINE TRANSIENT, ADJUSTABLE VERSION

V_OUT= 2.5V

C_FB= 10nF

R₁= 39.2kW

C_OUT= 10mF

V_OUT

100mV/div

4.5V

250mA

3.5V

I_OUT

V_IN

10mA

10ms/div

5ms/div

Figure 29.

Figure 30.

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APPLICATION INFORMATION

The TPS737xx belongs to a family of new generation

LDO regulators that use an NMOS pass transistor to

achieve ultra-low-dropout performance, reverse

current blockage, and freedom from output capacitor

constraints. These features combined with an enable

input make the TPS737xx ideal for portable

applications. This regulator family offers a wide

selection of fixed output voltage versions and an

adjustable output version. All versions have thermal

and over-current protection, including foldback

current limit.

For best accuracy, make the parallel combination of

R₁and R₂approximately equal to 19kΩ. This 19kΩ,

in addition to the internal 8kΩ resistor, presents the

same impedance to the error amp as the 27kΩ

bandgap reference output. This impedance helps

compensate for leakages into the error amp

terminals.

INPUT AND OUTPUT CAPACITOR

REQUIREMENTS

Although an input capacitor is not required for stability

if input impedance is very low, it is good analog

design practice to connect a 0.1μF to 1μF low

equivalent series resistance (ESR) capacitor across

the input supply near the regulator. This capacitor

counteracts reactive input sources and improves

transient response, noise rejection, and ripple

rejection. A higher-value capacitor may be necessary

if large, fast rise-time load transients are anticipated

or the device is located several inches from the

power source.

Figure 31 shows the basic circuit connections for the

fixed voltage models. Figure 32 gives the connections

for the adjustable output version (TPS73701).

V_IN

V_OUT

OUT

TPS737xx

GND

OFF

The TPS737xx requires a 1.0µF output capacitor for

stability. It is designed to be stable for all available

types and values of capacitors. In applications where

multiple low ESR capacitors are in parallel, ringing

may occur when the product of C_OUTand total ESR

drops below 50nΩF. Total ESR includes all parasitic

resistances, including capacitor ESR and board,

socket, and solder joint resistance. In most

applications, the sum of capacitor ESR and trace

resistance will meet this requirement.

Figure 31. Typical Application Circuit for Fixed-

Voltage Versions

Optional input capacitor.

May improve source

Output capacitor

impedance, noise, or PSRR.

must be ³ 1.0mF.

V_IN

V_OUT

OUT

TPS73701

R₁

R₂

C_FB

GND

OUTPUT NOISE

OFF

A precision bandgap reference is used to generate

the internal reference voltage, V_REF. This reference is

the dominant noise source within the TPS737xx and

it generates approximately 32μV_RMS(10Hz to

100kHz) at the reference output (NR). The regulator

control loop gains up the reference noise with the

same gain as the reference voltage, so that the noise

voltage of the regulator is approximately given by:

Optional capacitor

reduces output noise

and improves

(R₁+ R₂)

R₂

V_OUT

x 1.204

transient response.

Figure 32. Typical Application Circuit for

Adjustable-Voltage Version

(

)

V_OUT

V_REF

R₁) R₂

V_N+ 32mV_RMS

+ 32mV_RMS

R₁and R₂can be calculated for any output voltage

using the formula shown in Figure 32. Sample

resistor values for common output voltages are

shown in Figure 2.

R₂

(1)

Since the value of V_REFis 1.2V, this relationship

reduces to:

mV_RMS

_+ 27ǒ Ǔ

( )

V_NmV_RMS

V_OUT

(2)

for the case of no C_NR

Submit Documentation Feedback

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SBVS067O –JANUARY 2006–REVISED JUNE 2012

An internal 27kΩ resistor in series with the noise

reduction pin (NR) forms a low-pass filter for the

voltage reference when an external noise reduction

capacitor, C_NR, is connected from NR to ground. For

C_NR= 10nF, the total noise in the 10Hz to 100kHz

bandwidth is reduced by a factor of ~3.2, giving the

approximate relationship:

ENABLE PIN AND SHUTDOWN

The enable pin (EN) is active high and is compatible

with standard TTL-CMOS levels. A V_ENbelow 0.5V

(max) turns the regulator off and drops the GND pin

current to approximately 10nA. When EN is used to

shutdown the regulator, all charge is removed from

the pass transistor gate, and the output ramps back

up to a regulated V_OUT(see Figure 23).

mV_RMS

V_N(mV_RMS) = 8.5

x V_OUT(V)

(

)

(3)

When shutdown capability is not required, EN can be

connected to V_IN. However, the pass gate may not be

discharged using this configuration, and the pass

transistor may be left on (enhanced) for a significant

time after V_INhas been removed. This scenario can

result in reverse current flow (if the IN pin is low

impedance) and faster ramp times upon power-up. In

addition, for V_INramp times slower than a few

milliseconds, the output may overshoot upon power-

up.

for C_NR= 10nF.

This noise reduction effect is shown as RMS Noise

Voltage vs C_NRin the Typical Characteristics section.

The TPS73701 adjustable version does not have the

NR pin available. However, connecting a feedback

capacitor, C_FB, from the output to the feedback pin

(FB) reduces output noise and improve load transient

performance. This capacitor should be limited to

0.1µF.

Note that current limit foldback can prevent device

start-up under some conditions. See the Internal

Current Limit section for more information.

The TPS737xx uses an internal charge pump to

develop an internal supply voltage sufficient to drive

the gate of the NMOS pass element above V_OUT. The

charge pump generates ~250μV of switching noise at

~4MHz; however, charge-pump noise contribution is

negligible at the output of the regulator for most

DROPOUT VOLTAGE

The TPS737xx uses an NMOS pass transistor to

achieve extremely low dropout. When (V_IN– V_OUT) is

less than the dropout voltage (V_DO), the NMOS pass

device is in its linear region of operation and the

input-to-output resistance is the R_{DS, ON}of the NMOS

pass element.

values of I_OUTand C_OUT

BOARD LAYOUT RECOMMENDATION TO

IMPROVE PSRR AND NOISE PERFORMANCE

For large step changes in load current, the TPS737xx

requires a larger voltage drop from V_INto V_OUTto

avoid degraded transient response. The boundary of

this transient dropout region is approximately twice

the dc dropout. Values of V_IN– V_OUTabove this line

ensure normal transient response.

To improve ac performance such as PSRR, output

noise, and transient response, it is recommended that

the printed circuit board (PCB) be designed with

separate ground planes for V_INand V_OUT, with each

ground plane connected only at the GND pin of the

device. In addition, the ground connection for the

bypass capacitor should connect directly to the GND

pin of the device.

Operating in the transient dropout region can cause

an increase in recovery time. The time required to

recover from a load transient is a function of the

magnitude of the change in load current rate, the rate

of change in load current, and the available

headroom (V_INto V_OUTvoltage drop). Under worst-

case conditions [full-scale instantaneous load change

with (V_IN– V_OUT) close to dc dropout levels], the

INTERNAL CURRENT LIMIT

The TPS737xx internal current limit helps protect the

regulator during fault conditions. Foldback current

limit helps to protect the regulator from damage

during output short-circuit conditions by reducing

current limit when V_OUTdrops below 0.5V. See

Figure 12 in the Typical Characteristics section.

TPS737xx can take

couple of hundred

microseconds to return to the specified regulation

accuracy.

Note from Figure 12 that approximately –0.2V of V_OUT

results in a current limit of 0mA. Therefore, if OUT is

forced below –0.2V before EN goes high, the device

may not start up. In applications that work with both a

positive and negative voltage supply, the TPS737xx

should be enabled first.

Submit Documentation Feedback

TPS737xx

SBVS067O –JANUARY 2006–REVISED JUNE 2012

www.ti.com

TRANSIENT RESPONSE

After the EN pin is driven low, no bias voltage is

needed on any pin for reverse current blocking. Note

that reverse current is specified as the current flowing

out of the IN pin because of voltage applied on the

OUT pin. There will be additional current flowing into

the OUT pin as a result of the 80kΩ internal resistor

divider to ground (see Figure 1 and Figure 2).

The low open-loop output impedance provided by the

NMOS pass element in

voltage follower

configuration allows operation without a 1.0µF output

capacitor. As with any regulator, the addition of

additional capacitance from the OUT pin to ground

reduces undershoot magnitude but increases its

duration. In the adjustable version, the addition of a

capacitor, C_FB, from the OUT pin to the FB pin will

also improve the transient response.

For the TPS73701, reverse current may flow when

V_FBis more than 1.0V above V_IN.

THERMAL PROTECTION

The TPS737xx does not have active pull-down when

the output is over-voltage. This architecture allows

applications that connect higher voltage sources,

such as alternate power supplies, to the output. This

architecture also results in an output overshoot of

several percent if the load current quickly drops to

zero when a capacitor is connected to the output. The

duration of overshoot can be reduced by adding a

load resistor. The overshoot decays at a rate

determined by output capacitor C_OUTand the

internal/external load resistance. The rate of decay is

given by:

Thermal protection disables the output when the

junction temperature rises to approximately +160°C,

allowing the device to cool. When the junction

temperature cools to approximately +140°C, the

output circuitry is again enabled. Depending on power

dissipation, thermal resistance, and ambient

temperature, the thermal protection circuit may cycle

on and off. This cycling limits the dissipation of the

regulator, protecting it from damage due to

overheating.

Any tendency to activate the thermal protection circuit

indicates excessive power dissipation or an

inadequate heatsink. For reliable operation, junction

temperature should be limited to +125°C maximum.

To estimate the margin of safety in a complete design

(Fixed voltage version)

V_OUT

C_OUT 80kW ø R_LOAD

(4)

(5)

(including

heatsink),

increase

the

ambient

temperature until the thermal protection is triggered;

use worst-case loads and signal conditions. For good

reliability, thermal protection should trigger at least

+35°C above the maximum expected ambient

condition of your application. This produces a worst-

case junction temperature of +125°C at the highest

expected ambient temperature and worst-case load.

(Adjustable voltage version)

V_OUT

(

)

C_OUT 80kW ø R₁) R₂ø R_LOAD

REVERSE CURRENT

The NMOS pass element of the TPS737xx provides

inherent protection against current flow from the

output of the regulator to the input when the gate of

the pass device is pulled low. To ensure that all

charge is removed from the gate of the pass element,

the EN pin must be driven low before the input

voltage is removed. If this is not done, the pass

element may be left on because of stored charge on

the gate.

The internal protection circuitry of the TPS737xx has

been designed to protect against overload conditions.

It was not intended to replace proper heatsinking.

Continuously running the TPS737xx into thermal

shutdown degrades device reliability.

Submit Documentation Feedback

TPS737xx

www.ti.com

SBVS067O –JANUARY 2006–REVISED JUNE 2012

POWER DISSIPATION

Knowing the maximum R_θJA, the minimum amount of

PCB copper area needed for appropriate heatsinking

can be estimated using Figure 33.

Knowing the device power dissipation and proper

sizing of the thermal plane that is connected to the

tab or pad is critical to avoiding thermal shutdown

and ensuring reliable operation.

160

DCQ

DRV

DRB

140

Power dissipation of the device depends on input

voltage and load conditions and can be calculated

using Equation 6:

120

100

P_D+ V_IN* V_OUT I_OUT

(6)

Power dissipation can be minimized and greater

efficiency can be achieved by using the lowest

possible input voltage necessary to achieve the

required output voltage regulation.

On both SON (DRB) and SON (DRV) packages, the

primary conduction path for heat is through the

exposed pad to the printed circuit board (PCB). The

pad can be connected to ground or be left floating;

however, it should be attached to an appropriate

amount of copper PCB area to ensure the device

does not overheat. On the SOT-223 (DCQ) package,

the primary conduction path for heat is through the

tab to the PCB. That tab should be connected to

ground. The maximum junction-to-ambient thermal

resistance depends on the maximum ambient

temperature, maximum device junction temperature,

and power dissipation of the device and can be

calculated using Equation 7:

Board Copper Area (in²)

Note: θ_JAvalue at board size of 9in²(that is, 3in ×

3in) is a JEDEC standard.

Figure 33. θ_JAvs Board Size

Figure 33 shows the variation of θ_JAas a function of

ground plane copper area in the board. It is intended

only as a guideline to demonstrate the effects of heat

spreading in the ground plane and should not be

used to estimate actual thermal performance in real

application environments.

(

)

)125 C * T_A

NOTE: When the device is mounted on an

application PCB, it is strongly recommended to use

Ψ_JTand Ψ_JB, as explained in the Estimating Junction

Temperature section.

qJA

P_D

(7)

Submit Documentation Feedback

TPS737xx

SBVS067O –JANUARY 2006–REVISED JUNE 2012

www.ti.com

ESTIMATING JUNCTION TEMPERATURE

Using the thermal metrics Ψ_JTand Ψ_JB, as shown in

the Thermal Information table, the junction

temperature can be estimated with corresponding

formulas (given in Equation 8). For backwards

compatibility, an older θ_JC,Top parameter is listed as

well.

DRV

DCQ

DRB

Y_JB

DRV

DCQ

DRB

Y_JT

Y_JT: T_J= T_T+ Y_JT· P_D

Y_JB: T_J= T_B+ Y_JB· P_D

(8)

Where P_Dis the power dissipation shown by

Equation 6, T_Tis the temperature at the center-top of

the IC package, and T_Bis the PCB temperature

measured 1mm away from the IC package on the

PCB surface (as Figure 35 shows).

Board Copper Area (in²)

Figure 34. Ψ_JTand Ψ_JBvs Board Size

NOTE: Both T_Tand T_Bcan be measured on actual

application boards using a thermo-gun (an infrared

thermometer).

For a more detailed discussion of why TI does not

recommend using θ_JC(top)to determine thermal

characteristics, refer to application report SBVA025,

Using New Thermal Metrics, available for download

at www.ti.com. For further information, refer to

application report SPRA953, IC Package Thermal

Metrics, also available on the TI website.

For more information about measuring T_Tand T_B, see

the application note SBVA025, Using New Thermal

Metrics, available for download at www.ti.com.

By looking at Figure 34, the new thermal metrics (Ψ_JT

and Ψ_JB) have very little dependency on board size.

That is, using Ψ_JTor Ψ_JBwith Equation 8 is a good

way to estimate T_Jby simply measuring T_Tor T_B,

regardless of the application board size.

T_B

1mm

T_Ton top

of IC

T_Ton top

of IC

T_Bon PCB

surface

T_Bon PCB

surface

T_T

1mm

See note (1)

(a) Example DRB (SON) Package Measurement

(b) Example DRV (SON) Package Measurement

(1) Power dissipation may limit operating range. Check Thermal Information table.

Figure 35. Measuring Points for T_Tand T_B

Submit Documentation Feedback

TPS737xx

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SBVS067O –JANUARY 2006–REVISED JUNE 2012

REVISION HISTORY

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision N (June 2011) to Revision O

Page

•

Changed Thermal Information table data and footnote 2b ................................................................................................... 3

Changed V_FBInternal reference parameter in Electrical Characteristics table ..................................................................... 4

Changed title of Figure 8 ...................................................................................................................................................... 7

Changes from Revision M (October, 2010) to Revision N

Page

•

Added footnote (3) to Thermal Information table .................................................................................................................. 3

Added footnote to Figure 35 ............................................................................................................................................... 16

Submit Documentation Feedback

PACKAGE OPTION ADDENDUM

www.ti.com

11-Apr-2013

PACKAGING INFORMATION

Orderable Device

TPS73701DCQ

Status Package Type Package Pins Package

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

-40 to 125

Top-Side Markings

Samples

Drawing

Qty

(1)

(2)

(3)

(4)

ACTIVE

SOT-223

SON

DCQ

Green (RoHS

& no Sb/Br)

CU SN

Level-2-260C-1 YEAR

TPS73701

TPS73701DCQG4

TPS73701DCQR

TPS73701DCQRG4

TPS73701DRBR

TPS73701DRBRG4

TPS73701DRBT

TPS73701DRBTG4

TPS73701DRVR

TPS73701DRVT

TPS73718DCQ

ACTIVE

DCQ

DRB

DRV

DCQ

DRB

DCQ

Green (RoHS

& no Sb/Br)

CU NIPDAU

CU SN

TPS73701

BZN

2500

3000

250

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

CU NIPDAU

CU SN

Green (RoHS

& no Sb/Br)

SON

Green (RoHS

& no Sb/Br)

BZN

SON

Green (RoHS

& no Sb/Br)

BZN

SON

250

Green (RoHS

& no Sb/Br)

BZN

SON

3000

250

Green (RoHS

& no Sb/Br)

QTN

SON

Green (RoHS

& no Sb/Br)

QTN

SOT-223

SON

Green (RoHS

& no Sb/Br)

TPS73718

RAL

TPS73718DCQG4

TPS73718DCQR

TPS73718DCQRG4

TPS73718DRBR

TPS73718DRBT

TPS73725DCQ

Green (RoHS

& no Sb/Br)

CU NIPDAU

CU SN

2500

3000

250

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

CU NIPDAU

Green (RoHS

& no Sb/Br)

SON

Green (RoHS

& no Sb/Br)

RAL

SOT-223

Green (RoHS

& no Sb/Br)

TPS73725

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

11-Apr-2013

Orderable Device

Status Package Type Package Pins Package

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

Top-Side Markings

Samples

Drawing

Qty

(1)

(2)

(3)

(4)

TPS73725DCQG4

TPS73725DCQR

ACTIVE

SOT-223

DCQ

TBD

Call TI

CU SN

Call TI

-40 to 125

ACTIVE

DCQ

DRB

DCQ

DRV

DCQ

2500

3000

250

Green (RoHS

& no Sb/Br)

Level-2-260C-1 YEAR

TPS73725

TPS73725DCQRG4

TPS73730DRBR

TPS73730DRBT

TPS73733DCQ

SOT-223

SON

Green (RoHS

& no Sb/Br)

CU NIPDAU

CU SN

Level-2-260C-1 YEAR

-40 to 125

TPS73725

CVT

Green (RoHS

& no Sb/Br)

SON

Green (RoHS

& no Sb/Br)

CVT

SOT-223

SON

Green (RoHS

& no Sb/Br)

TPS73733

SIJ

TPS73733DCQG4

TPS73733DCQR

TPS73733DCQRG4

TPS73733DRVR

TPS73733DRVT

TPS73734DCQ

Green (RoHS

& no Sb/Br)

CU NIPDAU

CU SN

2500

3000

250

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

CU NIPDAU

Green (RoHS

& no Sb/Br)

SON

Green (RoHS

& no Sb/Br)

SIJ

SOT-223

Green (RoHS

& no Sb/Br)

OCH

TPS73734DCQR

2500

Green (RoHS

& no Sb/Br)

OCH

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

11-Apr-2013

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a

continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TPS73733 :

Automotive: TPS73733-Q1

•

NOTE: Qualified Version Definitions:

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

•

Addendum-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com

24-Apr-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS73701DCQRG4

TPS73701DRBR

TPS73701DRBT

TPS73701DRVR

TPS73701DRVT

TPS73718DCQRG4

TPS73718DRBR

TPS73718DRBT

TPS73725DCQRG4

TPS73730DRBR

TPS73730DRBT

TPS73733DCQRG4

TPS73733DRVR

TPS73733DRVT

TPS73734DCQR

SOT-223 DCQ

2500

3000

250

330.0

180.0

179.0

330.0

180.0

330.0

180.0

330.0

179.0

330.0

12.4

8.4

7.05

3.3

2.2

7.05

3.3

7.05

3.3

7.05

2.2

6.8

7.45

3.3

2.2

7.45

3.3

7.45

3.3

7.45

2.2

7.3

1.88

1.1

8.0

4.0

8.0

4.0

8.0

12.0

8.0

SON

DRB

DRV

1.1

250

1.1

3000

250

1.2

8.4

1.2

8.0

SOT-223 DCQ

2500

3000

250

12.4

8.4

1.88

1.1

12.0

8.0

SON

DRB

1.1

SOT-223 DCQ

2500

3000

250

1.88

1.1

SON

DRB

1.1

SOT-223 DCQ

2500

3000

250

1.88

1.2

SON

DRV

8.4

1.2

8.0

SOT-223 DCQ

2500

12.4

1.88

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

24-Apr-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS73701DCQRG4

TPS73701DRBR

TPS73701DRBT

TPS73701DRVR

TPS73701DRVT

TPS73718DCQRG4

TPS73718DRBR

TPS73718DRBT

TPS73725DCQRG4

TPS73730DRBR

TPS73730DRBT

TPS73733DCQRG4

TPS73733DRVR

TPS73733DRVT

TPS73734DCQR

SOT-223

SON

DCQ

DRB

DRV

DCQ

DRB

DCQ

DRB

DCQ

DRV

DCQ

2500

3000

250

358.0

367.0

552.0

210.0

552.0

195.0

358.0

367.0

210.0

358.0

367.0

210.0

358.0

195.0

358.0

335.0

367.0

185.0

200.0

335.0

367.0

185.0

335.0

367.0

185.0

335.0

200.0

335.0

35.0

36.0

35.0

36.0

45.0

35.0

45.0

35.0

SON

250

SON

3000

250

SON

SOT-223

SON

2500

3000

250

SON

SOT-223

SON

2500

3000

250

SON

SOT-223

SON

2500

3000

250

SON

SOT-223

2500

Pack Materials-Page 2

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that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which

anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause

harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use

of any TI components in safety-critical applications.

In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to

help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and

requirements. Nonetheless, such components are subject to these terms.

No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties

have executed a special agreement specifically governing such use.

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military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components

which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and

regulatory requirements in connection with such use.

TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of

non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.

Products

Applications

Audio

www.ti.com/audio

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

Automotive and Transportation www.ti.com/automotive

Communications and Telecom www.ti.com/communications

Amplifiers

Data Converters

DLP® Products

DSP

Computers and Peripherals

Consumer Electronics

Energy and Lighting

Industrial

www.ti.com/computers

www.ti.com/consumer-apps

www.ti.com/energy

dsp.ti.com

Clocks and Timers

Interface

www.ti.com/clocks

interface.ti.com

logic.ti.com

www.ti.com/industrial

www.ti.com/medical

Medical

Logic

Security

www.ti.com/security

Power Mgmt

Microcontrollers

RFID

power.ti.com

Space, Avionics and Defense

Video and Imaging

www.ti.com/space-avionics-defense

www.ti.com/video

microcontroller.ti.com

www.ti-rfid.com

www.ti.com/omap

OMAP Applications Processors

Wireless Connectivity

TI E2E Community

e2e.ti.com

www.ti.com/wirelessconnectivity

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TPS73701DRVR [TI]

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