TPS73718DCQ [TI]
1A Low-Dropout Regulator with Reverse Current Protection; 1A低压降稳压器具有反向电流保护
| 型号： | TPS73718DCQ |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1A Low-Dropout Regulator with Reverse Current Protection |
| 文件： | 总22页 (文件大小：974K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS737xx
www.ti.com.................................................................................................................................................... SBVS067I–JANUARY 2006–REVISED MARCH 2009
1A Low-Dropout Regulator
with Reverse Current Protection
1
FEATURES
DESCRIPTION
2
•
Stable with 1.0µF or Larger Ceramic Output
Capacitor
The TPS737xx family of linear low-dropout (LDO)
voltage regulators uses an NMOS pass element in a
voltage-follower configuration. This topology is
relatively insensitive to output capacitor value and
ESR, allowing a wide variety of load configurations.
Load transient response is excellent, even with a
small 1.0µF ceramic output capacitor. The NMOS
topology also allows very low dropout.
•
•
•
Input Voltage Range: 2.2V to 5.5V
Ultra-Low Dropout Voltage: 130mV typ at 1A
Excellent Load Transient Response—Even
With Only 1.0µF Output Capacitor
•
NMOS Topology Delivers Low Reverse
Leakage Current
The TPS737xx family uses an advanced BiCMOS
process to yield high precision while delivering very
low dropout voltages and low ground pin current.
Current consumption, when not enabled, is under
20nA and ideal for portable applications. These
devices are protected by thermal shutdown and
foldback current limit.
•
•
1.0% Initial Accuracy
3% Overall Accuracy Over Line, Load, and
Temperature
•
•
Less Than 20nA typical IQ in Shutdown Mode
Thermal Shutdown and Current Limit for Fault
Protection
DRB PACKAGE
3mm x 3mm SON
(TOP VIEW)
•
Available in Multiple Output Voltage Versions
–
–
Adjustable Output: 1.20V to 5.5V
OUT
N/C
1
2
3
4
8
7
6
5
IN
Custom Outputs Available Using Factory
Package-Level Programming
N/C
N/C
EN
NR/FB
GND
APPLICATIONS
•
Point of Load Regulation for DSPs, FPGAs,
ASICs, and Microprocessors
DCQ PACKAGE
SOT223
•
•
Post-Regulation for Switching Supplies
Portable/Battery-Powered Equipment
(TOP VIEW)
6
3
TAB IS GND
Optional
VIN
VOUT
1.0mF
IN
OUT
FB
1
2
4
5
TPS737xx
EN
GND
IN
GND
EN
ON
OFF
OUT NR/FB
Typical Application Circuit
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2009, Texas Instruments Incorporated
TPS737xx
SBVS067I–JANUARY 2006–REVISED MARCH 2009.................................................................................................................................................... www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
(2)
PRODUCT
VOUT
TPS737xxyyyz
XX is nominal output voltage (for example, 25 = 2.5V, 01 = Adjustable(3)).
YYY is package designator.
Z is package quantity.
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Most output voltages of 1.25V and 1.3V to 5.0V in 100mV increments are available on a quick-turn basis using innovative factory
package-level programming. Minimum order quantities apply; contact factory for details and availability.
(3) For fixed 1.20V operation, tie FB to OUT.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
PARAMETER
TPS737xx
–0.3 to +6.0
–0.3 to +6.0
–0.3 to +5.5
–0.3 to +6.0
Internally limited
Indefinite
UNIT
VIN range
V
V
V
V
VEN range
VOUT range
VNR, VFB range
Peak output current
Output short-circuit duration
Continuous total power dissipation
Junction temperature range, TJ
Storage temperature range
ESD rating, HBM
See Dissipation Ratings Table
–55 to +150
°C
°C
kV
V
–65 to +150
2
ESD rating, CDM
500
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
POWER DISSIPATION RATINGS(1)
DERATING FACTOR
ABOVE TA = +25°C POWER RATING POWER RATING POWER RATING
T
A ≤ +25°C
TA = +70°C
TA = +85°C
BOARD
PACKAGE
RθJC
RθJA
Low-K(2)
High-K(3)
High-K(3)(4)
DCQ
DCQ
DRB
15°C/W
15°C/W
1.2°C/W
53°C/W
45°C/W
40°C/W
18.9mW/°C
22.2mW/°C
25.0mW/°C
1.89W
2.22W
2.50W
1.04W
1.22W
1.38W
0.76W
0.89W
1.0W
(1) See Power Dissipation in the Applications section for more information related to thermal design.
(2) The JEDEC Low-K (1s) board design used to derive this data was a 3-inch × 3-inch, 2-layer board with 2-ounce copper traces on top of
the board.
(3) The JEDEC High-K (2s2p) board design used to derive this data was a 3-inch x 3-inch, multilayer board with 1-ounce internal power and
ground planes and 2-ounce copper traces on the top and bottom of the board.
(4) Based on preliminary thermal simulations.
2
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TPS737xx
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ELECTRICAL CHARACTERISTICS
Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 1.0V(1), IOUT = 10mA, VEN = 2.2V, and
COUT = 2.2µF, unless otherwise noted. Typical values are at TJ = +25°C.
TPS737xx
PARAMETER
Input voltage range(1),(2)
TEST CONDITIONS
MIN
TYP
MAX
5.5
UNIT
VIN
2.2
V
Internal reference
(TPS73701-DCQ)
TJ = +25°C
1.198
1.192
1.2
1.2
1.210
1.216
VFB
V
V
Internal reference
(TPS73701-DRB)
TJ = +25°C
Output voltage range
(TPS73701)(3)
VFB
5.5 – VDO
+1.0
Nominal
TJ = +25°C
–1.0
5.36V < VIN < 5.5V, VOUT = 5.08V,
10mA < IOUT < 800mA,
–40C < TJ < +85°C, TPS73701DCQ
VOUT
–2.0
–3.0
+2.0
+3.0
Accuracy(1),(4)
%
over VIN, IOUT
and T
,
VOUT + 0.5V ≤ VIN ≤ 5.5V;
10mA ≤ IOUT ≤ 1A
±0.5
ΔVOUT%/ΔVIN
ΔVOUT%/ΔIOUT
Line regulation(1)
VOUT(nom) + 0.5V ≤ VIN ≤ 5.5V
1mA ≤ IOUT ≤ 1A
0.01
0.002
%/V
Load regulation
%/mA
10mA ≤ IOUT ≤ 1A
0.0005
Dropout voltage(5)
(VIN = VOUT(nom) – 0.1V)
VDO
IOUT = 1A
130
500
2.2
mV
ZO(DO)
ICL
Output impedance in dropout
Output current limit
2.2V ≤ VIN ≤ VOUT + VDO
VOUT = 0.9 × VOUT(nom)
VOUT = 0V
0.25
1.6
450
0.1
400
1300
20
Ω
A
1.05
ISC
Short-circuit current
Reverse leakage current(6) (–IIN
mA
µA
IREV
)
VEN ≤ 0.5V, 0V ≤ VIN ≤ VOUT
IOUT = 10mA (IQ)
IOUT = 1A
IGND
GND pin current
µA
ISHDN
IFB
Shutdown current (IGND
)
VEN ≤ 0.5V, VOUT ≤ VIN ≤ 5.5
nA
FB pin current (TPS73701)
0.1
58
0.6
µA
f = 100Hz, IOUT = 1A
f = 10kHz, IOUT = 1A
Power-supply rejection ratio
(ripple rejection)
PSRR
VN
dB
37
Output noise voltage
BW = 10Hz – 100KHz
COUT = 10µF
27 × VOUT
600
µVRMS
tSTR
Startup time
VOUT = 3V, RL = 30Ω, COUT = 1µF
µs
V
VEN(HI)
VEN(LO)
IEN(HI)
EN pin high (enabled)
EN pin low (shutdown)
EN pin current (enabled)
1.7
0
VIN
0.5
V
VEN = 5.5V
20
+160
+140
nA
Shutdown, temperature increasing
Reset, temperature decreasing
TSD
TJ
Thermal shutdown temperature
Operating junction temperature
°C
°C
–40
+125
(1) Minimum VIN = VOUT + VDO or 2.2V, whichever is greater.
(2) For VOUT(nom) < 1.6V, when VIN ≤ 1.6V, the output will lock to VIN and may result in an over-voltage condition on the output. To avoid this
situation, disable the device before powering down VIN
.
(3) TPS73701 is tested at VOUT = 1.2V.
(4) Tolerance of external resistors not included in this specification.
(5) VDO is not measured for fixed output versions with VOUT(nom) < 2.3V since minimum VIN = 2.2V.
(6) Fixed-voltage versions only; refer to the Applications section for more information.
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TPS737xx
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FUNCTIONAL BLOCK DIAGRAMS
IN
4MHz
Charge Pump
EN
Thermal
Protection
Ref
Servo
Ω
27k
Bandgap
Error
Amp
Current
Limit
OUT
Ω
8k
GND
R1
R2
Ω
R1 + R2 = 80k
NR
Figure 1. Fixed Voltage Version
IN
Table 1. Standard 1%
Resistor Values for
Common Output Voltages
V
O
R
1
R
2
4MHz
1.2V
1.5V
1.8V
2.5V
2.8V
3.0V
3.3V
Short
Open
Charge Pump
23.2kΩ
28.0kΩ
39.2kΩ
44.2kΩ
46.4kΩ
52.3kΩ
95.3kΩ
56.2kΩ
36.5kΩ
33.2kΩ
30.9kΩ
30.1kΩ
EN
Thermal
Protection
Ref
Servo
Ω
27k
Bandgap
Error
Amp
NOTE: V
= (R + R )/R × 1.204;
1 2 2
OUT
OUT
FB
Current
Limit
R
R
19kΩ for best
1
2
accuracy.
GND
Ω
80k
Ω
8k
R1
R2
Figure 2. Adjustable Voltage Version
4
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TPS737xx
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PIN CONFIGURATIONS
DCQ PACKAGE
DRB PACKAGE
SOT223-6
3mm x 3mm SON
(TOP VIEW)
(TOP VIEW)
OUT
N/C
1
2
3
4
8
7
6
5
IN
6
3
TAB IS GND
N/C
N/C
EN
NR/FB
GND
1
2
4
5
IN
GND
EN
OUT NR/FB
Table 1. Pin Descriptions
SOT223
(DCQ)
3×3 SON
(DRB)
PIN
NAME
PIN NO.
PIN NO. DESCRIPTION
IN
1
8
Unregulated input supply
Ground
GND
3, 6
4, Pad
Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into
shutdown mode. Refer to the Shutdown section under Applications Information for more details. EN
must not be left floating and can be connected to IN if not used.
EN
5
5
Fixed voltage versions only—connecting an external capacitor to this pin bypasses noise generated
by the internal bandgap, reducing output noise to very low levels.
NR
FB
4
4
3
3
Adjustable voltage version only—this is the input to the control loop error amplifier, and is used to set
the output voltage of the device.
OUT
NC
2
1
Regulator output. A 1.0µF or larger capacitor of any type is required for stability.
—
2, 6, 7
Not connected
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TYPICAL CHARACTERISTICS
For all voltage versions at TJ = +25°C, VIN = VOUT(nom) + 1.0V, IOUT = 10mA, VEN = 2.2V, and COUT = 2.2µF, unless otherwise
noted.
LOAD REGULATION
LINE REGULATION
0.5
0.4
0.20
0.15
0.10
0.05
0
Referred to IOUT = 10mA
Referred to VIN = VOUT + 1.0V at IOUT = 10mA
-40°C
+25°C
+125°C
0.3
0.2
+25°C
+125°C
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.05
-0.10
-0.15
-0.20
-40°C
0
100 200 300 400 500 600 700 800 900 1000
IOUT (mA)
0
0.5
1.0
1.5
2.0
2.5
3.0 3.5
4.0
4.5
V
IN - VOUT (V)
Figure 3.
Figure 4.
DROPOUT VOLTAGE vs TEMPERATURE
DROPOUT VOLTAGE vs OUTPUT CURRENT
200
180
160
140
120
100
80
200
180
160
140
120
100
80
VOUT = 2.5V
+125°C
+25°C
60
60
-40°C
40
40
20
20
0
0
0
100 200 300 400 500 600 700 800 900 1000
IOUT (mA)
-50
-25
0
25
50
75
100
125
150
Temperature (°C)
Figure 5.
OUTPUT VOLTAGE HISTOGRAM
IOUT = 10mA
Figure 6.
DROPOUT VOLTAGE DRIFT HISTOGRAM
30
25
20
15
10
5
18
16
14
12
10
8
IOUT = 10mA
6
4
2
0
0
VOUT Error (%)
Worst Case dVOUT/dT (ppm/°C)
Figure 7.
Figure 8.
6
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TPS737xx
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TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ = +25°C, VIN = VOUT(nom) + 1.0V, IOUT = 10mA, VEN = 2.2V, and COUT = 2.2µF, unless otherwise
noted.
GROUND PIN CURRENT vs OUTPUT CURRENT
GROUND PIN CURRENT vs TEMPERATURE
3000
2500
2000
1500
1000
500
2500
2000
1500
1000
500
IOUT = 1A
VIN = 5.0V
VIN = 5.0V
VIN = 3.3V
VIN = 3.3V
VIN = 2.2V
VIN = 2.2V
0
0
-50
-25
0
25
50
75
100
125
0
200
400
600
800
1000
Temperature (°C)
IOUT (mA)
Figure 9.
Figure 10.
GROUND PIN CURRENT IN SHUTDOWN
vs TEMPERATURE
CURRENT LIMIT vs VOUT
(FOLDBACK)
1
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
VENABLE = 0.5V
VIN = VOUT + 0.5V
ICL
0.1
ISC
VOUT = 3.3V
0.5
0.01
-50
-25
0
25
50
75
100
125
0
1.0
1.5
2.0
2.5
3.0
3.5
Temperature (°C)
VOUT (V)
Figure 11.
Figure 12.
CURRENT LIMIT vs TEMPERATURE
CURRENT LIMIT vs VIN
2.0
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
VOUT = 1.2V
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-50
-25
0
25
50
75
100
125
VIN (V)
Temperature (°C)
Figure 13.
Figure 14.
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TPS737xx
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TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ = +25°C, VIN = VOUT(nom) + 1.0V, IOUT = 10mA, VEN = 2.2V, and COUT = 2.2µF, unless otherwise
noted.
PSRR (RIPPLE REJECTION) vs FREQUENCY
PSRR (RIPPLE REJECTION) vs VIN – VOUT
90
80
70
60
50
40
30
20
10
0
40
35
30
25
20
15
10
5
IOUT = 100mA
COUT = Any
IOUT = 1mA
COUT = 1mF
IOUT = 1mA
COUT = 10mF
IO = 100mA
CO = 1mF
IOUT = 1mA
COUT = Any
Frequency = 10kHz
COUT = 10mF
IOUT = 100mA
COUT = 10mF
VOUT = 2.5V
IOUT = 100mA
0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
10
100
1k
10k
100k
1M
10M
V
IN - VOUT (V)
Frequency (Hz)
Figure 15.
Figure 16.
TPS73701
RMS NOISE VOLTAGE vs CFB
NOISE SPECTRAL DENSITY
1
60
55
50
45
40
35
30
25
20
COUT = 1mF
0.1
COUT = 10mF
VOUT = 2.5V
COUT = 0mF
R1 = 39.2kW
IOUT = 150mA
10Hz < Frequency < 100kHz
0.01
10
100
1k
10k
100k
10p
100p
1n
10n
CFB (F)
Frequency (Hz)
Figure 17.
Figure 18.
RMS NOISE VOLTAGE vs CNR
RMS NOISE VOLTAGE vs COUT
60
50
40
30
20
10
0
140
120
100
80
VOUT = 5.0V
VOUT = 5.0V
VOUT = 3.3V
VOUT = 3.3V
VOUT = 1.5V
60
40
VOUT = 1.5V
20
CNR = 0.01mF
COUT = 0mF
10Hz < Frequency < 100kHz
10Hz < Frequency < 100kHz
0
0.1
1
10
1p
10p
100p
1n
10n
COUT (mF)
CNR (F)
Figure 19.
Figure 20.
8
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TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ = +25°C, VIN = VOUT(nom) + 1.0V, IOUT = 10mA, VEN = 2.2V, and COUT = 2.2µF, unless otherwise
noted.
TPS73733
LOAD TRANSIENT RESPONSE
TPS73733
LINE TRANSIENT RESPONSE
CNR = 10nF
CNR = 10nF
COUT = 10mF
VOUT
200mV/div
COUT = 10mF
100mV/div
VOUT
1A
5.3V
10mA
4.3V
IOUT
VIN
10ms/div
10ms/div
Figure 21.
Figure 22.
TPS73701
TURN-ON RESPONSE
TPS73701
TURN-OFF RESPONSE
RL = 20W
COUT = 10mF
VOUT
RL = 20W
RL = 20W
COUT = 1mF
1V/div
1V/div
COUT = 1mF
RL = 20W
COUT = 10mF
VOUT
2V
2V
VEN
1V/div
1V/div
0V
0V
VEN
100ms/div
100ms/div
Figure 23.
Figure 24.
TPS73701, VOUT = 3.3V
POWER-UP/POWER-DOWN
IENABLE vs TEMPERATURE
6
5
10
1
VIN
4
VOUT
3
2
1
0.1
0.01
0
-1
-2
50ms/div
-50
-25
0
25
50
75
100
125
Temperature (°C)
Figure 25.
Figure 26.
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TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ = +25°C, VIN = VOUT(nom) + 1.0V, IOUT = 10mA, VEN = 2.2V, and COUT = 2.2µF, unless otherwise
noted.
TPS73701
RMS NOISE VOLTAGE vs CFB
TPS73701
IFB vs TEMPERATURE
160
140
120
100
80
60
55
50
45
40
35
30
25
20
60
VOUT = 2.5V
40
COUT = 0mF
R1 = 39.2kW
20
10Hz < Frequency < 100kHz
0
-50
-25
0
25
50
75
100
125
10p
100p
1n
10n
Temperature (°C)
CFB (F)
Figure 27.
Figure 28.
TPS73701
TPS73701
LOAD TRANSIENT, ADJUSTABLE VERSION
LINE TRANSIENT, ADJUSTABLE VERSION
VOUT = 2.5V
CFB = 10nF
CFB = 10nF
R1 = 39.2kW
COUT = 10mF
COUT = 10mF
VOUT
VOUT
100mV/div
100mV/div
4.5V
250mA
3.5V
IOUT
VIN
10mA
10ms/div
5ms/div
Figure 29.
Figure 30.
10
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APPLICATION INFORMATION
in addition to the internal 8kΩ resistor, presents the
The TPS737xx belongs to a family of new generation
same impedance to the error amp as the 27kΩ
LDO regulators that use an NMOS pass transistor to
bandgap reference output. This impedance helps
achieve ultra-low-dropout performance, reverse
compensate for leakages into the error amp
current blockage, and freedom from output capacitor
terminals.
constraints. These features combined with an enable
input make the TPS737xx ideal for portable
INPUT AND OUTPUT CAPACITOR
applications. This regulator family offers a wide
REQUIREMENTS
selection of fixed output voltage versions and an
adjustable output version. All versions have thermal
and over-current protection, including foldback
current limit.
Although an input capacitor is not required for stability
if input impedance is very low, it is good analog
design practice to connect a 0.1µF to 1µF low
equivalent series resistance (ESR) capacitor across
the input supply near the regulator. This capacitor
counteracts reactive input sources and improves
transient response, noise rejection, and ripple
rejection. A higher-value capacitor may be necessary
if large, fast rise-time load transients are anticipated
or the device is located several inches from the
power source.
Figure 31 shows the basic circuit connections for the
fixed voltage models. Figure 32 gives the connections
for the adjustable output version (TPS73701).
VIN
VOUT
IN
OUT
TPS737xx
EN
GND
The TPS737xx requires a 1.0µF output capacitor for
stability. It is designed to be stable for all available
types and values of capacitors. In applications where
multiple low ESR capacitors are in parallel, ringing
may occur when the product of COUT and total ESR
drops below 50nΩF. Total ESR includes all parasitic
resistances, including capacitor ESR and board,
socket, and solder joint resistance. In most
applications, the sum of capacitor ESR and trace
resistance will meet this requirement.
ON
OFF
Figure 31. Typical Application Circuit for
Fixed-Voltage Versions
Optional input capacitor.
May improve source
Output capacitor
impedance, noise, or PSRR.
must be ³ 1.0mF.
VIN
VOUT
IN
OUT
TPS73701
OUTPUT NOISE
R1
R2
CFB
A precision bandgap reference is used to generate
the internal reference voltage, VREF. This reference is
the dominant noise source within the TPS737xx and
it generates approximately 32µVRMS (10Hz to
100kHz) at the reference output (NR). The regulator
control loop gains up the reference noise with the
same gain as the reference voltage, so that the noise
voltage of the regulator is approximately given by:
EN
GND
FB
ON
OFF
Optional capacitor
reduces output noise
and improves
(R1 + R2)
R2
VOUT
=
x 1.204
transient response.
Figure 32. Typical Application Circuit for
Adjustable-Voltage Version
(
)
VOUT
VREF
R1 ) R2
VN + 32mVRMS
+ 32mVRMS
R2
(1)
Since the value of VREF is 1.2V, this relationship
reduces to:
R1 and R2 can be calculated for any output voltage
using the formula shown in Figure 32. Sample
resistor values for common output voltages are
shown in Figure 2.
mVRMS
V
ǒ
Ǔ
+ 27ǒ Ǔ
( )
V
VN mVRMS
VOUT
(2)
For best accuracy, make the parallel combination of
R1 and R2 approximately equal to 19kΩ. This 19kΩ,
for the case of no CNR
.
Copyright © 2006–2009, Texas Instruments Incorporated
Submit Documentation Feedback
11
TPS737xx
SBVS067I–JANUARY 2006–REVISED MARCH 2009.................................................................................................................................................... www.ti.com
An internal 27kΩ resistor in series with the noise
reduction pin (NR) forms a low-pass filter for the
voltage reference when an external noise reduction
capacitor, CNR, is connected from NR to ground. For
CNR = 10nF, the total noise in the 10Hz to 100kHz
bandwidth is reduced by a factor of ~3.2, giving the
approximate relationship:
When shutdown capability is not required, EN can be
connected to VIN. However, the pass gate may not be
discharged using this configuration, and the pass
transistor may be left on (enhanced) for a significant
time after VIN has been removed. This scenario can
result in reverse current flow (if the IN pin is low
impedance) and faster ramp times upon power-up. In
addition, for VIN ramp times slower than a few
milliseconds, the output may overshoot upon
power-up.
mVRMS
VN(mVRMS) = 8.5
x VOUT(V)
V
(3)
for CNR = 10nF.
DROPOUT VOLTAGE
This noise reduction effect is shown as RMS Noise
Voltage vs CNR in the Typical Characteristics section.
The TPS737xx uses an NMOS pass transistor to
achieve extremely low dropout. When (VIN – VOUT) is
less than the dropout voltage (VDO), the NMOS pass
device is in its linear region of operation and the
input-to-output resistance is the RDS, ON of the NMOS
pass element.
The TPS73701 adjustable version does not have the
NR pin available. However, connecting a feedback
capacitor, CFB, from the output to the feedback pin
(FB) reduces output noise and improve load transient
performance. This capacitor should be limited to
0.1µF.
For large step changes in load current, the TPS737xx
requires a larger voltage drop from VIN to VOUT to
avoid degraded transient response. The boundary of
this transient dropout region is approximately twice
the dc dropout. Values of VIN – VOUT above this line
ensure normal transient response.
The TPS737xx uses an internal charge pump to
develop an internal supply voltage sufficient to drive
the gate of the NMOS pass element above VOUT. The
charge pump generates ~250µV of switching noise at
~4MHz; however, charge-pump noise contribution is
negligible at the output of the regulator for most
Operating in the transient dropout region can cause
an increase in recovery time. The time required to
recover from a load transient is a function of the
magnitude of the change in load current rate, the rate
of change in load current, and the available
headroom (VIN to VOUT voltage drop). Under
worst-case conditions [full-scale instantaneous load
change with (VIN – VOUT) close to dc dropout levels],
values of IOUT and COUT
.
BOARD LAYOUT RECOMMENDATION TO
IMPROVE PSRR AND NOISE PERFORMANCE
To improve ac performance such as PSRR, output
noise, and transient response, it is recommended that
the printed circuit board (PCB) be designed with
separate ground planes for VIN and VOUT, with each
ground plane connected only at the GND pin of the
device. In addition, the ground connection for the
bypass capacitor should connect directly to the GND
pin of the device.
the TPS737xx can take
microseconds to return to the specified regulation
accuracy.
a couple of hundred
TRANSIENT RESPONSE
The low open-loop output impedance provided by the
NMOS pass element in
a
voltage follower
INTERNAL CURRENT LIMIT
configuration allows operation without a 1.0µF output
capacitor. As with any regulator, the addition of
additional capacitance from the OUT pin to ground
reduces undershoot magnitude but increases its
duration. In the adjustable version, the addition of a
capacitor, CFB, from the OUT pin to the FB pin will
also improve the transient response.
The TPS737xx internal current limit helps protect the
regulator during fault conditions. Foldback current
limit helps to protect the regulator from damage
during output short-circuit conditions by reducing
current limit when VOUT drops below 0.5V. See
Figure 12 in the Typical Characteristicssection.
ENABLE PIN AND SHUTDOWN
The enable pin (EN) is active high and is compatible
with standard TTL-CMOS levels. A VEN below 0.5V
(max) turns the regulator off and drops the GND pin
current to approximately 10nA. When EN is used to
shutdown the regulator, all charge is removed from
the pass transistor gate, and the output ramps back
up to a regulated VOUT (see Figure 23).
12
Submit Documentation Feedback
Copyright © 2006–2009, Texas Instruments Incorporated
TPS737xx
www.ti.com.................................................................................................................................................... SBVS067I–JANUARY 2006–REVISED MARCH 2009
The TPS737xx does not have active pull-down when
the output is over-voltage. This architecture allows
applications that connect higher voltage sources,
such as alternate power supplies, to the output. This
architecture also results in an output overshoot of
several percent if the load current quickly drops to
zero when a capacitor is connected to the output. The
duration of overshoot can be reduced by adding a
Any tendency to activate the thermal protection circuit
indicates excessive power dissipation or an
inadequate heatsink. For reliable operation, junction
temperature should be limited to +125°C maximum.
To estimate the margin of safety in a complete design
(including
heatsink),
increase
the
ambient
temperature until the thermal protection is triggered;
use worst-case loads and signal conditions. For good
reliability, thermal protection should trigger at least
+35°C above the maximum expected ambient
load resistor. The overshoot decays at
a rate
determined by output capacitor COUT and the
internal/external load resistance. The rate of decay is
given by:
condition of your application. This produces
worst-case junction temperature of +125°C at the
highest expected ambient temperature and
worst-case load.
a
(Fixed voltage version)
VOUT
dV
dT
+
The internal protection circuitry of the TPS737xx has
been designed to protect against overload conditions.
It was not intended to replace proper heatsinking.
Continuously running the TPS737xx into thermal
shutdown degrades device reliability.
COUT 80kW ø RLOAD
(4)
(5)
(Adjustable voltage version)
VOUT
dV
dT
+
(
)
COUT 80kW ø R1 ) R2 ø RLOAD
POWER DISSIPATION
REVERSE CURRENT
The ability to remove heat from the die is different for
each
package
type,
presenting
different
The NMOS pass element of the TPS737xx provides
inherent protection against current flow from the
output of the regulator to the input when the gate of
the pass device is pulled low. To ensure that all
charge is removed from the gate of the pass element,
the EN pin must be driven low before the input
voltage is removed. If this is not done, the pass
element may be left on because of stored charge on
the gate.
considerations in the PCB layout. The PCB area
around the device that is free of other components
moves the heat from the device to the ambient air.
Performance data for JEDEC low- and high-K boards
are shown in the Power Dissipation Ratings table.
Using heavier copper will increase the effectiveness
in removing heat from the device. The addition of
plated through-holes to heat-dissipating layers also
improves the heatsink effectiveness.
After the EN pin is driven low, no bias voltage is
needed on any pin for reverse current blocking. Note
that reverse current is specified as the current flowing
out of the IN pin because of voltage applied on the
OUT pin. There will be additional current flowing into
the OUT pin as a result of the 80kΩ internal resistor
divider to ground (see Figure 1 and Figure 2).
Power dissipation depends on input voltage and load
conditions. Power dissipation (PD) is equal to the
product of the output current times the voltage drop
across the output pass element (VIN to VOUT):
ǒ
Ǔ
PD + VIN * VOUT IOUT
(6)
Power dissipation can be minimized by using the
lowest possible input voltage necessary to assure the
required output voltage.
For the TPS73701, reverse current may flow when
VFB is more than 1.0V above VIN.
THERMAL PROTECTION
PACKAGE MOUNTING
Thermal protection disables the output when the
junction temperature rises to approximately +160°C,
allowing the device to cool. When the junction
temperature cools to approximately +140°C, the
output circuitry is again enabled. Depending on power
dissipation, thermal resistance, and ambient
temperature, the thermal protection circuit may cycle
on and off. This cycling limits the dissipation of the
regulator, protecting it from damage due to
overheating.
Solder pad footprint recommendations for the
TPS737xx are presented in Application Bulletin
Solder Pad Recommendations for Surface-Mount
Devices (SBFA015), available from the Texas
Instruments web site at www.ti.com.
Copyright © 2006–2009, Texas Instruments Incorporated
Submit Documentation Feedback
13
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jun-2009
PACKAGING INFORMATION
Orderable Device
TPS73701DCQ
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOT-223
DCQ
6
6
6
6
8
8
8
8
6
6
6
6
6
6
6
6
8
8
6
6
6
6
6
6
78 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS73701DCQG4
TPS73701DCQR
TPS73701DCQRG4
TPS73701DRBR
TPS73701DRBRG4
TPS73701DRBT
TPS73701DRBTG4
TPS73718DCQ
SOT-223
SOT-223
SOT-223
SON
DCQ
DCQ
DCQ
DRB
DRB
DRB
DRB
DCQ
DCQ
DCQ
DCQ
DCQ
DCQ
DCQ
DCQ
DRB
DRB
DCQ
DCQ
DCQ
DCQ
DCQ
DCQ
78 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SON
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SON
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SON
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SOT-223
SOT-223
SOT-223
SOT-223
SOT-223
SOT-223
SOT-223
SOT-223
SON
78 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS73718DCQG4
TPS73718DCQR
TPS73718DCQRG4
TPS73725DCQ
78 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
78 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS73725DCQG4
TPS73725DCQR
TPS73725DCQRG4
TPS73730DRBR
TPS73730DRBT
TPS73733DCQ
78 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SON
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SOT-223
SOT-223
SOT-223
SOT-223
SOT-223
SOT-223
78 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS73733DCQG4
TPS73733DCQR
TPS73733DCQRG4
TPS73734DCQ
78 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
78 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS73734DCQR
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jun-2009
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS73733 :
Automotive: TPS73733-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jun-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
TPS73701DCQR
TPS73701DRBR
TPS73701DRBT
TPS73718DCQR
TPS73725DCQR
TPS73730DRBR
TPS73730DRBT
TPS73733DCQR
TPS73734DCQR
SOT-223 DCQ
6
8
8
6
6
8
8
6
6
2500
3000
250
330.0
330.0
180.0
330.0
330.0
330.0
180.0
330.0
330.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
6.8
3.3
3.3
6.8
6.8
3.3
3.3
6.8
6.8
7.3
3.3
3.3
7.3
7.3
3.3
3.3
7.3
7.3
1.88
1.1
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q3
Q2
Q2
Q3
Q3
Q2
Q2
Q3
Q3
SON
SON
DRB
DRB
1.1
SOT-223 DCQ
SOT-223 DCQ
2500
2500
3000
250
1.88
1.88
1.1
SON
SON
DRB
DRB
1.1
SOT-223 DCQ
SOT-223 DCQ
2500
2500
1.88
1.88
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jun-2009
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS73701DCQR
TPS73701DRBR
TPS73701DRBT
TPS73718DCQR
TPS73725DCQR
TPS73730DRBR
TPS73730DRBT
TPS73733DCQR
TPS73734DCQR
SOT-223
SON
DCQ
DRB
DRB
DCQ
DCQ
DRB
DRB
DCQ
DCQ
6
8
8
6
6
8
8
6
6
2500
3000
250
358.0
346.0
190.5
358.0
358.0
346.0
190.5
358.0
358.0
335.0
346.0
212.7
335.0
335.0
346.0
212.7
335.0
335.0
35.0
29.0
31.8
35.0
35.0
29.0
31.8
35.0
35.0
SON
SOT-223
SOT-223
SON
2500
2500
3000
250
SON
SOT-223
SOT-223
2500
2500
Pack Materials-Page 2
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