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TPS75301QPWPR [TI]

FAST-TRANSIENT-RESPONSE 1.5-A LOW-DROPOUT VOLTAGE REGULATORS; 快速瞬态响应1.5 -A低压差稳压器
TPS75301QPWPR
型号： TPS75301QPWPR
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

FAST-TRANSIENT-RESPONSE 1.5-A LOW-DROPOUT VOLTAGE REGULATORS
快速瞬态响应1.5 -A低压差稳压器

线性稳压器IC 调节器 电源电路 光电二极管 输出元件
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TPS75101Q, TPS75115Q, TPS75118Q, TPS75125Q, TPS75133Q WITH POWER GOOD  
TPS75301Q, TPS75315Q, TPS75318Q, TPS75325Q, TPS75333Q WITH RESET  
FAST-TRANSIENT-RESPONSE 1.5-A LOW-DROPOUT VOLTAGE REGULATORS  
SLVS241B – MARCH 2000 – REVISED JUNE 2003  
PWP PACKAGE  
(TOP VIEW)  
1.5-A Low-Dropout Voltage Regulator  
Available in 1.5-V, 1.8-V, 2.5-V, 3.3-V, Fixed  
Output and Adjustable Versions  
GND/HEATSINK  
GND/HEATSINK  
NC  
NC  
GND  
NC  
NC  
NC  
NC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
NC  
IN  
IN  
Open Drain Power-Good (PG) Status  
Output (TPS751xxQ)  
Open Drain Power-On Reset With 100-ms  
Delay (TPS753xxQ)  
EN  
†
PG or RESET  
Dropout Voltage Typically 160 mV at 1.5 A  
(TPS75133Q)  
FB/SENSE  
OUTPUT  
OUTPUT  
Ultralow 75 µA Typical Quiescent Current  
NC  
GND/HEATSINK  
GND/HEATSINK  
Fast Transient Response  
2% Tolerance Over Specified Conditions  
For Fixed-Output Versions  
NC – No internal connection  
PG is on the TPS751xx and RESET is on the TPS753xx  
†
20-Pin TSSOP (PWP) PowerPAD Package  
Thermal Shutdown Protection  
description  
The TPS753xxQ and TPS751xxQ are low dropout regulators with integrated power-on reset and power-good  
(PG) functions respectively. These devices are capable of supplying 1.5 A of output current with a dropout of  
160 mV (TPS75133Q, TPS75333Q). Quiescent current is 75 µA at full load and drops down to 1 µA when the  
device is disabled. TPS751xxQ and TPS753xxQ are designed to have fast transient response for larger load  
current changes.  
TPS75x33Q  
DROPOUT VOLTAGE  
TPS75x15Q  
vs  
JUNCTION TEMPERATURE  
LOAD TRANSIENT RESPONSE  
300  
250  
I =1.5 A  
L
C =100 µF (Tantalum)  
L
O
50  
0
V
=1.5 V  
200  
I
= 1.5 A  
O
–50  
–100  
–150  
1.5  
150  
100  
I
O
= 0.5 A  
50  
0
0
–40  
10  
60  
110  
160  
0
1
2
3
4
5
6
7
8
9
10  
T
J
– Junction Temperature – °C  
t – Time – ms  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PowerPAD is a trademark of Texas Instruments.  
Copyright 2000 – 2003, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
TPS75101Q, TPS75115Q, TPS75118Q, TPS75125Q, TPS75133Q WITH POWER GOOD  
TPS75301Q, TPS75315Q, TPS75318Q, TPS75325Q, TPS75333Q WITH RESET  
FAST-TRANSIENT-RESPONSE 1.5-A LOW-DROPOUT VOLTAGE REGULATORS  
SLVS241B – MARCH 2000 – REVISED JUNE 2003  
description (continued)  
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 160 mV  
at an output current of 1.5 A for the TPS75x33Q) and is directly proportional to the output current. Additionally,  
since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent  
of output loading (typically 75 µA over the full range of output current, 1 mA to 1.5 A). These two key  
specifications yield a significant improvement in operating life for battery-powered systems.  
The device is enabled when EN is connected to a low level voltage. This LDO family also features a sleep mode;  
applying a TTL high signal to EN (enable) shuts down the regulator, reducing the quiescent current to less than  
1 µA at T = 25°C.  
J
For the TPS751xxQ, the power-good terminal (PG) is an active high, open drain output, which can be used to  
implement a power-on reset or a low-battery indicator.  
The RESET (SVS, POR, or power on reset) output of the TPS753xxQ initiates a reset in microcomputer and  
microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS753xxQ  
monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage.  
When the output reaches 95% of its regulated voltage, RESET goes to a high-impedance state after a 100-ms  
delay. RESET goes to a logic-low state when the regulated output voltage is pulled below 95% (i.e., over load  
condition) of its regulated voltage.  
The TPS751xxQ or TPS753xxQ is offered in 1.5-V, 1.8-V, 2.5-V and 3.3-V fixed-voltage versions and in an  
adjustable version (programmable over the range of 1.5 V to 5 V). Output voltage tolerance is specified as a  
maximum of 2% over line, load, and temperature ranges. The TPS751xxQ and TPS753xxQ families are  
available in 20-pin TSSOP (PWP) packages.  
AVAILABLE OPTIONS  
TSSOP (PWP)  
OUTPUT VOLTAGE  
(TYP)  
T
J
PG  
RESET  
3.3 V  
TPS75133QPWP  
TPS75125QPWP  
TPS75118QPWP  
TPS75115QPWP  
TPS75101QPWP  
TPS75333QPWP  
TPS75325QPWP  
TPS75318QPWP  
TPS75315QPWP  
TPS75301QPWP  
2.5 V  
1.8 V  
–40°C to 125°C  
1.5 V  
Adjustable 1.5 V to 5 V  
NOTE: The TPS75x01 is programmable using an external resistor divider (see application  
information). The PWP package is available taped and reeled. Add an R suffix to the  
device type (e.g., TPS75201QPWPR) to indicate tape and reel.  
3
4
6
7
8
9
PG or  
RESET  
V
IN  
IN  
PG or RESET Output  
I
SENSE  
OUT  
V
O
5
0.22 µF  
EN  
OUT  
†
C
O
+
47 µF  
GND  
17  
†
See application information section for capacitor selection details.  
Figure 1. Typical Application Configuration (For Fixed Output Options)  
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
TPS75101Q, TPS75115Q, TPS75118Q, TPS75125Q, TPS75133Q WITH POWER GOOD  
TPS75301Q, TPS75315Q, TPS75318Q, TPS75325Q, TPS75333Q WITH RESET  
FAST-TRANSIENT-RESPONSE 1.5-A LOW-DROPOUT VOLTAGE REGULATORS  
SLVS241B – MARCH 2000 – REVISED JUNE 2003  
functional block diagram—adjustable version  
IN  
EN  
PG or RESET  
_
+
OUT  
+
_
100 ms Delay  
(for RESET Option)  
R1  
R2  
V
ref  
= 1.1834 V  
FB  
GND  
External to the device  
functional block diagram—fixed-voltage version  
IN  
EN  
PG or RESET  
_
+
OUT  
SENSE  
+
_
100 ms Delay  
(for RESET Option)  
R1  
R2  
V
ref  
= 1.1834 V  
GND  
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
TPS75101Q, TPS75115Q, TPS75118Q, TPS75125Q, TPS75133Q WITH POWER GOOD  
TPS75301Q, TPS75315Q, TPS75318Q, TPS75325Q, TPS75333Q WITH RESET  
FAST-TRANSIENT-RESPONSE 1.5-A LOW-DROPOUT VOLTAGE REGULATORS  
SLVS241B – MARCH 2000 – REVISED JUNE 2003  
Terminal Functions (TPS751xxQ)  
TERMINAL  
I/O  
DESCRIPTION  
NAME  
NO.  
EN  
5
I
I
Enable Input  
FB/SENSE  
7
17  
Feedback input voltage for adjustable device (sense input for fixed options)  
GND  
Regulator Ground  
Ground/heatsink  
Input voltage  
GND/HEATSINK  
1, 10, 11, 20  
3, 4  
IN  
I
NC  
2, 12, 13, 14,  
15, 16, 18, 19  
No connection  
OUTPUT  
PG  
8, 9  
6
O
O
Regulated output voltage  
Power good output  
Terminal Functions (TPS753xxQ)  
TERMINAL  
I/O  
DESCRIPTION  
NAME  
NO.  
EN  
5
I
I
Enable Input  
FB/SENSE  
7
17  
Feedback input voltage for adjustable device (sense input for fixed options)  
GND  
Regulator Ground  
Ground/heatsink  
Input voltage  
GND/HEATSINK  
1, 10, 11, 20  
3, 4  
IN  
I
NC  
2, 12, 13, 14,  
15, 16, 18, 19  
No connection  
OUTPUT  
RESET  
8, 9  
6
O
O
Regulated output voltage  
Reset output  
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
TPS75101Q, TPS75115Q, TPS75118Q, TPS75125Q, TPS75133Q WITH POWER GOOD  
TPS75301Q, TPS75315Q, TPS75318Q, TPS75325Q, TPS75333Q WITH RESET  
FAST-TRANSIENT-RESPONSE 1.5-A LOW-DROPOUT VOLTAGE REGULATORS  
SLVS241B – MARCH 2000 – REVISED JUNE 2003  
TPS753xxQ RESET timing diagram  
V
I
V
V
res  
res  
(see Note A)  
t
V
O
V
IT+  
(see Note B)  
V
IT+  
(see Note B)  
Threshold  
Voltage  
Less than 5% of the  
output voltage  
V
IT–  
(see Note B)  
V
IT–  
(see Note B)  
t
RESET  
Output  
100 ms  
Delay  
100 ms  
Delay  
Output  
Undefined  
Output  
Undefined  
t
NOTES: A.  
V
is the minimum input voltage for a valid RESET. The symbol V is not currently listed within EIA or JEDEC  
res  
res  
standards for semiconductor symbology.  
B. VIT –Trip voltage is typically 5% lower than the output voltage (95%V ) V  
to V  
is the hysteresis voltage.  
IT+  
O
IT–  
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
TPS75101Q, TPS75115Q, TPS75118Q, TPS75125Q, TPS75133Q WITH POWER GOOD  
TPS75301Q, TPS75315Q, TPS75318Q, TPS75325Q, TPS75333Q WITH RESET  
FAST-TRANSIENT-RESPONSE 1.5-A LOW-DROPOUT VOLTAGE REGULATORS  
SLVS241B – MARCH 2000 – REVISED JUNE 2003  
TPS751xxQ PG timing diagram  
V
I
V
V
PG  
PG  
(see Note A)  
t
V
O
V (see Note B)  
IT+  
V (see Note B)  
IT+  
Threshold  
Voltage  
V (see Note B)  
IT–  
V (see Note B)  
IT–  
t
PG  
Output  
Output  
Undefined  
Output  
Undefined  
t
NOTES: A.  
V
is the minimum input voltage for a valid PG. The symbol V  
is not currently listed within EIA or JEDEC standards for  
PG  
semiconductor symbology.  
PG  
B. VIT –Trip voltage is typically 17% lower than the output voltage (83%V ) V  
to V  
is the hysteresis voltage.  
IT+  
O
IT–  
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
TPS75101Q, TPS75115Q, TPS75118Q, TPS75125Q, TPS75133Q WITH POWER GOOD  
TPS75301Q, TPS75315Q, TPS75318Q, TPS75325Q, TPS75333Q WITH RESET  
FAST-TRANSIENT-RESPONSE 1.5-A LOW-DROPOUT VOLTAGE REGULATORS  
SLVS241B – MARCH 2000 – REVISED JUNE 2003  
absolute maximum ratings over operating junction temperature range (unless otherwise noted)  
‡
Input voltage range , V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6.0 V  
I
Voltage range at EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 16.5 V  
Maximum PG voltage (TPS751xxQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5 V  
Maximum RESET voltage (TPS753xxQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5 V  
Peak output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited  
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See dissipation rating tables  
Output voltage, V (OUTPUT, FB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V  
O
Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C  
J
Storage temperature range, T  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C  
stg  
ESD rating, HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV  
†
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
All voltage values are with respect to network terminal ground.  
DISSIPATION RATING TABLE 1 – FREE-AIR TEMPERATURES  
AIR FLOW  
(CFM)  
T
< 25°C  
DERATING FACTOR  
T
= 70°C  
T = 85°C  
A
A
A
PACKAGE  
POWER RATING  
ABOVE T = 25°C  
POWER RATING POWER RATING  
A
0
2.9 W  
23.5 mW/°C  
34.6 mW/°C  
23.8 mW/°C  
57.9 mW/°C  
1.9 W  
2.8 W  
1.9 W  
4.6 W  
1.5 W  
2.2 W  
1.5 W  
3.8 W  
§
PWP  
PWP  
300  
0
4.3 W  
3 W  
300  
7.2 W  
§
This parameter is measured with the recommended copper heat sink pattern on a 1-layer PCB, 5-in × 5-in PCB, 1 oz. copper,  
2-in × 2-in coverage (4 in ).  
This parameter is measured with the recommended copper heat sink pattern on a 8-layer PCB, 1.5-in × 2-in PCB, 1 oz. copper  
2
2
2
with layers 1, 2, 4, 5, 7, and 8 at 5% coverage (0.9 in ) and layers 3 and 6 at 100% coverage (6 in ). For more information, refer  
to TI technical brief SLMA002.  
recommended operating conditions  
MIN  
2.7  
1.5  
0
MAX  
5.5  
5
UNIT  
V
#
Input voltage, V  
I
Output voltage range, V  
V
O
Output current, I  
1.5  
125  
A
O
Operating virtual junction temperature, T  
–40  
°C  
J
#
To calculate the minimum input voltage for your maximum output current, use the following equation: V  
= V  
+ V  
.
DO(max load)  
I(min)  
O(max)  
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
TPS75101Q, TPS75115Q, TPS75118Q, TPS75125Q, TPS75133Q WITH POWER GOOD  
TPS75301Q, TPS75315Q, TPS75318Q, TPS75325Q, TPS75333Q WITH RESET  
FAST-TRANSIENT-RESPONSE 1.5-A LOW-DROPOUT VOLTAGE REGULATORS  
SLVS241B – MARCH 2000 – REVISED JUNE 2003  
electrical characteristics over recommended operating junction temperature range (T = –40°C to  
J
125°C), V = V  
+ 1 V, I = 1 mA, EN = 0 V, C = 47 µF (unless otherwise noted)  
I
O(typ)  
O
o
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
1.5 V ≤ V ≤ 5.5 V,  
T = 25°C  
J
V
O
Adjustable  
Voltage  
O
1.5 V ≤ V ≤ 5.5 V  
0.98 V  
1.02 V  
O
O
O
T = 25°C,  
2.7 V < V < 5.5 V  
IN  
1.5  
1.8  
2.5  
3.3  
75  
J
1.5 V Output  
1.8 V Output  
2.5 V Output  
3.3 V Output  
2.7 V < V < 5.5 V  
IN  
1.470  
1.530  
T = 25°C,  
J
2.8 V < V < 5.5 V  
IN  
Output voltage  
(see Notes 1 and 3)  
V
2.8 V < V < 5.5 V  
IN  
1.764  
2.450  
3.234  
1.836  
2.550  
3.366  
125  
T = 25°C,  
J
3.5 V < V < 5.5 V  
IN  
3.5 V < V < 5.5 V  
IN  
T = 25°C,  
J
4.3 V < V < 5.5 V  
IN  
4.3 V < V < 5.5 V  
IN  
T = 25°C,  
J
See Note 3  
Quiescent current (GND current) (see Note 2)  
µA  
See Note 3  
Output voltage line regulation (∆V /V  
(see Notes 1 and 2)  
O
O
)
)
V
+ 1 V < V ≤ 5.5 V, T = 25°C  
0.01  
O
O
I
J
%/V  
Output voltage line regulation (∆V /V  
(see Notes 1 and 2)  
O
O
V
+ 1 V < V < 5.5 V  
0.1  
4.5  
I
Load regulation (see Note 3)  
1
mV  
BW = 300 Hz to 50 kHz, V = 1.5 V  
O
Output noise voltage  
60  
µVrms  
C
= 100 µF,  
T = 25°C  
J
O
Output current Limit  
V
O
= 0 V  
3.3  
150  
1
A
°C  
µA  
µA  
µA  
V
Thermal shutdown junction temperature  
Standby current  
EN = V  
EN = V  
T = 25°C,  
J
I,  
I
10  
1
FB input current  
TPS75x01Q  
FB = 1.5 V  
–1  
High level enable input voltage  
Low level enable input voltage  
2
0.7  
V
f = 100 Hz,  
T = 25°C,  
J
C
= 100 µF,  
O
Power supply ripple rejection (see Note 2)  
63  
1
dB  
V
See Note 1, I = 1.5 A  
O
Minimum input voltage for valid  
PG  
I
= 300µA,  
V
(PG)  
≤ 0.8 V  
1.3  
86  
O(PG)  
Trip threshold voltage  
PG  
V
O
decreasing  
80  
%V  
%V  
V
O
(TPS751xxQ)  
Hysteresis voltage  
Output low voltage  
Leakage current  
Measured at V  
0.5  
O
O
V = 2.7 V,  
I
I
= 1mA  
0.15  
0.4  
1
O(PG)  
V
(PG)  
= 5.5 V  
µA  
NOTES: 1. Minimum IN operating voltage is 2.7 V or V  
+ 1 V, whichever is greater. Maximum IN voltage 5.5 V.  
O(typ)  
= 5.5 V:  
2. If V ≤ 1.8 V then V = 2.7 V, V  
imin imax  
O
V
V
2.7 V  
O
O
imax  
100  
Line Reg. (mV)  
% V  
1000  
If V ≥ 2.5 V then V  
= V + 1 V, V  
= 5.5 V:  
% V  
O
imin  
O
imax  
V
V
V
1 V  
imax  
O
Line Reg. (mV)  
1000  
100  
3.  
I
O
= 1 mA to 1.5 A  
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
TPS75101Q, TPS75115Q, TPS75118Q, TPS75125Q, TPS75133Q WITH POWER GOOD  
TPS75301Q, TPS75315Q, TPS75318Q, TPS75325Q, TPS75333Q WITH RESET  
FAST-TRANSIENT-RESPONSE 1.5-A LOW-DROPOUT VOLTAGE REGULATORS  
SLVS241B – MARCH 2000 – REVISED JUNE 2003  
electrical characteristics over recommended operating junction temperature range (T = –40°C to  
J
125°C), V = V  
+ 1 V, I = 1 mA, EN = 0 V, C = 47 µF (unless otherwise noted) (continued)  
I
O(typ)  
O o  
PARAMETER  
TEST CONDITIONS  
= 300 µA,  
MIN  
TYP  
MAX  
1.3  
UNIT  
Minimum input voltage for valid RESET  
Trip threshold voltage  
Hysteresis voltage  
I
V
≤ 0.8 V  
1.1  
V
O(RESET)  
(RESET)  
V
decreasing  
92  
98  
%V  
%V  
V
O
O
Measured at V  
0.5  
Reset  
(TPS753xxQ)  
O
O
Output low voltage  
I
= 1 mA  
0.15  
0.4  
1
O(RESET)  
Leakage current  
V
= 5.5 V  
µA  
ms  
µA  
µA  
V
(RESET)  
RESET time-out delay  
100  
0
EN = V  
–1  
–1  
2
1
1
I
Input current (EN)  
EN = 0 V  
High level EN input voltage  
Low level EN input voltage  
0.7  
V
I
= 1.5 A,  
V = 3.2 V,  
I
O
J
160  
T = 25°C  
Dropout voltage, (3.3 V output) (see Note 4)  
mV  
I
O
= 1.5 A,  
V = 3.2 V  
I
300  
NOTE 4: IN voltage equals V (Typ) – 100 mV; TPS75x15Q, TPS75x18Q and TPS75x25Q dropout voltage limited by input voltage range  
O
limitations (i.e., TPS75x33Q input voltage needs to drop to 3.2 V for purpose of this test).  
Table of Graphs  
FIGURE  
vs Output current  
vs Junction temperature  
vs Junction temperature  
vs Frequency  
2, 3  
4, 5  
6
V
Output voltage  
O
Ground current  
Power supply ripple rejection  
Output spectral noise density  
Output impedance  
7
vs Frequency  
8
Z
o
vs Frequency  
9
vs Input voltage  
10  
V
DO  
Dropout voltage  
vs Junction temperature  
vs Output voltage  
11  
Input voltage (min)  
12  
Line transient response  
Load transient response  
Output voltage  
13, 15  
14, 16  
17  
V
O
vs Time  
Equivalent series resistance (ESR)  
vs Output current  
19, 20  
9
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TPS75101Q, TPS75115Q, TPS75118Q, TPS75125Q, TPS75133Q WITH POWER GOOD  
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FAST-TRANSIENT-RESPONSE 1.5-A LOW-DROPOUT VOLTAGE REGULATORS  
SLVS241B – MARCH 2000 – REVISED JUNE 2003  
TYPICAL CHARACTERISTICS  
TPS75x33Q  
TPS75x15Q  
OUTPUT VOLTAGE  
vs  
OUTPUT VOLTAGE  
vs  
OUTPUT CURRENT  
OUTPUT CURRENT  
3.305  
1.503  
1.502  
1.501  
V = 2.7 V  
V = 4.3 V  
I
I
T
J
= 25°C  
T
J
= 25°C  
3.303  
3.301  
V
O
V
O
1.5  
1.499  
1.498  
1.497  
3.299  
3.297  
3.295  
0
500  
1000  
1500  
500  
1000  
1500  
0
I
O
– Output Current – mA  
I
O
– Output Current – mA  
Figure 2  
Figure 3  
TPS75x15Q  
TPS75x33Q  
OUTPUT VOLTAGE  
vs  
OUTPUT VOLTAGE  
vs  
JUNCTION TEMPERATURE  
JUNCTION TEMPERATURE  
3.37  
1.53  
1.52  
V = 4.3 V  
I
V = 2.7 V  
I
3.35  
3.33  
1 mA  
1.51  
1.50  
1.49  
1.48  
1 mA  
3.31  
3.29  
1.5 A  
1.5 A  
3.27  
3.25  
3.23  
1.47  
–40  
10  
60  
110  
160  
–40  
10  
60  
110  
160  
T
J
– Junction Temperature – °C  
T
J
– Junction Temperature – °C  
Figure 4  
Figure 5  
10  
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TPS75101Q, TPS75115Q, TPS75118Q, TPS75125Q, TPS75133Q WITH POWER GOOD  
TPS75301Q, TPS75315Q, TPS75318Q, TPS75325Q, TPS75333Q WITH RESET  
FAST-TRANSIENT-RESPONSE 1.5-A LOW-DROPOUT VOLTAGE REGULATORS  
SLVS241B – MARCH 2000 – REVISED JUNE 2003  
TYPICAL CHARACTERISTICS  
TPS75xxxQ  
TPS75x33Q  
GROUND CURRENT  
POWER SUPPLY RIPPLE REJECTION  
vs  
vs  
JUNCTION TEMPERATURE  
FREQUENCY  
90  
85  
80  
75  
100  
V = 5 V  
I
90  
80  
70  
I
O
= 1.5 A  
V = 4.3 V  
I
C
= 100 µF  
= 1 mA  
= 25°C  
O
I
O
T
J
60  
50  
40  
30  
20  
70  
65  
60  
V = 4.3 V  
I
C
= 100 µF  
= 1.5 A  
= 25°C  
O
I
O
T
J
55  
50  
10  
0
–40  
10  
60  
110  
160  
10  
100  
1k  
10k  
100k  
1M  
10M  
T
J
– Junction Temperature – °C  
f – Frequency – Hz  
Figure 6  
Figure 7  
TPS75x33Q  
OUTPUT SPECTRAL NOISE DENSITY  
TPS75x33Q  
OUTPUT IMPEDANCE  
vs  
vs  
FREQUENCY  
FREQUENCY  
1
10  
2
V = 4.3 V  
I
1.8  
1.6  
V
C
T
= 3.3 V  
= 100 µF  
= 25°C  
O
O
C
= 100 µF  
= 1 mA  
O
I
O
J
1.4  
1.2  
1
I
O
= 1.5 A  
1
0.8  
0.6  
0.4  
0.2  
0
–1  
10  
C
= 100 µF  
= 1.5 A  
O
I
O
I
= 1 mA  
O
–2  
10  
10  
100  
1k  
10k  
50k  
10  
100  
1K  
10K  
100K  
1M  
10M  
f – Frequency – Hz  
f – Frequency – Hz  
Figure 8  
Figure 9  
11  
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TPS75101Q, TPS75115Q, TPS75118Q, TPS75125Q, TPS75133Q WITH POWER GOOD  
TPS75301Q, TPS75315Q, TPS75318Q, TPS75325Q, TPS75333Q WITH RESET  
FAST-TRANSIENT-RESPONSE 1.5-A LOW-DROPOUT VOLTAGE REGULATORS  
SLVS241B – MARCH 2000 – REVISED JUNE 2003  
TYPICAL CHARACTERISTICS  
TPS75x01Q  
TPS75x33Q  
DROPOUT VOLTAGE  
DROPOUT VOLTAGE  
vs  
vs  
INPUT VOLTAGE  
JUNCTION TEMPERATURE  
300  
300  
I
O
= 1.5 A  
250  
250  
T
= 125°C  
200  
150  
100  
J
200  
150  
100  
I
O
= 1.5 A  
T
J
= 25°C  
T
= –40°C  
J
I
O
= 0.5 A  
50  
0
50  
0
2.5  
3
3.5  
4
4.5  
5
–40  
10  
60  
110  
160  
V – Input Voltage – V  
I
T
J
– Junction Temperature – °C  
Figure 10  
Figure 11  
INPUT VOLTAGE (MIN)  
vs  
OUTPUT VOLTAGE  
TPS75x15Q  
LINE TRANSIENT RESPONSE  
4
I
C
V
=1.5 A  
I
O
= 1.5 A  
dv  
dt  
1 V  
µs  
O
100 µF  
O=  
=1.5 V  
O
100  
T
A
= 25°C  
0
T
A
= 125°C  
–100  
3
T
A
= –40°C  
2.7  
4
3
2
1.5 1.75  
2
2.25 2.5 2.75  
– Output Voltage – V  
3
3.25 3.5  
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9  
t – Time – ms  
1
V
O
Figure 12  
Figure 13  
12  
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FAST-TRANSIENT-RESPONSE 1.5-A LOW-DROPOUT VOLTAGE REGULATORS  
SLVS241B – MARCH 2000 – REVISED JUNE 2003  
TYPICAL CHARACTERISTICS  
TPS75x15Q  
TPS75x33Q  
LOAD TRANSIENT RESPONSE  
LINE TRANSIENT RESPONSE  
I =1.5 A  
L
I =1.5 A  
O
dv  
dt  
1 V  
µs  
C =100 µF (Tantalum)  
L
O
C =100 µF (Tantalum)  
O
50  
0
V
=1.5 V  
V =3.3 V  
O
100  
0
–50  
–100  
–150  
1.5  
–100  
5.3  
4.3  
0
0
1
2
3
4
5
6
7
8
9
10  
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9  
1
t – Time – ms  
t – Time – ms  
Figure 14  
Figure 15  
TPS75x33Q  
OUTPUT VOLTAGE  
vs  
TPS75x33Q  
TIME (STARTUP)  
LOAD TRANSIENT RESPONSE  
I
C
V
=1.5 A  
V = 4.3 V  
I
J
O
3.3  
=100 µF (Tantalum)  
=3.3 V  
T
= 25°C  
O
50  
0
O
–50  
–100  
0
4.3  
0
–150  
1.5  
0
0
0.2  
0.4  
0.6  
0.8  
1
0
1
2
3
4
5
6
7
8
9
10  
t – Time – ms  
t – Time – ms  
Figure 16  
Figure 17  
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FAST-TRANSIENT-RESPONSE 1.5-A LOW-DROPOUT VOLTAGE REGULATORS  
SLVS241B – MARCH 2000 – REVISED JUNE 2003  
TYPICAL CHARACTERISTICS  
To Load  
IN  
V
I
OUT  
+
C
O
R
EN  
L
GND  
ESR  
Figure 18. Test Circuit for Typical Regions of Stability (Figures 19 and 20) (Fixed Output Options)  
TYPICAL REGION OF STABILITY  
EQUIVALENT SERIES RESISTANCE  
vs  
TYPICAL REGION OF STABILITY  
EQUIVALENT SERIES RESISTANCE  
vs  
†
†
OUTPUT CURRENT  
OUTPUT CURRENT  
10  
10  
V
C
= 3.3 V  
= 100 µF  
V
C
= 3.3 V  
= 47 µF  
o
o
o
o
V = 4.3 V  
V = 4.3 V  
I
T = 25°C  
J
I
J
T
= 25°C  
1
1
Region of Stability  
Region of Stability  
0.1  
0.1  
0.01  
0.05  
Region of Instability  
Region of Instability  
0.01  
0
0.5  
1
1.5  
0
0.5  
1
1.5  
I
O
– Output Current – A  
I
O
– Output Current – A  
Figure 19  
Figure 20  
†
Equivalentseriesresistance(ESR)referstothetotalseriesresistance, includingtheESRofthecapacitor, anyseriesresistanceaddedexternally,  
and PWB trace resistance to C .  
o
14  
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TPS75101Q, TPS75115Q, TPS75118Q, TPS75125Q, TPS75133Q WITH POWER GOOD  
TPS75301Q, TPS75315Q, TPS75318Q, TPS75325Q, TPS75333Q WITH RESET  
FAST-TRANSIENT-RESPONSE 1.5-A LOW-DROPOUT VOLTAGE REGULATORS  
SLVS241B – MARCH 2000 – REVISED JUNE 2003  
APPLICATION INFORMATION  
The TPS751xxQ or TPS753xxQ family includes four fixed-output voltage regulators (1.5 V, 1.8 V, 2.5 V and 3.3  
V), and an adjustable regulator, the TPS75x01Q (adjustable from 1.5 V to 5 V).  
minimum load requirements  
TheTPS751xxQandTPS753xxQfamiliesarestableevenatnoload;nominimumloadisrequiredforoperation.  
pin functions  
enable (EN)  
The EN terminal is an input which enables or shuts down the device. If EN is a logic high, the device will be in  
shutdown mode. When EN goes to logic low, then the device will be enabled.  
power-good (PG) (TPS751xxQ)  
The PG terminal is an open drain, active high output that indicates the status of V (output of the LDO). When  
O
V
reaches 83% of the regulated voltage, PG will go to a high impedance state. It will go to a low-impedance  
O
state when V falls below 83% (i.e. over load condition) of the regulated voltage. The open drain output of the  
O
PG terminal requires a pullup resistor  
.
sense (SENSE)  
The SENSE terminal of the fixed-output options must be connected to the regulator output, and the connection  
should be as short as possible. Internally, SENSE connects to a high-impedance wide-bandwidth amplifier  
through a resistor-divider network and noise pickup feeds through to the regulator output. It is essential to route  
the SENSE connection in such a way to minimize/avoid noise pickup. Adding RC networks between the SENSE  
terminal and V to filter noise is not recommended because it may cause the regulator to oscillate.  
O
feedback (FB)  
FB is an input terminal used for the adjustable-output options and must be connected to an external feedback  
resistor divider. The FB connection should be as short as possible. It is essential to route it in such a way to  
minimize/avoid noise pickup. Adding RC networks between FB terminal and V to filter noise is not  
O
recommended because it may cause the regulator to oscillate.  
reset (RESET) (TPS753xxQ)  
The RESET terminal is an open drain, active low output that indicates the status of V . When V reaches 95%  
O
O
of the regulated voltage, RESET will go to a low-impedance state after a 100-ms delay. RESET will go to a  
high-impedance state when V is below 95% of the regulated voltage. The open-drain output of the RESET  
O
terminal requires a pullup resistor.  
GND/HEATSINK  
All GND/HEATSINK terminals are connected directly to the mount pad for thermal-enhanced operation. These  
terminals could be connected to GND or left floating.  
input capacitor  
For a typical application, an input bypass capacitor (0.22 µF – 1 µF) is recommended for device stability. This  
capacitor should be as close to the input pins as possible. For fast transient condition where droop at the input  
of the LDO may occur due to high inrush current, it is recommended to place a larger capacitor at the input as  
well. The size of this capacitor is dependant on the output current and response time of the main power supply,  
as well as the distance to the load (LDO).  
15  
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FAST-TRANSIENT-RESPONSE 1.5-A LOW-DROPOUT VOLTAGE REGULATORS  
SLVS241B – MARCH 2000 – REVISED JUNE 2003  
APPLICATION INFORMATION  
output capacitor  
As with most LDO regulators, the TPS751xxQ and TPS753xxQ require an output capacitor connected between  
OUT and GND to stabilize the internal control loop. The minimum recommended capacitance value is 47 µF  
and the ESR (equivalent series resistance) must be between 100 mΩ and 10 Ω. Solid tantalum electrolytic,  
aluminum electrolytic, and multilayer ceramic capacitors are all suitable, provided they meet the requirements  
described in this section. Larger capacitors provide a wider range of stability and better load transient response.  
This information, along with the ESR graphs, is included to assist in selection of suitable capacitance for the  
user’s application. When necessary to achieve low height requirements along with high output current and/or  
high load capacitance, several higher ESR capacitors can be used in parallel to meet these guidelines.  
ESR and transient response  
LDOs typically require an external output capacitor for stability. In fast transient response applications,  
capacitors are used to support the load current while LDO amplifier is responding. In most applications, one  
capacitor is used to support both functions.  
Besides its capacitance, every capacitor also contains parasitic impedances. These parasitic impedances are  
resistive as well as inductive. The resistive impedance is called equivalent series resistance (ESR), and the  
inductive impedance is called equivalent series inductance (ESL). The equivalent schematic diagram of any  
capacitor can therefore be drawn as shown in Figure 21.  
R
L
ESL  
ESR  
C
Figure 21. – ESR and ESL  
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FAST-TRANSIENT-RESPONSE 1.5-A LOW-DROPOUT VOLTAGE REGULATORS  
SLVS241B – MARCH 2000 – REVISED JUNE 2003  
APPLICATION INFORMATION  
In most cases one can neglect the effect of inductive impedance ESL. Therefore, the following application  
focuses mainly on the parasitic resistance ESR.  
Figure 22 shows the output capacitor and its parasitic impedances in a typical LDO output stage.  
I
O
LDO  
+
R
V
ESR  
ESR  
–
V
V
I
O
R
LOAD  
C
O
Figure 22. LDO Output Stage With Parasitic Resistances ESR and ESL  
In steady state (dc state condition), the load current is supplied by the LDO (solid arrow) and the voltage across  
the capacitor is the same as the output voltage (V(C ) = V ). This means no current is flowing into the C  
O
O
O
branch. If I suddenly increases (transient condition), the following occurs:  
O
The LDO is not able to supply the sudden current need due to its response time (t in Figure 23). Therefore,  
1
capacitor C provides the current for the new load condition (dashed arrow). C now acts like a battery with  
O
O
an internal resistance, ESR. Depending on the current demand at the output, a voltage drop will occur at  
. This voltage is shown as V in Figure 22.  
R
ESR  
ESR  
When C is conducting current to the load, initial voltage at the load will be V = V(C ) – V . Due to the  
ESR  
O
O
O
dischargeofC ,theoutputvoltageV willdropcontinuouslyuntiltheresponsetimet oftheLDOisreached  
O
O
1
and the LDO will resume supplying the load. From this point, the output voltage starts rising again until it  
reaches the regulated voltage. This period is shown as t in Figure 23.  
2
Figure 23 also shows the impact of different ESRs on the output voltage. The left brackets show different levels  
of ESRs where number 1 displays the lowest and number 3 displays the highest ESR.  
From above, the following conclusions can be drawn:  
The higher the ESR, the larger the droop at the beginning of load transient.  
The smaller the output capacitor, the faster the discharge time and the bigger the voltage droop during the  
LDO response period.  
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FAST-TRANSIENT-RESPONSE 1.5-A LOW-DROPOUT VOLTAGE REGULATORS  
SLVS241B – MARCH 2000 – REVISED JUNE 2003  
APPLICATION INFORMATION  
conclusion  
To minimize the transient output droop, capacitors must have a low ESR and be large enough to support the  
minimum output voltage requirement.  
I
O
V
O
1
2
ESR 1  
ESR 2  
3
ESR 3  
t
t
1
2
Figure 23. Correlation of Different ESRs and Their Influence to the Regulation of V at a  
O
Load Step From Low-to-High Output Current  
18  
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FAST-TRANSIENT-RESPONSE 1.5-A LOW-DROPOUT VOLTAGE REGULATORS  
SLVS241B – MARCH 2000 – REVISED JUNE 2003  
APPLICATION INFORMATION  
programming the TPS75x01Q adjustable LDO regulator  
The output voltage of the TPS75x01Q adjustable regulator is programmed using an external resistor divider as  
shown in Figure 24. The output voltage is calculated using:  
R1  
R2  
(1)  
V
V
1
O
ref  
Where:  
V
= 1.1834 V typ (the internal reference voltage)  
ref  
Resistors R1 and R2 should be chosen for approximately 40-µA divider current. Lower value resistors can be  
used but offer no inherent advantage and waste more power. Higher values should be avoided as leakage  
currents at FB increase the output voltage error. The recommended design procedure is to choose  
R2 = 30.1 kΩ to set the divider current at 40 µA and then calculate R1 using:  
V
O
R1  
1
R2  
(2)  
V
ref  
OUTPUT VOLTAGE  
PROGRAMMING GUIDE  
TPS75x01Q  
OUTPUT  
VOLTAGE  
R1  
R2  
UNIT  
PG or  
IN  
V
I
PG or RESET Output  
250 kΩ  
RESET  
0.22 µF  
2.5 V  
3.3 V  
3.6 V  
33.2  
53.6  
61.9  
30.1  
30.1  
30.1  
kΩ  
kΩ  
kΩ  
≥ 2 V  
EN  
OUT  
V
O
≤ 0.7 V  
R1  
C
O
NOTE: To reduce noise and prevent  
oscillation, R1 and R2 need to be as close  
as possible to the FB/SENSE terminal.  
FB/SENSE  
GND  
R2  
Figure 24. TPS75x01Q Adjustable LDO Regulator Programming  
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FAST-TRANSIENT-RESPONSE 1.5-A LOW-DROPOUT VOLTAGE REGULATORS  
SLVS241B – MARCH 2000 – REVISED JUNE 2003  
APPLICATION INFORMATION  
regulator protection  
The TPS751xxQ or TPS753xxQ PMOS-pass transistor has a built-in back diode that conducts reverse currents  
when the input voltage drops below the output voltage (e.g., during power down). Current is conducted from  
the output to the input and is not internally limited. When extended reverse voltage is anticipated, external  
limiting may be appropriate.  
The TPS751xxQ or TPS753xxQ also features internal current limiting and thermal protection. During normal  
operation, the TPS751xxQ or TPS753xxQ limits output current to approximately 3.3 A. When current limiting  
engages, the output voltage scales back linearly until the overcurrent condition ends. While current limiting is  
designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of  
the package. If the temperature of the device exceeds 150°C(typ), thermal-protection circuitry shuts it down.  
Once the device has cooled below 130°C(typ), regulator operation resumes.  
power dissipation and junction temperature  
Specified regulator operation is assured to a junction temperature of 125°C; the maximum junction temperature  
should be restricted to 125°C under normal operating conditions. This restriction limits the power dissipation  
the regulator can handle in any given application. To ensure the junction temperature is within acceptable limits,  
calculate the maximum allowable dissipation, P  
, and the actual dissipation, P , which must be less than  
D(max)  
D
or equal to P  
.
D(max)  
The maximum-power-dissipation limit is determined using the following equation:  
T max  
J
T
A
(3)  
P
D(max)  
R
JA  
Where:  
T max is the maximum allowable junction temperature  
J
R
is the thermal resistance junction-to-ambient for the package, i.e., 34.6°C/W for the 20-terminal  
θJA  
PWP with no airflow (see Table 1).  
T is the ambient temperature.  
A
The regulator dissipation is calculated using:  
P
V
V
I
(4)  
D
I
O
O
Power dissipation resulting from quiescent current is negligible. Excessive power dissipation will trigger the  
thermal protection circuit.  
20  
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TPS75101Q, TPS75115Q, TPS75118Q, TPS75125Q, TPS75133Q WITH POWER GOOD  
TPS75301Q, TPS75315Q, TPS75318Q, TPS75325Q, TPS75333Q WITH RESET  
FAST-TRANSIENT-RESPONSE 1.5-A LOW-DROPOUT VOLTAGE REGULATORS  
SLVS241B – MARCH 2000 – REVISED JUNE 2003  
THERMAL INFORMATION  
thermally enhanced TSSOP-20 (PWP – PowerPad )  
The thermally enhanced PWP package is based on the 20-pin TSSOP, but includes a thermal pad [see  
Figure 25(c)] to provide an effective thermal contact between the IC and the PWB.  
Traditionally, surface mount and power have been mutually exclusive terms. A variety of scaled-down  
TO220-typepackageshaveleadsformedasgullwingstomakethemapplicableforsurface-mountapplications.  
These packages, however, suffer from several shortcomings: they do not address the very low profile  
requirements (<2 mm) of many of today’s advanced systems, and they do not offer a pin-count high enough  
to accommodate increasing integration. On the other hand, traditional low-power surface-mount packages  
require power-dissipation derating that severely limits the usable range of many high-performance analog  
circuits.  
The PWP package (thermally enhanced TSSOP) combines fine-pitch surface-mount technology with thermal  
performance comparable to much larger power packages.  
The PWP package is designed to optimize the heat transfer to the PWB. Because of the very small size and  
limited mass of a TSSOP package, thermal enhancement is achieved by improving the thermal conduction  
paths that remove heat from the component. The thermal pad is formed using a lead-frame design (patent  
pending) and manufacturing technique to provide the user with direct connection to the heat-generating IC.  
When this pad is soldered or otherwise coupled to an external heat dissipator, high power dissipation in the  
ultrathin, fine-pitch, surface-mount package can be reliably achieved.  
DIE  
Side View (a)  
Thermal  
Pad  
DIE  
End View (b)  
Bottom View (c)  
Figure 25. Views of Thermally Enhanced PWP Package  
Because the conduction path has been enhanced, power-dissipation capability is determined by the thermal  
considerations in the PWB design. For example, simply adding a localized copper plane (heat-sink surface),  
which is coupled to the thermal pad, enables the PWP package to dissipate 2.5 W in free air (reference  
2
Figure 27(a), 8 cm of copper heat sink and natural convection). Increasing the heat-sink size increases the  
power dissipation range for the component. The power dissipation limit can be further improved by adding  
2
airflow to a PWB/IC assembly (see Figures 26 and 27). The line drawn at 0.3 cm in Figures 26 and 27 indicates  
performance at the minimum recommended heat-sink size, illustrated in Figure 29.  
21  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
TPS75101Q, TPS75115Q, TPS75118Q, TPS75125Q, TPS75133Q WITH POWER GOOD  
TPS75301Q, TPS75315Q, TPS75318Q, TPS75325Q, TPS75333Q WITH RESET  
FAST-TRANSIENT-RESPONSE 1.5-A LOW-DROPOUT VOLTAGE REGULATORS  
SLVS241B – MARCH 2000 – REVISED JUNE 2003  
THERMAL INFORMATION  
thermally enhanced TSSOP-20 (PWP – PowerPad ) (continued)  
The thermal pad is directly connected to the substrate of the IC, which for the TPS751xxQPWP and  
TPS753XXQPWP series is a secondary electrical connection to device ground. The heat-sink surface that is  
added to the PWP can be a ground plane or left electrically isolated. In TO220-type surface-mount packages,  
the thermal connection is also the primary electrical connection for a given terminal which is not always ground.  
The PWP package provides up to 16 independent leads that can be used as inputs and outputs (Note: leads  
1, 10, 11, and 20 are internally connected to the thermal pad and the IC substrate).  
THERMAL RESISTANCE  
vs  
COPPER HEAT-SINK AREA  
150  
125  
100  
Natural Convection  
50 ft/min  
100 ft/min  
150 ft/min  
200 ft/min  
75  
50  
25  
250 ft/min  
300 ft/min  
0 0.3  
1
2
3
4
5
6
7
8
2
Copper Heat-Sink Area – cm  
Figure 26  
22  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
TPS75101Q, TPS75115Q, TPS75118Q, TPS75125Q, TPS75133Q WITH POWER GOOD  
TPS75301Q, TPS75315Q, TPS75318Q, TPS75325Q, TPS75333Q WITH RESET  
FAST-TRANSIENT-RESPONSE 1.5-A LOW-DROPOUT VOLTAGE REGULATORS  
SLVS241B – MARCH 2000 – REVISED JUNE 2003  
THERMAL INFORMATION  
thermally enhanced TSSOP-20 (PWP – PowerPad ) (continued)  
3.5  
3.5  
T
A
= 25°C  
T
A
= 55°C  
300 ft/min  
3
2.5  
2
3
2.5  
2
150 ft/min  
300 ft/min  
150 ft/min  
Natural Convection  
1.5  
1.5  
Natural Convection  
1
0.5  
0
1
0.5  
0
0
2
4
6
8
0
2
4
6
8
0.3  
0.3  
2
2
Copper Heat-Sink Size – cm  
Copper Heat-Sink Size – cm  
(a)  
(b)  
3.5  
T
A
= 105°C  
3
2.5  
2
1.5  
1
150 ft/min  
300 ft/min  
Natural Convection  
0.5  
0
0
0.3  
2
4
6
8
2
Copper Heat-Sink Size – cm  
(c)  
Figure 27. Power Ratings of the PWP Package at Ambient Temperatures of 25°C, 55°C, and 105°C  
23  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
TPS75101Q, TPS75115Q, TPS75118Q, TPS75125Q, TPS75133Q WITH POWER GOOD  
TPS75301Q, TPS75315Q, TPS75318Q, TPS75325Q, TPS75333Q WITH RESET  
FAST-TRANSIENT-RESPONSE 1.5-A LOW-DROPOUT VOLTAGE REGULATORS  
SLVS241B – MARCH 2000 – REVISED JUNE 2003  
THERMAL INFORMATION  
thermally enhanced TSSOP-20 (PWP – PowerPad ) (continued)  
Figure 28 is an example of a thermally enhanced PWB layout for use with the new PWP package. This board  
configuration was used in the thermal experiments that generated the power ratings shown in Figure 26 and  
Figure27. Asdiscussedearlier, copperhasbeenaddedonthePWBtoconductheatawayfromthedevice. R  
θJA  
for this assembly is illustrated in Figure 26 as a function of heat-sink area. A family of curves is included to  
illustrate the effect of airflow introduced into the system.  
Heat-Sink Area  
1 oz Copper  
Board thickness  
Board size  
62 mils  
3.2 in. × 3.2 in.  
FR4  
Board material  
Copper trace/heat sink 1 oz  
Exposed pad mounting 63/67 tin/lead solder  
Figure 28. PWB Layout (Including Copper Heatsink Area) for Thermally Enhanced PWP Package  
From Figure 26, R  
power-dissipation limit for the component/PWB assembly, with the equation:  
for a PWB assembly can be determined and used to calculate the maximum  
θJA  
T max  
T
J
A
P
D(max)  
(5)  
R
JA(system)  
Where:  
T max is the maximum specified junction temperature (150°C absolute maximum limit, 125°C recommended  
J
operating limit) and T is the ambient temperature.  
A
P
shouldthenbeappliedtotheinternalpowerdissipatedbytheTPS75133QPWPregulator.Theequation  
D(max)  
for calculating total internal power dissipation of the TPS75133QPWP is:  
P
V
V
I
V
I
(6)  
D(total)  
I
O
O
I
Q
Since the quiescent current of the TPS75133QPWP is very low, the second term is negligible, furthersimplifying  
the equation to:  
P
V
V
I
(7)  
D(total)  
I
O
O
2
For the case where T = 55°C, airflow = 200 ft/min, copper heat-sink area = 4 cm , the maximum  
A
power-dissipation limit can be calculated. First, from Figure 26, we find the system R  
the maximum power-dissipation limit is:  
is 50°C/W; therefore,  
θJA  
T max  
T
°
°
J
A
125 C 55 C  
P
1.4 W  
(8)  
D(max)  
°
R
50 C W  
JA(system)  
24  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
TPS75101Q, TPS75115Q, TPS75118Q, TPS75125Q, TPS75133Q WITH POWER GOOD  
TPS75301Q, TPS75315Q, TPS75318Q, TPS75325Q, TPS75333Q WITH RESET  
FAST-TRANSIENT-RESPONSE 1.5-A LOW-DROPOUT VOLTAGE REGULATORS  
SLVS241B – MARCH 2000 – REVISED JUNE 2003  
THERMAL INFORMATION  
thermally enhanced TSSOP-20 (PWP – PowerPad ) (continued)  
If the system implements a TPS75133QPWP regulator, where V = 5 V and I = 800 mA, the internal power  
I
O
dissipation is:  
P
V
V
I
(5 3.3) 0.8  
1.36 W  
(9)  
D(total)  
I
O
O
Comparing P  
with P  
D(max)  
reveals that the power dissipation in this example does not exceed the  
D(total)  
calculated limit. When it does, one of two corrective actions should be made: raising the power-dissipation limit  
by increasing the airflow or the heat-sink area, or lowering the internal power dissipation of the regulator by  
reducing the input voltage or the load current. In either case, the above calculations should be repeated with  
the new system parameters.  
mounting information  
The primary requirement is to complete the thermal contact between the thermal pad and the PWB metal. The  
thermal pad is a solderable surface and is fully intended to be soldered at the time the component is mounted.  
Although voiding in the thermal-pad solder-connection is not desirable, up to 50% voiding is acceptable. The  
data included in Figures 26 and 27 is for soldered connections with voiding between 20% and 50%. The thermal  
analysis shows no significant difference resulting from the variation in voiding percentage.  
Figure 29 shows the solder-mask land pattern for  
the PWP package. The minimum recommended  
heat-sink area is also illustrated. This is simply a  
copper plane under the body extent of the  
package, including metal routed under terminals  
1, 10, 11, and 20.  
Minimum Recommended  
Heat-Sink Area  
Location of Exposed  
Thermal Pad on  
PWP Package  
Figure 29. PWP Package Land Pattern  
25  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
PACKAGE OPTION ADDENDUM  
www.ti.com  
4-Mar-2005  
PACKAGING INFORMATION  
Orderable Device  
Status (1)  
Package Package  
Type  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Drawing  
PWP  
PWP  
PWP  
PWP  
PWP  
PWP  
PWP  
PWP  
PWP  
PWP  
PWP  
PWP  
PWP  
PWP  
PWP  
TPS75101QPWP  
TPS75101QPWPR  
TPS75115QPWP  
TPS75115QPWPR  
TPS75118QPWP  
TPS75118QPWPR  
TPS75125QPWP  
TPS75125QPWPR  
TPS75133QPWP  
TPS75133QPWPR  
TPS75301QPWP  
TPS75301QPWPR  
TPS75315QPWP  
TPS75315QPWPR  
TPS75315QPWPRG4  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
HTSSOP  
HTSSOP  
HTSSOP  
HTSSOP  
HTSSOP  
HTSSOP  
HTSSOP  
HTSSOP  
HTSSOP  
HTSSOP  
HTSSOP  
HTSSOP  
HTSSOP  
HTSSOP  
HTSSOP  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
70  
2000  
70  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
CU NIPDAU Level-1-220C-UNLIM  
CU NIPDAU Level-1-220C-UNLIM  
CU NIPDAU Level-1-220C-UNLIM  
CU NIPDAU Level-1-220C-UNLIM  
CU NIPDAU Level-1-220C-UNLIM  
CU NIPDAU Level-1-220C-UNLIM  
CU NIPDAU Level-1-220C-UNLIM  
CU NIPDAU Level-1-220C-UNLIM  
CU NIPDAU Level-1-220C-UNLIM  
CU NIPDAU Level-1-220C-UNLIM  
CU NIPDAU Level-1-220C-UNLIM  
CU NIPDAU Level-1-220C-UNLIM  
CU NIPDAU Level-1-220C-UNLIM  
CU NIPDAU Level-1-220C-UNLIM  
2000  
70  
2000  
70  
2000  
70  
2000  
70  
2000  
70  
2000  
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
TPS75318QPWP  
TPS75318QPWPR  
TPS75325QPWP  
TPS75325QPWPR  
TPS75333QPWP  
TPS75333QPWPR  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
HTSSOP  
HTSSOP  
HTSSOP  
HTSSOP  
HTSSOP  
HTSSOP  
PWP  
PWP  
PWP  
PWP  
PWP  
PWP  
20  
20  
20  
20  
20  
20  
70  
2000  
70  
None  
None  
None  
None  
None  
None  
CU NIPDAU Level-1-220C-UNLIM  
CU NIPDAU Level-1-220C-UNLIM  
CU NIPDAU Level-1-220C-UNLIM  
CU NIPDAU Level-1-220C-UNLIM  
CU NIPDAU Level-1-220C-UNLIM  
CU NIPDAU Level-1-220C-UNLIM  
2000  
70  
2000  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional  
product content details.  
None: Not yet available Lead (Pb-Free).  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,  
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
4-Mar-2005  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 2  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,  
enhancements, improvements, and other changes to its products and services at any time and to discontinue  
any product or service without notice. Customers should obtain the latest relevant information before placing  
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms  
and conditions of sale supplied at the time of order acknowledgment.  
TI warrants performance of its hardware products to the specifications applicable at the time of sale in  
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI  
deems necessary to support this warranty. Except where mandated by government requirements, testing of all  
parameters of each product is not necessarily performed.  
TI assumes no liability for applications assistance or customer product design. Customers are responsible for  
their products and applications using TI components. To minimize the risks associated with customer products  
and applications, customers should provide adequate design and operating safeguards.  
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,  
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process  
in which TI products or services are used. Information published by TI regarding third-party products or services  
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.  
Use of such information may require a license from a third party under the patents or other intellectual property  
of the third party, or a license from TI under the patents or other intellectual property of TI.  
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without  
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction  
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for  
such altered documentation.  
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that  
product or service voids all express and any implied warranties for the associated TI product or service and  
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.  
Following are URLs where you can obtain information on other Texas Instruments products and application  
solutions:  
Products  
Applications  
Audio  
Amplifiers  
amplifier.ti.com  
www.ti.com/audio  
Data Converters  
dataconverter.ti.com  
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DSP  
dsp.ti.com  
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Digital Control  
Military  
www.ti.com/broadband  
www.ti.com/digitalcontrol  
www.ti.com/military  
Interface  
Logic  
interface.ti.com  
logic.ti.com  
Power Mgmt  
Microcontrollers  
power.ti.com  
Optical Networking  
Security  
www.ti.com/opticalnetwork  
www.ti.com/security  
www.ti.com/telephony  
www.ti.com/video  
microcontroller.ti.com  
Telephony  
Video & Imaging  
Wireless  
www.ti.com/wireless  
Mailing Address:  
Texas Instruments  
Post Office Box 655303 Dallas, Texas 75265  
Copyright 2005, Texas Instruments Incorporated  

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