TPS77101DGK [TI]
150-mA LDO REGULATORS WITH INTEGRATED RESET OR PG; 集成了复位或PG 150 mA的LDO稳压器
| 型号： | TPS77101DGK |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 150-mA LDO REGULATORS WITH INTEGRATED RESET OR PG |
| 文件： | 总23页 (文件大小：357K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS77101, TPS77118, TPS77127, TPS77128, TPS77133 WITH RESET OUTPUT
TPS77201, TPS77218, TPS77227, TPS77228, TPS77233 WITH POWER GOOD OUTPUT
150-mA LDO REGULATORS WITH INTEGRATED RESET OR PG
SLVS225A – FEBRUARY 2000 – REVISED MARCH 2000
TPS771xx
Open Drain Power-On Reset With 220-ms
Delay (TPS771xx)
DGK PACKAGE
(TOP VIEW)
Open Drain Power-Good (PG) Status
Output (TPS772xx)
FB/SENSE
RESET
EN
OUT
OUT
IN
1
2
3
4
8
7
6
5
150-mA Low-Dropout Voltage Regulator
Available in 1.8-V, 2.7-V, 2.8-V, 3.3-V, Fixed
Output and Adjustable Versions
GND
IN
TPS772xx
DGK PACKAGE
(TOP VIEW)
Dropout Voltage Typically 115 mV
at 150 mA (TPS77133, TPS77233)
Ultra Low 92-µA Quiescent Current (Typ)
FB/SENSE
PG
1
2
3
4
8
7
6
5
OUT
OUT
IN
8-Pin MSOP (DGK) Package
Low Noise (55 µV
) Without External
rms
EN
Filter (Bypass) Capacitor (TPS77118,
TPS77218)
GND
IN
2% Tolerance Over Specified Conditions
for Fixed-Output Versions
TPS77x33
DROPOUT VOLTAGE
vs
JUNCTION TEMPERATURE
Fast Transient Response
Thermal Shutdown Protection
300
250
200
150
description
The TPS771xx and TPS772xx are low dropout
regulators with integrated power-on reset and
power good (PG) function respectively. These
devicesarecapableofsupplying150mAofoutput
current with a dropout of 115 mV (TPS77133,
TPS77233). Quiescent current is 92 µA at full load
dropping down to 1 µA when device is disabled.
These devices are optimized to be stable with a
wide range of output capacitors including lowESR
ceramic (10 µF) or low capacitance (1 µF)
tantalum capacitors. These devices have ex-
I
= 150 mA
O
100
50
I
= 10 mA
O
I
O
= 0 A
tremely low noise output performance (55 µV
)
rms
without using any added filter capacitors.
TPS771xx and TPS772xx are designed to have
fast transient response for larger load current
changes.
0
–40
0
40
80
120
140
T
J
– Junction Temperature – °C
The TPS771xx or TPS772xx is offered in 1.8-V, 2.7-V, 2.8-V and 3.3-V fixed-voltage versions and in an
adjustable version (programmable over the range of 1.5 V to 5.5 V). Output voltage tolerance is 2% over line,
load, and temperature ranges. The TPS771xx and TPS772xx families are available in 8-pin MSOP (DGK)
packages.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2000, Texas Instruments Incorporated
This document contains information on products in more than one phase
of development. The status of each device is indicated on the page(s)
specifying its electrical characteristics.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS77101, TPS77118, TPS77127, TPS77128, TPS77133 WITH RESET OUTPUT
TPS77201, TPS77218, TPS77227, TPS77228, TPS77233 WITH POWER GOOD OUTPUT
150-mA LDO REGULATORS WITH INTEGRATED RESET OR PG
SLVS225A – FEBRUARY 2000 – REVISED MARCH 2000
description (continued)
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 115 mV
at an output current of 150 mA for 3.3 volt option) and is directly proportional to the output current. Additionally,
since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent
of output loading (typically 92 µA over the full range of output current, 0 mA to 150 mA). These two key
specifications yield a significant improvement in operating life for battery-powered systems.
The device is enabled when the EN pin is connected to a low-level input voltage. This LDO family also features
a sleep mode; applying a TTL high signal to EN (enable) shuts down the regulator, reducing the quiescent
current to less than 1 µA at T = 25°C.
J
The TPS771xx features an integrated power-on reset, commonly used as a supply voltage supervisor (SVS)
or reset output voltage. The RESET output of the TPS771xx initiates a reset in DSP, microcomputer or
microprocessor systems at power-up and in the event of an undervoltage condition. An internal comparator in
the TPS771xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated
output voltage. When OUT reaches 95% of its regulated voltage, RESET will go to a high-impedance state after
a 220 ms delay. RESET will go to low-impedance state when OUT is pulled below 95% (i.e. over load condition)
of its regulated voltage.
For the TPS772xx, the power good terminal (PG) is an active high output, which can be used to implement a
power-on reset or a low-battery indicator. An internal comparator in the TPS772xx monitors the output voltage
of the regulator to detect an undervoltage condition on the regulated output voltage. When OUTfalls below 82%
of its regulated voltage, PG will go to a low-impedance state. PG will go to a high-impedance state when OUT
is above 82% of its regulated voltage.
AVAILABLE OPTIONS
OUTPUT
VOLTAGE
(V)
PACKAGED DEVICES
T
J
MSOP
(DGK)
TYP
3.3
2.8
2.7
1.8
TPS77133DGK
TPS77233DGK
TPS77228DGK
TPS77227DGK
TPS77218DGK
TPS77128DGK
TPS77127DGK
TPS77118DGK
–40°C to 125°C
Adjustable
1.5 V to 5.5 V
TPS77101DGK
TPS77201DGK
The TPS77101 and TPS77201 are programmable using an external resistor divider
(see application information). The DGK package is available taped and reeled. Add
an R suffix to the device type (e.g., TPS77101DGKR).
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS77101, TPS77118, TPS77127, TPS77128, TPS77133 WITH RESET OUTPUT
TPS77201, TPS77218, TPS77227, TPS77228, TPS77233 WITH POWER GOOD OUTPUT
150-mA LDO REGULATORS WITH INTEGRATED RESET OR PG
SLVS225A – FEBRUARY 2000 – REVISED MARCH 2000
5
6
7
8
1
V
I
IN
IN
OUT
OUT
V
O
SENSE
3
0.1 µF
2
PG or
RESET
EN
PG or RESET
10 µF
+
GND
4
Figure 1. Typical Application Configuration (For Fixed Output Options)
functional block diagram—adjustable version
IN
EN
PG or RESET
OUT
_
+
+
_
220 ms Delay
(for TPS771xx Option)
R1
V
ref
= 1.1834 V
FB/SENSE
R2
GND
External to the device
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS77101, TPS77118, TPS77127, TPS77128, TPS77133 WITH RESET OUTPUT
TPS77201, TPS77218, TPS77227, TPS77228, TPS77233 WITH POWER GOOD OUTPUT
150-mA LDO REGULATORS WITH INTEGRATED RESET OR PG
SLVS225A – FEBRUARY 2000 – REVISED MARCH 2000
functional block diagram—fixed-voltage version
IN
EN
PG or RESET
_
+
OUT
SENSE
+
_
220 ms Delay
(for TPS771xx Option)
R1
R2
V
ref
= 1.1834 V
GND
Terminal Functions (TPS771xx)
TERMINAL
NAME
I/O
DESCRIPTION
NO.
1
FB/SENSE
RESET
EN
I
O
I
Feedback input voltage for adjustable device (sense input for fixed options)
2
Reset output
3
Enable input
GND
4
Regulator ground
Input voltage
IN
5, 6
7, 8
I
OUT
O
Regulated output voltage
Terminal Functions (TPS772xx)
TERMINAL
I/O
DESCRIPTION
NAME
FB/SENSE
PG
NO.
1
I
O
I
Feedback input voltage for adjustable device (sense input for fixed options)
2
Power good
EN
3
Enable input
GND
4
Regulator ground
Input voltage
IN
5, 6
7, 8
I
OUT
O
Regulated output voltage
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS77101, TPS77118, TPS77127, TPS77128, TPS77133 WITH RESET OUTPUT
TPS77201, TPS77218, TPS77227, TPS77228, TPS77233 WITH POWER GOOD OUTPUT
150-mA LDO REGULATORS WITH INTEGRATED RESET OR PG
SLVS225A – FEBRUARY 2000 – REVISED MARCH 2000
TPS771xx RESET timing diagram
V
I
†
V
res
V
res
t
‡
‡
V
O
V
IT+
V
IT+
Threshold
Voltage
‡
‡
V
IT–
V
IT–
t
RESET
Output
220 ms
Delay
220 ms
Delay
Output
Undefined
Output
Undefined
t
†
V
is the minimum input voltage for a valid RESET. The symbol V is not currently listed within EIA or JEDEC standards
res
res
for semiconductor symbology.
‡
VIT –Trip voltage is typically 5% lower than the output voltage (95%V ) V
O
IT–
to V
is the hysteresis voltage.
IT+
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS77101, TPS77118, TPS77127, TPS77128, TPS77133 WITH RESET OUTPUT
TPS77201, TPS77218, TPS77227, TPS77228, TPS77233 WITH POWER GOOD OUTPUT
150-mA LDO REGULATORS WITH INTEGRATED RESET OR PG
SLVS225A – FEBRUARY 2000 – REVISED MARCH 2000
TPS772xx PG timing diagram
V
I
†
V
res
V
res
t
‡
‡
V
O
V
IT+
V
IT+
Threshold
Voltage
‡
‡
V
IT–
V
IT–
t
PG
Output
Output
Undefined
Output
Undefined
t
†
V
is the minimum input voltage for a valid PG. The symbol V
is not currently listed within EIA or JEDEC standards for
res
semiconductor symbology.
res
‡
VIT –Trip voltage is typically 18% lower than the output voltage (82%V ) V
O
IT–
to V
is the hysteresis voltage.
IT+
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS77101, TPS77118, TPS77127, TPS77128, TPS77133 WITH RESET OUTPUT
TPS77201, TPS77218, TPS77227, TPS77228, TPS77233 WITH POWER GOOD OUTPUT
150-mA LDO REGULATORS WITH INTEGRATED RESET OR PG
SLVS225A – FEBRUARY 2000 – REVISED MARCH 2000
absolute maximum ratings over operating junction temperature range
(unless otherwise noted)
‡
Input voltage range , V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 13.5 V
I
Voltage range at EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 16.5 V
Maximum RESET voltage (TPS771xx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5 V
Maximum PG voltage (TPS772xx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5 V
Peak output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See dissipation rating tables
Output voltage, V (OUT, FB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
O
Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
J
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
ESD rating, HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV
†
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network terminal ground.
DISSIPATION RATING TABLE – FREE-AIR TEMPERATURES
AIR FLOW
(CFM)
θ
θ
T
< 25°C
DERATING FACTOR
T
= 70°C
T = 85°C
A
A
A
JA
JC
PACKAGE
(°C/W) (°C/W) POWER RATING
ABOVE T = 25°C
POWER RATING POWER RATING
A
0
266.2
255.2
242.8
3.84
3.92
4.21
376 mW
392 mW
412 mW
3.76 mW/°C
3.92 mW/°C
4.12 mW/°C
207 mW
216 mW
227 mW
150 mW
157 mW
165 mW
150
250
DGK
recommended operating conditions
MIN
2.7
1.5
0
MAX
UNIT
§
Input voltage, V
10
5.5
V
V
I
Output voltage range, V
O
Output current, I (see Note 1)
150
125
mA
°C
O
Operating virtual junction temperature, T (see Note 1)
–40
J
§
To calculate the minimum input voltage for your maximum output current, use the following equation: V
I(min)
= V
+ V
.
DO(max load)
O(max)
NOTE 1: Continuous current and operating junction temperature are limited by internal protection circuitry, but it is not recommended that the
device operate under conditions beyond those specified in this table for extended periods of time.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS77101, TPS77118, TPS77127, TPS77128, TPS77133 WITH RESET OUTPUT
TPS77201, TPS77218, TPS77227, TPS77228, TPS77233 WITH POWER GOOD OUTPUT
150-mA LDO REGULATORS WITH INTEGRATED RESET OR PG
SLVS225A – FEBRUARY 2000 – REVISED MARCH 2000
electrical characteristics over recommended operating junction temperature range (–40°C to
125°C), V = V
+ 1 V, I = 1 mA, EN = 0 V, C = 10 µF (unless otherwise noted)
I
O(typ)
O
O
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.5 V ≤ V ≤ 5.5 V,
T = 25°C
J
V
O
Adjustable
O
voltage
1.5 V ≤ V ≤ 5.5 V
0.98V
1.02V
O
O
O
T = 25°C,
2.8 V < V < 10 V
IN
1.8
2.7
J
1.8 V Output
2.8 V < V < 10 V
IN
1.764
1.836
T = 25°C,
J
3.7 V < V < 10 V
IN
Output voltage
(see Notes 2 and 4)
2.7 V Output
2.8 V Output
3.3 V Output
V
3.7 V < V < 10 V
IN
2.646
2.744
3.234
2.754
2.856
3.366
125
T = 25°C,
J
3.8 V < V < 10 V
IN
2.8
3.8 V < V < 10 V
IN
T = 25°C,
J
4.3 V < V < 10 V
IN
3.3
4.3 V < V < 10 V
IN
T = 25°C
J
92
Quiescent current (GND current) (see Notes 2 and 4)
µA
V
V
+ 1 V < V ≤ 10 V, T = 25°C
0.005
%/V
%/V
mV
Output voltage line regulation (∆V /V
(see Note 3)
)
O
I
J
O
O
+ 1 V < V ≤ 10 V
0.05
O
I
Load regulation
T = 25°C
J
1
BW = 300 Hz to 100 kHz, T = 25°C,
TPS77118, TPS77218
J
Output noise voltage
55
µVrms
Output current Limit
Peak output current
V
= 0 V
0.9
400
144
1.3
A
O
2 ms pulse width,
50% duty cycle
mA
°C
Thermal shutdown junction temperature
EN = V
EN = V
T = 25°C
J
1
3
µA
µA
I,
I
Standby current
Adjustable
Voltage
FB input current
FB = 1.5 V
1
µA
High level enable input voltage
Low level enable input voltage
Enable input current
2
V
V
0.7
1
–1
µA
dB
V
Power supply ripple rejection (TPS77118, TPS77218) f = 1 KHz,
T = 25°C
55
J
Minimum input voltage for valid PG
Trip threshold voltage
Hysteresis voltage
I
= 300µA
V
(PG)
≤ 0.8 V
1.1
(PG)
V
decreasing
79
85
%V
%V
V
O
O
PG
(TPS772xx)
Measured at V
0.5
O
O
Output low voltage
V = 2.7 V,
I
= 1mA
0.15
0.4
1
I
(PG)
Leakage current
V
= 5 V
µA
(PG)
NOTES: 2. Minimum input operating voltage is 2.7 V or V
current 1 mA.
+ 1 V, whichever is greater. Maximum input voltage = 10 V, minimum output
O(typ)
3. If V < 1.8 V then V
imax
= 10 V, V
= 2.7 V:
O
imin
V
V
2.7 V
O
imax
100
Line Regulation (mV)
% V
1000
If V > 2.5 V then V
= 10 V, V
= Vo + 1 V:
O
imax
imin
V
V
V
1
O
imax
100
O
Line Regulation (mV)
% V
1000
4.
I
O
= 1 mA to 150 mA
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS77101, TPS77118, TPS77127, TPS77128, TPS77133 WITH RESET OUTPUT
TPS77201, TPS77218, TPS77227, TPS77228, TPS77233 WITH POWER GOOD OUTPUT
150-mA LDO REGULATORS WITH INTEGRATED RESET OR PG
SLVS225A – FEBRUARY 2000 – REVISED MARCH 2000
electrical characteristics over recommended operating junction temperature range (–40°C to
125°C), V = V
+ 1 V, I = 1 mA, EN = 0 V, C = 10 µF (unless otherwise noted) (continued)
I
O(typ)
O
O
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Minimum input voltage for valid RESET
Trip threshold voltage
Hysteresis voltage
I
= 300 µA
1.1
V
(RESET)
V
decreasing
92
98
%V
%V
V
O
O
Measured at V
0.5
Reset
(TPS771xx)
O
O
Output low voltage
V = 2.7 V,
I
= 1 mA
0.15
0.4
1
I
(RESET)
Leakage current
V
= 5 V
µA
(RESET)
RESET time-out delay
220
150
ms
I
O
I
O
I
O
I
O
= 150 mA,
= 150 mA,
= 150 mA,
= 150 mA
T = 25°C
J
2.8 V
Output
265
200
V
DO
Dropout voltage (see Note 5)
mV
T = 25°C
J
115
3.3 V
Output
NOTE 5: IN voltage equals V (Typ) – 100 mV; 1.8 V, and 2.7 V dropout voltage limited by input voltage range limitations (i.e., 3.3 V input voltage
O
needs to drop to 3.2 V for purpose of this test).
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
vs Output current
vs Junction temperature
vs Junction temperature
vs Frequency
2, 3
4, 5
6
V
Output voltage
O
Ground current
Power supply rejection ratio
Output spectral noise density
Output impedance
7
vs Frequency
8
Z
o
vs Frequency
9
vs Input voltage
10
V
DO
Dropout voltage
vs Junction temperature
11
Line transient response
Load transient response
Output voltage
12, 14
13, 15
16
vs Time
Equivalent series resistance (ESR)
vs Output current
18 – 21
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS77101, TPS77118, TPS77127, TPS77128, TPS77133 WITH RESET OUTPUT
TPS77201, TPS77218, TPS77227, TPS77228, TPS77233 WITH POWER GOOD OUTPUT
150-mA LDO REGULATORS WITH INTEGRATED RESET OR PG
SLVS225A – FEBRUARY 2000 – REVISED MARCH 2000
TYPICAL CHARACTERISTICS
TPS77x33
TPS77x18
OUTPUT VOLTAGE
vs
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
OUTPUT CURRENT
3.302
1.802
1.801
3.301
3.3
1.800
1.799
1.798
3.299
3.298
0
50
100
150
0
50
100
150
I
O
– Output Current – mA
I
O
– Output Current – mA
Figure 2
Figure 3
TPS77x33
TPS77x18
OUTPUT VOLTAGE
vs
OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
1.86
1.84
3.35
3.33
V = 2.8 V
I
V = 4.3 V
I
I
O
= 150 mA
1.82
1.80
1.78
3.31
3.29
I
O
= 150 mA
3.27
3.25
1.77
–40
0
T
40
80
120
140
–40
0
T
40
80
120
140
– Junction Temperature – °C
J
– Junction Temperature – °C
J
Figure 4
Figure 5
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS77101, TPS77118, TPS77127, TPS77128, TPS77133 WITH RESET OUTPUT
TPS77201, TPS77218, TPS77227, TPS77228, TPS77233 WITH POWER GOOD OUTPUT
150-mA LDO REGULATORS WITH INTEGRATED RESET OR PG
SLVS225A – FEBRUARY 2000 – REVISED MARCH 2000
TYPICAL CHARACTERISTICS
TPS77xxx
GROUND CURRENT
vs
JUNCTION TEMPERATURE
115
110
I
O
= 150 mA
105
100
95
I
O
= 1 mA
90
85
80
–40
10
60
110
140
T
J
– Junction Temperature – °C
Figure 6
TPS77x33
TPS77x33
POWER SUPPLY REJECTION RATIO
OUTPUT SPECTRAL NOISE DENSITY
vs
vs
FREQUENCY
FREQUENCY
10
100
90
80
70
60
50
40
30
20
10
0
C
T
= 10 µF
= 25°C
O
J
C
= 10 µF
= 25°C
O
I
= 1 mA
L
T
J
I
L
= 150 mA
1
I
= 1 mA
L
0.1
0.01
I
= 150 mA
L
100
1k
10k
100k
10
100
1k
10k
100k
1M
10M
f – Frequency – Hz
f – Frequency – Hz
Figure 7
Figure 8
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS77101, TPS77118, TPS77127, TPS77128, TPS77133 WITH RESET OUTPUT
TPS77201, TPS77218, TPS77227, TPS77228, TPS77233 WITH POWER GOOD OUTPUT
150-mA LDO REGULATORS WITH INTEGRATED RESET OR PG
SLVS225A – FEBRUARY 2000 – REVISED MARCH 2000
TYPICAL CHARACTERISTICS
TPS77x33
OUTPUT IMPEDANCE
vs
FREQUENCY
10
I
L
= 1 mA
1
0.1
I
L
= 150 mA
0.01
10
100
1k
10k
100k
1M
10M
f – Frequency – Hz
Figure 9
TPS77x33
TPS77x01
DROPOUT VOLTAGE
vs
DROPOUT VOLTAGE
vs
JUNCTION TEMPERATURE
INPUT VOLTAGE
250
200
150
100
300
I
= 150 mA
O
250
200
150
T
J
= 125 °C
T
J
= 25 °C
T
J
= –40 °C
I
O
= 150 mA
100
I
= 10 mA
O
50
0
50
0
I
O
= 0 A
2.7
3.2
3.7
4.2
4.7
–40
0
T
40
80
120
140
V – Input Voltage – V
I
– Junction Temperature – °C
J
Figure 10
Figure 11
12
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TPS77101, TPS77118, TPS77127, TPS77128, TPS77133 WITH RESET OUTPUT
TPS77201, TPS77218, TPS77227, TPS77228, TPS77233 WITH POWER GOOD OUTPUT
150-mA LDO REGULATORS WITH INTEGRATED RESET OR PG
SLVS225A – FEBRUARY 2000 – REVISED MARCH 2000
TYPICAL CHARACTERISTICS
TPS77x18
TPS77x18
LINE TRANSIENT RESPONSE
LOAD TRANSIENT RESPONSE
3.8
2.8
150
0
10
0
0
–50
–10
I
C
T
= 150 mA
O
C
= 10 µF
O
–100
= 10 µF
O
T
J
= 25°C
= 25°C
J
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
t – Time – ms
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
t – Time – ms
1
Figure 12
Figure 13
TPS77x33
TPS77x33
LINE TRANSIENT RESPONSE
LOAD TRANSIENT RESPONSE
C
= 10 µF
= 25°C
O
T
J
5.3
4.3
150
0
+10
0
0
–50
–10
C
= 10 µF
= 25°C
= 150 mA
O
T
I
J
–100
O
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
t – Time – ms
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
t – Time – ms
1
Figure 14
Figure 15
13
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TPS77101, TPS77118, TPS77127, TPS77128, TPS77133 WITH RESET OUTPUT
TPS77201, TPS77218, TPS77227, TPS77228, TPS77233 WITH POWER GOOD OUTPUT
150-mA LDO REGULATORS WITH INTEGRATED RESET OR PG
SLVS225A – FEBRUARY 2000 – REVISED MARCH 2000
TYPICAL CHARACTERISTICS
TPS77x33
OUTPUT VOLTAGE
vs
TIME (AT STARTUP)
C
= 10 µF
= 25°C
O
EN
0
T
J
0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
t – Time – ms
Figure 16
To Load
IN
V
I
OUT
+
R
L
C
O
EN
GND
ESR
Figure 17. Test Circuit for Typical Regions of Stability (Figures 25 through 28) (Fixed Output Options)
14
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TPS77101, TPS77118, TPS77127, TPS77128, TPS77133 WITH RESET OUTPUT
TPS77201, TPS77218, TPS77227, TPS77228, TPS77233 WITH POWER GOOD OUTPUT
150-mA LDO REGULATORS WITH INTEGRATED RESET OR PG
SLVS225A – FEBRUARY 2000 – REVISED MARCH 2000
TYPICAL CHARACTERISTICS
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE
vs
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE
vs
†
†
OUTPUT CURRENT
OUTPUT CURRENT
10
10
Region of Instability
Region of Instability
V
C
= 3.3 V
= 1 µF
O
O
V = 4.3 V
I
J
1
T
= 25°C
Region of Stability
1
Region of Stability
0.1
V
C
= 3.3 V
= 10 µF
O
O
V = 4.3 V
I
J
T
= 25°C
Region of Instability
100
Region of Instability
100 150
0.1
0.01
0
50
150
0
50
I
O
– Output Current – mA
I
O
– Output Current – mA
Figure 18
Figure 19
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE
vs
TYPICAL REGION OF STABILITY
†
†
EQUIVALENT SERIES RESISTANCE
vs
OUTPUT CURRENT
OUTPUT CURRENT
10
10
Region of Instability
Region of Instability
V
C
= 3.3 V
= 1 µF
O
O
V = 4.3 V
I
J
1
T
= 125 °C
Region of Stability
1
Region of Stability
0.1
V
C
= 3.3 V
= 10 µF
O
O
V = 4.3 V
I
J
T
= 125°C
Region of Instability
100
Region of Instability
100 150
0.1
0.01
0
50
150
0
50
I
O
– Output Current – mA
I
O
– Output Current – mA
Figure 20
Figure 21
†
Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any series resistance added
externally, and PWB trace resistance to C
.
O
15
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TPS77101, TPS77118, TPS77127, TPS77128, TPS77133 WITH RESET OUTPUT
TPS77201, TPS77218, TPS77227, TPS77228, TPS77233 WITH POWER GOOD OUTPUT
150-mA LDO REGULATORS WITH INTEGRATED RESET OR PG
SLVS225A – FEBRUARY 2000 – REVISED MARCH 2000
APPLICATION INFORMATION
pin functions
enable (EN)
The EN terminal is an input which enables or shuts down the device. If EN is a logic high, the device will be in
shutdown mode. When EN goes to logic low, then the device will be enabled.
power good (PG) (TPS772xx)
The PG terminal is an open drain, active high output that indicates the status of V (output of the LDO). When
out
V
reaches 82% of the regulated voltage, PG will go to a high impedance state. It will go to a low-impedance
out
state when V falls below 82% (i.e. over load condition) of the regulated voltage. The open drain output of the
out
PG terminal requires a pullup resistor
.
sense (SENSE)
The SENSE terminal of the fixed-output options must be connected to the regulator output, and the connection
should be as short as possible. Internally, SENSE connects to a high-impedance wide-bandwidth amplifier
through a resistor-divider network and noise pickup feeds through to the regulator output. It is essential to route
the SENSE connection in such a way to minimize/avoid noise pickup. Adding RC networks between the SENSE
terminal and V to filter noise is not recommended because it may cause the regulator to oscillate.
out
feedback (FB)
FB is an input terminal used for the adjustable-output options and must be connected to an external feedback
resistor divider. The FB connection should be as short as possible. It is essential to route it in such a way to
minimize/avoid noise pickup. Adding RC networks between FB terminal and V
recommended because it may cause the regulator to oscillate.
to filter noise is not
out
reset (RESET) (TPS771xx)
TheRESETterminalisanopendrain, activelowoutputthatindicatesthestatusofV . WhenV reaches95%
out
out
of the regulated voltage, RESET will go to a low-impedance state after a 220-ms delay. RESET will go to a
high-impedance state when V is below 95% of the regulated voltage. The open-drain output of the RESET
out
terminal requires a pullup resistor.
16
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TPS77101, TPS77118, TPS77127, TPS77128, TPS77133 WITH RESET OUTPUT
TPS77201, TPS77218, TPS77227, TPS77228, TPS77233 WITH POWER GOOD OUTPUT
150-mA LDO REGULATORS WITH INTEGRATED RESET OR PG
SLVS225A – FEBRUARY 2000 – REVISED MARCH 2000
APPLICATION INFORMATION
external capacitor requirements
An input capacitor is not usually required; however, a bypass capacitor (0.047 µF or larger) improves load
transient response and noise rejection if the TPS771xx or TPS772xx is located more than a few inches from
the power supply. A higher-capacitance capacitor may be necessary if large (hundreds of milliamps) load
transients with fast rise times are anticipated.
Most low noise LDOs require an external capacitor to further reduce noise. This will impact the cost and board
space. TheTPS771xxandTPS772xxhaveverylownoisespecificationrequirementswithoutusinganyexternal
components.
Like all low dropout regulators, the TPS771xx or TPS772xx requires an output capacitor connected between
OUT (output of the LDO) and GND (signal ground) to stabilize the internal control loop. The minimum
recommended capacitance value is 1 µF provided the ESR meets the requirement in Figures 19 and 21. In
addition, a low-ESR capacitor can be used if the capacitance is at least 10 µF and the ESR meets the
requirements in Figures 18 and 20. Solid tantalum electrolytic, aluminum electrolytic, and multilayer ceramic
capacitors are all suitable, provided they meet the requirements described previously.
Ceramic capacitors have different types of dielectric material with each exhibiting different temperature and
voltage variation. The most common types are X5R, X7R, Y5U, Z5U, and NPO. The NPO type ceramic type
capacitors are generally the most stable over temperature. However, the X5R and X7R are also relatively stable
over temperature (with the X7R being the more stable of the two) and are therefore acceptable to use. The Y5U
and Z5U types provide high capacitance in a small geometry, but exhibit large variations over temperature;
therefore, the Y5U and Z5U are not generally recommended for use on this LDO. Independent of which type
of capacitor is used, one must make certain that at the worst case condition the capacitance/ESR meets the
requirement specified in Figures 18 – 21.
17
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TPS77101, TPS77118, TPS77127, TPS77128, TPS77133 WITH RESET OUTPUT
TPS77201, TPS77218, TPS77227, TPS77228, TPS77233 WITH POWER GOOD OUTPUT
150-mA LDO REGULATORS WITH INTEGRATED RESET OR PG
SLVS225A – FEBRUARY 2000 – REVISED MARCH 2000
APPLICATION INFORMATION
Figure 22 shows the output capacitor and its parasitic impedances in a typical LDO output stage.
I
out
LDO
+
R
V
ESR
ESR
–
V
V
in
out
R
LOAD
C
out
Figure 22. – LDO Output Stage With Parasitic Resistances ESR and ESL
In steady state (dc state condition), the load current is supplied by the LDO (solid arrow) and the voltage across
the capacitor is the same as the output voltage (V = V . This means no current is flowing into the C
Cout
out)
out
branch. If I
suddenly increases (transient condition), the following occurs;
out
The LDO is not able to supply the sudden current need due to its response time (t in Figure 23). Therefore,
1
capacitor C provides the current for the new load condition (dashed arrow). C now acts like a battery with
out
out
an internal resistance, ESR. Depending on the current demand at the output, a voltage drop will occur at R
.
ESR
This voltage is shown as V
in Figure 22.
ESR
When C is conducting current to the load, initial voltage at the load will be V = V
– V
. Due to the
ESR
out
out
Cout
1
discharge of C , the output voltage V will drop continuously until the response time t of the LDO is reached
out
out
and the LDO will resume supplying the load. From this point, the output voltage starts rising again until it reaches
the regulated voltage. This period is shown as t in Figure 23.
2
The figure also shows the impact of different ESRs on the output voltage. The left brackets show different levels
of ESRs where number 1 displays the lowest and number 3 displays the highest ESR.
From above, the following conclusions can be drawn:
The higher the ESR, the larger the droop at the beginning of load transient.
The smaller the output capacitor, the faster the discharge time and the bigger the voltage droop during the
LDO response period.
18
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TPS77101, TPS77118, TPS77127, TPS77128, TPS77133 WITH RESET OUTPUT
TPS77201, TPS77218, TPS77227, TPS77228, TPS77233 WITH POWER GOOD OUTPUT
150-mA LDO REGULATORS WITH INTEGRATED RESET OR PG
SLVS225A – FEBRUARY 2000 – REVISED MARCH 2000
APPLICATION INFORMATION
conclusion
To minimize the transient output droop, capacitors must have a low ESR and be large enough to support the
minimum output voltage requirement.
I
out
V
out
1
2
ESR 1
ESR 2
3
ESR 3
t
t
1
2
Figure 23. – Correlation of Different ESRs and Their Influence to the Regulation of V
at a
out
Load Step From Low-to-High Output Current
19
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TPS77101, TPS77118, TPS77127, TPS77128, TPS77133 WITH RESET OUTPUT
TPS77201, TPS77218, TPS77227, TPS77228, TPS77233 WITH POWER GOOD OUTPUT
150-mA LDO REGULATORS WITH INTEGRATED RESET OR PG
SLVS225A – FEBRUARY 2000 – REVISED MARCH 2000
APPLICATION INFORMATION
programming the TPS77x01 adjustable LDO regulator
The output voltage of the TPS77x01 adjustable regulator is programmed using an external resistor divider as
shown in Figure 28. The output voltage is calculated using:
R1
R2
(1)
V
V
1
O
ref
Where:
V
= 1.1834 V typ (the internal reference voltage)
ref
Resistors R1 and R2 should be chosen for approximately 7-µA divider current. Lower value resistors can be
used but offer no inherent advantage and waste more power. Higher values should be avoided as leakage
currents at FB increase the output voltage error. The recommended design procedure is to choose
R2 = 30.1 kΩ to set the divider current at 7 µA and then calculate R1 using:
V
O
R1
1
R2
(2)
V
ref
OUTPUT VOLTAGE
PROGRAMMING GUIDE
TPS77x01
OUTPUT
VOLTAGE
R1
R2
UNIT
PG or
RESET
V
I
IN
PG or RESET Output
250 kΩ
0.1 µF
2.5 V
3.3 V
3.6 V
174
287
324
169
169
169
kΩ
kΩ
kΩ
EN
OUT
V
O
R1
C
O
NOTE: To reduce noise and prevent
oscillation, R1 and R2 need to be as
close as possible to the FB/SENSE
terminal.
FB/SENSE
GND
R2
Figure 24. TPS77x01 Adjustable LDO Regulator Programming
20
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150-mA LDO REGULATORS WITH INTEGRATED RESET OR PG
SLVS225A – FEBRUARY 2000 – REVISED MARCH 2000
APPLICATION INFORMATION
regulator protection
The TPS771xx or TPS772xx PMOS-pass transistor has a built-in back diode that conducts reverse currents
when the input voltage drops below the output voltage (e.g., during power down). Current is conducted from
the output to the input and is not internally limited. When extended reverse voltage is anticipated, external
limiting may be appropriate.
The TPS771xx or TPS772xx also features internal current limiting and thermal protection. During normal
operation, the TPS771xx or TPS772xx limits output current to approximately 0.9 A. When current limiting
engages, the output voltage scales back linearly until the overcurrent condition ends. While current limiting is
designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of
the package. If the temperature of the device exceeds 150°C(typ), thermal-protection circuitry shuts it down.
Once the device has cooled below 130°C(typ), regulator operation resumes.
power dissipation and junction temperature
Specified regulator operation is assured to a junction temperature of 125°C; the maximum junction temperature
should be restricted to 125°C under normal operating conditions. This restriction limits the power dissipation
the regulator can handle in any given application. To ensure the junction temperature is within acceptable limits,
calculate the maximum allowable dissipation, P
, and the actual dissipation, P , which must be less than
D(max)
D
or equal to P
.
D(max)
The maximum-power-dissipation limit is determined using the following equation:
T max
J
T
A
P
D(max)
R
JA
Where:
T max is the maximum allowable junction temperature
J
R
is the thermal resistance junction-to-ambient for the package, i.e., 266.2°C/W for the 8-terminal
θJA
MSOP with no airflow.
T is the ambient temperature.
A
The regulator dissipation is calculated using:
P
V
V
I
D
I
O
O
Power dissipation resulting from quiescent current is negligible. Excessive power dissipation will trigger the
thermal protection circuit.
21
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TPS77101, TPS77118, TPS77127, TPS77128, TPS77133 WITH RESET OUTPUT
TPS77201, TPS77218, TPS77227, TPS77228, TPS77233 WITH POWER GOOD OUTPUT
150-mA LDO REGULATORS WITH INTEGRATED RESET OR PG
SLVS225A – FEBRUARY 2000 – REVISED MARCH 2000
MECHANICAL DATA
DGK (R-PDSO-G8)
PLASTIC SMALL-OUTLINE PACKAGE
0,38
0,25
M
0,65
8
0,25
5
0,15 NOM
3,05
2,95
4,98
4,78
Gage Plane
0,25
0°–6°
1
4
0,69
3,05
2,95
0,41
Seating Plane
0,10
0,15
0,05
1,07 MAX
4073329/B 04/98
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-187
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
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Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
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TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
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Copyright 2000, Texas Instruments Incorporated
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