TPS78332DDCR_技术文档

TPS783xx

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SBVS133 –FEBRUARY 2010

500nA I_Q, 150mA, Ultra-Low Quiescent Current

Low-Dropout Linear Regulator

1

FEATURES

DESCRIPTION

2

•

Low I_Q: 500nA

The TPS783 family of low-dropout regulators (LDOs)

offers the benefits of ultra-low power (I_Q= 500nA),

and miniaturized packaging.

150mA, Low-Dropout Regulator

Low-Dropout at +25°C, 130mV at 150mA

Low-Dropout at +85°C, 175mV at 150mA

3% Accuracy Over Load/Line/Temperature

This LDO is designed specifically for battery-powered

applications where ultra-low quiescent current is a

critical parameter. The TPS783, with ultra-low I_Q

Available in Fixed Voltage Options Using

Innovative Factory EEPROM Programming

(500nA),

microcontrollers,

applications.

is

ideal

and

for

other

microprocessors,

battery-powered

•

Stable with a 1.0mF Ceramic Capacitor

Thermal Shutdown and Overcurrent Protection

CMOS Logic Level-Compatible Enable Pin

DDC (TSOT23-5) Package

The absence of pulldown circuitry at the output of the

TPS783 LDO gives an application the flexibility to use

the regulator output capacitor as a temporary backup

power supply for a short period of time without the

presence of the battery when the LDO is disabled

(during battery replacement).

APPLICATIONS

•

TI MSP430 Attach Applications

Power Rails with Programming Mode

Wireless Handsets, Smartphones, PDAs, MP3

Players, and Other Battery-Operated Handheld

Products

The ultra-low power and miniaturized packaging allow

designers to customize power consumption for

specific applications. Consult with your local factory

representative for exact voltage options and ordering

information; minimum order quantities may apply.

TPS783xxDDC

TSOT23-5

The TPS783 family is designed to be compatible with

the TI MSP430 and other similar products. The

enable pin (EN) is compatible with standard CMOS

logic. This LDO is stable with any output capacitor

greater than 1.0mF. Therefore, this device requires

minimal board space because of miniaturized

packaging and a potentially small output capacitor.

The TPS783 series also features thermal shutdown

and current limit to protect the device during fault

conditions. All packages have an operating

temperature range of T_J= –40°C to +105°C.

(TOP VIEW)

IN

GND

EN

1

2

3

5

4

OUT

GND

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS783xx

SBVS133 –FEBRUARY 2010

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

AVAILABLE OPTIONS⁽¹⁾

TPS78315

TPS78318

TPS78319

TPS78320

TPS78322

TPS78323

TPS78325

TPS78326

Output

Voltage (V)

1.5

1.8

1.9

2.0

2.2

2.3

2.5

2.6

TPS78328

TPS78329

TPS78330

TPS78332

TPS78333

TPS78336

TPS78342

Output

Voltage (V)

2.8

2.9

3.0

3.2

3.3

3.6

4.2

(1) Additional output voltage options are available on a quick-turn basis using innovative, factory EEPROM programming. Minimum-order

quantities may apply; contact your sales representative for details and availability

ORDERING INFORMATION⁽¹⁾

PRODUCT

V_OUT

TPS783xxyyyz

XX is the nominal output voltage

YYY is the package designator.

Z is the tape and reel quantity (R = 3000, T = 250).

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

At T_J= –40°C to +105°C, unless otherwise noted. All voltages are with respect to GND.

PARAMETER

TPS783xx

–0.3 to +6.0

UNIT

Input voltage range, V_IN

Enable

V

–0.3 to V_IN+ 0.3V

Output voltage range, V_OUT

Maximum output current, I_OUT

Output short-circuit duration

Total continuous power dissipation, P_DISS

Internally limited

Indefinite

See Dissipation Ratings Table

Human body model (HBM)

Charged device model (CDM)

2

kV

V

ESD rating

500

Operating junction temperature range, T_J

Storage temperature range, T_STG

–40 to +105

–55 to +150

°C

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may

degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond

those specified is not implied.

DISSIPATION RATINGS

DERATING FACTOR

BOARD

PACKAGE

R_qJC

R_qJA

ABOVE T_A= +25°C

T_A< +25°C

T_A= +70°C

T_A= +85°C

High-K⁽¹⁾

DDC

90°C/W

200°C/W

5.0mW/°C

500mW

275mW

200mW

(1) The JEDEC high-K (2s2p) board used to derive this data was a 3-inch × 3-inch, multilayer board with 1-ounce internal power and

ground planes and 2-ounce copper traces on top and bottom of the board.

2

TPS783xx

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SBVS133 –FEBRUARY 2010

ELECTRICAL CHARACTERISTICS

Over operating temperature range (T_J= –40°C to +105°C), V_IN= V_OUT(NOM)+ 0.5V or 2.2V, whichever is greater;

I_OUT= 100mA, V_EN= V_IN, C_OUT= 1.0mF, fixed V_OUTtest conditions, unless otherwise noted. Typical values at T_J= +25°C.

TPS783xx

PARAMETER

TEST CONDITIONS

MIN

2.2

–2

TYP

MAX

5.5

UNIT

V

V_IN

Input voltage range

Nominal

T_J= +25°C

±1

+2

%

V_OUT

DC output accuracy

Over V_IN, I_OUT

temperature

,

V_OUT+ 0.5V ≤ V_IN≤ 5.5V,

100mA ≤ I_OUT≤ 150mA

–3.0

±2.0

+3.0

%

ΔV_OUT/ΔV_INLine regulation

ΔV_OUT/ΔI_OUTLoad regulation

V_OUT(NOM)+ 0.5V ≤ V_IN≤ 5.5V

100mA ≤ I_OUT≤ 150mA

±1.0

130

%

V_DO

Dropout voltage⁽¹⁾

Output noise voltage

Output current limit

V_IN= 95% V_OUT(NOM), I_OUT= 150mA

250

mV

BW = 100Hz to 100kHz, V_IN= 2.2V,

V_OUT= 1.2V, I_OUT= 1mA

V_N

86

mV_RMS

I_CL

V_OUT= 0.90 × V_OUT(NOM)

I_OUT= 0mA

150

230

420

8

400

800

mA

nA

mA

nA

I_GND

Ground pin current

I_OUT= 150mA

I_SHDN

Shutdown current (I_GND

)

V_EN≤ 0.4V, V_IN(MIN)≤ V_IN< 5.5V

18

150

500

Output leakage current at

shutdown⁽²⁾

V_IN= Open, V_EN= 0.4V,

V_OUT= V_OUT(NOM)

I_OUT-SHDN

170

nA

V_ENHI

V_ENLO

I_EN

Enable high-level voltage

Enable low-level voltage

EN pin current

V_IN= 5.5V

1.2

0

V_IN

0.4

40

V

V_IN= 5.5V

V

V_IN= V_EN= 5.5V

3

40

20

15

nA

dB

f = 10Hz

V_IN= 4.3V,

V_OUT= 3.3V,

I_OUT= 150mA

PSRR

t_STR

Power-supply rejection ratio

Startup time⁽³⁾

f = 100Hz

f = 1kHz

C_OUT= 1.0mF, V_OUT= 10% V_OUT(NOM)to

V_OUT= 90% V_OUT(NOM)

500

ms

Shutdown, temperature increasing

Reset, temperature decreasing

+160

+140

°C

T_SD

T_J

Thermal shutdown temperature

Operating junction temperature

–40

+105

(1) V_DOis not measured for devices with V_OUT(NOM)≤ 2.3V because minimum V_IN= 2.2V.

(2) See Shutdown in the Application Information section for more details.

(3) Time from V_EN= 1.2V to V_OUT= 90% (V_OUT(NOM)).

3

TPS783xx

SBVS133 –FEBRUARY 2010

www.ti.com

FUNCTIONAL BLOCK DIAGRAM

IN

OUT

Current

Limit

Thermal

Shutdown

EEPROM

Bandgap

EN

Logic

GND

PIN CONFIGURATIONS

DDC PACKAGE

TSOT23-5

(TOP VIEW)

IN

GND⁽¹⁾

EN

1

2

3

5

4

OUT

GND⁽¹⁾

(1) All ground pins must be connected to ground for proper operation.

Table 1. PIN DESCRIPTIONS

NAME

DDC

DESCRIPTION

Regulated output voltage pin. A small (1mF) ceramic capacitor is needed from this pin to ground to

assure stability. See the Input and Output Capacitor Requirements in the Application Information

section for more details.

OUT

5

N/C

EN

—

3

Not connected.

Driving the enable pin (EN) over 1.2V turns ON the regulator. Driving this pin below 0.4V puts the

regulator into shutdown mode, reducing operating current to 18nA typical.

GND

2, 4

ALL ground pins must be tied to ground for proper operation.

Input pin. A small capacitor is needed from this pin to ground to assure stability. Typical input capacitor

= 1.0mF. Both input and output capacitor grounds should be tied back to the IC ground with no

significant impedance between them.

IN

1

Thermal pad

—

It is recommended that the thermal pad on the SON-6 package be connected to ground.

4

TPS783xx

www.ti.com

SBVS133 –FEBRUARY 2010

TYPICAL CHARACTERISTICS

Over the operating temperature range of T_J= –40°C to +105°C, V_IN= V_OUT(TYP)+ 0.5V or 2.2V, whichever is greater;

I_OUT= 100mA, V_EN= V_IN, C_OUT= 1mF, and C_IN= 1mF, unless otherwise noted.

TPS78330 LINE REGULATION

I_OUT= 5mA, V_OUT(NOM)= 3.0V

TPS78330 LINE REGULATION

I_OUT= 150mA, V_OUT(NOM)= 3.0V

1.0

0.8

3

2

-40°C

0.6

0.4

1

+85°C

+25°C

-40°C

0.2

+25°C

0

+105°C

-0.2

-0.4

-0.6

-0.8

-1.0

+105°C

+85°C

-1

-2

-3

3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5

V_IN(V)

3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5

V_IN(V)

Figure 1.

Figure 2.

TPS78330 LOAD REGULATION

V_IN= 3.5V, V_OUT(NOM)= 3.0V

TPS78330 DROPOUT VOLTAGE vs OUTPUT CURRENT

V_OUT(NOM)= 3.0V, V_IN= 0.95 × V_OUT(NOM)

3

2

200

+85°C

150

+105°C

1

-40°C

+25°C

+85°C

0

100

+105°C

-1

-2

-3

+25°C

50

-40°C

0

25

50

75

100

125

150

0

25

50

75

100

125

150

I_OUT(mA)

Figure 3.

Figure 4.

TPS78330 DROPOUT VOLTAGE vs JUNCTION TEMPERATURE

V_OUT(NOM)= 3.0V, V_IN= 0.95 × V_OUT(NOM)

250

200

150

100

50

100mA

50mA

150mA

10mA

0

-40 -25 -10

5

20 35 50 65 80 95 110 125

T_J(°C)

Figure 5.

5

TPS783xx

SBVS133 –FEBRUARY 2010

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TYPICAL CHARACTERISTICS (continued)

Over the operating temperature range of T_J= –40°C to +105°C, V_IN= V_OUT(TYP)+ 0.5V or 2.2V, whichever is greater;

I_OUT= 100mA, V_EN= V_IN, C_OUT= 1mF, and C_IN= 1mF, unless otherwise noted.

TPS78330 GROUND PIN CURRENT vs INPUT VOLTAGE

I_OUT= 0mA, V_OUT(NOM)= 3.0V

TPS78330 CURRENT LIMIT vs INPUT VOLTAGE

V_OUT= 95% V_OUT(NOM), V_OUT(NOM)= 3.0V

900

800

700

300

290

280

270

260

250

240

230

220

210

200

+85°C

600

500

400

300

-40°C

200

+25°C

100

0

+85°C

+105°C

3.8

4.0

4.2

4.4

4.6

4.8

5.0

5.2

5.4 5.5

3.5 3.7 3.9 4.1 4.3

4.5 4.7 4.9 5.1 5.3 5.5

V_IN(V)

Figure 6.

Figure 7.

TPS78330 ENABLE PIN CURRENT vs INPUT VOLTAGE

TPS78330 ENABLE PIN HYSTERESIS vs

I_OUT= 100mA, V_OUT(NOM)= 3.0V

JUNCTION TEMPERATURE, I_OUT= 1mA, V_OUT(NOM)= 3.0V

1.2

3.0

2.7

1.1

+105°C

2.4

2.1

1.8

1.5

1.2

0.9

0.6

0.3

0

1.0

V_ENOn

0.9

0.8

0.7

+85°C

V_ENOff

0.6

0.5

0.4

+25°C

-40°C

-40 -25 -10

5

20 35 50 65 80 95 110 125

3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5

V_IN(V)

T_J(°C)

Figure 8.

Figure 9.

TPS78330 OUTPUT CURRENT LEAKAGE AT SHUTDOWN

V_OUT= V_OUT(NOM)= 3.0V, V_EN= 0.4V

250

200

150

+105°C

100

+85°C

+25°C

50

0

-40°C

1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0

V_OUT(V)

Figure 10.

6

TPS783xx

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SBVS133 –FEBRUARY 2010

TYPICAL CHARACTERISTICS (continued)

Over the operating temperature range of T_J= –40°C to +105°C, V_IN= V_OUT(TYP)+ 0.5V or 2.2V, whichever is greater;

I_OUT= 100mA, V_EN= V_IN, C_OUT= 1mF, and C_IN= 1mF, unless otherwise noted.

TPS78330

TPS78330 OUTPUT SPECTRAL NOISE DENSITY

%ΔV_OUTvs JUNCTION TEMPERATURE

C_IN= 1mF, C_OUT= 2.2mF, V_IN= 3.5V, V_OUT(NOM)= 3.0V

V_IN= 3.5V, V_OUT(NOM)= 3.0V

100

10

1

3

2

10mA

100mA

1

150mA

0

150mA

5mA

0.1

0.01

-1

-2

-3

50mA

1mA

1mA = 130mV_RMS

50mA = 134mV_RMS

150mA = 138.0mV_RMS

0.001

10

100

1k

10k

100k

-40 -25 -10

5

20 35 50 65 80 95 110 125

T_J(°C)

Frequency (Hz)

Figure 11.

Figure 12.

TPS78330 RIPPLE REJECTION vs FREQUENCY

TPS78330 INPUT VOLTAGE RAMP vs

OUTPUT VOLTAGE

V_IN= 3.5V, V_OUT(NOM= 3.0V, C_OUT= 2.2mF

80

V_IN= 0.0V to 5.0V

V_IN

V_OUT= 3.0V

I_OUT= 150mA

C_OUT= 10mF

70

60

50

40

30

20

10

0

1mA

Enable

50mA

V_OUT

Load Current

0V

150mA

Time (20ms/div)

10

100

1k

10k

100k

1M

Frequency (Hz)

Figure 13.

Figure 14.

TPS78330 OUTPUT VOLTAGE vs

ENABLE (SLOW RAMP)

TPS78330 INPUT VOLTAGE vs

DELAY TO OUTPUT

V_IN

Enable

V

_IN= 5.5V

_OUT= 3.0V

V

I_OUT= 150mA

C_OUT= 10mF

V_IN

V_OUT

V_ENABLE

V_IN= 5.5V

V_OUT= 3.0V

I_OUT= 150mA

C_OUT= 10mF

V_OUT

Load Current

0V

Time (20ms/div)

Time (500ms/div)

Figure 15.

Figure 16.

7

TPS783xx

SBVS133 –FEBRUARY 2010

www.ti.com

TYPICAL CHARACTERISTICS (continued)

Over the operating temperature range of T_J= –40°C to +105°C, V_IN= V_OUT(TYP)+ 0.5V or 2.2V, whichever is greater;

I_OUT= 100mA, V_EN= V_IN, C_OUT= 1mF, and C_IN= 1mF, unless otherwise noted.

TPS78330

LOAD TRANSIENT RESPONSE

Enable

V_IN

V_OUT

V_IN= 5.5V

V_OUT= 3.0V

I_OUT= 0mA to 10mA

Load

C_OUT= 10mF

Current

0A

Time (5ms/div)

Figure 17.

8

TPS783xx

www.ti.com

SBVS133 –FEBRUARY 2010

APPLICATION INFORMATION

X5R- and X7R-type capacitors are best because they

have minimal variation in value and ESR over

temperature. Maximum ESR should be less than

1.0Ω. With tolerance and dc bias effects, the

minimum capacitance to ensure stability is 1mF.

APPLICATION EXAMPLES

The TPS783 family of LDOs is factory-programmable

to have a fixed output. Note that during startup or

steady-state conditions, it is important that the EN pin

voltage never exceed V_IN+ 0.3V.

EXTENDING BATTERY LIFE IN KEEP-ALIVE

CIRCUITRY APPLICATIONS FOR MSP430

AND OTHER LOW-POWER

4.2V to 5.5V

2.7V

V_IN

V_OUT

IN

OUT

1mF

MICROCONTROLLERS

TPS78327

One of the primary advantages of a low quiescent

current LDO is its extremely low energy requirement.

Counter-intuitively, this requirement enables a longer

battery life compared to using only the battery as an

On

Off

EN

unregulated

voltage

supply

for

low-power

GND

microcontrollers such as the MSP430. Figure 19

illustrates the characteristic performance of an

unregulated (3.0V) battery supply versus a regulated

TPS783 supply for a typical MSP430 application.

Figure 18. Typical Application Circuit

90

Battery, V_CC= 3.0V

INPUT AND OUTPUT CAPACITOR

REQUIREMENTS

80

TPS783, V_CC= 2.2V

70

60

50

40

30

20

10

0

Although an input capacitor is not required for

stability, it is good analog design practice to connect

a 0.1mF to 1.0mF low equivalent series resistance

(ESR) capacitor across the input supply near the

regulator. This capacitor counteracts reactive input

sources and improves transient response, noise

rejection, and ripple rejection.

A

higher-value

capacitor may be necessary if large, fast rise-time

load transients are anticipated, or if the device is not

located near the power source. If source impedance

is not sufficiently low, a 0.1mF input capacitor may be

necessary to ensure stability.

5 10

20

30

40

50

60

70

80

90 100

Duty Cycle (Time in Active Mode) (%)

Calculated with an MSP430F model, operating at 6MHz.

The TPS783 series are designed to be stable with

standard ceramic capacitors with values of 1.0mF or

larger at the output.

Figure 19. Battery Life Comparison vs Duty Cycle

for MSP430 Application

Table 2 summarizes this comparison.

Table 2. Battery Life Comparison vs Active Mode Time for MSP430 Application

DUTY CYCLE

(%)

TPS783xx

(NO. OF DAYS)

BATTERY

(NO. OF DAYS)

1mA LDO

(NO. OF DAYS)

CONDITION/PERFORMANCE

Efficiency with V_BAT= 3.0V and V_CC= 2.2V (V_O/V_I)

LDO quiescent current (I_Q)

—

73%

0.5mA

2.19mA

0.5mA

5742

1320

151

100%

0

73%

1mA

MSP430 active current

—

3.09mA

0.6mA

6286

998

2.19mA

0.5mA

4373

1085

148

MSP430 low-power current

—

Active mode, 1 sec/hour

0.028

0.28

2.8

28

Active mode, 10 sec/hour

Active mode, 100 sec/hour

106

Active mode, 1000 sec/hour

15.4

10.7

3.0

15.4

Active mode, 100% duty cycle (on all the time)

100

4.2

9

TPS783xx

SBVS133 –FEBRUARY 2010

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SUPERCAPACITOR-BASED BACKUP

POWER

I_LP

The very low leakage current at the LDO output gives

a system the flexibility to use the device output

capacitor as a temporary backup power supply for a

short period of time, without the presence of the

battery when the LDO is disabled (during battery

replacement). The leakage current going into the

regulator output from the output capacitor, when the

LDO is disabled, is typically 170nA, see Figure 10.

IN

OUT

No Battery

C_OUT

MSP430

TPS783xx

10% Duty Cycle

EN = Low

EN

SVS

GND

150nA = I_LKG

Battery Low

Low-Power Mode

SYSTEM EXAMPLE

Figure 21. MSP430 Application While Battery is

Replaced

When the system is active, a voltage supervisor

enables the regulator and puts the MSP430 into

active mode when there is a battery installed and its

voltage is above a certain threshold, as shown in

Figure 20. (The dashed red line indicates the ground

current.)

The time that the capacitor can provide an

appropriate voltage level to the MSP430 (that is, the

maximum time it should take to replace a depleted

battery with a new battery), or t_MAX, can vary from a

few seconds to a few minutes, depending on several

factors, as Equation 1 shows:

I

mC

•

the nominal output of the regulator, V_OUT(Nom)

(equivalent to the initial voltage of the capacitor

when the regulator is disabled);

IN

OUT

Battery

MSP430

TPS783xx

10% Duty Cycle

•

the minimum voltage required by the MSP430,

EN = High

EN

V_MIN

the leakage current into the regulator output, or

I_LKG

;

SVS

GND

;

500nA

Battery OK

the current demand from the MSP430 in

low-power mode, or I_LP; and

the size of the output capacitor C_OUT

t_MAX

Figure 20. MSP430 Application in Active Mode

When the battery is depleted, the voltage supervisor

signals the user to replace the system battery. Once

the battery is removed, the voltage supervisor

disables the regulator and signals the MSP430 to go

into low-power mode. At this moment, the output

capacitor acts as a power supply for the MSP430

during the absence of the battery while it is being

replaced, as Figure 21 illustrates. (The dashed red

line indicates the ground current.)

V

_OUT(Nom)- V_MIN

C_OUT

=

I_LKG+ I_LP

(1)

The PMOS pass element in the TPS783 series has a

built-in body diode that conducts current when the

voltage at OUT exceeds the voltage at IN. This

current is not limited, so if extended reverse voltage

operation is anticipated, external limiting up to the

maximum rated current for the device may be

appropriate.

BOARD LAYOUT RECOMMENDATIONS TO

IMPROVE PSRR AND NOISE PERFORMANCE

To improve ac performance (such as PSRR, output

noise, and transient response), it is recommended

that the printed circuit board (PCB) be designed with

separate ground planes for V_INand V_OUT, with each

ground plane connected only at the GND pin of the

device. In addition, the output capacitor must be as

near to the ground pin of the device as possible to

ensure a common reference for regulation purposes.

High ESR capacitors may degrade PSRR.

10

TPS783xx

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SBVS133 –FEBRUARY 2010

INTERNAL CURRENT LIMIT

TRANSIENT RESPONSE

The TPS783 is internally current-limited to protect the

regulator during fault conditions. During current limit,

the output sources a fixed amount of current that is

largely independent of output voltage. For reliable

operation, the device should not be operated in a

current limit state for extended periods of time.

As with any regulator, increasing the size of the

output capacitor reduces over/undershoot magnitude

but increases duration of the transient response. For

more information, see Figure 17.

MINIMUM LOAD

The TPS783 series are stable with no output load.

Traditional PMOS LDO regulators suffer from lower

loop gain at very light output loads. The TPS783

employs an innovative, low-current circuit under very

light or no-load conditions, resulting in improved

output voltage regulation performance down to zero

output current. See Figure 17 for the load transient

response.

SHUTDOWN

The enable pin (EN) is active high and is compatible

with standard and low-voltage CMOS levels. When

shutdown capability is not required, EN should be

connected to the IN pin, as shown in Figure 22.

4.2V to 5.5V

2.7V

V_IN

V_OUT

IN

OUT

1mF

THERMAL INFORMATION

THERMAL PROTECTION

TPS78327

EN

Thermal protection disables the device output when

the junction temperature rises to approximately

+160°C, allowing the device to cool. Once the

junction temperature cools to approximately +140°C,

the output circuitry is enabled. Depending on power

dissipation, thermal resistance, and ambient

temperature, the thermal protection circuit may cycle

on and off again. This cycling limits the dissipation of

the regulator, protecting it from damage as a result of

overheating.

GND

Figure 22. Circuit Showing EN Tied High when

Shutdown Capability is Not Required

DROPOUT VOLTAGE

Any tendency to activate the thermal protection circuit

indicates excessive power dissipation or an

inadequate heatsink. For reliable operation, junction

temperature should be limited to +105°C maximum.

To estimate the margin of safety in a complete design

The TPS783 series use a PMOS pass transistor to

achieve low dropout. When (V_IN– V_OUT) is less than

the dropout voltage (V_DO), the PMOS pass device is

the linear region of operation and the input-to-output

resistance is the R_DS(ON)of the PMOS pass element.

V_DOapproximately scales with output current

because the PMOS device behaves like a resistor in

dropout. As with any linear regulator, PSRR and

(including

heatsink),

increase

the

ambient

temperature until the thermal protection is triggered;

use worst-case loads and signal conditions.

The internal protection circuitry of the TPS783 series

has been designed to protect against overload

conditions. However, it is not intended to replace

proper heatsinking. Continuously running the TPS783

series into thermal shutdown degrades device

reliability.

transient response are degraded as (V_IN– V_OUT

)

approaches dropout. This effect is shown in the

Typical Characteristics section. Refer to application

report SLVA207, Understanding LDO Dropout,

available for download from www.ti.com.

11

TPS783xx

SBVS133 –FEBRUARY 2010

www.ti.com

POWER DISSIPATION

dissipation depends on input voltage and load

conditions. Power dissipation (P_D) is equal to the

product of the output current times the voltage drop

across the output pass element (V_INto V_OUT), as

shown in Equation 2:

The ability to remove heat from the die is different for

each

package

type,

presenting

different

considerations in the PCB layout. The PCB area

around the device that is free of other components

moves the heat from the device to the ambient air.

Performance data for JEDEC low- and high-K boards

are given in the Dissipation Ratings table. Using

heavier copper increases the effectiveness in

removing heat from the device. The addition of plated

through-holes to heat-dissipating layers also

improves the heatsink effectiveness. Power

P_D= (V_IN- V_OUT) ´ I_OUT

(2)

PACKAGE MOUNTING

Solder pad footprint recommendations for the

TPS783 series are available from the Texas

Instruments web site at www.ti.com through the

TPS783 series product folders.

12

PACKAGE OPTION ADDENDUM

www.ti.com

4-Mar-2010

PACKAGING INFORMATION

Orderable Device

TPS78330DDCR

TPS78330DDCT

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SOT

DDC

5

3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

SOT

DDC

5

250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

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information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

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型号：	TPS78332DDCR
厂家：	TEXAS INSTRUMENTS
描述：	3.2V FIXED POSITIVE LDO REGULATOR, 0.25V DROPOUT, PDSO5, PLASTIC, SOT-5 光电二极管输出元件调节器
文件：	总15页 (文件大小：333K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS78332DDCR [TI]

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