TPS78512QWDRBRQ1 [TI]

1-A, High-PSRR Low-Dropout Voltage Regulator With High Accuracy and Enable;


型号：	TPS78512QWDRBRQ1
厂家：	TEXAS INSTRUMENTS
描述：	1-A, High-PSRR Low-Dropout Voltage Regulator With High Accuracy and Enable
文件：	总42页 (文件大小：2978K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS785-Q1

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SBVS388A – JANUARY 2021 – REVISED APRIL 2021

TPS785-Q1

1-A, High-PSRR Low-Dropout Voltage Regulator With High Accuracy and Enable

1 Features

3 Description

•

AEC-Q100 qualified for automotive applications:

– Temperature grade 1: –40°C to +125°C, T_A

Device junction temperature: –40°C to +150°C, T_J

Input voltage range: 1.7 V to 6.0 V

Available output voltages:

– Adjustable option: 1.2 V to 5.5 V

– Fixed options: 0.65 V to 5.0 V

Output accuracy: 0.5% typical, 1.7% maximum

Low I_Q: 25 μA (typical)

The TPS785-Q1 ultra low-dropout regulator (LDO) is

a small, low quiescent current LDO that can source

1 A with excellent line and load transient performance.

•

The low output noise and great PSRR performance

make the device suitable to power-sensitive analog

loads. The TPS785-Q1 is a flexible device for post

regulation because this device supports an input

voltage range from 1.7 V to 6.0 V and offers an

adjustable output range of 1.2 V to 5.5 V. The device

also features fixed output voltages from 0.65 V to

5.0 V for powering common voltage rails.

•

Ultra-low dropout:

– 315 mV (max) at 1 A (3.3 V_OUT

)

•

Internal 550 μs soft-start time to reduce inrush

current

Active output discharge

Packages:

– 3-mm × 3-mm wettable flank VSON (8)

– 5-pin TO-252, R_θJA= 31.6°C/W

The TPS785-Q1 offers foldback current limit to reduce

power dissipation during a over current condition. The

EN input helps with power sequencing requirements

of the system. The internal soft-start provides a

controlled start up reducing the inrush current allowing

for lower input capacitance to be used.

•

2 Applications

The TPS785-Q1 provides an active pulldown circuit to

quickly discharge output loads when disabled.

•

Automotive head units

Hybrid instrument clusters

Telematics control units

Medium- and short-range radar

DC/DC converters

Device Information⁽¹⁾

PART NUMBER

PACKAGE

BODY SIZE (NOM)

3.00 mm x 3.00 mm

6.10 mm x 6.60 mm

Wettable flank

VSON (8)

TPS785-Q1

TO-252 (5)

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

VIN

VOUT

OUT

CIN

COUT

DC/DC

Converter

TPS785-Q1

GND GND

GND

VEN

GND

Typical Application Circuit

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

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Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings ....................................... 4

6.2 ESD Ratings .............................................................. 4

6.3 Recommended Operating Conditions ........................5

6.4 Thermal Information ...................................................5

6.5 Electrical Characteristics ............................................6

6.6 Typical Characteristics................................................8

7 Detailed Description......................................................14

7.1 Overview...................................................................14

7.2 Functional Block Diagrams....................................... 14

7.3 Feature Description...................................................15

7.4 Device Functional Modes..........................................18

8 Application and Implementation..................................19

8.1 Application Information............................................. 19

8.2 Typical Application.................................................... 26

9 Power Supply Recommendations................................27

10 Layout...........................................................................27

10.1 Layout Guidelines................................................... 27

10.2 Layout Examples.................................................... 29

11 Device and Documentation Support..........................30

11.1 Device Support........................................................30

11.2 Documentation Support.......................................... 30

11.3 Receiving Notification of Documentation Updates..30

11.4 Support Resources................................................. 30

11.5 Trademarks............................................................. 30

11.6 Electrostatic Discharge Caution..............................30

11.7 Glossary..................................................................30

12 Mechanical, Packaging, and Orderable

Information.................................................................... 30

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision * (January 2021) to Revision A (April 2021)

Page

•

Changed document status from advance information to production data.......................................................... 1

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5 Pin Configuration and Functions

OUT

Thermal

Pad

Thermal

Pad

GND

Figure 5-1. DRB Package (Fixed), 8-Pin VSON,

Top View

Figure 5-2. DRB Package (Adjustable), 8-Pin VSON,

Top View

Thermal Pad

Not to scale

Figure 5-3. KVU Package (Fixed), 5-Pin TO-252,

Top View

Figure 5-4. KVU Package (Adjustable), 5-Pin

TO-252, Top View

Table 5-1. Pin Functions

DRB

I/O

DESCRIPTION

DRB

(Fixed)

KVU

(Fixed)

KVU

(Adjustable)

NAME

(Adjustable)

Enable pin. Driving this pin to logic high enables the device; driving this

pin to logic low disables the device. Do not float this pin. If not used,

connect EN to IN.

Input

Feedback pin. Input to the control-loop error amplifier. This pin is used to

set the output voltage of the device with the use of external resistors. Do

not float this pin. For adjustable-voltage version devices only.

—

Input

—

GND

Ground pin. This pin must be connected to ground on the board.

Input pin. For best performance, place the nominal recommended value

or larger ceramic capacitor from IN to GND; see the Recommended

Operating Conditions table. Place the input capacitor as close to the

input of the device as possible.

Input

—

No connect pin. This pin is not internally connected. Connect to ground

for best thermal performance or leave floating.

2, 3, 4, 6

3, 4, 6

—

A 0.47-µF or greater effective capacitance is required from OUT to

ground for stability. For best transient response, use a 1-µF or larger

ceramic capacitor from OUT to ground. Place the output capacitor

as close to output of the device as possible; see the Recommended

Operating Conditions table.

OUT

Output

—

The thermal pad is electrically connected to the GND pin. Connect

the thermal pad to a large-area GND plane for improved thermal

performance.

Thermal

Pad

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

UNIT

Supply, V_IN

6.5

Enable, V_EN

6.5

V_IN+ 0.3⁽²⁾

Voltage

Output, V_OUT

Feedback, V_FB

Current

Output, I_OUT

Internally limited

Operating junction, T_J

Storage, T_stg

–40

–65

150

°C

Temperature

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) The absolute maximum rating is V_IN+ 0.3 V or 6.5 V, whichever is smaller.

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

Charged-device model (CDM), per AEC Q100-011

V_(ESD)

Electrostatic discharge

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

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6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

1.7

1.2

0.65

0.1

1⁽¹⁾

NOM

MAX

6.0

UNIT

V_IN

Input voltage

Adjustable output

Fixed output

5.5

V_OUT

Output voltage

5.0

C_IN

Input capacitor

µF

C_OUT

C_FF

Output capacitor

200

100

Feed-forward capacitor⁽²⁾

Output current

I_OUT

C_OUT,ESR

V_EN

Output capacitor ESR

Enable voltage

0.001

F_EN

Enable toggle frequency

Junction temperature

150

kHz

°C

T_J

–40

(1) The minimum effective capacitance is 0.47 µF.

(2) Feed-forward capacitor is optional and not required for stability.

6.4 Thermal Information

TPS785-Q1

THERMAL METRIC⁽¹⁾

DRB (VSON)

8 PINS

59.5

KVU (TO-252)

5 PINS

31.6

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

40.4

31.4

10.4

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

3.5

4.6

ψ_JB

31.3

10.3

R_θJC(bot)

15.7

3.3

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

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6.5 Electrical Characteristics

at operating temperature range (T_J= –40°C to +150°C), V_IN= V_OUT(nom)+ 0.75 V or 2.0 V (whichever is greater), I_OUT

1 mA, V_EN= V_IN, and C_IN= C_OUT= 1 µF, unless otherwise noted. All typical values at T_J= 25°C.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_IN

Input voltage

1.7

6.0

5.5

5.0

0.5

Adjustable output

Fixed output

1.2

V_OUT

Output voltage

0.65

–0.5

–1

1 mA ≤ I_OUT≤ 1 A,

T_J= 25°C

V_OUT(nom)+ 0.75 V or 2.0 V

(whichever is greater) ≤ V_IN

6.0 V

V_OUT

Output accuracy^{(5) (1)}

Line regulation

–40°C ≤ T_J≤ 85°C

–40°C ≤ T_J≤ 150°C

≤

–1.7

1.7

V_OUT(nom)+ 0.75 V or 2.0 V (whichever is greater) ≤ V_IN

6.0 V

≤

0.3

0.1 mA ≤ I_OUT≤ 1 A

–40°C ≤ T_J≤ 85°C

V_OUT≤ 3.3 V

–7.5

7.5

Load regulation

0.1 mA ≤ I_OUT≤ 1 A,

–40°C ≤ T_J≤ 150°C

V_OUT> 3.3 V

Load transient response

settling time^{(2) (3)}

I_OUT= 300 mA to

700 mA

µs

I_OUT= 300 mA to

700 mA

–2%

%V_OUT

ΔV_OUT

t_R= t_F= 1 µs, C_OUT= 10 µF

Load transient response

I_OUT= 700 mA to

300 mA

10% %V_OUT

%V_OUT

overshoot, undershoot ^{(3) (6)}

I_OUT= 0 mA to

1000 mA

–10%

I_OUT= 0 mA

T_J= 25°C

µA

V_OUT(nom)+ 0.5 V or 2.0 V

(whichever is greater) ≤ V_IN

6.0 V

–40°C ≤ T_J≤ 85°C

–40°C ≤ T_J≤ 150°C

T_J= 25°C

≤

I_OUT= 500 µA

V_OUT(nom)+ 0.5 V or 2.0 V

(whichever is greater) ≤ V_IN

6.0 V

I_GND

Ground current

–40°C ≤ T_J≤ 85°C

–40°C ≤ T_J≤ 150°C

I_OUT= 100 µA

V_OUT(nom)+ 0.5 V or 2.0 V

(whichever is greater) ≤ V_IN

6.0 V

–40°C ≤ T_J≤ 85°C

µA

V_EN≤ 0.3 V

T_J= 25°C

0.01

0.05

0.25

V_OUT(nom)+ 0.5 V or 2.0 V

(whichever is greater) ≤ V_IN

6.0 V

I_SHDN

Shutdown current

–40°C ≤ T_J≤ 85°C

–40°C ≤ T_J≤ 150°C

V_FB

I_FB

Feedback voltage

Adjustable output only

1.182

–0.05

1.2

1.218

0.05

Feedback pin current

0.01

µA

V_IN= V_OUT(nom)+ 1.25 V or 2.0 V (whichever is greater),

V_OUT= 0.9 x V_OUT(nom)

I_CL

I_SC

Output current limit

1.04

1.65

(4)

Short-circuit current limit

V_OUT= 0 V

550

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6.5 Electrical Characteristics (continued)

at operating temperature range (T_J= –40°C to +150°C), V_IN= V_OUT(nom)+ 0.75 V or 2.0 V (whichever is greater), I_OUT

1 mA, V_EN= V_IN, and C_IN= C_OUT= 1 µF, unless otherwise noted. All typical values at T_J= 25°C.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

1130

960

0.65 V ≤ V_OUT< 0.8 V

0.8 V ≤ V_OUT< 1.0 V

1.0 V ≤ V_OUT< 1.2 V

1.2 V ≤ V_OUT< 1.5 V

1.5 V ≤ V_OUT< 1.8 V

1.8 V ≤ V_OUT< 2.5 V

2.5 V ≤ V_OUT< 3.3 V

3.3 V ≤ V_OUT≤ 5.5 V

0.65 V ≤ V_OUT< 0.8 V

0.8 V ≤ V_OUT< 1.0 V

1.0 V ≤ V_OUT< 1.2 V

1.2 V ≤ V_OUT< 1.5 V

1.5 V ≤ V_OUT< 1.8 V

1.8 V ≤ V_OUT< 2.5 V

2.5 V ≤ V_OUT< 3.3 V

3.3 V ≤ V_OUT≤ 5.5 V

800

725

Dropout voltage (DRB

package)

I_OUT= 1 A,

V_OUT= 0.95 x V_OUT(nom)

500

425

350

315

1225

1070

V_DO

915

755

605

540

455

425

I_OUT= 1 A,

V_OUT= 0.95 x V_OUT(nom)

Dropout voltage (KVU

package)

I_OUT= 850 mA,

V_OUT= 0.95 x V_OUT(nom)

V_OUT= 1.8 V

V_OUT= 1.2 V

500

I_OUT= 500 mA,

V_OUT= 0.95 x V_OUT(nom)

f = 1 kHz

I_OUT= 1 A, V_IN

V_OUT+ 1 V

PSRR

Power-supply rejection ratio

f = 100 kHz

f = 1 MHz

Output noise voltage

UVLO threshold

BW = 10 Hz to 100 kHz, V_OUT= 1.2 V

µV_RMS

V_INrising

1.28

1.17

1.42

1.29

130

550

1.62

V_UVLO

V_INfalling

1.42

V_UVLO(HYST)

t_STR

UVLO hysteresis

V_INhysteresis

Start-up time

From EN low-to-high transition to V_OUT= V_OUT(nom)x 92%

280

0.9

785

0.3

µs

V_EN(HI)

EN pin logic high voltage

EN pin logic low voltage

Enable pin current

Pulldown resistance

V_EN(LOW)

I_EN

V_IN= V_EN= 6.0 V

V_IN= 3.3 V

R_PULLDOWN

100

Thermal shutdown

temperature

T_SD(shutdown)

T_SD(reset)

Shutdown, temperature increasing

Reset, temperature decreasing

170

155

°C

Thermal shutdown reset

temperature

(1) Resistor tolerance is not included in overall accuracy in the adjustable version.

(2) The settling time is measured from when I_OUTis stepped from 300 mA to 700 mA to when the output voltage recovers to V_OUT

V_OUT(nom)- 5 mV.

(3) This specification is verified by design.

(4) The output is being forced to 90% of the nominal V_OUTvalue.

(5) Based on ambient temperature power dissipation should be limited to avoid thermal shutdown.

(6) This specification is in relation to the change from the nominal output voltage (V_OUT(nom)).

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6.6 Typical Characteristics

at operating temperature T_J= 25°C, I_OUT= 1 mA, V_EN= 1.0 V, C_IN= 1.0 µF, C_OUT= 1.0 µF, and V_IN= V_OUT(NOM)+ 0.75 V or

1.7 V (whichever is greater), unless otherwise noted; typical values are at T_J= 25°C

0.25

0.2

0.25

0.2

0.15

0.1

0.15

0.1

0.05

-0.05

-0.1

-0.15

-0.2

-0.25

-0.05

-0.1

-0.15

-0.2

-0.25

T_J

-55èC

-40èC

0èC

85èC

125èC

150èC

-55èC

-40èC

0èC

25èC

85èC

125èC

150èC

25èC

5.5 5.55 5.6 5.65 5.7 5.75 5.8 5.85 5.9 5.95

Input Voltage (V)

3.8 4.05 4.3 4.55 4.8 5.05 5.3 5.55 5.8

Input Voltage (V)

V_OUT= 5.0 V

V_OUT= 3.3 V

Figure 6-2. Output Accuracy vs V_IN

Figure 6-1. Output Accuracy vs V_IN

0.2

0.15

0.1

0.2

0.15

0.1

0.05

-0.05

-0.1

-0.15

-0.2

0.05

300 mA

500 mA

1 A

-55èC

-40èC

0èC

25èC

85èC

125èC

150èC

-60 -40 -20

20 40 60 80 100 120 140 160

Temperature èC

1.5

2.5

3.5 4

Input Voltage (V)

4.5

5.5

V_OUT= 1.2 V

Figure 6-4. Output Accuracy vs Temperature

I_OUT= 50 mA, V_OUT= 1.2 V

Figure 6-3. Output Accuracy vs V_IN

0.2

0.15

0.1

1500

1400

1300

1200

1100

1000

900

800

700

600

500

400

300

200

100

-55 èC

-40 èC

0 èC

25 èC

85 èC

125 èC

150 èC

0.05

-55èC

-40èC

0èC

25èC

85èC

125èC

150èC

-0.05

-0.1

0.5

1.5

2.5

3.5

Output Voltage (V)

4.5

5.5

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Output Current (A)

I_OUT= 1 A

Figure 6-6. Dropout vs Output Voltage

V_OUT= 1.2 V

Figure 6-5. Output Accuracy vs Output Current

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6.6 Typical Characteristics (continued)

at operating temperature T_J= 25°C, I_OUT= 1 mA, V_EN= 1.0 V, C_IN= 1.0 µF, C_OUT= 1.0 µF, and V_IN= V_OUT(NOM)+ 0.75 V or

1.7 V (whichever is greater), unless otherwise noted; typical values are at T_J= 25°C

1000

700

-55 èC

-40 èC

0 èC

25 èC

85 èC

125 èC

150 èC

-55 èC

-40 èC

0 èC

25 èC

85 èC

125 èC

150 èC

500

300

200

100

1E-6

1E-5

0.0001 0.001

Output Current (A)

0.01

0.1

0.5

1.5

2.5

3 4

Input Voltage (V)

3.5

4.5

5.5

I_OUT= 500 µA

Figure 6-8. I_GNDvs I_OUT

Figure 6-7. I_GNDvs V_IN

1000

900

800

700

600

500

400

300

200

100

-55 èC

-40 èC

0 èC

25 èC

85 èC

125 èC

150 èC

1.00E-6 0.15

0.30

0.45 0.60

Output Current (A)

0.75

0.90

-60 -40 -20

20 40 60 80 100 120 140 160

Temperature (èC)

V_OUT= 1.2 V, V_IN= 2 V

I_OUT= 500 µA

Figure 6-9. I_GNDvs I_OUT

Figure 6-10. 500-µA Ground Current vs Temperature

396

394

392

390

388

386

384

382

380

3.5

T_J

50 mA

-55èC

-40èC

0èC

25èC

85èC

125èC

150èC

2.5

1.5

0.5

-0.5

0.5

1.5

2.5

3.5

Input Voltage (V)

4.5

5.5

-60 -40 -20

20 40 60 80 100 120 140 160

Temperature (èC)

V_EN= 0.3 V

Figure 6-12. I_SHDNvs V_IN

I_OUT= 50 mA

Figure 6-11. 50-mA Ground Current vs Temperature

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6.6 Typical Characteristics (continued)

at operating temperature T_J= 25°C, I_OUT= 1 mA, V_EN= 1.0 V, C_IN= 1.0 µF, C_OUT= 1.0 µF, and V_IN= V_OUT(NOM)+ 0.75 V or

1.7 V (whichever is greater), unless otherwise noted; typical values are at T_J= 25°C

0.8

0.75

0.7

300

250

200

150

100

V_EN(HI)

V_EN(LO)

T_J

-55èC

-40èC

0èC

25èC

150èC

85èC

125èC

0.65

0.6

0.55

0.5

0.45

-75

-50

-25

100 125 150

Temperature (èC)

0.5

1.5

2.5

3.5

Input Voltage (V)

4.5

5.5

V_IN= 2 V

V_EN= 0.3 V

Figure 6-14. V_EN(HI)and V_EN(LOW)Thresholds vs Temperature

Figure 6-13. Pulldown Resistor (R_Pulldown) vs V_IN

0.85

17.5

V_EN(HI)

V_EN(LO)

4.5

0.8

12.5

3.5

0.75

0.7

V_OUT

V_IN

7.5

2.5

0.65

0.6

2.5

1.5

-2.5

-5

0.5

0.55

-75

-50

-25

100 125 150

100 200 300 400 500 600 700 800 900 1000

Time (ms)

Temperature (èC)

V_IN= 6 V

V_OUT= 3.3 V, I_OUT= 1 mA, slew rate = 1 V/µs

Figure 6-16. Line Transient

Figure 6-15. V_EN(HI)and V_EN(LOW)Thresholds vs Temperature

5.5

4.5

3.5

2.5

-2

-4

-6

-8

-10

-2

-4

-6

-8

-10

1.5

V_IN

-40èC

25èC

85èC

150èC

-40èC

25èC

85èC

0.5

80 100 120 140 160 180 200

Time (ms)

80 100 120 140 160 180 200

Time (ms)

V_OUT= 3.3 V, I_OUT= 300 mA, slew rate = 1 V/µs

V_OUT= 3.3 V, I_OUT= 1 A, slew rate = 1 V/µs

Figure 6-17. Line Transient vs Temperature

Figure 6-18. Line Transient vs Temperature

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6.6 Typical Characteristics (continued)

at operating temperature T_J= 25°C, I_OUT= 1 mA, V_EN= 1.0 V, C_IN= 1.0 µF, C_OUT= 1.0 µF, and V_IN= V_OUT(NOM)+ 0.75 V or

1.7 V (whichever is greater), unless otherwise noted; typical values are at T_J= 25°C

5.5

1500

1200

900

4.5

600

300

3.5

-10

-20

-30

-40

-50

-300

-600

-900

-1200

-1500

2.5

-2

-4

-6

-8

-10

-40èC

25èC

150èC

I_OUT

1.5

V_IN

-40èC

25èC

85èC

0.5

100 200 300 400 500 600 700 800 900 1000

Time (ms)

80 100 120 140 160 180 200

Time (ms)

V_OUT= 3.3 V, I_OUT= 300 mA to 700 mA, rise time = 1 µs

V_OUT= 3.3 V, I_OUT= 500 mA, slew rate = 1 V/µs

Figure 6-20. Load Transient vs Temperature

Figure 6-19. Line Transient vs Temperature

450

300

150

100

1500

1000

500

-50

-100

-150

-500

-1000

-1500

-25

-50

-75

-150

-300

-450

-40èC

25èC

150èC

I_OUT

-40èC

25èC

150èC

I_OUT

100 200 300 400 500 600 700 800 900 1000

Time (ms)

100 200 300 400 500 600 700 800 900 1000

Time (ms)

V_OUT= 3.3 V, I_OUT= 0 mA to 1 A, rise time = 1 µs

V_OUT= 3.3 V, I_OUT= 0 mA to 100 mA, rise time = 1 µs

Figure 6-21. Load Transient vs Temperature

Figure 6-22. Load Transient vs Temperature

0 nF (151 mV_RMS

)

1 nF (55.2 mV_RMS

)

4.7 nF (49.1 mV_RMS

10 nF (39.7 mV_RMS

100 nF (30.1 mV_RMS

)

0.5

0.3

0.2

0.3

0.2

0.1

0.05

1.2 V (29.7 mV_RMS

)

0.03

0.02

0.03

0.02

3.3 V (151 mV_RMS

5.0 V (190 mV_RMS

)

0.01

100

10k

Frequency (Hz)

100k

10M

100

10k

Frequency (Hz)

100k

10M

V_OUT= 3.3 V, I_OUT= 1 A

Figure 6-23. Noise vs C_FF

I_OUT= 1 A

Figure 6-24. Noise vs V_OUT

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6.6 Typical Characteristics (continued)

at operating temperature T_J= 25°C, I_OUT= 1 mA, V_EN= 1.0 V, C_IN= 1.0 µF, C_OUT= 1.0 µF, and V_IN= V_OUT(NOM)+ 0.75 V or

1.7 V (whichever is greater), unless otherwise noted; typical values are at T_J= 25°C

3.75 V V_IN

3.85 V V_IN

3.95 V V_IN

4.05 V V_IN

4.15 V V_IN

4.3 V V_IN

1 mF

4.7 mF

10 mF

100

10k

Frequency (Hz)

100k

10M

100

10k

Frequency (Hz)

100k

10M

V_OUT= 3.3 V, I_OUT= 1 A

Figure 6-25. PSRR vs V_IN

Figure 6-26. PSRR vs C_OUT

-20

-40

-60

-80

-100

-120

-140

V_IN

V_EN

V_OUT

I_IN

-1

1 A

500 mA

300 mA

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Time (ms)

100

10k

Frequency (Hz)

100k

10M

V_IN= 5.5 V, C_IN= 0 µF, C_OUT= 1 µF, V_OUT= 5.0 V,

I_OUT= 0 mA

V_OUT= 3.3 V

Figure 6-27. PSRR vs I_OUT

Figure 6-28. Start-Up Inrush Current With

C_OUT= 1 µF

280

Input Voltage

Enable Voltage

Output Voltage

Output Current

Input Voltage

Enable Voltage

Output Voltage

Output Current

240

200

160

120

240

200

160

120

-1

-40

-1

-40

200 400 600 800 1000 1200 1400 1600 1800 2000

Time (ms)

200 400 600 800 1000 1200 1400 1600 1800 2000

Time (ms)

V_IN= V_EN= 5.5 V, C_IN= 0 µF, C_OUT= 1 µF, V_OUT= 1.2 V,

I_OUT= 50 mA, T_A= -40°C

V_IN= V_EN= 5.5 V, C_IN= 0 µF, C_OUT= 1 µF, V_OUT= 1.2 V,

I_OUT= 50 mA, T_A= 25°C

Figure 6-29. Start Up

Figure 6-30. Start Up

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6.6 Typical Characteristics (continued)

at operating temperature T_J= 25°C, I_OUT= 1 mA, V_EN= 1.0 V, C_IN= 1.0 µF, C_OUT= 1.0 µF, and V_IN= V_OUT(NOM)+ 0.75 V or

1.7 V (whichever is greater), unless otherwise noted; typical values are at T_J= 25°C

280

240

200

160

120

Input Voltage

Enable Voltage

Output Voltage

Output Current

-20

-40

-60

-80

-100

-120

-140

V_IN

V_EN

V_OUT

I_IN

-1

-40

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Time (ms)

200 400 600 800 1000 1200 1400 1600 1800 2000

Time (ms)

V_IN= V_EN= 5.5 V, C_IN= 0 µF, C_OUT= 1 µF, V_OUT= 5.0 V,

I_OUT= 0 mA

V_IN= V_EN= 5.5 V, C_IN= 0 µF, C_OUT= 1 µF, V_OUT= 1.2 V,

I_OUT= 50 mA, T_A= 150°C

Figure 6-32. Start-Up Inrush Current With

C_OUT= 1 µF

Figure 6-31. Start Up

160

0.5

-80

0.2

0.1

-160

-240

-320

-400

-480

-560

0.05

V_IN

V_EN

V_OUT

I_IN

Stable region

0.02

0.01

0.005

0.002

0.001

-1

0.0005

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Time (ms)

0.5

3 4 567 10

20 30 50 70100 200

500

C_OUT(mF)

V_IN= 5.5 V, C_IN= 0 µF, C_OUT= 4.7 µF, V_OUT= 5.0 V,

I_OUT= 0 mA

C_OUTdenotes nominal capacitor size

(not effective capacitance)

Figure 6-33. Start-Up Inrush Current With

C_OUT= 4.7 µF

Figure 6-34. ESR vs C_OUT

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7 Detailed Description

7.1 Overview

The TPS785-Q1 is an ultra low-dropout, high PSRR, high-accuracy linear voltage regulator that is optimized for

excellent transient performance. These characteristics make the device ideal for most automotive applications.

This regulator offers foldback current limit, output enable, active discharge, undervoltage lockout (UVLO), and

thermal protection.

7.2 Functional Block Diagrams

Current

Limit

OUT

1.2-V

Bandgap

120 Ω

UVLO

Internal

Controller

Thermal

Shutdown

GND

Figure 7-1. Adjustable Version Block Diagram

Current

Limit

OUT

1.2-V

Bandgap

2.18 Mꢀ

120 Ω

UVLO

2.42 Mꢀ

550 kꢀ

Internal

Controller

Thermal

Shutdown

GND

Figure 7-2. Fixed Version Block Diagram

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7.3 Feature Description

7.3.1 Foldback Current Limit

The device has an internal current limit circuit that protects the regulator during transient high-load current faults

or shorting events. The current limit is a hybrid brickwall-foldback scheme. The current limit transitions from a

brickwall scheme to a foldback scheme at the foldback voltage (V_FOLDBACK). In a high-load current fault with

the output voltage above V_FOLDBACK, the brickwall scheme limits the output current to the current limit (I_CL).

When the voltage drops below V_FOLDBACK, a foldback current limit activates that scales back the current as the

output voltage approaches GND. When the output is shorted, the device supplies a typical current called the

short-circuit current limit (I_SC). I_CLand I_SCare listed in the Electrical Characteristics table.

For this device, V_FOLDBACK= 0.4 × V_OUT(NOM)

The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the

device begins to heat up because of the increase in power dissipation. When the device is in brickwall current

limit, the pass transistor dissipates power [(V_IN– V_OUT) × I_CL]. When the device output is shorted and the output

is below V_FOLDBACK, the pass transistor dissipates power [(V_IN– V_OUT) × I_SC]. If thermal shutdown is triggered,

the device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on.

If the output current fault condition continues, the device cycles between current limit and thermal shutdown. For

more information on current limits, see the Know Your Limits application report.

Figure 7-3 shows a diagram of the foldback current limit.

V_OUT

Brickwall

V_OUT(NOM)

V_FOLDBACK

Foldback

0 V

I_OUT

I_RATED

0 mA

I_SC

I_CL

Figure 7-3. Foldback Current Limit

7.3.2 Output Enable

The enable pin (EN) is active high. Enable the device by forcing the voltage of the enable pin to exceed the

minimum EN pin high-level input voltage (see the Electrical Characteristics table). Turn off the device by forcing

the voltage of the enable pin to drop below the maximum EN pin low-level input voltage (see the Electrical

Characteristics table). If shutdown capability is not required, connect EN to IN.

This device has an internal pulldown circuit that activates when the device is disabled to actively discharge the

output voltage.

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7.3.3 Active Discharge

The device has an internal pulldown MOSFET that connects an R_PULLDOWNresistor to ground when the device is

disabled to actively discharge the output voltage. The active discharge circuit is activated by the enable pin.

Do not rely on the active discharge circuit to discharge the output voltage after the input supply has collapsed

because reverse current can possibly flow from the output to the input. This reverse current flow can cause

damage to the device, especially when a large output capacitor is used. Limit reverse current to no more than

5% of the device rated current for a short period of time.

7.3.4 Undervoltage Lockout (UVLO) Operation

The UVLO circuit ensures that the device stays disabled before its input supply reaches the minimum

operational voltage range, and ensures that the device shuts down when the input supply collapses. Figure

7-4 shows the UVLO circuit response to various input voltage events. The diagram can be separated into the

following parts:

•

Region A: The device does not start until the input reaches the UVLO rising threshold.

Region B: Normal operation, regulating device.

Region C: Brownout event above the UVLO falling threshold (UVLO rising threshold – UVLO hysteresis). The

output may fall out of regulation but the device remains enabled.

•

Region D: Normal operation, regulating device.

Region E: Brownout event below the UVLO falling threshold. The device is disabled in most cases and the

output falls because of the load and active discharge circuit. The device is reenabled when the UVLO rising

threshold is reached by the input voltage and a normal start-up follows.

•

Region F: Normal operation followed by the input falling to the UVLO falling threshold.

Region G: The device is disabled when the input voltage falls below the UVLO falling threshold to 0 V. The

output falls because of the load and active discharge circuit.

UVLO Rising Threshold

UVLO Hysteresis

V_IN

V_OUT

tAt

tBt

tDt

tEt

tFt

tGt

Figure 7-4. Typical UVLO Operation

7.3.5 Dropout Voltage

Dropout voltage (V_DO) is defined as the input voltage minus the output voltage (V_IN– V_OUT) at the rated output

current (I_RATED), where the pass transistor is fully on. I_RATEDis the maximum I_OUTlisted in the Recommended

Operating Conditions table. The pass transistor is in the ohmic or triode region of operation, and acts as a

switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed

output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than

the nominal output regulation, then the output voltage falls as well.

For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (R_DS(ON)) of the

pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for

that current scales accordingly. The following equation calculates the R_DS(ON)of the device.

V_DO

R_DS(ON)

I_RATED

(1)

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7.3.6 Thermal Shutdown

The device contains a thermal shutdown protection circuit to disable the device when the junction temperature

(T_J) of the pass transistor rises to T_SD(shutdown)(typical). Thermal shutdown hysteresis assures that the device

resets (turns on) when the temperature falls to T_SD(reset)(typical).

The thermal time-constant of the semiconductor die is fairly short, thus the device may cycle on and off

when thermal shutdown is reached until power dissipation is reduced. Power dissipation during startup can

be high from large V_IN– V_OUTvoltage drops across the device or from high inrush currents charging large

output capacitors. Under some conditions, the thermal shutdown protection disables the device before startup

completes.

For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating

Conditions table. Operation above this maximum temperature causes the device to exceed its operational

specifications. Although the internal protection circuitry of the device is designed to protect against thermal

overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device

into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability.

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7.4 Device Functional Modes

7.4.1 Device Functional Mode Comparison

The Device Functional Mode Comparison table shows the conditions that lead to the different modes of

operation. See the Electrical Characteristics table for parameter values.

Table 7-1. Device Functional Mode Comparison

PARAMETER

OPERATING MODE

V_IN

V_EN

I_OUT

T_J

Normal operation

Dropout operation

V_IN> V_OUT(nom)+ V_DOand V_IN> V_IN(min)

V_IN(min)< V_IN< V_OUT(nom)+ V_DO

V_EN> V_EN(HI)

I_OUT< I_OUT(max)

T_J< T_SD(shutdown)

Disabled

(any true condition

disables the device)

V_IN< V_UVLO

V_EN< V_EN(LOW)

Not applicable

T_J> T_SD(shutdown)

7.4.2 Normal Operation

The device regulates to the nominal output voltage when the following conditions are met:

•

The input voltage is greater than the nominal output voltage plus the dropout voltage (V_OUT(nom)+ V_DO)

The output current is less than the current limit (I_OUT< I_CL)

The device junction temperature is less than the thermal shutdown temperature (T_J< T_SD

)

•

The enable voltage has previously exceeded the enable rising threshold voltage and has not yet decreased

to less than the enable falling threshold

7.4.3 Dropout Operation

If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other

conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage

tracks the input voltage. During this mode, the transient performance of the device becomes significantly

degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load

transients in dropout can result in large output-voltage deviations.

When the device is in a steady dropout state (defined as when the device is in dropout, V_IN< V_OUT(NOM)+ V_DO

directly after being in a normal regulation state, but not during startup), the pass transistor is driven into the

ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output

voltage plus the dropout voltage (V_OUT(NOM)+ V_DO), the output voltage can overshoot for a short period of time

while the device pulls the pass transistor back into the linear region.

7.4.4 Disabled

The output of the device can be shutdown by forcing the voltage of the enable pin to less than the maximum

EN pin low-level input voltage (see the Electrical Characteristics table). When disabled, the pass transistor is

turned off, internal circuits are shutdown, and the output voltage is actively discharged to ground by an internal

discharge circuit from the output to ground.

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8 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

8.1 Application Information

8.1.1 Recommended Capacitor Types

The device is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input

and output. Multilayer ceramic capacitors have become the industry standard for these types of applications and

are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and

C0G-rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of

Y5V-rated capacitors is discouraged because of large variations in capacitance.

Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and

temperature. As a rule of thumb, expect the effective capacitance to decrease by as much as 50%. The input

and output capacitors recommended in the Recommended Operating Conditions table account for an effective

capacitance of approximately 50% of the nominal value.

8.1.2 Input and Output Capacitor Requirements

The device requires an input capacitor of 1.0 µF or larger as specified in the Recommended Operating

Conditions table for stability. A higher value capacitor may be necessary if large, fast rise-time load or line

transients are anticipated or if the device is located several inches from the input power source.

The device also requires an output capacitor of 1.0 µF or larger as specified in the Recommended Operating

Conditions table for stability. Dynamic performance of the device is improved by using a higher capacitor than

the minimum output capacitor.

8.1.3 Adjustable Device Feedback Resistors

The device requires external feedback divider resistors to set the output voltage. Figure 8-1 shows how the

output voltage of an adjustable device can be configured from 1.2 V to 5.5 V by using a resistor divider network.

Feed-forward capacitor CFF is not required for stability (optional)

VIN

OUT

VOUT

COUT

CFF

CIN

TPS785-Q1

GND

VEN

GND

Figure 8-1. Adjustable Operation

Equation 2 calculates the values of the R₁and R₂resistors to set the output voltage:

V_OUT= V_FB× (1 + R₁/ R₂) + I_FB× R₁

(2)

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To disregard the effect of the FB pin current error term in Equation 2 and to achieve best accuracy, choose

R₂to be equal to or smaller than 550 kΩ so that the current flowing through R₁and R₂is at least 100 times

larger than the I_FBcurrent listed in the Electrical Characteristics table. Lowering the value of R₂increases the

immunity against noise injection. Increasing the value of R₂reduces the quiescent current for achieving higher

efficiency at low load currents. Equation 3 calculates the setting that provides the maximum feedback divider

series resistance.

(R₁+ R₂) ≤ V_OUT/ (I_FB× 100)

(3)

8.1.4 Load Transient Response

The load-step transient response is the output voltage response by the LDO to a step in load current, whereby

output voltage regulation is maintained. There are two key transitions during a load transient response: the

transition from a light to a heavy load and the transition from a heavy to a light load. The regions shown in Figure

8-2 are broken down as follows. Regions A, E, and H are where the output voltage is in steady-state.

tAt

tCt

tDt

tEt

tGt

tHt

Figure 8-2. Load Transient Waveform

During transitions from a light load to a heavy load, the:

•

Initial voltage dip is a result of the depletion of the output capacitor charge and parasitic impedance to the

output capacitor (region B)

Recovery from the dip results from the LDO increasing its sourcing current, and leads to output voltage

regulation (region C)

•

Initial voltage rise results from the LDO sourcing a large current, and leads to the output capacitor charge to

increase (region F)

Recovery from the rise results from the LDO decreasing its sourcing current in combination with the load

discharging the output capacitor (region G)

A larger output capacitance reduces the peaks during a load transient but slows down the response time of the

device. A larger DC load also reduces the peaks because the amplitude of the transition is lowered and a higher

current discharge path is provided for the output capacitor.

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8.1.5 Exiting Dropout

Some applications have transients that place the LDO into dropout, such as slower ramps on V_INduring start-up.

As with other LDOs, the output can overshoot on recovery from these conditions. A ramping input supply causes

an LDO to overshoot on start-up, as shown in Figure 8-3, when the slew rate and voltage levels are in the

correct range. Use an enable signal to avoid this condition.

Input Voltage

Response time for

LDO to get back into

regulation.

Load current discharges

output voltage.

V_IN= V_OUT(nom)+ V_DO

Output Voltage

Dropout

V_OUT= V_IN- V_DO

Output Voltage in

normal regulation.

Time

Figure 8-3. Start-Up Into Dropout

Line transients out of dropout can also cause overshoot on the output of the regulator. These overshoots are

caused by the error amplifier having to drive the gate capacitance of the pass element and bring the gate back to

the correct voltage for proper regulation. Figure 8-4 illustrates what is happening internally with the gate voltage

and how overshoot can be caused during operation. When the LDO is placed in dropout, the gate voltage (V_GS

)

is pulled all the way down to ground to give the pass device the lowest on-resistance as possible. However, if

a line transient occurs when the device is in dropout, the loop is not in regulation and can cause the output to

overshoot until the loop responds and the output current pulls the output voltage back down into regulation. If

these transients are not acceptable, then continue to add input capacitance in the system until the transient is

slow enough to reduce the overshoot.

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Transient response

time of the LDO

Input Voltage

Load current

discharges

output

voltage

Dropout

V_OUT= V_IN- V_DO

Output Voltage

V_DO

Output Voltage in

normal regulation

Time

VGS voltage

(pass device

fully off)

Input Voltage

VGS voltage for

normal operation

VGS voltage for

normal operation

Gate Voltage

VGS voltage in

dropout (pass device

fully on)

Time

Figure 8-4. Line Transients From Dropout

8.1.6 Dropout Voltage

The device uses a PMOS pass transistor to achieve low dropout. When (V_IN– V_OUT) is less than the dropout

voltage (V_DO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the

R_DS(ON)of the PMOS pass element. V_DOscales approximately with output current because the PMOS device

behaves like a resistor in dropout mode. As with any linear regulator, PSRR and transient response degrade as

(V_IN– V_OUT) approaches dropout operation.

8.1.7 Reverse Current

As with most LDOs, excessive reverse current can damage this device.

Reverse current flows through the body diode on the pass element instead of the normal conducting channel.

At high magnitudes, this current flow degrades the long-term reliability of the device as a result of one of the

following conditions:

•

Degradation caused by electromigration

Excessive heat dissipation

Potential for a latch-up condition

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Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute

maximum rating of V_OUT> V_IN+ 0.3 V:

•

If the device has a large C_OUTand the input supply collapses with little or no load current

The output is biased when the input supply is not established

The output is biased above the input supply

If reverse current flow is expected in the application, external protection must be used to protect the device.

Figure 8-5 shows one approach of protecting the device.

Schottky Diode

Internal Body Diode

OUT

Device

C_OUT

C_IN

GND

Figure 8-5. Example Circuit for Reverse Current Protection Using a Schottky Diode

8.1.8 Feed-Forward Capacitor (C_FF)

For the adjustable-voltage version device, a feed-forward capacitor (C_FF) can be connected from the OUT pin

to the FB pin. C_FFimproves transient, noise, and PSRR performance, but is not required for regulator stability.

Recommended C_FFvalues are listed in the Recommended Operating Conditions table. A higher capacitance

C_FFcan be used; however, the startup time increases. For a detailed description of C_FFtradeoffs, see the Pros

and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator application report.

8.1.9 Power Dissipation (P_D)

Circuit reliability demands that proper consideration be given to device power dissipation, location of the circuit

on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator

must be as free as possible of other heat-generating devices that cause added thermal stresses.

As a first-order approximation, power dissipation in the regulator depends on the input-to-output voltage

difference and load conditions. Use Equation 4 to approximate P_D:

P_D= (V_IN– V_OUT) × I_OUT

(4)

Power dissipation can be minimized, and thus greater efficiency achieved, by proper selection of the system

voltage rails. Proper selection allows the minimum input-to-output voltage differential to be obtained. The low

dropout of the TPS785-Q1 allows for maximum efficiency across a wide range of output voltages.

The main heat conduction path for the device is through the thermal pad on the package. As such, the thermal

pad must be soldered to a copper pad area under the device. This pad area contains an array of plated vias that

conduct heat to any inner plane areas or to a bottom-side copper plane.

The maximum power dissipation determines the maximum allowable junction temperature (T_J) for the device.

According to Equation 5, power dissipation and junction temperature are most often related by the junction-to-

ambient thermal resistance (R_θJA) of the combined PCB and device package and the temperature of the ambient

air (T_A). Equation 6 rearranges Equation 5 for output current.

T_J= T_A+ (R_θJA× P_D)

(5)

(6)

I_OUT= (T_J– T_A) / [R_θJA× (V_IN– V_OUT)]

Unfortunately, this thermal resistance (R_θJA) is highly dependent on the heat-spreading capability built into the

particular PCB design, and therefore varies according to the total copper area, copper weight, and location

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of the planes. The R_θJArecorded in the Recommended Operating Conditions table is determined by the

JEDEC standard, PCB, and copper-spreading area, and is only used as a relative measure of package thermal

performance. For a well-designed thermal layout, R_θJAis actually the sum of the VSON package junction-to-case

(bottom) thermal resistance (R_θJC(bot)) plus the thermal resistance contribution by the PCB copper.

8.1.9.1 Estimating Junction Temperature

The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures

of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal

resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics

are determined to be significantly independent of the copper-spreading area. The key thermal metrics (Ψ_JTand

Ψ_JB) are used in accordance with Equation 7 and are given in the Recommended Operating Conditions table.

Ψ_JT: T_J= T_T+ Ψ_JT× P_Dand Ψ_JB: T_J= T_B+ Ψ_JB× P_D

(7)

where:

•

P_Dis the power dissipated as explained in Equation 4

T_Tis the temperature at the center-top of the device package, and

T_Bis the PCB surface temperature measured 1 mm from the device package and centered on the package

edge

8.1.9.2 Recommended Area for Continuous Operation

The operational area of an LDO is limited by the dropout voltage, output current, junction temperature, and input

voltage. The recommended area for continuous operation for a linear regulator is given in Figure 8-6 and can be

separated into the following parts:

•

Dropout voltage limits the minimum differential voltage between the input and the output (V_IN– V_OUT) at a

given output current level. See the Dropout Voltage section for more details.

The rated output currents limits the maximum recommended output current level. Exceeding this rating

causes the device to fall out of specification.

The rated junction temperature limits the maximum junction temperature of the device. Exceeding this rating

causes the device to fall out of specification and reduces long-term reliability.

– The shape of the slope is given by Equation 6. The slope is nonlinear because the maximum rated

junction temperature of the LDO is controlled by the power dissipation across the LDO; thus when V_IN

V_OUTincreases the output current must decrease.

–

•

The rated input voltage range governs both the minimum and maximum of V_IN– V_OUT.

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Figure 8-6 shows the recommended area of operation for this device on a JEDEC-standard high-K board with a

R_θJAas given in the Recommended Operating Conditions table.

Output current limited

by dropout

Rated output

current

Output current limited by thermals

Limited by

minimum V_IN

Limited by

maximum V_IN

V_INœ V_OUT(V)

Figure 8-6. Region Description of Continuous Operation Regime

8.1.9.3 Power Dissipation versus Ambient Temperature

Figure 8-7 is based off of a JESD51-7 four-layer high-K board. The allowable power dissipation was estimated

using the following equation. As disscussed in the An empirical analysis of the impact of board layout on

LDO thermal performance application report, thermal dissipation can be improved in the JEDEC high-K layout

by adding top layer copper and increasing the number of thermal vias. If a good thermal layout is used, the

allowable thermal dissipation can be improved by up to 50%.

T_A+ R_θJAx P_D≤ 150°C

(8)

4.5

DRB Package

KVU Package

3.5

2.5

1.5

0.5

-40

-20

100 120 140

Ambient Temerature (èC)

Figure 8-7. Allowable Power Dissipation

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8.2 Typical Application

VIN

VOUT

OUT

CIN

COUT

DC/DC

Converter

TPS785-Q1

GND GND

GND

VEN

GND

Figure 8-8. Operation From a DC/DC Converter

8.2.1 Design Requirements

Table 8-1 summarizes the design requirement for this application.

Table 8-1. Design Parameters

PARAMETER

DESIGN REQUIREMENT

Input voltage

Output voltage

4.05 V

3.3 V, ±1.5%

600 mA

10 µF

Output load

Output capacitor

Maximum ambient temperature

85°C

8.2.2 Detailed Design Procedure

For this design example, the 3.3-V, fixed-version device is selected. The device is powered of a DC/DC

converter connected to a battery. A 750-mV headroom between V_INand V_OUTis used to keep the device within

the dropout voltage specification and to ensure the device stays in regulation under all load and temperature

conditions for this design.

8.2.3 Application Curve

A 10-µF capacitor is used to reduce overshoot and undershoot of output voltage during load transients with

ramps rates greater than 1 A/μs. Figure 8-9 shows a capture of load transient behavior for this application.

2,000

1,800

1,600

1,400

1,200

1,000

800

V_OUT

I_OUT

-20

-40

-60

-80

-100

-120

-140

600

400

200

2,000

400

800

1,200

1,600

Time (ms)

V_IN= 4.05 V, V_OUT= 3.3 V, C_OUT= 10 µF,

I_OUTslew rate = 1 A/µs

Figure 8-9. I_OUTTransient From 1 mA to 600 mA

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9 Power Supply Recommendations

This device is designed to operate from an input supply voltage range of 1.95 V to 6.0 V. The input supply must

be well regulated and free of spurious noise. To ensure that the output voltage is well regulated and dynamic

performance is optimum, the input supply must be at least V_OUT(nom)+ 0.75 V. TI requires using a 1-µF or greater

input capacitor to reduce the impedance of the input supply, especially during transients.

10 Layout

10.1 Layout Guidelines

•

Place input and output capacitors as close to the device as possible.

Use copper planes for device connections in order to optimize thermal performance.

Place thermal vias around the device to distribute the heat.

Only place tented thermal vias directly beneath the thermal pad of the DRB package. An untented via can

wick solder or solder paste away from the thermal pad joint during the soldering process, leading to a

compromised solder joint on the thermal pad.

10.1.1 Additional Layout Considerations

The high impedance of the FB pin makes the regulator sensitive to parasitic capacitances that may couple

undesirable signals from nearby components (especially from logic and digital devices, such as microcontrollers

and microprocessors); these capacitively coupled signals may produce undesirable output voltage transients. In

these cases, TI recommends using a fixed-voltage version of the device, or isolating the FB node by placing a

copper ground plane on the layer directly underneath the LDO circuitry and FB pin to minimize any undesirable

signal coupling.

110

100

110

100

1oz PCB

2oz PCB

1oz PCB

2oz PCB

100

PCB Copper Area (cm²)

4-layer PCB

2-layer PCB

Figure 10-1. Junction-to-Ambient Thermal

Resistance (R_θJA) vs PCB Copper Area (DRB

Package)

Figure 10-2. Junction-to-Ambient Thermal

Resistance (R_θJA) vs PCB Copper Area (DRB

Package)

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1oz PCB

2oz PCB

1oz PCB

2oz PCB

100

90 100

PCB Cuppoer Area (cm²)

PCB Copper Area (cm²)

4-layer PCB

2-layer PCB

Figure 10-3. Junction-to-Board Characterization

Parameter (ψ_JB) vs PCB Copper Area (DRB

Package)

Figure 10-4. Junction-to-Board Characterization

Parameter (ψ_JB) vs PCB Copper Area (DRB

Package)

105

2 Layer PCB, 1 oz copper

2 Layer PCB, 2 oz copper

4 Layer PCB, 1 oz copper

4 Layer PCB, 2 oz copper

2 Layer PCB, 2 oz copper

4 Layer PCB, 1 oz copper

4 Layer PCB, 2 oz copper

90 100

Cu Area Per Layer (cm²)

Figure 10-5. Junction-to-Ambient Thermal

Resistance (R_θJA) vs PCB Copper Area (KVU

Package)

Figure 10-6. Junction-to-Board Characterization

Parameter (ψ_JB) vs PCB Copper Area (KVU

Package)

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10.2 Layout Examples

C_OUT

C_IN

R1 OUT

OUT

C_FF

GND

GND PLANE

Represents a thermal via

Figure 10-8. Layout Example for the DRB Package

Fixed Version

Figure 10-7. Layout Example for the DRB Package

Adjustable Version

GND PLANE

Thermal Pad

GND

CFF

C_OUT

GND

C_IN

C_OUT

OUT

EN IN

OUT

EN IN

Feed-forward capacitor

CFF is not required for

stability (optional)

Routing via

Thermal via

Routing via

Thermal via

Figure 10-10. Layout Example for the KVU Package

Fixed Version

Figure 10-9. Layout Example for the KVU Package

Adjustable Version

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11 Device and Documentation Support

11.1 Device Support

11.1.1 Device Nomenclature

Table 11-1. Device Nomenclature

PRODUCT^{(1) (2)}

V_OUT

xx(x) is the nominal output voltage. For output voltages with a resolution of 100 mV, two digits are used

in the ordering number; otherwise, three digits are used (for example, 28 = 2.8 V or 01 = adjustable).

W denotes a wettable flank package.

TPS785xx(x)Q(W)yyyRQ1

yyy is the package designator.

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the

device product folder on www.ti.com.

(2) Output voltages from 0.65 V to 5.5 V in 50-mV increments are available. Contact the factory for details and availability.

11.2 Documentation Support

11.2.1 Related Documentation

For related documentation see the following:

•

Texas Instruments, Universal Low-Dropout (LDO) Linear Voltage Regulator MultiPkgLDOEVM-823 Evaluation

Module user's guide

Texas Instruments, Pros and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator

application report

Texas Instruments, An empirical analysis of the impact of board layout on LDO thermal performance

application report

11.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

11.4 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

11.5 Trademarks

TI E2E^™is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

11.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

11.7 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

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22-Apr-2021

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

PTPS78501QKVURQ1

PTPS78501QWDRBRQ1

PTPS78518QKVURQ1

PTPS78518QWDRBRQ1

PTPS78533QKVURQ1

PTPS78533QWDRBRQ1

PTPS78550QKVURQ1

PTPS78550QWDRBRQ1

ACTIVE

TO-252

SON

KVU

2500

3000

2500

3000

2500

3000

2500

3000

Non-RoHS &

Non-Green

Call TI

-40 to 150

ACTIVE

DRB

KVU

Non-RoHS &

Non-Green

Call TI

TO-252

SON

Non-RoHS &

Non-Green

DRB

KVU

Non-RoHS &

Non-Green

TO-252

SON

Non-RoHS &

Non-Green

DRB

KVU

Non-RoHS &

Non-Green

TO-252

SON

Non-RoHS &

Non-Green

DRB

Non-RoHS &

Non-Green

TPS78501QKVURQ1

TPS78501QWDRBRQ1

TPS785075QWDRBRQ1

TPS78510QKVURQ1

TPS78510QWDRBRQ1

TPS78511QKVURQ1

TPS78511QWDRBRQ1

TPS78512QKVURQ1

TPS78512QWDRBRQ1

TPS78518QKVURQ1

ACTIVE

TO-252

SON

KVU

DRB

KVU

DRB

KVU

DRB

KVU

DRB

KVU

2500 RoHS & Green

3000 RoHS & Green

2500 RoHS & Green

3000 RoHS & Green

2500 RoHS & Green

3000 RoHS & Green

2500 RoHS & Green

3000 RoHS & Green

2500 RoHS & Green

NIPDAU

Level-3-260C-168 HR

Level-2-260C-1 YEAR

Level-3-260C-168 HR

Level-2-260C-1 YEAR

Level-3-260C-168 HR

Level-2-260C-1 YEAR

Level-3-260C-168 HR

Level-2-260C-1 YEAR

Level-3-260C-168 HR

-40 to 150

8501QKVU

8501QW

SON

85075Q

TO-252

SON

8510QKVU

8510QW

NIPDAU

TO-252

SON

8511QKVU

8511QW

NIPDAU

TO-252

SON

8512QKVU

8512QW

NIPDAU

TO-252

8518QKVU

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

22-Apr-2021

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS78518QWDRBRQ1

TPS78533QKVURQ1

TPS78533QWDRBRQ1

TPS78550QKVURQ1

TPS78550QWDRBRQ1

ACTIVE

SON

TO-252

SON

DRB

KVU

DRB

KVU

DRB

3000 RoHS & Green

2500 RoHS & Green

3000 RoHS & Green

2500 RoHS & Green

3000 RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

Level-3-260C-168 HR

Level-2-260C-1 YEAR

Level-3-260C-168 HR

Level-2-260C-1 YEAR

-40 to 150

8518QW

8533QKVU

8533QW

NIPDAU

TO-252

SON

8550QKVU

8550QW

NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

22-Apr-2021

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com

22-Apr-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS78501QKVURQ1

TPS78510QKVURQ1

TPS78511QKVURQ1

TPS78512QKVURQ1

TPS78518QKVURQ1

TPS78533QKVURQ1

TPS78550QKVURQ1

TO-252

KVU

2500

330.0

16.4

6.9

10.5

2.7

8.0

16.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

22-Apr-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS78501QKVURQ1

TPS78510QKVURQ1

TPS78511QKVURQ1

TPS78512QKVURQ1

TPS78518QKVURQ1

TPS78533QKVURQ1

TPS78550QKVURQ1

TO-252

KVU

2500

340.0

38.0

Pack Materials-Page 2

PACKAGE OUTLINE

VSON - 1 mm max height

DRB0008J

PLASTIC QUAD FLAT PACK- NO LEAD

3.1

2.9

PIN 1 INDEX AREA

3.1

2.9

0.1 MIN

(0.13)

SECTION A-A

TYPICAL

1 MAX

SEATING PLANE

0.08 C

0.05

0.00

1.75

1.55

(0.2) TYP

6X 0.65

(0.19)

SYMM

2.5

2.3

1.95

0.36

0.26

PIN 1 ID

(OPTIONAL)

0.1

0.05

C A B

SYMM

0.5

0.3

4225036/A 06/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

VSON - 1 mm max height

DRB0008J

PLASTIC QUAD FLAT PACK- NO LEAD

(2.8)

(1.65)

8X (0.6)

8X (0.31)

SYMM

6X (0.65)

SYMM

(1.95) (2.4)

(0.95)

(R0.05) TYP

(Ø 0.2) VIA

TYP

(0.575)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 20X

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

METAL

SOLDER MASK

OPENING

EXPOSED METAL

SOLDER MASK

OPENING

METAL

NON- SOLDER MASK

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4225036/A 06/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

VSON - 1 mm max height

DRB0008J

PLASTIC QUAD FLAT PACK- NO LEAD

(2.8)

(1.51)

8X (0.6)

8X (0.31)

SYMM

(1.06)

6X (0.65)

SYMM

(1.95)

(0.63)

(R0.05) TYP

METAL

TYP

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

81% PRINTED COVERAGE BY AREA

SCALE: 20X

4225036/A 06/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TPS78512QWDRBRQ1 [TI]

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