TPS78633KTTRG3 [TI]
ULTRALOW-NOISE, HIGH-PSRR, FAST, RF, 1.5-A LOW-DROPOUT LINEAR REGULATORS; 超低噪声，高PSRR ，快速射频， 1.5 -A低压差线性稳压器
| 型号： | TPS78633KTTRG3 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ULTRALOW-NOISE, HIGH-PSRR, FAST, RF, 1.5-A LOW-DROPOUT LINEAR REGULATORS |
| 文件： | 总21页 (文件大小：753K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS786xx
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SLVS389G–SEPTEMBER 2002–REVISED JULY 2006
ULTRALOW-NOISE, HIGH-PSRR, FAST, RF, 1.5-A
LOW-DROPOUT LINEAR REGULATORS
FEATURES
DESCRIPTION
•
1.5-A Low-Dropout Regulator With Enable
The TPS786xx family of low-dropout (LDO)
low-power linear voltage regulators features high
power-supply rejection ratio (PSRR), ultralow noise,
fast start-up, and excellent line and load transient
responses in small outline, SOT223-6 and DDPAK-5
packages. Each device in the family is stable, with a
small 1-µF ceramic capacitor on the output. The
family uses an advanced, proprietary BiCMOS
fabrication process to yield extremely low dropout
voltages (for example, 390 mV at 1.5 A). Each
device achieves fast start-up times (approximately 50
•
Available in Fixed and Adjustable (1.2-V to
5.5-V) Output Versions
•
•
•
•
•
•
High PSRR (49 dB at 10 kHz)
Ultralow Noise (48 µVRMS, TPS78630)
Fast Start-Up Time (50 µs)
Stable With a 1-µF Ceramic Capacitor
Excellent Load/Line Transient Response
Very Low Dropout Voltage (390 mV at Full
Load, TPS78630)
µs with
a 0.001 µF bypass capacitor) while
consuming very low quiescent current (265 µA,
typical). Moreover, when the device is placed in
standby mode, the supply current is reduced to less
than 1 µA. The TPS78630 exhibits approximately 48
µVRMS of output voltage at 3.0 V output noise with a
0.1 µF bypass capacitor. Applications with analog
components that are noise sensitive, such as
portable RF electronics, benefit from the high PSRR,
low noise features, and the fast response time.
•
6-Pin SOT223 and 5-Pin DDPAK Package
APPLICATIONS
•
•
•
•
•
RF: VCOs, Receivers, ADCs
Audio
Bluetooth®, Wireless LAN
Cellular and Cordless Telephones
Handheld Organizers, PDAs
TPS78630
TPS78630
DCQ PACKAGE
SOT223-6
(TOP VIEW)
RIPPLE REJECTION
vs
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
FREQUENCY
1
2
3
4
EN
IN
GND
OUT
NR/FB
80
70
60
50
40
30
20
10
0
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
V
= 4 V
IN
V
= 5.5 V
= 2.2 µF
6
GND
IN
C
C
= 10 µF
C
C
OUT
= 0.01 µF
OUT
= 0.1 µF
I
= 1 mA
= 1.5 A
OUT
NR
NR
5
I
OUT
KTT PACKAGE
DDPAK-5
(TOP VIEW)
I
= 1 mA
OUT
EN
1
2
IN
GND
I
= 1.5 A
OUT
TAB
GND
3
4
OUT
1
10
100
1k
10k 100k 1M 10M
100
1k
10k
100k
NR/FB
Frequency (Hz)
Frequency (Hz)
5
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2006, Texas Instruments Incorporated
TPS786xx
www.ti.com
SLVS389G–SEPTEMBER 2002–REVISED JULY 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
ORDERING INFORMATION(1)
(2)
PRODUCT
VOUT
TPS786xxyyyz
XX is nominal output voltage (for example, 28 = 2.8 V, 285 = 2.85 V, 01 = Adjustable).
YYY is package designator.
Z is package quantity.
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Output voltages from 1.3 V to 5.0 V in 100 mV increments are available; minimum order quantities may apply. Contact factory for details
and availability.
ABSOLUTE MAXIMUM RATINGS
over operating temperature (unless otherwise noted)(1)
VALUE
VIN range
–0.3 V to 6 V
–0.3 V to VIN + 0.3 V
6 V
VEN range
VOUT range
Peak output current
ESD rating, HBM
Internally limited
2 kV
ESD rating, CDM
500 V
Continuous total power dissipation
Junction temperature range, TJ
Storage temperature range, Tstg
See Dissipation Ratings table
–40°C to +150°C
–65°C to +150°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
PACKAGE DISSIPATION RATINGS
PACKAGE
DDPAK
BOARD
High-K(1)
Low-K(2)
RθJC
RθJA
2 °C/W
15 °C/W
23 °C/W
53 °C/W
SOT223
(1) The JEDEC high-K (2s2p) board design used to derive this data was a 3-in x 3-in (7,5-cm x 7,5-cm), multilayer board with 1 ounce
internal power and ground planes and 2 ounce copper traces on top and bottom of the board.
(2) The JEDEC low-K (1s) board design used to derive this data was a 3-in x 3-in (7,5-cm x 7,5cm), two-layered board with 2 ounce copper
traces on top of the board.
2
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SLVS389G–SEPTEMBER 2002–REVISED JULY 2006
ELECTRICAL CHARACTERISTICS
Over recommended operating temperature range (TJ = –40°C to +125°C), VEN = VIN, VIN = VOUT(nom) + 1 V(1), IOUT = 1 mA,
COUT = 10 µF, CNR = 0.01 µF, unless otherwise noted. Typical values are at +25°C.
PARAMETER
TEST CONDITIONS
MIN
2.7
TYP
MAX
5.5
UNIT
V
(1)
Input voltage, VIN
Internal reference, VFB (TPS78601)
Continuous output current IOUT
1.200
0
1.225
1.250
V
1.5
A
Output voltage range TPS78601
1.225
(0.98)VOUT
–2.0
5.5 – VDO
V
Output
voltage
TPS78601(2) 0 µA ≤ IOUT ≤ 1.5 A, VOUT + 1 V ≤ VIN ≤ 5.5 V(1)
VOUT (1.02)VOUT
+2.0
V
Accuracy
Fixed VOUT
0 µA ≤ IOUT ≤ 1.5 A, VOUT + 1 V ≤ VIN ≤ 5.5 V
VOUT + 1 V ≤ VIN ≤ 5.5 V
0 µA ≤ IOUT ≤ 1.5 A
IOUT = 1.5 A
%
(1)
Output voltage line regulation (∆VOUT%/VIN
)
5
7
12
%/V
mV
Load regulation (∆VOUT%/VOUT
)
TPS78628
TPS78630
TPS78633
410
390
340
580
550
510
4.2
385
1
Dropout voltage(3)
VIN = VOUT(nom)– 0.1 V
IOUT = 1.5 A
mV
IOUT = 1.5 A
Output current limit
Ground pin current
Shutdown current(4)
FB pin current
VOUT = 0 V
2.4
A
0 µA ≤ IOUT ≤ 1.5 A
VEN = 0 V, 2.7 V ≤ VIN ≤ 5.5 V
VFB = 1.225 V
260
µA
µA
µA
0.07
1
f = 100 Hz, IOUT = 10 mA
f = 100 Hz, IOUT = 1.5 A
f = 10 kHz, IOUT = 1.5 A
f = 100 kHz, IOUT = 1.5 A
CNR = 0.001 µF
59
52
49
32
66
51
49
48
50
75
110
Power-supply ripple rejection
TPS78630
dB
CNR = 0.0047 µF
BW = 100 Hz to 100 kHz,
Output noise voltage (TPS78630)
Time, start-up (TPS78630)
µVRMS
IOUT = 1.5 A
CNR = 0.01 µF
CNR = 0.1 µF
CNR = 0.001 µF
RL = 2 Ω, COUT = 1 µF
CNR = 0.0047 µF
CNR = 0.01 µF
µs
High-level enable input voltage
Low-level enable input voltage
EN pin current
2.7 V ≤ VIN ≤ 5.5 V
2.7 V ≤ VIN ≤ 5.5 V
VEN = 0
1.7
0
VIN
0.7
1
V
V
–1
µA
V
UVLO threshold
VCC rising
2.25
2.65
UVLO hysteresis
100
mV
(1) Minimum VIN = VOUT + VDO or 2.7 V, whichever is greater.
(2) Tolerance of external resistors not included in this specification.
(3) Dropout is not measured for TPS78618 or TPS78625 since minimum VIN = 2.7 V.
(4) For adjustable version, this applies only after VIN is applied; then VEN transitions high to low.
3
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SLVS389G–SEPTEMBER 2002–REVISED JULY 2006
FUNCTIONAL BLOCK DIAGRAM—ADJUSTABLE VERSION
IN
OUT
Ω
300
Current
Sense
UVLO
Overshoot
Detect
GND
EN
ILIM
SHUTDOWN
R1
R2
FB
UVLO
Thermal
Shutdown
Quickstart
External to
the Device
Bandgap
Reference
1.225 V
VREF
VIN
Ω
250 k
FUNCTIONAL BLOCK DIAGRAM—FIXED VERSION
IN
OUT
Ω
300
Current
Sense
UVLO
Overshoot
Detect
GND
EN
ILIM
SHUTDOWN
R1
R2
UVLO
Thermal
Shutdown
Ω
R2 = 40 k
Quickstart
Bandgap
Reference
1.225 V
VREF
VIN
NR
Ω
250 k
Terminal Functions
TERMINAL
DCQ
KTT
NAME
(SOT223)
(DDPAK)
DESCRIPTION
Noise-reduction pin for fixed versions only. An external bypass capacitor, connected to this terminal, in conjunction
with an internal resistor, creates a low-pass filter to further reduce regulator noise.
NR
5
1
5
The EN terminal is an input that enables or shuts down the device. When EN is a logic high, the device is enabled.
When the device is a logic low, the device is in shutdown mode.
EN
1
FB
GND
IN
5
3, 6
2
5
Feedback input voltage for the adjustable device.
Regulator ground
3, TAB
2
4
Input supply
OUT
4
Regulator output
4
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SLVS389G–SEPTEMBER 2002–REVISED JULY 2006
TYPICAL CHARACTERISTICS
TPS78630
TPS78628
TPS78628
OUTPUT VOLTAGE
OUTPUT VOLTAGE
GROUND CURRENT
vs OUTPUT CURRENT
vs JUNCTION TEMPERATURE
vs JUNCTION TEMPERATURE
2.798
3.05
3.04
3.03
3.02
3.01
3.00
2.99
2.98
2.97
2.96
2.95
350
V
C
= 4 V
= 10 µF
OUT
= 25°C
V
C
= 3.8 V
V
= 3.8 V
IN
IN
IN
= 10 µF
C
OUT
= 10 µF
OUT
340
330
320
310
300
290
2.794
T
J
I
= 1 mA
OUT
2.790
I
= 1.5 A
OUT
2.786
I
= 1.5 A
OUT
I
= 1 mA
OUT
2.782
2.778
0.0
0.3
0.6
0.9
(A)
1.2
1.5
−40−25−10
5
20 35 50 65 80 95 110 125
(°C)
−40−25−10
5
20 35 50 65 80 95 110 125
(°C)
I
T
J
T
J
OUT
Figure 1.
Figure 2.
Figure 3.
TPS78630
TPS78630
TPS78630
OUTPUT SPECTRAL
NOISE DENSITY
vs FREQUENCY
OUTPUT SPECTRAL
NOISE DENSITY
vs FREQUENCY
OUTPUT SPECTRAL
NOISE DENSITY
vs FREQUENCY
0.6
0.5
0.4
0.3
0.2
0.1
0.0
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
V
C
C
= 5.5 V
V
C
C
= 5.5 V
V
= 5.5 V
IN
= 10 µF
OUT
= 1.5 A
IN
IN
= 2.2 µF
= 10 µF
C
I
OUT
= 0.1 µF
OUT
= 0.1 µF
NR
NR
OUT
I
= 1.5 A
OUT
C
NR
= 0.1 µF
C
NR
= 0.0047 µF
I
= 1 mA
C
NR
= 0.01 µF
OUT
C
= 0.001 µF
NR
I
= 1 mA
OUT
I
= 1.5 A
OUT
100
1k
10k
100k
100
1k
10k
100k
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
Frequency (Hz)
Figure 4.
Figure 5.
Figure 6.
TPS78630
ROOT MEAN SQUARED
OUTPUT NOISE
TPS78628
TPS78630
RIPPLE REJECTION
vs FREQUENCY
DROPOUT VOLTAGE
vs BYPASS CAPACITANCE
vs JUNCTION TEMPERATURE
80
70
60
50
40
30
20
10
0
600
500
400
300
200
100
0
80
70
60
50
40
30
20
10
0
V
C
C
= 4 V
V
= 2.7 V
= 10 µF
OUT
= 1.5 A
IN
IN
= 10 µF
C
I
OUT
= 0.01 µF
I
= 1 mA
OUT
NR
OUT
I
= 1.5 A
OUT
I
C
= 1.5 A
= 10 µF
OUT
OUT
BW = 100 Hz to 100 kHz
0.001 µF
0.0047 µF
0.01 µF
(µF)
0.1 µF
−40−25−10
5
20 35 50 65 80 95 110 125
(°C)
1
10
100
1k 10k 100k 1M 10M
C
NR
f (Hz)
T
J
Figure 7.
Figure 8.
Figure 9.
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SLVS389G–SEPTEMBER 2002–REVISED JULY 2006
TYPICAL CHARACTERISTICS (continued)
TPS78630
RIPPLE REJECTION
vs FREQUENCY
TPS78630
RIPPLE REJECTION
vs FREQUENCY
TPS78630
RIPPLE REJECTION
vs FREQUENCY
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
V
C
C
= 4 V
V
C
C
= 4 V
V
C
C
= 4 V
IN
= 2.2 µF
OUT
= 0.01 µF
NR
IN
IN
= 2.2 µF
= 10 µF
OUT
= 0.1 µF
OUT
= 0.1 µF
I
= 1 mA
I
= 1 mA
I
= 1 mA
= 1.5 A
OUT
OUT
OUT
NR
NR
I
OUT
I
= 1.5 A
OUT
I
= 1.5 A
OUT
1
10
100
1k 10k 100k 1M 10M
1
10
100
1k 10k 100k 1M 10M
1
10
100
1k 10k 100k 1M 10M
f (Hz)
f (Hz)
f (Hz)
Figure 10.
Figure 11.
Figure 12.
TPS78618
LINE TRANSIENT RESPONSE
TPS78630
LINE TRANSIENT RESPONSE
TPS78628
LOAD TRANSIENT RESPONSE
5
4
3
2
2
1
0
6
5
4
3
V
C
C
= 3.8 V
I
C
C
= 1.5 A
IN
di
dt
dv
dt
OUT
1.5 A
ms
1 V
ms
dv
dt
1 V
ms
−1
I
C
C
= 1.5 A
= 10 µF
OUT
= 0.01 µF
OUT
+
+
+
= 10 µF
= 10 µF
OUT
= 0.01 µF
OUT
= 0.01 µF
NR
NR
60
30
150
75
80
40
NR
0
0
0
−30
−60
−75
−150
−40
−80
0
20 40 60 80 100 120 140 160 180 200
0
100 200 300 400 500 600 700 800 900 1000
0
20 40 60 80 100 120 140 160 180 200
t (µs)
t (µs)
t (µs)
Figure 13.
Figure 14.
Figure 15.
TPS78625
POWER UP/
POWER DOWN
TPS78630
DROPOUT VOLTAGE
vs OUTPUT CURRENT
TPS78601
DROPOUT VOLTAGE
vs INPUT VOLTAGE
600
4.0
3.5
3.0
2.5
500
450
400
350
300
250
200
150
100
50
V
R
C
= 2.5 V
= 1.6 Ω
= 0.01 µF
OUT
L
500
400
300
200
100
0
NR
T
= 125°C
= 25°C
J
T
= 125°C
J
T
J
T
J
= 25°C
2.0
1.5
1.0
0.5
0
T
J
= −40°C
V
IN
T
J
= −40°C
I
= 1.5 A
OUT
V
OUT
C
C
= 10 µF
OUT
= 0.01 µF
NR
0
0
200 400 600 800 1000 1200 1400
(mA)
0
400
800
1200
1600
2000
2.5
3.0
3.5
4.0
(V)
4.5
5.0
I
V
Time (µs)
OUT
IN
Figure 16.
Figure 17.
Figure 18.
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SLVS389G–SEPTEMBER 2002–REVISED JULY 2006
TYPICAL CHARACTERISTICS (continued)
TPS78630
TYPICAL REGIONS OF STABILITY
EQUIVALENT SERIES RESISTANCE
(ESR)
TPS78630
TYPICAL REGIONS OF STABILITY
EQUIVALENT SERIES RESISTANCE
(ESR)
MINIMUM REQUIRED
INPUT VOLTAGE
vs
OUTPUT VOLTAGE
vs OUTPUT CURRENT
vs OUTPUT CURRENT
100
5.0
4.5
4.0
3.5
3.0
2.5
2.0
100
C
OUT
= 1 µF
C
OUT
= 2.2 µF
I
= 1.5 A
OUT
Region of
Instability
Region of
Instability
10
10
T
J
= 125°C
1
0.1
1
0.1
Region of Stability
Region of Stability
T
J
= −40°C
T
J
= 25°C
0.01
0.01
1
30
125
500
(mA)
1000
1500
1.5
2.0
2.5
3.0
(V)
3.5
4.0
1
30
125
500
(mA)
1000
1500
I
I
OUT
OUT
V
OUT
Figure 19.
Figure 20.
Figure 21.
TPS78630
TYPICAL REGIONS OF STABILITY
EQUIVALENT SERIES RESISTANCE
(ESR)
vs OUTPUT CURRENT
START-UP
100
10
3
2.75
2.50
2.25
2
V
C
= 4 V,
IN
C
OUT
= 10 µF
C
=
NR
= 10 µF,
OUT
0.0047 µF
I
= 1.5 A
IN
Region of
Instability
Enable
C
=
NR
0.001 µF
1.75
1.50
1.25
1
1
0.1
C
=
NR
0.01 µF
Region of Stability
0.75
0.50
0.25
0
0.01
0
100
200
300
400
500
600
1
30
125
500
(mA)
1000
1500
t (µs)
I
OUT
Figure 22.
Figure 23.
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SLVS389G–SEPTEMBER 2002–REVISED JULY 2006
APPLICATION INFORMATION
because any leakage current creates an IR drop
across the internal resistor, thus creating an output
error. Therefore, the bypass capacitor must have
minimal leakage current. The bypass capacitor
should be no more than 0.1-µF to ensure that it is
fully charged during the quickstart time provided by
the internal switch shown in the functional block
diagram.
The TPS786xx family of low-dropout (LDO)
regulators has been optimized for use in
noise-sensitive equipment. The device features
extremely low dropout voltages, high PSRR, ultralow
output noise, low quiescent current (265 µA,
typically), and enable input to reduce supply currents
to less than 1 µA when the regulator is turned off.
A typical application circuit is shown in Figure 24.
For example, the TPS78630 exhibits only 48 µVRMS
of output voltage noise using a 0.1-µF ceramic
bypass capacitor and
a 10-µF ceramic output
VIN
VOUT
capacitor. Note that the output starts up slower as
the bypass capacitance increases due to the RC
time constant at the bypass pin that is created by the
internal 250-kΩ resistor and external capacitor.
IN
OUT
TPS786xx
GND
µ
µ
F
0.1
F
2.2
EN
NR
µ
0.01
F
BOARD LAYOUT RECOMMENDATIONS TO
IMPROVE PSRR AND NOISE
PERFORMANCE
Figure 24. Typical Application Circuit
To improve ac measurements like PSRR, output
noise, and transient response, it is recommended
that the board be designed with separate ground
planes for VIN and VOUT, with each ground plane
connected only at the ground pin of the device. In
addition, the ground connection for the bypass
capacitor should connect directly to the ground pin of
the device.
EXTERNAL CAPACITOR REQUIREMENTS
A 2.2-µF or larger ceramic input bypass capacitor,
connected between IN and GND and located close
to the TPS786xx, is required for stability and
improves transient response, noise rejection, and
ripple rejection. A higher-value input capacitor may
be necessary if large, fast-rise-time load transients
are anticipated and the device is located several
inches from the power source.
REGULATOR MOUNTING
The tab of the SOT223-6 package is electrically
connected to ground. For best thermal performance,
the tab of the surface-mount version should be
soldered directly to a circuit-board copper area.
Increasing the copper area improves heat
dissipation.
Like most low-dropout regulators, the TPS786xx
requires an output capacitor connected between
OUT and GND to stabilize the internal control loop.
The minimum recommended capacitor is 1 µF. Any
1 µF or larger ceramic capacitor is suitable.
Solder pad footprint recommendations for the
devices are presented in Application Report
SBFA015, Solder Pad Recommendations for
Surface-Mount Devices, available from the TI web
site at www.ti.com.
The internal voltage reference is a key source of
noise in an LDO regulator. The TPS786xx has an
NR pin which is connected to the voltage reference
through a 250-kΩ internal resistor. The 250-kΩ
internal resistor, in conjunction with an external
bypass capacitor connected to the NR pin, creates a
low pass filter to reduce the voltage reference noise
and, therefore, the noise at the regulator output. In
order for the regulator to operate properly, the
current flow out of the NR pin must be at a minimum,
8
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SLVS389G–SEPTEMBER 2002–REVISED JULY 2006
PROGRAMMING THE TPS78601
ADJUSTABLE LDO REGULATOR
In order to improve the stability of the adjustable
version, it is suggested that a small compensation
capacitor be placed between OUT and FB.
The output voltage of the TPS78601 adjustable
regulator is programmed using an external resistor
divider as shown in Figure 25. The output voltage is
calculated using Equation 1:
The approximate value of this capacitor can be
calculated using Equation 3:
−7
(3 x 10 ) x (R ) R )
1
2
C
+
1
R
ǒ Ǔ
(R x R )
1
1
2
(3)
V
+ V
1 )
OUT
REF
R
2
(1)
The suggested value of this capacitor for several
resistor ratios is shown in the table below. If this
capacitor is not used (such as in a unity-gain
configuration), then the minimum recommended
output capacitor is 2.2 µF instead of 1 µF.
where:
•
VREF = 1.2246 V typ (the internal reference
voltage)
Resistors R1 and R2 should be chosen for
approximately 40-µA divider current. Lower value
resistors can be used for improved noise
performance, but the device wastes more power.
Higher values should be avoided, as leakage current
at FB increases the output voltage error.
REGULATOR PROTECTION
The TPS786xx PMOS-pass transistor has a built-in
back diode that conducts reverse current when the
input voltage drops below the output voltage (for
example, during power down). Current is conducted
from the output to the input and is not internally
limited. If extended reverse voltage operation is
anticipated, external limiting might be appropriate.
The recommended design procedure is to choose
R2 = 30.1 kΩ to set the divider current at 40 µA,
C1 = 15 pF for stability, and then calculate R1 using
Equation 2:
The TPS786xx features internal current limiting and
thermal protection. During normal operation, the
TPS786xx limits output current to approximately
2.8 A. When current limiting engages, the output
voltage scales back linearly until the overcurrent
condition ends. While current limiting is designed to
prevent gross device failure, care should be taken
not to exceed the power dissipation ratings of the
package. If the temperature of the device exceeds
approximately 165°C, thermal-protection circuitry
shuts it down. Once the device has cooled down to
below approximately 140°C, regulator operation
resumes.
V
ǒ Ǔ
OUT
R +
* 1 R
1
2
V
REF
(2)
OUTPUT VOLTAGE
PROGRAMMING GUIDE
VIN
VOUT
IN
EN
OUT
FB
OUTPUT
TPS78601
R1
R2
C1
µ
1
F
VOLTAGE
R
1
R
2
C
1
µ
2.2
F
GND
1.8 V
14.0 kΩ
57.9 kΩ
30.1 kΩ
30.1 kΩ
33 pF
15 pF
3.6 V
Figure 25. TPS78601 Adjustable LDO Regulator Programming
9
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SLVS389G–SEPTEMBER 2002–REVISED JULY 2006
THERMAL INFORMATION
increase in temperature due to the regulator power
dissipation. The temperature rise is computed by
multiplying the maximum expected power dissipation
by the sum of the thermal resistances between the
junction and the case (RθJC), the case to heatsink
(RθCS), and the heatsink to ambient (RθSA). Thermal
resistances are measures of how effectively an
object dissipates heat. Typically, the larger the
device, the more surface area available for power
dissipation and the lower the object's thermal
resistance.
The amount of heat that an LDO linear regulator
generates is directly proportional to the amount of
power it dissipates during operation. All integrated
circuits have
a
maximum allowable junction
temperature (TJmax) above which normal operation
is not assured. A system designer must design the
operating environment so that the operating junction
temperature (TJ) does not exceed the maximum
junction temperature (TJmax). The two main
environmental variables that a designer can use to
improve thermal performance are air flow and
external heatsinks. The purpose of this information is
to aid the designer in determining the proper
operating environment for a linear regulator that is
operating at a specific power level.
Figure 26 illustrates these thermal resistances for (a)
a SOT223 package mounted in a JEDEC low-K
board, and (b) a DDPAK package mounted on a
JEDEC high-K board.
In general, the maximum expected power (PDmax)
consumed by a linear regulator is computed as
shown in Equation 4:
Equation 5 summarizes the computation:
ǒ
qSAǓ
(5)
T
+ T ) P max R
) R
) R
qCS
J
A
D
qJC
ǒ
Ǔ
PD max + VIN(avg) * VOUT(avg) IOUT(avg) ) VIN(avg) IQ
The RθJC is specific to each regulator as determined
by its package, lead frame, and die size provided in
the regulator data sheet. The RθSA is a function of
the type and size of heatsink. For example, black
body radiator type heatsinks can have RθCS values
ranging from 5°C/W for very large heatsinks to
50°C/W for very small heatsinks. The RθCS is a
function of how the package is attached to the
heatsink. For example, if a thermal compound is
used to attach a heatsink to a SOT223 package,
(4)
where:
•
•
•
•
VIN(avg) is the average input voltage.
VOUT(avg) is the average output voltage.
IOUT(avg) is the average output current.
IQ is the quiescent current.
For most TI LDO regulators, the quiescent current is
insignificant compared to the average output current;
therefore, the term VIN(avg)× IQ can be neglected. The
operating junction temperature is computed by
adding the ambient temperature (TA) and the
RθCS of 1°C/W is reasonable.
T
T
A
J
A
CIRCUIT BOARD COPPER AREA
R
θ
JC
B
C
B
C
B
R
θ
θ
CS
A
C
R
SA
C
DDPAK Package
(b)
SOT223 Package
(a)
T
A
Figure 26. Thermal Resistances
10
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SLVS389G–SEPTEMBER 2002–REVISED JULY 2006
Even if no external black body radiator type heatsink
is attached to the package, the board on which the
regulator is mounted provides some heatsinking
through the pin solder connections. Some packages,
like the DDPAK and SOT223 packages, use a
copper plane underneath the package or the circuit
board ground plane for additional heatsinking to
improve their thermal performance. Computer-aided
thermal modeling can be used to compute very
accurate approximations of an integrated circuit's
From Figure 27, DDPAK Thermal Resistance vs
Copper Heatsink Area, the ground plane needs to be
1 cm2 for the part to dissipate 2.5 W. The operating
environment used in the computer model to construct
Figure 27 consisted of a standard JEDEC High-K
board (2S2P) with a 1 oz. internal copper plane and
ground plane. The package is soldered to a 2 oz.
copper pad. The pad is tied through thermal vias to
the 1 oz. ground plane. Figure 28 shows the side
view of the operating environment used in the
computer model.
thermal
performance
in
different
operating
environments (for example, different types of circuit
boards, different types and sizes of heatsinks,
different air flows, etc.). Using these models, the
three thermal resistances can be combined into one
thermal resistance between junction and ambient
(RθJA). This RθJA is valid only for the specific
operating environment used in the computer model.
40
No Air Flow
35
150 LFM
30
Equation 5 simplifies into Equation 6:
T
+ T ) P max R
250 LFM
25
J
A D qJA
(6)
(7)
Rearranging Equation 6 gives Equation 7:
T * T
+
J
A
20
15
R
qJA
P max
D
Using Equation 6 and the computer model generated
curves shown in Figure 27 and Figure 30, a designer
can quickly compute the required heatsink thermal
0.1
1
10
100
2
PCB Copper Area (cm )
resistance/board area for
a
given ambient
temperature, power dissipation, and operating
environment.
Figure 27. DDPAK Thermal Resistance
vs PCB Copper Area
DDPAK POWER DISSIPATION
The DDPAK package provides an effective means of
managing power dissipation in surface mount
applications. The DDPAK package dimensions are
provided in the mechanical drawing section at the
end of the data sheet. The addition of a copper plane
directly underneath the DDPAK package enhances
the thermal performance of the package.
2 oz. Copper Solder Pad
with 25 Thermal Vias
1 oz. Copper
Power Plane
To illustrate, the TPS78625 in a DDPAK package
was chosen. For this example, the average input
voltage is 5 V, the output voltage is 2.5 V, the
Thermal Vias,
0.3 mm Diameter,
1.5 mm Pitch
average output current is
1
A, the ambient
1 oz. Copper
Ground Plane
temperature 55°C, the air flow is 150 LFM, and the
operating environment is the same as documented
below. Neglecting the quiescent current, the
maximum average power is shown in Equation 8:
Figure 28. DDPAK Thermal Resistance
Computer Model
(
)
P max + 5 * 2.5 V 1 A + 2.5 W
D
(8)
Substituting TJmax for TJ into Equation 6 gives
Equation 9:
R
max + (125 * 55)°Cń2.5 W + 28°CńW
qJA
(9)
11
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SLVS389G–SEPTEMBER 2002–REVISED JULY 2006
From the data in Figure 29 and rearranging
Equation 6, the maximum power dissipation for a
different ground plane area and a specific ambient
temperature can be computed.
180
160
No Air Flow
140
120
100
80
5
T
A
= 55°C
250 LFM
4
3
60
150 LFM
40
20
No Air Flow
0
0.1
1
10
2
1
2
PCB Copper Area (in )
Figure 30. SOT223 Thermal Resistance
vs PCB Copper Area
0.1
1
10
2
100
PCB Copper Area (cm )
From the data in Figure 30 and rearranging
Equation 6, the maximum power dissipation for a
different ground plane area and a specific ambient
temperature can be computed, as shown in
Figure 31.
Figure 29. DDPAK Maximum Power Dissipation
vs PCB Copper Area
SOT223 POWER DISSIPATION
The SOT223 package provides an effective means
of managing power dissipation in surface-mount
applications. The SOT223 package dimensions are
provided in the mechanical drawing section at the
end of the data sheet. The addition of a copper plane
directly underneath the SOT223 package enhances
the thermal performance of the package.
6
T
A
= 25°C
5
4
3
2
1
0
2
4 in PCB Area
To illustrate, the TPS78625 in a SOT223 package
was chosen. For this example, the average input
voltage is 3.3 V, the output voltage is 2.5 V, the
2
0.5 in PCB Area
average output current is
1
A, the ambient
temperature 55°C, no air flow is present, and the
operating environment is the same as documented
below. Neglecting the quiescent current, the
maximum average power is calculated as shown in
Equation 10:
0
25
50
75
100
125
150
T
A
− Ambient Temperature (°C)
(
)
P max + 3.3 * 2.5 V 1 A + 800 mW
D
(10)
Substituting TJmax for TJ into Equation 6 gives
Equation 11:
Figure 31. SOT223 Maximum Power Dissipation
vs Ambient Temperature
R
max + (125 * 55)°Cń800 mW + 87.5°CńW
qJA
(11)
From Figure 30, RθJA vs PCB Copper Area, the
ground plane needs to be 0.55 in2 for the part to
dissipate 800 mW. The operating environment used
to construct Figure 30 consisted of a board with 1 oz.
copper planes. The package is soldered to a 1 oz.
copper pad on the top of the board. The pad is tied
through thermal vias to the 1 oz. ground plane.
12
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PACKAGE OPTION ADDENDUM
www.ti.com
28-Apr-2008
PACKAGING INFORMATION
Orderable Device
TPS78601DCQ
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOT-223
DCQ
6
6
6
6
5
5
5
5
5
6
6
6
6
5
5
5
5
5
5
6
6
6
6
5
5
78 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS78601DCQG4
TPS78601DCQR
TPS78601DCQRG4
TPS78601KTT
SOT-223
SOT-223
SOT-223
DCQ
DCQ
DCQ
KTT
KTT
KTT
KTT
KTT
DCQ
DCQ
DCQ
DCQ
KTT
KTT
KTT
KTT
KTT
KTT
DCQ
DCQ
DCQ
DCQ
KTT
KTT
78 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
OBSOLETE DDPAK/
TO-263
TBD
Call TI
CU SN
CU SN
CU SN
CU SN
Call TI
TPS78601KTTR
TPS78601KTTRG3
TPS78601KTTT
TPS78601KTTTG3
TPS78618DCQ
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DDPAK/
TO-263
500 Green (RoHS &
no Sb/Br)
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
DDPAK/
TO-263
500 Green (RoHS &
no Sb/Br)
DDPAK/
TO-263
50 Green (RoHS &
no Sb/Br)
DDPAK/
TO-263
50 Green (RoHS &
no Sb/Br)
SOT-223
SOT-223
SOT-223
SOT-223
78 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS78618DCQG4
TPS78618DCQR
TPS78618DCQRG4
TPS78618KTT
78 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
OBSOLETE DDPAK/
TO-263
TBD
Call TI
CU SN
CU SN
CU SN
CU SN
CU SN
Call TI
TPS78618KTTR
TPS78618KTTRE3
TPS78618KTTRG3
TPS78618KTTT
TPS78618KTTTG3
TPS78625DCQ
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DDPAK/
TO-263
500 Green (RoHS &
no Sb/Br)
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
DDPAK/
TO-263
500 Green (RoHS &
no Sb/Br)
DDPAK/
TO-263
500 Green (RoHS &
no Sb/Br)
DDPAK/
TO-263
50 Green (RoHS &
no Sb/Br)
DDPAK/
TO-263
50 Green (RoHS &
no Sb/Br)
SOT-223
SOT-223
SOT-223
SOT-223
78 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS78625DCQG4
TPS78625DCQR
TPS78625DCQRG4
TPS78625KTT
78 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
OBSOLETE DDPAK/
TO-263
TBD
Call TI
Call TI
TPS78625KTTR
ACTIVE
DDPAK/
TO-263
500 Green (RoHS &
no Sb/Br)
CU SN
Level-2-260C-1 YEAR
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Apr-2008
Orderable Device
TPS78625KTTRG3
TPS78625KTTT
TPS78625KTTTG3
TPS78628DCQ
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
DDPAK/
TO-263
KTT
5
5
5
6
6
6
6
5
5
5
5
5
6
6
6
6
5
5
5
5
5
6
6
6
6
5
500 Green (RoHS &
no Sb/Br)
CU SN
CU SN
CU SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
DDPAK/
TO-263
KTT
KTT
DCQ
DCQ
DCQ
DCQ
KTT
KTT
KTT
KTT
KTT
DCQ
DCQ
DCQ
DCQ
KTT
KTT
KTT
KTT
KTT
DCQ
DCQ
DCQ
DCQ
KTT
50 Green (RoHS &
no Sb/Br)
DDPAK/
TO-263
50 Green (RoHS &
no Sb/Br)
SOT-223
SOT-223
SOT-223
SOT-223
78 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS78628DCQG4
TPS78628DCQR
TPS78628DCQRG4
TPS78628KTT
78 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
OBSOLETE DDPAK/
TO-263
TBD
Call TI
CU SN
CU SN
CU SN
CU SN
Call TI
TPS78628KTTR
TPS78628KTTRG3
TPS78628KTTT
TPS78628KTTTG3
TPS78630DCQ
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DDPAK/
TO-263
500 Green (RoHS &
no Sb/Br)
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
DDPAK/
TO-263
500 Green (RoHS &
no Sb/Br)
DDPAK/
TO-263
50 Green (RoHS &
no Sb/Br)
DDPAK/
TO-263
50 Green (RoHS &
no Sb/Br)
SOT-223
SOT-223
SOT-223
SOT-223
78 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS78630DCQG4
TPS78630DCQR
TPS78630DCQRG4
TPS78630KTT
78 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
OBSOLETE DDPAK/
TO-263
TBD
Call TI
CU SN
CU SN
CU SN
CU SN
Call TI
TPS78630KTTR
TPS78630KTTRG3
TPS78630KTTT
TPS78630KTTTG3
TPS78633DCQ
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DDPAK/
TO-263
500 Green (RoHS &
no Sb/Br)
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
DDPAK/
TO-263
500 Green (RoHS &
no Sb/Br)
DDPAK/
TO-263
50 Green (RoHS &
no Sb/Br)
DDPAK/
TO-263
50 Green (RoHS &
no Sb/Br)
SOT-223
SOT-223
SOT-223
SOT-223
78 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS78633DCQG4
TPS78633DCQR
TPS78633DCQRG4
TPS78633KTT
78 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
OBSOLETE DDPAK/
TO-263
TBD
Call TI
Call TI
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
28-Apr-2008
Orderable Device
TPS78633KTTR
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
DDPAK/
TO-263
KTT
5
5
5
5
5
500 Green (RoHS &
no Sb/Br)
CU SN
CU SN
CU SN
CU SN
CU SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
TPS78633KTTRE3
TPS78633KTTRG3
TPS78633KTTT
DDPAK/
TO-263
KTT
KTT
KTT
KTT
500 Green (RoHS &
no Sb/Br)
DDPAK/
TO-263
500 Green (RoHS &
no Sb/Br)
DDPAK/
TO-263
50 Green (RoHS &
no Sb/Br)
TPS78633KTTTG3
DDPAK/
TO-263
50 Green (RoHS &
no Sb/Br)
TPS78650DCQR
TPS78650DCQT
PREVIEW
PREVIEW
SOT-223
SOT-223
DCQ
DCQ
6
6
2500
TBD
TBD
Call TI
Call TI
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
TPS78601DCQR
TPS78618DCQR
TPS78625DCQR
TPS78628DCQR
TPS78630DCQR
TPS78633DCQR
SOT-223 DCQ
SOT-223 DCQ
SOT-223 DCQ
SOT-223 DCQ
SOT-223 DCQ
SOT-223 DCQ
6
6
6
6
6
6
2500
2500
2500
2500
2500
2500
330.0
330.0
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
12.4
12.4
6.8
6.8
6.8
6.8
6.8
6.8
7.3
7.3
7.3
7.3
7.3
7.3
1.88
1.88
1.88
1.88
1.88
1.88
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
Q3
Q3
Q3
Q3
Q3
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS78601DCQR
TPS78618DCQR
TPS78625DCQR
TPS78628DCQR
TPS78630DCQR
TPS78633DCQR
SOT-223
SOT-223
SOT-223
SOT-223
SOT-223
SOT-223
DCQ
DCQ
DCQ
DCQ
DCQ
DCQ
6
6
6
6
6
6
2500
2500
2500
2500
2500
2500
358.0
358.0
358.0
358.0
358.0
358.0
335.0
335.0
335.0
335.0
335.0
335.0
35.0
35.0
35.0
35.0
35.0
35.0
Pack Materials-Page 2
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www.ti.com/clocks
interface.ti.com
logic.ti.com
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Security
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