TPS7A1018PDSET [TI]

具有使能功能的 300mA、低输入电压 (0.75V)、超低 IQ、低压降稳压器 | DSE | 6 | -40 to 125;


型号：	TPS7A1018PDSET
厂家：	TEXAS INSTRUMENTS
描述：	具有使能功能的 300mA、低输入电压 (0.75V)、超低 IQ、低压降稳压器 \| DSE \| 6 \| -40 to 125 稳压器
文件：	总40页 (文件大小：2644K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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TPS7A10

ZHCSHU2B –MARCH 2018–REVISED OCTOBER 2018

TPS7A10 300mA 低输入电压、低输出电压、超低压降稳压器

1 特性

3 说明

•

超低输入电压范围：0.75V 至 3.3V

可实现最低功率损耗的超低压降：

TPS7A10 是一款超小型低静态电流低压降稳压器

(LDO)，它能够实现 300mA 的拉电流并具有出色的交

流性能（负载和线路瞬态响应）。该器件具有 0.75V

至 3.3V 的输入范围以及 0.5V 至 3.0V 的输出范围，并

在负载、线路和温度上具有 1.5% 的极高精度。此性能

非常适合于为更低的现代 MCU 内核电压和模拟传感器

供电。

–

在 300mA 下为 70mV（最大值）(V_OUT

1.0V)，YKA 封装

•

低静态电流：

–

V_INI_Q= 1.6µA（典型值）

V_BIASI_Q= 6µA（典型值）

•

负载、线路和温度上的精度为 1.5%

高 PSRR：频率 1kHz 时为 60dB

可提供固定输出电压：

主要电源路径通过 V_IN，可连接至高于输出电压的值低

至 70mV 的电源。该器件使用一个用于为 LDO 的内部

电路供电的附加 V_BIAS电源轨，支持极低的输入电压。

V_IN和 V_BIAS分别消耗 1.6µA 和 6µA 的极低静态电

流。低 I_Q和超低压降特性有助于提高功耗敏感型应

用中解决方案的效率。例如，V_IN可以是高效直流/直

流降压稳压器的输出，而 V_BIAS引脚可以连接至一个可

再充电电池。

–

0.5V 至 3.0V（阶跃为 50mV）

_BIAS范围：1.7V 至 5.5V

•

封装：

–

0.74mm × 1.09mm WCSP-5

1.50mm × 1.50mm WSON-6

•

内置软启动功能，具有单调 V_OUT上升

TPS7A10 配备了一个有源下拉电路，用于在处于禁用

状态时对输出进行快速放电，并提供已知的启动状态。

有源输出放电

2 应用

TPS7A10 可采用超小型 5 引脚 DSBGA (YKA) 封装，

从而使其非常适合空间受限的应用。该器件还可采用

6 引脚 WSON (DSE) 封装。

•

智能手表、健身追踪器

无线耳机和耳塞

摄像头模块

器件信息⁽¹⁾

智能手机和平板电脑

便携式医疗设备

器件型号

封装

WSON (6)

封装尺寸（标称值）

1.50mm × 1.50mm

0.74mm ×

1.09mm（0.35mm

间距）

TPS7A10

DSBGA (5)

(1) 如需了解所有可用封装，请参阅产品说明书末尾的封装选项附

录。

压降与 I_OUT和温度间的关系（YKA 封装）

典型应用电路

V_BATTERY

T_J

C_BIAS

-40 °C

0 °C

25 °C

85 °C

105 °C

125 °C

BIAS

V_OUT

OUT

Standalone

OUT

C_IN

C_OUT

TPS7A10

DC/DC Converter

or PMU

GND

V_EN

90 120 150 180 210 240 270 300

Output Current (mA)

D013

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SBVS314

TPS7A10

ZHCSHU2B –MARCH 2018–REVISED OCTOBER 2018

www.ti.com.cn

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics........................................... 5

6.6 Typical Characteristics.............................................. 7

Detailed Description ............................................ 14

7.1 Overview ................................................................. 14

7.2 Functional Block Diagram ....................................... 14

7.3 Feature Description................................................. 15

7.4 Device Functional Modes........................................ 17

Application and Implementation ........................ 18

8.1 Application Information............................................ 18

8.2 Typical Application .................................................. 22

Power Supply Recommendations...................... 24

10 Layout................................................................... 24

10.1 Layout Guidelines ................................................. 24

10.2 Layout Examples................................................... 24

11 器件和文档支持 ..................................................... 25

11.1 器件支持 ............................................................... 25

11.2 文档支持................................................................ 25

11.3 接收文档更新通知 ................................................. 25

11.4 社区资源................................................................ 25

11.5 商标....................................................................... 25

11.6 静电放电警告......................................................... 25

11.7 术语表 ................................................................... 26

12 机械、封装和可订购信息....................................... 26

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision A (June 2018) to Revision B

Page

•

已添加 YKA 封装添加至以下章节的可实现最低功率损耗的超低压降项目的子项目： ......................................................... 1

已添加在部分中添加了最后一个句子说明部分的关断相关文字 ........................................................................................... 1

已更改将 WSON (DSE) 封装从“预告信息”更改为“生产数据（正在供货）” ........................................................................... 1

已添加 YKA 封装添加至压降与 I_OUT和温度间的关系（YKA 封装）一图的标题中 ............................................................... 1

已添加 YKA Package to captions of Output Accuracy Over Temperature, YKA Package and Output Accuracy Over

Temperature, YKA Package figures....................................................................................................................................... 7

•

已添加 Output Accuracy Over Temperature, DSE Package and Output Accuracy Over Temperature, DSE Package

figures..................................................................................................................................................................................... 7

•

已添加 YKA Package to caption of Dropout vs I_IOUTand Temperature, YKA Package figure ............................................... 7

已添加 Dropout vs I_IOUTand Temperature, DSE Package figure .......................................................................................... 8

Changes from Original (March 2018) to Revision A

Page

•

已更改从“预告信息”更改为“生产数据（正在供货）” .............................................................................................................. 1

TPS7A10

www.ti.com.cn

ZHCSHU2B –MARCH 2018–REVISED OCTOBER 2018

5 Pin Configuration and Functions

DSE Package

6-Pin WSON

Top View

YKA Package

5-Pin DSBGA

Top View

OUT

GND

BIAS

OUT

GND

BIAS

Not to scale

Pin Functions

I/O

DESCRIPTION

NAME

DSE

YKA

Input pin. For best transient response and to minimize input impedance, use the

recommended or larger value ceramic capacitor from IN to ground. as listed in the

Recommended Operation Conditions. Place the input capacitor as close as possible to input

of the device.

Regulated output pin. A capacitor is required from OUT to ground for stability. For best

transient response, use larger than the minimum recommended value ceramic capacitor.

Follow the recommended capacitor value as listed in the Recommended Operation

Conditions. Place the output capacitor as close as possible to output of the device.

OUT

GND

BIAS

—

Ground pin. This pin must be connected to ground.

BIAS pin. This pin enables the use of low-input voltage, low-output voltage conditions, (LILO).

For best response, use the recommended or larger value ceramic capacitor from BIAS to

ground as listed in the Recommended Operation Conditions. Place the bias capacitor as

close as possible to input of the device.

Enable pin. Driving this pin to logic high enables the device. Driving this pin to logic low

disables the device. If enable functionality is not required, this pin must be connected to IN or

BIAS; however, connecting EN to IN is only acceptable if the V_INvoltage is greater than 0.9 V.

TPS7A10

ZHCSHU2B –MARCH 2018–REVISED OCTOBER 2018

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range unless otherwise noted.⁽¹⁾

MIN

–0.3

MAX UNIT

Supply, V_IN

3.6

Enable, V_EN

Voltage

6.0

Bias, V_BIAS

6.0

V_IN+ 0.3⁽²⁾

Output, V_OUT

Current

Maximum output current

Internally limited

Operating junction temperature, T_J

Storage temperature, T_stg

–40

–65

150

°C

Temperature

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The absolute maximum rating is 3.6 or (V_IN+ 0.3) , whichever is less.

6.2 ESD Ratings

VALUE

±1000

±500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)

Electrostatic discharge

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating junction temperature range (unless otherwise noted).

MIN

0.75

1.7

0.5

NOM

MAX

3.3

UNIT

V_IN

Input voltage

V_BIAS

V_OUT

I_OUT

C_IN

Bias voltage

5.5

Output voltage

3.0

Peak output current

Input capacitor

300

µF

℃

2.2

C_BIAS

C_OUT

T_J

Bias capacitor

0.1

(1)

Output capacitor

Operating junction temperature

2.2

–40

125

(1) Maximum ESR must be lower than 250 mΩ

6.4 Thermal Information

TPS7A10

YKA (WSCP)

THERMAL METRIC⁽¹⁾

DSE (WSON)

6 PINS

188.8

82.9

UNIT

5 PINS

169.4

1.1

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

101.0

6.6

55.4

1.7

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

ψ_JB

100.4

N/A

55.6

N/A

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics .

TPS7A10

www.ti.com.cn

ZHCSHU2B –MARCH 2018–REVISED OCTOBER 2018

6.5 Electrical Characteristics

over T_J= –40°C to +125°C, V_IN= V_OUT(NOM)+ 0.5 V, V_BIAS= V_OUT(NOM)+ 1.4 V, I_OUT= 1 mA, V_EN= 1.0 V, C_IN= 2.2 μF, C_OUT

2.2 μF, and C_BIAS= 0.1 μF ( unless otherwise noted); all typical values are at T_J= 25°C .

PARAMETER

Nominal Accuracy

TEST CONDITIONS

MIN

TYP

MAX UNIT

T_J= 25°C

–0.5

0.5

–20°C ≤ T_J≤ 85, DSE package

V_OUT(NOM)+ 0.5 V ≤ V_IN≤ 3.3 V,

V_OUT(NOM)+ 1.4 V ≤ V_BIAS≤ 5.5 V,

1 mA ≤ I_OUT≤ 300 mA

–1.25

1.25

–40°C ≤ T_J≤ 85, YKA package

V_OUT(NOM)+ 0.5 V ≤ V_IN≤ 3.3 V,

V_OUT(NOM)+ 1.4 V ≤ V_BIAS≤ 5.5 V,

1 mA ≤ I_OUT≤ 300 mA

Accuracy over

temperature

1.25

1.5

–40°C ≤ T_J≤ 125, DSE and YKA

package

V_OUT(NOM)+ 0.5 V ≤ V_IN≤ 3.3 V,

V_OUT(NOM)+ 1.4 V ≤ V_BIAS≤ 5.5 V,

1 mA ≤ I_OUT≤ 300 mA

–1.5

ΔV_OUT/ ΔV_IN

ΔV_OUT/ ΔV_BIAS

ΔV_OUT/ ΔI_OUT

V_INline regulation

V_BIASline regulation

Load regulation

V_OUT(NOM)+ 0.5 V ≤ V_IN≤ 3.3 V

V_OUT(NOM)+ 1.4 V ≤ V_BIAS≤ 5.5 V

0.1 mA ≤ I_OUT≤ 300 mA

T_J= 25°C, I_OUT= 0 mA

–40°C < T_J< 85°C, I_OUT= 0 mA

I_OUT= 0 mA

0.001

0.03

0.2

%/V

%/A

2.1

2.3

2.6

I_Q(BIAS)

Bias pin current

µA

I_OUT= 300 mA

T_J= 25°C, I_OUT= 0 mA

–40°C < T_J< 85°C, I_OUT= 0 mA

I_OUT= 0 mA

1.6

I_Q(IN)

Input pin current⁽¹⁾

I_OUT= 300 mA

–40°C < T_J< 85°C,

V_IN= 3.3 V, V_BIAS= 5.5 V, V_EN≤ 0.4 V

400

1200

I_SHDN(BIAS)

V_BIASshutdown current

V_INshutdown current

µA

–40°C < T_J< 125°C,

V_IN= 3.3 V, V_BIAS= 5.5 V, V_EN≤ 0.4 V

–40°C < T_J< 85°C,

V_IN= 3.3 V, V_BIAS= 5.5 V, V_EN≤ 0.4 V

I_SHDN(IN)

–40°C < T_J< 125°C,

V_IN= 3.3 V, V_BIAS= 5.5 V, V_EN≤ 0.4 V

V_OUT= 0.9 × V_OUT(NOM), YKA package

V_OUT= 0.9 × V_OUT(NOM), DSE package

V_OUT= 0 V

325

350

450

150

600

625

I_CL

I_SC

Output current limit

Short circuit current limit

V_IN= V_OUT(NOM)– 0.1 V, I_OUT= 300 mA,

YKA package

V_DO(IN)

V_INdropout voltage⁽²⁾

V_BIASdropout voltage⁽²⁾

V_IN= V_OUT(NOM)– 0.1 V, I_OUT= 300 mA,

DSE package

I_OUT= 300 mA

I_OUT= 150 mA

0.85

0.75

1.05

0.95

V_DO(BIAS)

(1) This current flowing from V_INto GND.

(2) Dropout is not measured for V_OUT< 1.0 V

TPS7A10

ZHCSHU2B –MARCH 2018–REVISED OCTOBER 2018

www.ti.com.cn

Electrical Characteristics (continued)

over T_J= –40°C to +125°C, V_IN= V_OUT(NOM)+ 0.5 V, V_BIAS= V_OUT(NOM)+ 1.4 V, I_OUT= 1 mA, V_EN= 1.0 V, C_IN= 2.2 μF, C_OUT

2.2 μF, and C_BIAS= 0.1 μF ( unless otherwise noted); all typical values are at T_J= 25°C .

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

f = 1 kHz,

V_OUT= 1.1 V, I_OUT= 50 mA

f = 100 kHz,

V_OUT= 1.1 V, I_OUT= 50 mA

V_INpower-supply rejection

ratio

V_INPSRR

f = 1 MHz,

V_OUT= 1.1 V, I_OUT= 50 mA

f = 1.5 MHz,

V_OUT= 1.1 V, I_OUT= 50 mA

f = 1 kHz,

V_OUT= 1.1 V, I_OUT= 300 mA

f = 100 kHz,

V_OUT= 1.1 V, I_OUT= 300 mA

V_BIASpower-supply

rejection ratio

V_BIASPSRR

f = 1 MHz,

V_OUT= 1.1 V, I_OUT= 300 mA

Bandwidth = 10 Hz to 100 kHz,

V_OUT= 1.0 V, I_OUT= 50 mA

V_n

Output voltage noise

93.9

µV_RMS

V_BIASrising

V_BIASfalling

V_BIAShysteresis

V_INrising

1.46

1.35

1.54

1.44

1.63

1.55

V_UVLO(BIAS)

V_{UVLO_HYST(BIAS)}

V_UVLO(IN)

Bias supply UVLO

Bias supply hysteresis

Input supply UVLO

µs

645

565

675

600

710

640

V_INfalling

V_{UVLO_HYST(IN)}

t_STR

Input supply hysteresis

Start-up time⁽³⁾

V_INhysteresis

525

1200

0.4

V_HI(EN)

EN pin logic high voltage

EN pin logic low voltage

EN pin current

0.9

V_LO(EN)

I_EN

EN = 5.5 V

120

160

145

R_PULLDOWN

Pulldown resistor

V_BIAS= 3.3 V, P version only

Shutdown, temperature rising

Reset, temperature falling

Thermal shutdown

temperature

T_SD

°C

(3) Startup time = time from EN assertion to 0.95 × V_OUT(NOM).

TPS7A10

www.ti.com.cn

ZHCSHU2B –MARCH 2018–REVISED OCTOBER 2018

6.6 Typical Characteristics

at T_J= –40 °C to +125 °C, V_IN= V_OUT(NOM)+ 0.5 V, V_BIAS= V_OUT(NOM)+ 1.4 V, I_OUT= 1 mA, V_EN= V_IN, C_IN= 2.2 µF, C_OUT

2.2 µF, and C_BIAS= 0.1 µF (unless otherwise noted); typical values are at T_J= 25°C

0.25

0.2

0.25

0.2

T_J

-40 °C

0 °C

25 °C

85 °C

105 °C

125 °C

-40 °C

0 °C

25 °C

85 °C

105 °C

125 °C

0.15

0.1

0.15

0.1

0.05

-0.05

-0.1

-0.15

-0.2

-0.25

-0.05

-0.1

-0.15

-0.2

-0.25

1.4 1.6 1.8

2.2 2.4 2.6 2.8

Input Voltage (V)

3.2 3.4

90 120 150 180 210 240 270 300

Output Current (mA)

V_OUT= 1.0 V

图 1. Output Accuracy Over Temperature, YKA Package

0.5

图 2. Output Accuracy Over Temperature, YKA Package

0.5

0.4

0.3

0.2

0.1

0.4

0.3

0.2

0.1

-0.1

-0.2

-0.3

-0.4

-0.5

-0.1

-0.2

-0.3

-0.4

-0.5

T_J

25 èC

85 èC

T_J

25 èC

85 èC

-40 èC

0 èC

105 èC

125 èC

-40 èC

0 èC

105 èC

125 èC

1.4 1.6 1.8

2.2 2.4 2.6 2.8

Input Voltage (V)

3.2 3.4

90 120 150 180 210 240 270 300

Output Current (mA)

V_OUT= 1.0 V

图 3. Output Accuracy Over Temperature, DSE Package

0.25

图 4. Output Accuracy Over Temperature, DSE Package

T_J

0.2

0.15

0.1

-40 °C

0 °C

25 °C

85 °C

105 °C

125 °C

-40 °C

0 °C

25 °C

85 °C

105 °C

125 °C

0.05

-0.05

-0.1

-0.15

-0.2

-0.25

2.5

3.5

4.5

5.5

90 120 150 180 210 240 270 300

Output Current (mA)

Bias Voltage (V)

D013

V_OUT= 1.0 V

图 5. Output Accuracy Over Temperature and V_BIAS

图 6. Dropout vs I_IOUTand Temperature, YKA Package

TPS7A10

ZHCSHU2B –MARCH 2018–REVISED OCTOBER 2018

www.ti.com.cn

Typical Characteristics (接下页)

at T_J= –40 °C to +125 °C, V_IN= V_OUT(NOM)+ 0.5 V, V_BIAS= V_OUT(NOM)+ 1.4 V, I_OUT= 1 mA, V_EN= V_IN, C_IN= 2.2 µF, C_OUT

2.2 µF, and C_BIAS= 0.1 µF (unless otherwise noted); typical values are at T_J= 25°C

100

1100

1000

900

800

700

600

500

400

T_J

-40 èC

85 èC

105 èC

125 èC

0 èC

25 èC

T_J

-40 °C

0 °C

25 °C

85 °C

105 °C

125 °C

90 120 150 180 210 240 270 300

Output Current (mA)

90 120 150 180 210 240 270 300

Output Current (mA)

D013

V_OUT= 1.0 V

图 8. Dropout vs V_BIASand Temperature

V_OUT= 1.0 V

图 7. Dropout vs I_IOUTand Temperature, DSE Package

200

100

700

200

700

600

500

400

300

200

100

V_OUT

I_OUT

V_OUT

I_OUT

600

500

400

300

200

100

-100

-200

-300

-400

-500

-600

-100

-200

-300

-400

-500

-600

-100

100 200 300 400 500 600 700 800 900 1000

200 400 600 800 1000 1200 1400 1600 1800 2000

Time (µs)

D028

V_OUT= 1.1 V, I_OUT= 0 mA to 150 mA

V_OUT= 1.1 V, I_OUT= 1 mA to 150 mA

图 9. I_OUTTransient

图 10. I_OUTTransient

200

100

700

200

100

700

V_OUT

I_OUT

V_OUT

I_OUT

600

500

400

300

200

100

600

500

400

300

200

100

-100

-200

-300

-400

-500

-600

-100

-200

-300

-400

-500

-600

-100

100 200 300 400 500 600 700 800 900 1000

200 400 600 800 1000 1200 1400 1600 1800 2000

Time (µs)

D028

V_OUT= 1.1 V, I_OUT= 0 mA to 300 mA

V_OUT= 1.1 V, I_OUT= 1 mA to 300 mA

图 11. I_OUTTransient

图 12. I_OUTTransient

TPS7A10

www.ti.com.cn

ZHCSHU2B –MARCH 2018–REVISED OCTOBER 2018

Typical Characteristics (接下页)

at T_J= –40 °C to +125 °C, V_IN= V_OUT(NOM)+ 0.5 V, V_BIAS= V_OUT(NOM)+ 1.4 V, I_OUT= 1 mA, V_EN= V_IN, C_IN= 2.2 µF, C_OUT

2.2 µF, and C_BIAS= 0.1 µF (unless otherwise noted); typical values are at T_J= 25°C

5.5

100

5.5

100

4.5

-50

4.5

-50

-100

-150

-200

-250

-300

-350

-400

-100

-150

-200

-250

-300

-350

-400

V_IN

V_OUT

V_IN

V_OUT

3.5

2.5

1.5

100 200 300 400 500 600 700 800 900 1000

Time (µs)

100 200 300 400 500 600 700 800 900 1000

Time (µs)

V_OUT= 1.1 V, I_OUT= 300 mA

V_OUT= 1.1 V, I_OUT= 1 mA

图 13. V_INTransient

图 14. V_INTransient

1.2

T_J

0.8

0.6

0.4

0.2

-40 °C

0 °C

25 °C

85 °C

105 °C

125 °C

T_J

-40 °C

0 °C

25 °C

85 °C

105 °C

125 °C

100

150

200

250

300

350

400

450

500

1.5

2.5

3.5

4.5

5.5

Output Current (mA)

Bias Voltage (V)

D012

D007

I_OUT= 0 mA

图 15. Foldback Current Limit Over Temperature

图 16. I_Q(V_BIAS) Over Temperature

2.2

1.8

1.6

1.4

1.2

T_J

-40 °C

0 °C

-40 °C

0 °C

25 °C

85 °C

105 °C

125 °C

85 °C

105 °C

125 °C

25 °C

1.5

2.5

3.5

4.5

5.5

1.25 1.5 1.75

2.25 2.5 2.75

3.25 3.5

Bias Voltage (V)

Input Voltage (V)

D007

D008

I_OUT= 300 mA

图 17. I_Q(V_BIAS) Over Temperature

I_OUT= 0 mA

图 18. I_Q(V_IN) Over Temperature

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Typical Characteristics (接下页)

at T_J= –40 °C to +125 °C, V_IN= V_OUT(NOM)+ 0.5 V, V_BIAS= V_OUT(NOM)+ 1.4 V, I_OUT= 1 mA, V_EN= V_IN, C_IN= 2.2 µF, C_OUT

2.2 µF, and C_BIAS= 0.1 µF (unless otherwise noted); typical values are at T_J= 25°C

3.5

T_J

-40 °C

0 °C

25 °C

85 °C

105 °C

125 °C

2.5

1.5

0.5

T_J

25 °C

85 °C

-40 °C

0 °C

105 °C

-0.5

1.25 1.5 1.75

2.25 2.5 2.75

3.25 3.5

0.6

0.9

1.2

1.5

1.8

2.1

2.4

2.7

3.3

Input Voltage (V)

D009

D011

I_OUT= 300 mA

V_OUT= 1.0 V, V_EN< 0.4 V

图 19. I_Q(V_IN) Over Temperature

图 20. I_SHDN(V_IN) Over Temperature

2.5

2.75

2.5

2.25

1.75

1.5

1.25

0.75

0.5

0.25

V_IN

V_OUT

V_BIAS

V_EN

V_IN

V_OUT

V_BIAS

V_EN

-0.5

-0.25

100 200 300 400 500 600 700 800 900 1000

Time (µs)

100 200 300 400 500 600 700 800 900 1000

Time (µs)

V_OUT= 1.1 V

图 21. Startup With V_EN= V_IN

图 22. Startup With Separated V_EN

1.5

V_IN

V_OUT

V_EN

V_BIAS

V_IN

V_OUT

V_EN

V_BIAS

0.5

-0.5

100 200 300 400 500 600 700 800 900 1000

Time (µs)

100 200 300 400 500 600 700 800 900 1000

Time (µs)

V_OUT= 0.5 V

图 23. Startup With V_ENand V_BIASPowering Up

图 24. Startup With V_BIASPowering Up After V_INand V_EN

Simultaneously

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Typical Characteristics (接下页)

at T_J= –40 °C to +125 °C, V_IN= V_OUT(NOM)+ 0.5 V, V_BIAS= V_OUT(NOM)+ 1.4 V, I_OUT= 1 mA, V_EN= V_IN, C_IN= 2.2 µF, C_OUT

2.2 µF, and C_BIAS= 0.1 µF (unless otherwise noted); typical values are at T_J= 25°C

I _OUT

1 mA

10 mA

50 mA

I _OUT

1 mA

10 mA

50 mA

100 mA

200 mA

300 mA

100 mA

200 mA

300 mA

100

10k

100k

10M

100

10k

100k

10M

Frequency (Hz)

C_IN= 0 µF, V_OUT= 1.1 V, V_BIAS= 2.5 V, C_BIAS= 0.1 µF

C_IN= 0 µF, V_OUT= 0.5 V, V_BIAS= 1.9 V, C_BIAS= 0.1 µF

图 25. PSRR vs Frequency and I_OUT

图 26. PSRR vs Frequency and I_OUT

2.2 mF Cout

22 mF Cout

2.2mF Cout

22mF Cout

100

10k

100k

10M

100

10k

100k

10M

Frequency (Hz)

C_IN= 0 µF, V_OUT= 1.1 V, V_BIAS= 2.5 V, C_BIAS= 0.1 µF

C_IN= 0 µF, V_OUT= 0.5 V, V_BIAS= 1.9 V, C_BIAS= 0.1 µF

图 27. PSRR vs Frequency and C_OUT

图 28. PSRR vs Frequency and C_OUT

V_DO

200mV

400mV

600mV

800mV

1.0V

V_IN-V_OUT

200mV

400mV

600mV

800mV

1.0V

100

10k

100k

10M

100

10k

100k

10M

Frequency (Hz)

C_IN= 0 µF, V_OUT= 1.1 V, I_OUT= 300 mA, V_BIAS= 2.5 V,

C_BIAS= 0.1 µF

C_IN= 0 µF, V_OUT= 0.5 V, I_OUT= 300 mA, V_BIAS= 1.9 V,

C_BIAS= 0.1 µF

图 29. PSRR vs Frequency and V_DO

图 30. PSRR vs Frequency and V_DO

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Typical Characteristics (接下页)

at T_J= –40 °C to +125 °C, V_IN= V_OUT(NOM)+ 0.5 V, V_BIAS= V_OUT(NOM)+ 1.4 V, I_OUT= 1 mA, V_EN= V_IN, C_IN= 2.2 µF, C_OUT

2.2 µF, and C_BIAS= 0.1 µF (unless otherwise noted); typical values are at T_J= 25°C

V_OUT= 0.5 V, 42.3 µV_RMS

V_OUT= 1.0 V, 87.6 µV_RMS

V_OUT= 3.0 V, 201.1 µV_RMS

0.1

V_BIAS

2.5V

3.0V

3.5V

4.0V

4.5V

5.0V

5.5V

0.01

0.005

100

10k

100k

10M

100

10k

100k

10M

Frequency (Hz)

D023

V_OUT= 1.1 V, I_OUT= 300 mA, C_BIAS= 0 µF

I_OUT= 300 mA

图 31. V_BIASPSRR vs Frequency and V_BIAS

图 32. Output Noise vs Frequency and V_OUT

I_OUT, (mV_RMS

50 mA, (93.9)

100 mA, (90.8)

150 mA, (89.6)

)

C_OUT, (mV_RMS

)

200 mA, (88.8)

250 mA, (87.8)

300 mA, (87.6)

2.2 µF, (87.6)

4.7 µF, (85.1)

10 µF, (89.4)

0.1

0.01

0.005

100

10k

100k

10M

100

10k

100k

10M

Frequency (Hz)

D025

V_OUT= 1.0 V, V_BIAS= 2.5 V

图 33. Output Noise vs Frequency and I_OUT

V_EN(LO)

V_OUT= 1.0 V, I_OUT= 300 mA

图 34. Output Noise vs Frequency and C_OUT

0.605

0.595

0.585

0.575

0.565

0.555

0.545

0.535

0.525

0.515

0.69

0.68

0.67

0.66

0.65

0.64

0.63

0.62

0.61

0.6

V_EN(HI)

V_{IN UVLO (Falling)}

V_{IN UVLO (Rising)}

0.59

0.58

-40

-20

100 120 140

-40

-20

100 120 140

Temperature (èC)

Temperature (°C)

D014

D015

图 35. Enable High and Low Thresholds vs Temperature

图 36. V_UVLO(IN)Rising and Falling Thresholds vs

Temperature

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Typical Characteristics (接下页)

at T_J= –40 °C to +125 °C, V_IN= V_OUT(NOM)+ 0.5 V, V_BIAS= V_OUT(NOM)+ 1.4 V, I_OUT= 1 mA, V_EN= V_IN, C_IN= 2.2 µF, C_OUT

2.2 µF, and C_BIAS= 0.1 µF (unless otherwise noted); typical values are at T_J= 25°C

1.65

1.6

1.55

1.5

1.45

1.4

1.35

V_{BIAS UVLO (Falling)}

V_{BIAS UVLO (Rising)}

1.3

-40

-20

80 100 120 140

Temperature (°C)

D016

图 37. V_UVLO(BIAS)Rising and Falling Thresholds vs Temperature

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7 Detailed Description

7.1 Overview

The TPS7A10 is a low input, ultra-low dropout, and low quiescent current linear regulator that is optimized for

excellent transient performance. These characteristics make the device ideal for most battery-powered

applications. The implementation of the BIAS pin on the TPS7A10 vastly improves efficiency of low-voltage

output applications by allowing the use of a preregulated, low-voltage input supply that offers sub-band-gap

output voltages. The high power-supply rejection ratio (PSRR), low noise, low ground pin current, and ultra-small

packaging make this device suitable for ultra-portable applications. This device also offers high output voltage

accuracy of 1.5% over the recommended junction temperature range.

7.2 Functional Block Diagram

Current

Limit

BIAS

OUT

Thermal

Shutdown

Global

UVLO

Active Discharge

P-Version Only

Bandgap

GND

Internal

Controller

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7.3 Feature Description

7.3.1 Excellent Transient Response

The TPS7A10 responds quickly to a transient on the input supply (line transient) or the output current (load

transient) that results from the device high input impedance and low output impedance across frequency. This

same capability also means that the device has a high power-supply rejection ratio (PSRR) and low internal

noise floor (e_n). The low-dropout regulator (LDO) approximates an ideal power supply in ac (small-signal) and dc

(large-signal) conditions.

The choice of external component values optimizes the small- and large-signal response; see the Input and

Output Capacitor Requirements section for proper selection.

7.3.2 Global Undervoltage Lockout (UVLO)

The TPS7A10 uses two undervoltage lockout (UVLO) circuits: one on the BIAS pin and one on the IN pin to

prevent the device from turning on before both V_BIASand V_INrise above their lockout voltages. The two UVLO

signals are connected internally through an AND gate, as shown in 图 38. This internal connection allows the

device to be turned off when either rail is below its lockout voltage.

UVLO(IN)

Global UVLO

UVLO(BIAS)

图 38. Global UVLO circuit

7.3.3 Active Discharge

The active discharge option (P version only) have internal pulldown MOSFET that connects a 120-Ω resistor to

ground when the device is disabled in order to actively discharge the output voltage. The active discharge circuit

is activated by driving the enable pin to logic low to disable the device, or when the device is in thermal

shutdown.

The discharge time after disabling the device depends on the output capacitance (C_OUT) and the load resistance

(R_L) in parallel with the 120-Ω pulldown resistor. 公式 1 calculates the discharge time constant:

120 · R_L

t =

· C_OUT

120 + R_L

(1)

Do not rely on the active discharge circuit for discharging a large amount of output capacitance after the input

supply collapses because reverse current can possibly flow from the output to the input. This reverse current flow

can cause damage to the device. Limit reverse current to no more than 5% of the device-rated current.

7.3.4 Enable

The enable pin for this device is active high. The output of the device is turned on when the enable pin voltage is

greater than the EN pin logic high voltage, and the output of the device is turned off when the enable pin voltage

is less than the EN pin voltage logic low .

The EN pin can be tied to the IN pin, the BIAS pin, or can be driven separately to enable and disable the device;

however, connecting the EN pin to the IN pin is only acceptable if the V_INvoltage is greater than 0.9 V.

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Feature Description (接下页)

7.3.5 Sequencing Requirement

The V_IN, V_BIAS, and V_ENvoltages can be sequenced in any order without causing damage to the device. The start

up is always monotonic regardless of the sequencing order or the ramp rates of IN, BIAS, and EN pins. For

optimum device performance, have V_BIASpresent before enabling the device in any sequence order between V_IN

and V_ENbecause the device internal circuitry is powered off the V_BIAS, refer to Recommended Operating

Conditions for proper voltage ranges of V_IN, V_BIAS, and V_EN

7.3.6 Internal Foldback Current Limit

The internal foldback current limit circuit is used to protect the LDO against high-load current faults or shorting

events. The foldback mechanism lowers the current limit as the output voltage decreases, and limits power

dissipation during short-circuit events while still allowing for the device to operate at the rated output current; see

图 15.

For example, when V_OUTis 90% of V_OUT(nom), the current limit is I_CL(typical); however, if V_OUTis forced to 0 V, the

current limit is I_SC(typical).

In many LDOs, the foldback current limit can prevent start up into a constant-current load or a negatively-biased

output. A brick-wall current limit is when there is an abrupt current stop after the current limit is reached. The

foldback mechanism for this device goes into a brick-wall current limit when V_OUT> 500 mV (typical), thus limiting

current to I_CL(typical). When V_OUTis approximately 0 V, current is limited to I_SC(typical) in order to provide

normal start up into a variety of loads.

Thermal shutdown can activate during a current-limit event because of the high power dissipation typically found

in these conditions. To provide proper operation of the current limit, minimize the inductances to the input and

load. Continuous operation in current limit is not recommended.

7.3.7 Thermal Shutdown

The device contains a thermal shutdown protection circuit to disable the device when the thermal junction

temperature (T_J) of the main pass-FET rises to the thermal shutdown temperature (T_SD) for shutdown listed in

the Electrical Characteristics. Thermal shutdown hysteresis makes sure that the LDO resets again (turns on)

when the temperature falls to the T_SDfor reset.

The thermal time constant of the semiconductor die is fairly short, and thus the device may cycle on and off

when thermal shutdown is reached until the power dissipation is reduced.

For reliable operation, limit the junction temperature to a maximum of 125°C. Operation above 125°C causes the

device to exceed the operational specifications. Although the internal protection circuitry of the device is

designed to protect against thermal overload conditions, this circuitry is not intended to replace proper heat

sinking. Continuously running the device into thermal shutdown or above a junction temperature of 125°C

reduces long-term reliability.

A fast start up when T_J> the T_SDfor reset causes the device thermal shutdown to assert at T_SDfor reset, and

prevents the device from turning on until the junction temperature is reduced below T_SDfor reset.

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7.4 Device Functional Modes

The device has the following modes of operation:

•

Normal operation: The device regulates to the nominal output voltage.

Dropout operation: The pass element operates as a resistor and the output voltage is set as V_IN– V_DO

Disabled: The output of the device is disabled and the discharge circuit is activated.

表 1 shows the conditions that lead to the different modes of operation.

表 1. Device Functional Mode Comparison

PARAMETER

OPERATING MODE

V_IN

V_BIAS

V_EN

I_OUT

T_J

Normal mode

Dropout mode

V_IN> V_OUT(nom)+ V_DOand V_IN> V_IN(min)V_BIAS> V_OUT+ 1.05 V

V_EN> V_HI(EN)

I_OUT< I_CL

T_J< T_SDfor shutdown

V_IN(min)< V_IN< V_OUT(nom)+ V_DO

V_IN< V_UVLO(IN)

V_BIAS< V_OUT+ 1.05 V

V_BIAS< V_BIAS(UVLO)

Disabled mode

(any true condition

disables the device)

V_EN< V_LO(EN)

—

T_J> T_SDfor shutdown

7.4.1 Normal Mode

The device regulates the output to the nominal output voltage when all normal mode conditions in 表 1 are met.

7.4.2 Dropout Mode

The device is not in regulation, and the output voltage tracks the input voltage minus the voltage drop across the

pass element of the device. In this mode, PSRR and the noise performance of the device are significantly

degraded.

7.4.3 Disable Mode

In this mode, the pass element is turned off, the internal circuits are shut down, and the output voltage is actively

discharged to ground by an internal resistor.

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8 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

Successfully implementing an LDO in an application depends on the application requirements. This section

discusses key device features and the best implementation to achieve a reliable design.

8.1.1 Recommended Capacitor Types

The device is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input,

output, and BIAS pins. Multilayer ceramic capacitors are the industry standard for these types of applications, but

must be used with good judgment. Ceramic capacitors that use X7R-, X5R-, and COG-rated dielectric materials

provide relatively good capacitive stability across temperature. Avoid Y5V-rated capacitors because of large

variations in capacitance.

Regardless of the ceramic capacitor type selected, ceramic capacitance varies with operating voltage and

temperature. As a rule of thumb, assume that effective capacitance decreases by as much as 50%. The input,

output, and bias capacitors recommended in the Recommended Operating Conditions table account for an

effective capacitance of approximately 50% of the nominal value.

8.1.2 Input and Output Capacitor Requirements

A minimum 2.2-µF ceramic capacitor at the input is required for stability, A minimum 2.2-µF ceramic capacitor

with a maximum ESR value of less than 250 mΩ at the output is also required for stability. The input capacitor

counteracts reactive input sources and improves transient response, input ripple, and PSRR. A higher-value

input capacitor may be necessary if large, fast rise-time load or line transients are anticipated, or if the device is

located several inches from the input power source. Dynamic performance of the device is improved with the use

of an output capacitor larger than the minimum value specified in the Recommended Operating Conditions table.

Although a bias capacitor is not required, connect a 0.1-µF ceramic capacitor from BIAS to GND for best analog

design practice. This capacitor counteracts reactive bias sources if the source impedance is not sufficiently low.

Place the input, output, and bias capacitors as close as possible to the device to minimize traces parasitics.

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Application Information (接下页)

8.1.3 Load Transient Response

The load-step transient response is the output voltage response by the LDO to a step in load current while output

voltage regulation is maintained. See 图 9, 图 10, 图 11, and 图 12 for typical load transient response. There are

two key transitions during a load transient response: the transition from a light to a heavy load, and the transition

from a heavy to a light load. The regions in 图 39 are broken down as described in this section. Regions A, E,

and H are where the output voltage is in steady-state operation.

tAt

tCt

tDt

tEt

tGt

tHt

图 39. Load Transient Waveform

During transitions from a light load to a heavy load:

•

The initial voltage dip is a result of the depletion of the output capacitor charge and parasitic impedance to the

output capacitor (region B)

•

Recovery from the dip results from the LDO increasing the sourcing current, and leads to output voltage

regulation (region C)

During transitions from a heavy load to a light load:

•

The initial voltage rise results from the LDO sourcing a large current, and leads to the output capacitor charge

to increase (region F)

•

Recovery from the rise results from the LDO decreasing the sourcing current in combination with the load

discharging the output capacitor (region G)

A larger output capacitance reduces the peaks during a load transient, but slows down the response time of the

device. A larger dc load also reduces the peaks because the amplitude of the transition is lowered, and a higher

current discharge path is provided for the output capacitor.

8.1.4 Dropout Voltage

Generally, dropout voltage refers to the minimum voltage difference between the input and output voltage (V_DO

V_IN– V_OUT) that is required for regulation. When V_IN– V_OUTdrops below the required V_DOfor the given load

current, the device functions as a resistive switch and does not regulate output voltage. Dropout voltage is

proportional to the output current because the device is operating as a resistive switch.

Dropout voltage is affected by the drive strength of the pass-element gate. This drive strength is nonlinear with

respect to V_INon this device.

8.1.5 Behavior During Transition From Dropout Into Regulation

Some applications may have transients that place this device into dropout, especially when this device can be

powered from a battery with relatively high ESR. The load transient saturates the output stage of the error

amplifier when the pass element is driven fully on, making the pass element function like a resistor from V_INto

V_OUT. The error amplifier response time to this load transient is limited because the error amplifier must first

recover from saturation and then place the pass element back into active mode. During this time, V_OUT

overshoots because the pass element is functioning as a resistor from V_INto V_OUT

When V_INramps up slowly for start-up, the slow ramp-up voltage may place the device in dropout. As with many

other LDOs, the output can overshoot on recovery from this condition. However, this condition is easily avoided

through the use of the enable signal.

If operating under these conditions, apply a higher dc load or increase the output capacitance to reduce the

overshoot. These solutions provide a path to dissipate the excess charge.

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Application Information (接下页)

8.1.6 Undervoltage Lockout Circuit Operation

The V_INUVLO circuit makes sure that the device remains disabled before the input supply reaches the minimum

operational voltage range. The V_INUVLO circuit also makes sure that the device shuts down when the input

supply collapses. Similarly, the V_BIASUVLO circuit makes sure that the device stays disabled before the bias

supply reaches the minimum operational voltage range. The V_BIASUVLO circuit also makes sure that the device

shuts down when the bias supply collapses.

图 40 depicts the UVLO circuit response to various input or bias voltage events. This figure can be separated into

the following parts:

•

Region A: The device does not start until the input or bias voltage reaches the UVLO rising threshold.

Region B: Normal operation, regulating device

Region C: Brownout event above the UVLO falling threshold (UVLO rising threshold – UVLO hysteresis). The

output may fall out of regulation, but the device is still enabled.

•

Region D: Normal operation, regulating device

Region E: Brownout event below the UVLO falling threshold. The device is disabled in most cases, and the

output falls as a result of the load and active discharge circuit. The device is re-enabled when the UVLO

rising threshold is reached, and a normal start-up follows.

•

Region F: Normal operation followed by the input or bias falling to the UVLO falling threshold

Region G: The device is disabled as the input or bias voltages fall below the UVLO falling threshold to 0 V.

The output falls as a result of the load and active discharge circuit.

UVLO Rising Threshold

UVLO Hysteresis

V_IN/ V_BIAS

V_OUT

tAt

tBt

tDt

tEt

tFt

tGt

图 40. Typical V_INor V_BIASUVLO Circuit Operation

8.1.7 Power Dissipation (P_D)

Circuit reliability demands that proper consideration be given to device power dissipation, location of the circuit

on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator

must be as free as possible of other heat-generating devices that cause added thermal stresses.

公式 2 calculates the maximum allowable power dissipation for the device in a given package:

P_D-MAX= [(T_J– T_A) / R_θJA

]

(2)

公式 3 represents the actual power being dissipated in the device:

P_D= (I_GND+ I_OUT) × (V_IN– V_OUT

)

(3)

Power dissipation can be minimized, and thus greater efficiency achieved, by proper selection of the system

voltage rails. Proper selection allows the minimum input-to-output voltage differential to be obtained. The low

dropout of the TPS7A10 allows for maximum efficiency across a wide range of output voltages.

The main heat conduction path for the device depends on the ambient temperature and the thermal resistance

across the various interfaces between the die junction and ambient air.

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Application Information (接下页)

The maximum power dissipation determines the maximum allowable junction temperature (T_J) for the device.

According to 公式 4, maximum power dissipation and junction temperature are most often related by the junction-

to-ambient thermal resistance (R_θJA) of the combined PCB and device package and the temperature of the

ambient air (T_A). The equation is rearranged in 公式 5 for output current.

T_J= T_A+ (R_θJA× P_D)

(4)

(5)

I_OUT= (T_J– T_A) / [R_θJA× (V_IN– V_OUT)]

Unfortunately, this thermal resistance (R_θJA) is highly dependent on the heat-spreading capability built into the

particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the

planes. The R_θJArecorded in the Thermal Information table is determined by the JEDEC standard, PCB, and

copper-spreading area, and is only used as a relative measure of package thermal performance.

8.1.7.1 Estimating Junction Temperature

The JEDEC standard recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures of

the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal

resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics

are determined to be significantly independent of the copper-spreading area. The key thermal metrics (Ψ_JTand

Ψ_JB) are used in accordance with 公式 6 and are given in the Thermal Information table.

Ψ_JT: T_J= T_T+ Ψ_JT× P_Dand Ψ_JB: T_J= T_B+ Ψ_JB× P_D

where:

•

P_Dis the power dissipated as explained in 公式 3

T_Tis the temperature at the center-top of the device package

T_Bis the PCB surface temperature measured 1 mm from the device package and centered on the package

edge

(6)

8.1.7.2 Recommended Area for Continuous Operation

The operational area of an LDO is limited by the dropout voltage, output current, junction temperature, and input

voltage. The recommended area for continuous operation for a linear regulator is shown in 图 41, and can be

separated into the following regions:

•

Dropout voltage limits the minimum differential voltage between the input and the output (V_IN– V_OUT) at a

given output current level.

The rated output currents limits the maximum recommended output current level. Exceeding this rating

causes the device to fall out of specification.

The rated junction temperature limits the maximum junction temperature of the device. Exceeding this rating

causes the device to fall out of specification and reduces long-term reliability.

–

公式 5 provides the shape of the slope. The slope is nonlinear because the maximum rated junction

temperature of the LDO is controlled by the power dissipation across the LDO, thus when V_IN– V_OUT

increases, the output current must decrease.

•

The rated input voltage range governs both the minimum and maximum of V_IN– V_OUT.

Output Current Limited

by Dropout

Rated Output

Current

Output Current Limited

by Thermals

Limited by

Minimum V_IN

Maximum V_IN

V_INœ V_OUT(V)

图 41. Region Description of Continuous Operation Regime

TPS7A10

ZHCSHU2B –MARCH 2018–REVISED OCTOBER 2018

www.ti.com.cn

8.2 Typical Application

V_BATTERY

C_BIAS

BIAS

1.4 V

1.2 V

C_OUT

V_OUT

OUT

Standalone

DC/DC Converter

or PMU

C_IN

TPS7A10

GND

V_EN

图 42. Supplying a Clean DC Voltage

8.2.1 Design Requirements

表 2 summarizes the design requirements for 图 42.

表 2. Design Parameters

DESIGN PARAMETER

EXAMPLE VALUE

V_IN

1.4 V

2.7 V

1.2 V

V_BIAS

V_OUT

I_OUT

10-mA typical, 300-mA peak

65°C

Maximum ambient temperature

8.2.2 Detailed Design Procedure

For this design example, the 1.2-V, fixed-version TPS7A1012 device is selected. Use a 4.7-µF input capacitor to

minimize transient currents drawn from the DC/DC convertor. Use a 4.7-µF output capacitor for optimized load

transient response. The dropout voltage (V_DO) is kept within the TPS7A10 dropout voltage specification for the

1.2-V output voltage option inorder to keep the device in regulation under all load and temperature conditions for

this design. The high-PSRR and low-noise measurements for this design example are given in the Thermal

Dissipation section.

8.2.2.1 Input Current

During normal operation, the input current to the LDO is approximately equal to the output current of the LDO.

During startup, the input current is higher as a result of the inrush current charging the output capacitor. Use 公式

7 to calculate the current through the input.

_OUT´ dV_OUT(t)

V_OUT(t)

R_LOAD

I_OUT(t)

where:

•

V_OUT(t) is the instantaneous output voltage of the turnon ramp

dV_OUT(t) / dt is the slope of the V_OUTramp

R_LOADis the resistive load impedance

(7)

TPS7A10

www.ti.com.cn

ZHCSHU2B –MARCH 2018–REVISED OCTOBER 2018

8.2.2.2 Thermal Dissipation

The junction temperature can be determined using the junction-to-ambient thermal resistance (R_θJA) and the total

power dissipation (P_D). Use 公式 8 to calculate the power dissipation. As 公式 9 shows, multiply P_Dby R_θJAand

add the ambient temperature (T_A) to calculate the junction temperature (T_J).

P_D= (I_GND+ I_OUT) × (V_IN– V_OUT

)

(8)

(9)

T_J= R_θJA× P_D+ T_A

If the (T_J(MAX)) value does not exceed 125°C, use 公式 10 to calculate the maximum ambient temperature. 公式

11 calculates the maximum ambient temperature with a value of 99.59°C.

T_A(MAX)= T_J(MAX)– R_θJA× P_D

(10)

(11)

T_A(MAX)= 125°C – 169.4 × (1.4 V – 1.2 V) × (0.3 A) = 114.84°C

8.2.3 Application Curve

I_OUT

10 mA

40 mA

80 mA

120 mA

160 mA

200 mA

250 mA

300 mA

-10

100

10k

100k

10M

Input Voltage (V)

D036

V_IN= 1.4 V, V_OUT= 1.2 V, V_BIAS= 2.7 V,

C_IN= 4.7 µF, C_OUT= 4.7 µF, C_BIAS= 0.1 µF

图 43. PSRR vs Frequency and I_OUT

TPS7A10

ZHCSHU2B –MARCH 2018–REVISED OCTOBER 2018

www.ti.com.cn

9 Power Supply Recommendations

This device is designed to operate from an input supply voltage range of 0.75 V to 3.3 V, and a bias supply

voltage range of 1.7 V to 5.5 V. The input and bias supplies must be well regulated and free of spurious noise.

To make sure that the output voltage is well regulated and dynamic performance is optimum, the input supply

must be at least V_OUT(nom)+ 0.5 V and V_BIAS= V_OUT(nom)+ 1.05 V.

10 Layout

10.1 Layout Guidelines

For correct printed circuit board (PCB) layout, follow these guidelines:

•

Place input, output, and bias capacitors as close to the device as possible.

Use copper planes for device connections to optimize thermal performance.

Place thermal vias around the device to distribute heat.

10.2 Layout Examples

OUT

C_OUT

C_IN

GND

C_BIAS

BIAS

图 44. Recommended Layout for the YKA Package

OUT

C_OUT

C_IN

GND

C_BIAS

BIAS

图 45. Recommended Layout for the DSE Package

TPS7A10

www.ti.com.cn

ZHCSHU2B –MARCH 2018–REVISED OCTOBER 2018

11 器件和文档支持

11.1 器件支持

11.1.1 开发支持

11.1.1.1 评估模块

我们为您提供了评估模块 (EVM)，可以借此来对使用 TPS7A10 时的电路性能进行初始评估。可通过德州仪器 (TI)

网站上的产品文件夹申请获取 TPS7A10EVM，也可以直接从 TI eStore 购买。

11.1.1.2 Spice 模型

可以通过 TPS7A10 产品文件夹的工具与软件选项卡获取该器件的 Spice 模型。

11.1.2 器件命名规则

表 3. 器件命名规则⁽¹⁾⁽²⁾

产品

V_OUT

xx(x) 为标称输出电压。对于分辨率为 50mV 的输出电压，订货编号中使用两位数字；否则，使用三位数

字（例如，28 = 2.8V；125 = 1.25 V）。

yyy 为封装标识符。

TPS7A10xx(x)yyyz

z 为封装数量。R 表示卷，T 表示带。

(1) 要获得最新的封装和订货信息，请参阅本文档末尾的封装选项附录，或者访问器件产品文件夹（www.ti.com.cn）。

(2) 可提供 0.5V 至 3.0V 的输出电压（以 50mV 为单位增量）。有关器件的详细信息和供货情况，请联系制造商。

11.2 文档支持

11.2.1 相关文档

请参阅如下相关文档：

•

德州仪器 (TI)，《TPS7A10EVM-004 评估模块》用户指南

德州仪器 (TI)，《使用新的热度量指标》应用报告

德州仪器 (TI)，《AN-1112 DSBGA 晶圆级芯片级封装》应用报告

11.3 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.4 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

11.5 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.6 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

TPS7A10

ZHCSHU2B –MARCH 2018–REVISED OCTOBER 2018

www.ti.com.cn

11.7 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、缩写和定义。

12 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS7A1006PDSER

TPS7A1006PDSET

TPS7A1006PYKAR

TPS7A1008PDSER

TPS7A1008PDSET

TPS7A1008PYKAR

TPS7A10105PDSER

TPS7A10105PDSET

TPS7A10105PYKAR

TPS7A1010PDSER

TPS7A1010PDSET

TPS7A1010PYKAR

TPS7A1011PDSER

TPS7A1011PDSET

TPS7A1011PYKAR

TPS7A1012PDSER

TPS7A1012PDSET

TPS7A1012PYKAR

TPS7A1015PDSER

TPS7A1015PDSET

ACTIVE

WSON

DSBGA

WSON

DSBGA

WSON

DSBGA

WSON

DSBGA

WSON

DSBGA

WSON

DSBGA

WSON

DSE

YKA

DSE

YKA

DSE

YKA

DSE

YKA

DSE

YKA

DSE

YKA

DSE

3000 RoHS & Green

250 RoHS & Green

NIPDAUAG

Level-1-260C-UNLIM

-40 to 125

NIPDAUAG

SNAGCU

12000 RoHS & Green

3000 RoHS & Green

NIPDAUAG

SNAGCU

250

RoHS & Green

12000 RoHS & Green

3000 RoHS & Green

NIPDAUAG

SNAGCU

250

RoHS & Green

12000 RoHS & Green

3000 RoHS & Green

NIPDAUAG

SNAGCU

250

RoHS & Green

12000 RoHS & Green

3000 RoHS & Green

NIPDAUAG

SNAGCU

250

RoHS & Green

12000 RoHS & Green

3000 RoHS & Green

NIPDAUAG

SNAGCU

250

RoHS & Green

12000 RoHS & Green

3000 RoHS & Green

NIPDAUAG

250

RoHS & Green

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS7A1015PYKAR

TPS7A1018PDSER

TPS7A1018PDSET

TPS7A1018PYKAR

TPS7A1025PDSER

TPS7A1025PDSET

TPS7A1025PYKAR

TPS7A1028PDSER

TPS7A1028PDSET

TPS7A1028PYKAR

TPS7A1030PDSER

TPS7A1030PDSET

TPS7A1030PYKAR

ACTIVE

DSBGA

WSON

DSBGA

WSON

DSBGA

WSON

DSBGA

WSON

DSBGA

YKA

DSE

YKA

DSE

YKA

DSE

YKA

DSE

YKA

12000 RoHS & Green

3000 RoHS & Green

SNAGCU

Level-1-260C-UNLIM

-40 to 125

NIPDAUAG

SNAGCU

250

RoHS & Green

12000 RoHS & Green

3000 RoHS & Green

NIPDAUAG

SNAGCU

250

RoHS & Green

12000 RoHS & Green

3000 RoHS & Green

NIPDAUAG

SNAGCU

250

RoHS & Green

12000 RoHS & Green

3000 RoHS & Green

NIPDAUAG

SNAGCU

250

RoHS & Green

12000 RoHS & Green

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com

25-Jan-2019

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS7A1006PDSER

TPS7A1006PDSET

TPS7A1006PYKAR

TPS7A1008PDSER

TPS7A1008PDSET

TPS7A1008PYKAR

TPS7A10105PDSER

TPS7A10105PDSET

TPS7A10105PYKAR

TPS7A1010PDSER

TPS7A1010PDSET

TPS7A1010PYKAR

TPS7A1011PDSER

TPS7A1011PDSET

TPS7A1011PYKAR

TPS7A1012PDSER

TPS7A1012PDSET

TPS7A1012PYKAR

WSON

DSBGA

WSON

DSBGA

WSON

DSBGA

WSON

DSBGA

WSON

DSBGA

WSON

DSBGA

DSE

YKA

DSE

YKA

DSE

YKA

DSE

YKA

DSE

YKA

DSE

YKA

3000

250

180.0

8.4

1.83

0.9

1.83

1.25

1.83

1.25

1.83

1.25

1.83

1.25

1.83

1.25

1.83

1.25

0.89

0.48

0.89

0.48

0.89

0.48

0.89

0.48

0.89

0.48

0.89

0.48

4.0

2.0

4.0

2.0

4.0

2.0

4.0

2.0

4.0

2.0

4.0

2.0

8.0

12000

3000

250

1.83

0.9

12000

3000

250

1.83

0.9

12000

3000

250

1.83

0.9

12000

3000

250

1.83

0.9

12000

3000

250

1.83

0.9

12000

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

25-Jan-2019

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS7A1015PDSER

TPS7A1015PDSET

TPS7A1015PYKAR

TPS7A1018PDSER

TPS7A1018PDSET

TPS7A1018PYKAR

TPS7A1025PDSER

TPS7A1025PDSET

TPS7A1025PYKAR

TPS7A1028PDSER

TPS7A1028PDSET

TPS7A1028PYKAR

TPS7A1030PDSER

TPS7A1030PDSET

TPS7A1030PYKAR

WSON

DSBGA

WSON

DSBGA

WSON

DSBGA

WSON

DSBGA

WSON

DSBGA

DSE

YKA

DSE

YKA

DSE

YKA

DSE

YKA

DSE

YKA

3000

250

180.0

8.4

1.83

0.9

1.83

1.25

1.83

1.25

1.83

1.25

1.83

1.25

1.83

1.25

0.89

0.48

0.89

0.48

0.89

0.48

0.89

0.48

0.89

0.48

4.0

2.0

4.0

2.0

4.0

2.0

4.0

2.0

4.0

2.0

8.0

12000

3000

250

1.83

0.9

12000

3000

250

1.83

0.9

12000

3000

250

1.83

0.9

12000

3000

250

1.83

0.9

12000

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS7A1006PDSER

TPS7A1006PDSET

WSON

DSE

3000

250

183.0

20.0

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

25-Jan-2019

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS7A1006PYKAR

TPS7A1008PDSER

TPS7A1008PDSET

TPS7A1008PYKAR

TPS7A10105PDSER

TPS7A10105PDSET

TPS7A10105PYKAR

TPS7A1010PDSER

TPS7A1010PDSET

TPS7A1010PYKAR

TPS7A1011PDSER

TPS7A1011PDSET

TPS7A1011PYKAR

TPS7A1012PDSER

TPS7A1012PDSET

TPS7A1012PYKAR

TPS7A1015PDSER

TPS7A1015PDSET

TPS7A1015PYKAR

TPS7A1018PDSER

TPS7A1018PDSET

TPS7A1018PYKAR

TPS7A1025PDSER

TPS7A1025PDSET

TPS7A1025PYKAR

TPS7A1028PDSER

TPS7A1028PDSET

TPS7A1028PYKAR

TPS7A1030PDSER

TPS7A1030PDSET

TPS7A1030PYKAR

DSBGA

WSON

DSBGA

WSON

DSBGA

WSON

DSBGA

WSON

DSBGA

WSON

DSBGA

WSON

DSBGA

WSON

DSBGA

WSON

DSBGA

WSON

DSBGA

WSON

DSBGA

YKA

DSE

YKA

DSE

YKA

DSE

YKA

DSE

YKA

DSE

YKA

DSE

YKA

DSE

YKA

DSE

YKA

DSE

YKA

DSE

YKA

12000

3000

250

182.0

183.0

182.0

183.0

182.0

183.0

182.0

183.0

182.0

183.0

182.0

183.0

182.0

183.0

182.0

183.0

182.0

183.0

182.0

183.0

182.0

183.0

182.0

183.0

182.0

183.0

182.0

183.0

182.0

183.0

182.0

183.0

182.0

183.0

182.0

183.0

182.0

183.0

182.0

183.0

182.0

20.0

12000

3000

250

12000

3000

250

12000

3000

250

12000

3000

250

12000

3000

250

12000

3000

250

12000

3000

250

12000

3000

250

12000

3000

250

12000

Pack Materials-Page 3

PACKAGE OUTLINE

YKA0005

DSBGA - 0.4 mm max height

SCALE 13.000

DIE SIZE BALL GRID ARRAY

BALL A1

INDEX AREA

0.4 MAX

SEATING PLANE

0.05 C

0.18

0.13

BALL

TYP

0.35

0.7

SYMM

D: Max = 1.12 mm, Min = 1.06 mm

E: Max = 0.77 mm, Min = 0.71 mm

0.35

0.24

0.19

0.015

C A B

SYMM

4223737/B 05/2017

NanoFree Is a trademark of Texas Instruments.

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. NanoFree^TMpackage configuration.

www.ti.com

EXAMPLE BOARD LAYOUT

YKA0005

DSBGA - 0.4 mm max height

DIE SIZE BALL GRID ARRAY

(0.35)

5X ( 0.2)

(0.35)

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:50X

(

0.2)

0.0325 MAX

0.0325 MIN

METAL

UNDER

METAL

SOLDER MASK

EXSPOSED

EXPOSED

METAL

SOLDER MASK

OPENING

(

0.2)

METAL

SOLDER MASK

OPENING

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4223737/B 05/2017

NOTES: (continued)

4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).

www.ti.com

EXAMPLE STENCIL DESIGN

YKA0005

DSBGA - 0.4 mm max height

DIE SIZE BALL GRID ARRAY

(0.35)

5X ( 0.21)

(R0.05) TYP

(0.35)

SYMM

METAL

TYP

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.075 mm - 0.1 mm THICK STENCIL

SCALE:50X

4223737/B 05/2017

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

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PACKAGE OUTLINE

DSE0006A

WSON - 0.8 mm max height

SCALE 6.000

PLASTIC SMALL OUTLINE - NO LEAD

1.55

1.45

1.55

1.45

PIN 1 INDEX AREA

0.8 MAX

SEATING PLANE

0.08 C

(0.2) TYP

0.05

0.00

0.6

0.4

2X 1

4X 0.5

0.3

0.7

0.5

0.2

0.1

0.05

PIN 1 ID

C A B

4220552/A 04/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

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EXAMPLE BOARD LAYOUT

DSE0006A

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

PKG

(0.8)

5X (0.7)

6X (0.25)

SYMM

4X 0.5

(R0.05) TYP

(1.6)

LAND PATTERN EXAMPLE

SCALE:40X

0.05 MIN

ALL AROUND

0.05 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

SOLDER MASK

OPENING

PADS 4-6

NON SOLDER MASK

DEFINED

PADS 1-3

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4220552/A 04/2021

NOTES: (continued)

3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).

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EXAMPLE STENCIL DESIGN

DSE0006A

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

PKG

5X (0.7)

(0.8)

6X (0.25)

SYMM

4X (0.5)

(R0.05) TYP

(1.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:40X

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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