TPS7A1130PDRVT [TI]
具有使能功能的 500mA、低输入电压 (0.75V)、超低 IQ、低压降稳压器 | DRV | 6 | -40 to 125;型号: | TPS7A1130PDRVT |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有使能功能的 500mA、低输入电压 (0.75V)、超低 IQ、低压降稳压器 | DRV | 6 | -40 to 125 稳压器 |
文件: | 总40页 (文件大小:5146K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TPS7A11
SBVS316B – SEPTEMBER 2018 – REVISED DECEMBER 2020
TPS7A11 500-mA, Low VIN, Low VOUT, Ultra-Low Dropout Regulator
1 Features
3 Description
•
•
Ultra-low input voltage range: 0.75 V to 3.3 V
Ultra-low dropout for minimum power loss:
– 140 mV (maximum) at 500-mA DRV package
– 110 mV (maximum) at 500-mA YKA package
Low quiescent current:
The TPS7A11 is an ultra-small, low quiescent current,
low-dropout regulator (LDO). This device can source
500 mA with an outstanding ac performance (load and
line transient responses). This device has an input
range of 0.75 V to 3.3 V, and an output range of 0.5 V
to 3.0 V with a very high accuracy of 1.5% over load,
line, and temperature. This performance is ideal for
supplying power to the lower core voltages of modern
microcontrollers (MCUs) and analog sensors.
•
– VIN IQ = 1.6 µA (typical)
– VBIAS IQ = 6 µA (typical)
•
•
•
1.5% accuracy over load, line, and temperature
High PSRR: 64 dB at 1 kHz
Available in fixed-output voltages:
– 0.5 V to 3.0 V (in 50-mV steps)
VBIAS range: 1.7 V to 5.5 V
The primary power path is through the IN pin and can
be connected to a power supply as low as 140 mV
above the output voltage. This device supports very
low input voltages with the use of an additional VBIAS
rail that is used to power the internal circuitry of the
LDO. The IN and BIAS pins consume very low
quiescent current of 1.6 µA and 6 µA, respectively.
The low IQ and ultra-low dropout features help to
increase the efficiency of the solution in power-
sensitive applications. For example, the supply
voltage to the IN pin can be an output of a high-
efficiency, DC/DC step-down regulator and the BIAS
pin supply voltage can be a rechargeable battery.
•
•
Packages:
– 2.0-mm × 2.0-mm WSON (6)
– 0.74-mm × 1.09-mm DSBGA (5)
Active output discharge
•
2 Applications
•
•
•
•
•
•
Smart watches, fitness trackers
Wireless headphones and earbuds
Camera modules
Smart phones and tablets
Portable medical devices
Solid state drives (SSDs)
The TPS7A11 is equipped with an active pulldown
circuit to quickly discharge the output when disabled,
and provides a known start-up state.
The TPS7A11 is available in a small 2.00-mm × 2.00-
mm WSON, 6-pin (DRV) package and an ultra-small
0.74-mm × 1.09-mm, 5-pin DSBGA (YKA) package
that makes the device suitable for space-constrained
applications.
VBATTERY
CBIAS
Device Information (1)
BIAS
VOUT
IN
OUT
Standalone
IN
OUT
PART NUMBER
PACKAGE
BODY SIZE (NOM)
CIN
COUT
DC/DC Converter
Or PMU
TPS7A11
WSON (6)
2.00 mm × 2.00 mm
EN
GND
TPS7A11
GND
0.74 mm × 1.09 mm
(0.35-mm pitch)
DSBGA (5)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Circuit
140
TJ
-40 èC
0 èC
25 èC
85 èC
105 èC
125 èC
120
100
80
60
40
20
0
0
50 100 150 200 250 300 350 400 450 500
Output Current (mA)
Dropout vs IOUT and Temperature, YKA Package
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS7A11
www.ti.com
SBVS316B – SEPTEMBER 2018 – REVISED DECEMBER 2020
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings ....................................... 5
6.2 ESD Ratings .............................................................. 5
6.3 Recommended Operating Conditions ........................5
6.4 Thermal Information ...................................................6
6.5 Electrical Characteristics ............................................6
6.6 Typical Characteristics................................................8
7 Detailed Description......................................................14
7.1 Overview...................................................................14
7.2 Functional Block Diagram.........................................14
7.3 Feature Description...................................................14
7.4 Device Functional Modes..........................................17
8 Application and Implementation..................................18
8.1 Application Information............................................. 18
8.2 Typical Application.................................................... 22
9 Power Supply Recommendations................................23
10 Layout...........................................................................24
10.1 Layout Guidelines................................................... 24
10.2 Layout Examples.................................................... 24
11 Device and Documentation Support..........................25
11.1 Device Support........................................................25
11.2 Documentation Support.......................................... 25
11.3 Receiving Notification of Documentation Updates..25
11.4 Support Resources................................................. 25
11.5 Trademarks............................................................. 26
11.6 Electrostatic Discharge Caution..............................26
11.7 Glossary..................................................................26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (December 2018) to Revision B (December 2020)
Page
•
•
•
Updated the numbering format for tables and figures throughout the document............................................... 1
Updated sequencing requirement to clarify differences between "A" and "non-A" versions.............................15
Changed Device Nomenclature table...............................................................................................................25
Changes from Revision * (September 2018) to Revision A (December 2018)
Page
Changed YKA (DSBGA) package status from Preview to Production Data ......................................................1
Added Evaluation Module subsection ..............................................................................................................25
•
•
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SBVS316B – SEPTEMBER 2018 – REVISED DECEMBER 2020
5 Pin Configuration and Functions
OUT
1
2
3
6
5
4
IN
Thermal
Pad
NC
EN
GND
BIAS
Not to scale
TI recommends connecting the SON (DRV) package thermal pad to ground.
NC – No internal connection.
Figure 5-1. DRV Package, 6-Pin SON With Exposed Thermal Pad, Top View
Table 5-1. Pin Functions: DRV
PIN
I/O
DESCRIPTION
NAME
NO.
Input pin. A capacitor is required from IN to ground for stability. For best transient response, use
the nominal recommended value or larger ceramic capacitor from IN to ground. Follow the
recommended capacitor value as listed in the Recommended Operating Conditions table. Place
the input capacitor as close to the input pin of the device as possible.
IN
6
Input
Regulated output pin. A capacitor is required from OUT to ground for stability. For best transient
response, use the nominal recommended value or larger ceramic capacitor from OUT to ground.
Follow the recommended capacitor value as listed in the Recommended Operating Conditions
table. Place the output capacitor as close to the output pin of the device as possible.
OUT
GND
BIAS
1
5
4
Output
—
Ground pin. This pin must be connected to ground.
BIAS pin. This pin enables the use of low-input voltage, low-output voltage (LILO) conditions. For
best performance, use the nominal recommended value or larger ceramic capacitor from BIAS to
ground. Follow the recommended capacitor value as listed in the Recommended Operating
Conditions table. Place the bias capacitor as close to the bias pin of the device as possible.
Input
Enable pin. Driving this pin to logic high enables the device. Driving this pin to logic low disables
the device. If enable functionality is not required, this pin must be connected to IN or BIAS;
however, connecting EN to IN is only acceptable if the IN pin voltage is greater than 0.9 V.
EN
NC
3
2
Input
This pin is not internally connected. Connect to ground for better thermal dissipation or leave
floating.
—
—
Thermal pad
Connect the thermal pad to a large-area ground plane.
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SBVS316B – SEPTEMBER 2018 – REVISED DECEMBER 2020
IN
A1
A3
OUT
GND
BIAS
B2
C1
C3
EN
Not to scale
Figure 5-2. YKA Package, 5-Pin DSBGA, Top View
Table 5-2. Pin Functions: YKA
PIN
I/O
DESCRIPTION
NO.
NAME
Input pin. A capacitor is required from IN to ground for stability. For best transient response, use the
nominal recommended value or larger ceramic capacitor from IN to ground. Follow the recommended
capacitor value as listed in the Recommended Operating Conditions table. Place the input capacitor as
close to the input pin of the device as possible.
A1
IN
Input
Regulated output pin. A capacitor is required from OUT to ground for stability. For best transient
response, use the nominal recommended value or larger ceramic capacitor from OUT to ground. Follow
the recommended capacitor value as listed in the Recommended Operating Conditions table. Place the
output capacitor as close to the output pin of the device as possible.
A3
B2
C1
OUT
GND
BIAS
Output
—
Ground pin. This pin must be connected to ground.
BIAS pin. This pin enables the use of low-input voltage, low-output voltage (LILO) conditions. For best
performance, use the nominal recommended value or larger ceramic capacitor from BIAS to ground.
Follow the recommended capacitor value as listed in the Recommended Operating Conditions table.
Place the bias capacitor as close to the bias pin of the device as possible.
Input
Enable pin. Driving this pin to logic high enables the device. Driving this pin to logic low disables the
C3
EN
Input device. If enable functionality is not required, this pin must be connected to IN or BIAS; however,
connecting EN to IN is only acceptable if the IN pin voltage is greater than 0.9 V.
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SBVS316B – SEPTEMBER 2018 – REVISED DECEMBER 2020
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range unless otherwise noted.(1)
MIN
–0.3
–0.3
–0.3
–0.3
MAX UNIT
Input, VIN
3.6
Enable, VEN
Voltage
6.0
V
6.0
Bias, VBIAS
Output, VOUT
VIN + 0.3 (2)
Current
Maximum output
Operating junction, TJ
Storage, Tstg
Internally limited
A
–40
–65
150
150
°C
°C
Temperature
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The absolute maximum rating is 3.6 V or (VIN + 0.3 V), whichever is less.
6.2 ESD Ratings
VALUE
±3000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted).
MIN
0.75
1.7
0.5
0
NOM
MAX
3.3
UNIT
V
VIN
Input voltage
VBIAS
VOUT
IOUT
CIN
Bias voltage
5.5
V
Output voltage
3.0
V
Peak output current
Input capacitor
500
mA
µF
µF
µF
℃
2.2
CBIAS
COUT
TJ
Bias capacitor
0.1
(1)
Output capacitor
Operating junction temperature
2.2
22
–40
125
(1) Maximum ESR must be lower than 250 mΩ
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UNIT
SBVS316B – SEPTEMBER 2018 – REVISED DECEMBER 2020
6.4 Thermal Information
TPS7A11
DRV (WSON)
THERMAL METRIC(1)
YKA (DSBGA)
5 PINS
169.4
1.1
6 PINS
77.3
91.6
41.1
4.3
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
55.4
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.7
ψJB
41.0
18.6
55.6
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over TJ = –40°C to +125°C, VIN = VOUT(NOM) + 0.5 V, VBIAS = VOUT(NOM) + 1.4 V, IOUT = 1 mA, VEN = 1.0 V, CIN = 2.2 μF, COUT
= 2.2 μF, and CBIAS = 0.1 μF ( unless otherwise noted); all typical values are at TJ = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Nominal accuracy
TJ = 25°C
-0.5
0.5
%
–20°C ≤ TJ ≤ 85, DRV package
VOUT(NOM) + 0.5 V ≤ VIN ≤ 3.3 V,
VOUT(NOM) + 1.4 V ≤ VBIAS ≤ 5.5 V,
1 mA ≤ IOUT ≤ 500 mA
-1.25
-1.25
-1.5
1.25
–40°C ≤ TJ ≤ 85, YKA package
VOUT(NOM) + 0.5 V ≤ VIN ≤ 3.3 V,
VOUT(NOM) + 1.4 V ≤ VBIAS ≤ 5.5 V,
1 mA ≤ IOUT ≤ 500 mA
Accuracy over temperature
1.25
1.5
%
–40°C ≤ TJ ≤ 125,
VOUT(NOM) + 0.5 V ≤ VIN ≤ 3.3 V,
VOUT(NOM) + 1.4 V ≤ VBIAS ≤ 5.5 V,
1 mA ≤ IOUT ≤ 500 mA
ΔVOUT / ΔVIN
ΔVOUT / ΔVBIAS
ΔVOUT / ΔIOUT
VIN line regulation
VBIAS line regulation
Load regulation
VOUT(NOM) + 0.5 V ≤ VIN ≤ 3.3 V
VOUT(NOM) + 1.4 V ≤ VBIAS ≤ 5.5 V
0.1 mA ≤ IOUT ≤ 500 mA
TJ = 25°C, IOUT = 0 mA
–40°C < TJ < 85°C, IOUT = 0 mA
IOUT = 0 mA
0.001
0.03
0.2
%/V
%/V
%/A
3
6
8
11
IQ(BIAS)
Bias pin current
µA
14
IOUT = 500 mA
60
TJ = 25°C, IOUT = 0 mA
–40°C < TJ < 85°C, IOUT = 0 mA
IOUT = 0 mA
1.6
2.1
2.3
2.6
11
IQ(IN)
Input pin current(1)
µA
nA
IOUT = 500 mA
–40°C < TJ < 85°C,
VIN = 3.3 V, VBIAS = 5.5 V, VEN ≤ 0.4 V
400
1200
1
ISHDN(BIAS)
VBIAS shutdown current
–40°C < TJ < 125°C,
VIN = 3.3 V, VBIAS = 5.5 V, VEN ≤ 0.4 V
–40°C < TJ < 85°C,
VIN = 3.3 V, VBIAS = 5.5 V, VEN ≤ 0.4 V
ISHDN(IN)
VIN shutdown current
Output current limit
µA
–40°C < TJ < 125°C,
VIN = 3.3 V, VBIAS = 5.5 V, VEN ≤ 0.4 V
3
VOUT = 0.9 × VOUT(NOM), YKA Package
VOUT = 0.9 × VOUT(NOM), DRV Package
625
700
920
990
1175
1250
ICL
mA
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6.5 Electrical Characteristics (continued)
over TJ = –40°C to +125°C, VIN = VOUT(NOM) + 0.5 V, VBIAS = VOUT(NOM) + 1.4 V, IOUT = 1 mA, VEN = 1.0 V, CIN = 2.2 μF, COUT
= 2.2 μF, and CBIAS = 0.1 μF ( unless otherwise noted); all typical values are at TJ = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ISC
Short circuit current limit
VOUT = 0 V
300
mA
VIN = VOUT(NOM) – 0.1 V, IOUT = 500 mA,
YKA package
70
90
110
mV
140
VDO(IN)
VIN dropout voltage(2)
VIN = VOUT(NOM) – 0.1 V, IOUT = 500 mA,
DRV package
IOUT = 500 mA
IOUT = 250 mA
0.85
0.75
1.2
V
1.0
VDO(BIAS)
VBIAS dropout voltage(2)
f = 1 kHz,
VOUT = 1.0 V, IOUT = 50 mA
64
37
f = 100 kHz,
VOUT = 1.0 V, IOUT = 50 mA
VIN power-supply rejection
ratio
VIN PSRR
dB
f = 1 MHz,
VOUT = 1.0 V, IOUT = 50 mA
31
f = 1.5 MHz,
VOUT = 1.0 V, IOUT = 50 mA
35
f = 1 kHz,
VOUT = 1.0 V, IOUT = 500 mA
56
VBIAS power-supply
rejection ratio
f = 100 kHz,
VOUT = 1.0 V, IOUT = 500 mA
VBIAS PSRR
43
dB
f = 1 MHz,
VOUT = 1.0 V, IOUT = 500 mA
33
Bandwidth = 10 Hz to 100 kHz,
VOUT = 1.0 V, IOUT = 50 mA
Vn
Output voltage noise
93.9
µVRMS
VBIAS rising
VBIAS falling
VBIAS hysteresis
VIN rising
1.46
1.35
1.54
1.44
80
1.63
V
VUVLO(BIAS)
VUVLO_HYST(BIAS)
VUVLO(IN)
Bias supply UVLO
Bias supply hysteresis
Input supply UVLO
1.55
mV
645
565
675
600
75
710
mV
640
VIN falling
VUVLO_HYST(IN)
tSTR
Input supply hysteresis
Start-up time(3)
VIN hysteresis
mV
525
1200
0.4
µs
V
VHI(EN)
EN pin logic high voltage
EN pin logic low voltage
EN pin current
0.9
VLO(EN)
IEN
V
EN = 5.5 V
10
120
160
145
nA
Ω
RPULLDOWN
Pulldown resistor
VBIAS = 3.3 V, P version only
Shutdown, temperature rising
Reset, temperature falling
Thermal shutdown
temperature
TSD
°C
(1) This is the current flowing from VIN to GND.
(2) Dropout is not measured for VOUT < 1.0 V.
(3) Startup time = time from EN assertion to 0.95 × VOUT(NOM).
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6.6 Typical Characteristics
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 0.5 V, VBIAS = VOUT(NOM) + 1.4 V, IOUT = 1 mA, VEN = VIN, CIN = COUT
= 2.2 µF, and CBIAS = 0.1 µF (unless otherwise noted)
0.4
0.3
0.2
0.1
0
0.4
0.3
0.2
0.1
0
TJ
-40 èC
TJ
-40 èC
85 èC
105 èC
125 èC
85 èC
105 èC
125 èC
0 èC
25 èC
0 èC
25 èC
-0.1
-0.2
-0.3
-0.4
-0.1
-0.2
-0.3
-0.4
0
50 100 150 200 250 300 350 400 450 500
Output Current (mA)
1.4 1.6 1.8
2
2.2 2.4 2.6 2.8
Input Voltage (V)
3
3.2 3.4
DRV package
YKA package
Figure 6-1. Output Accuracy vs IOUT and Temperature
Figure 6-2. Output Accuracy vs VIN and Temperature
0.4
140
TJ
TJ
-40 èC
0 èC
25 èC
85 èC
105 èC
125 èC
-40èC
0èC
25èC
85èC
105èC
125èC
0.3
0.2
0.1
0
120
100
80
60
40
20
0
-0.1
-0.2
-0.3
-0.4
0
50 100 150 200 250 300 350 400 450 500
Output Current (mA)
0
50 100 150 200 250 300 350 400 450 500
Output Current (mA)
YKA package
DRV package
Figure 6-3. Output Accuracy vs IOUT and Temperature
Figure 6-4. VIN Dropout vs IOUT and Temperature
140
0.25
TJ
-40 èC
TJ
-40 èC
0 èC
0.2
0.15
0.1
85 èC
105 èC
125 èC
85 èC
105 èC
125 èC
120
100
80
60
40
20
0
0 èC
25 èC
25 èC
0.05
0
-0.05
-0.1
-0.15
-0.2
-0.25
2
2.5
3
3.5 4
Bias Voltage (V)
4.5
5
5.5
0
50 100 150 200 250 300 350 400 450 500
Output Current (mA)
YKA package
Figure 6-6. Output Accuracy vs VBIAS and Temperature
Figure 6-5. VIN Dropout vs IOUT and Temperature
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6.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 0.5 V, VBIAS = VOUT(NOM) + 1.4 V, IOUT = 1 mA, VEN = VIN, CIN = COUT
= 2.2 µF, and CBIAS = 0.1 µF (unless otherwise noted)
1100
1000
900
800
700
600
500
400
16
14
12
10
8
TJ
-40èC
TJ
25èC
85èC
85èC
105èC
125èC
-40èC
0èC
105èC
125èC
0èC
25èC
6
4
2
0
0
50 100 150 200 250 300 350 400 450 500
Output Current (mA)
1.5
2
2.5
3
3.5
4
Bias Voltage (V)
4.5
5
5.5
IOUT = 0 mA
Figure 6-7. VBIAS Dropout vs IOUT and Temperature
Figure 6-8. IQ(BIAS) vs VBIAS and Temperature
65
3
TJ
25èC
85èC
T
60
2.8
2.6
2.4
2.2
2
-40èC
0èC
105èC
125èC
-40 èC
85 èC
105 èC
125 èC
55
50
45
40
35
30
25
20
15
10
5
0 èC
25 èC
1.8
1.6
1.4
1.2
1
0
1.5
2
2.5
3
Bias Voltage (V)
3.5
4
4.5
5
5.5
0.5
1
1.5
2
Input Voltage (V)
2.5
3
3.5
IOUT = 500 mA
IOUT = 0 mA
Figure 6-9. IQ(BIAS) vs VBIAS and Temperature
Figure 6-10. IQ(IN) vs VIN and Temperature
18
1.2
1
TJ
-40èC
16
14
12
10
8
85èC
105èC
125èC
0èC
25èC
TJ
0.8
0.6
0.4
0.2
0
-40 èC
0 èC
25 èC
85 èC
105 èC
125 èC
6
4
2
0
1
1.5
2 2.5
Input Voltage (V)
3
3.5
100 200 300 400 500 600 700 800 900 1000 1100
Output Current (mA)
IOUT = 500 mA
Figure 6-11. IQ(IN) vs VIN and Temperature
Figure 6-12. Foldback Output Current Limit vs IOUT and
Temperature
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6.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 0.5 V, VBIAS = VOUT(NOM) + 1.4 V, IOUT = 1 mA, VEN = VIN, CIN = COUT
= 2.2 µF, and CBIAS = 0.1 µF (unless otherwise noted)
3.5
3
3
2.5
2
TJ
-40 èC
VIN
VEN
VBIAS
VOUT
85 èC
105 èC
125 èC
0 èC
25 èC
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
-0.5
-0.5
0.6
0.9
1.2
1.5
1.8 2.1
Input Voltage (V)
2.4
2.7
3
3.3
0
100 200 300 400 500 600 700 800 900 1000
Time (ms)
VOUT = 1.0 V, VEN < 0.4 V
Figure 6-13. ISHDN vs VIN and Temperature
VOUT = 0.5 V
Figure 6-14. Startup With VEN = VIN
3
2.5
2
3
2.5
2
VIN
VEN
VBIAS
VOUT
VIN
VEN
VBIAS
VOUT
1.5
1
1.5
1
0.5
0
0.5
0
-0.5
-0.5
0
100 200 300 400 500 600 700 800 900 1000
Time (ms)
0
100 200 300 400 500 600 700 800 900 1000
Time (ms)
VOUT = 0.5 V
VOUT = 0.5 V
Figure 6-15. Startup With VEN and VBIAS Powering Up
Simultaneously
Figure 6-16. Startup With Separated VEN
3
5
50
25
0
VIN
VEN
VBIAS
VOUT
4.5
4
2.5
2
3.5
3
-25
VIN
VOUT
-50
1.5
1
2.5
2
-75
-100
-125
-150
-175
0.5
0
1.5
1
0.5
0
-0.5
-200
100 200 300 400 500 600 700 800 900 1000
Time (ms)
0
100 200 300 400 500 600 700 800 900 1000
Time (ms)
0
VOUT = 0.5 V
VOUT = 1.0 V, IOUT = 1 mA
Figure 6-17. Startup With VBIAS Powering Up After VIN and VEN
Figure 6-18. VIN Transient
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6.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 0.5 V, VBIAS = VOUT(NOM) + 1.4 V, IOUT = 1 mA, VEN = VIN, CIN = COUT
= 2.2 µF, and CBIAS = 0.1 µF (unless otherwise noted)
5
4.5
4
50
200
100
500
450
400
350
300
250
200
150
100
50
0
0
-50
-100
-200
-300
-400
-500
-600
-700
-800
-900
-1000
3.5
3
-100
-150
-200
-250
-300
-350
-400
-450
VOUT
IOUT
VIN
VOUT
2.5
2
1.5
1
0
0.5
0
-50
-100
0
100 200 300 400 500 600 700 800 900 1000
Time (ms)
0
100 200 300 400 500 600 700 800 900 1000
Time (ms)
VOUT = 1.0 V, IOUT = 500 mA
VOUT = 1.0 V, IOUT = 0 mA to 250 mA
Figure 6-19. VIN Transient
Figure 6-20. IOUT Transient
200
100
500
200
0
1250
450
400
350
300
250
200
150
100
50
0
1000
750
500
250
0
-100
-200
-300
-400
-500
-600
-700
-800
-900
-1000
-200
-400
-600
-800
-1000
VOUT
IOUT
VOUT
IOUT
0
-50
-100
-250
1000
0
100 200 300 400 500 600 700 800 900 1000
Time (ms)
0
200
400
600
800
Time (ms)
VOUT = 1.0 V, IOUT = 1 mA to 250 mA
VOUT = 1.0 V, IOUT = 0 mA to 500 mA
Figure 6-21. IOUT Transient
Figure 6-22. IOUT Transient
200
0
1250
1000
750
500
250
0
100
90
80
70
60
50
40
30
20
10
0
IOUT
10 mA
50 mA
100 mA
200 mA
300 mA
400 mA
500 mA
-200
-400
-600
-800
VOUT
IOUT
-1000
0
-250
1000
200
400
Time (ms)
600
800
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
VOUT = 1.0 V, IOUT = 1 mA to 500 mA
CIN = 0 μF, VOUT = 1.0 V
Figure 6-24. VIN PSRR vs Frequency and IOUT
Figure 6-23. IOUT Transient
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6.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 0.5 V, VBIAS = VOUT(NOM) + 1.4 V, IOUT = 1 mA, VEN = VIN, CIN = COUT
= 2.2 µF, and CBIAS = 0.1 µF (unless otherwise noted)
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VDO
200 mV
400 mV
600 mV
COUT
10 mF
800 mV
1000 mV
2.2 mF
22 mF
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
CIN = 0 μF, VOUT = 1.0 V, IOUT = 500 mA, VDO = VIN – VOUT
CIN = 0 μF, VOUT = 1.0 V, IOUT = 500 mA
Figure 6-25. VIN PSRR vs Frequency and Dropout
Figure 6-26. VIN PSRR vs Frequency and COUT
100
50
IOUT, (mVRMS
50 mA, (91.2)
120 mA, (88.4)
200 mA, (86.8)
)
VBIAS
20
10
5
90
300 mA, (85.4)
400 mA, (83.7)
500 mA, (82.1)
2.4 V
3.0 V
3.5 V
4.0 V
4.5 V
5.0 V
5.5 V
80
70
60
50
40
30
20
10
0
2
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
VOUT = 1.0 V
Figure 6-28. Output Noise vs Frequency and IOUT
1.65
CIN = 2.2 μF, VOUT = 1.0 V, IOUT = 500 mA, CBIAS = 0 μF
Figure 6-27. VBIAS PSRR vs Frequency and VBIAS
20
VOUT = 0.5 V, 32.2 mVRMS
10
VOUT = 1.0 V, 82.2 mVRMS
1.6
1.55
1.5
5
VOUT = 3.0 V, 193.9 mVRMS
2
1
0.5
0.2
0.1
1.45
1.4
0.05
0.02
0.01
1.35
1.3
VBIAS UVLO (Falling)
VBIAS UVLO (Rising)
0.005
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
IOUT = 500 mA
Figure 6-29. Output Noise vs Frequency and VOUT
Figure 6-30. VUVLO(BIAS) Rising and Falling Threshold vs
Temperature
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6.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 0.5 V, VBIAS = VOUT(NOM) + 1.4 V, IOUT = 1 mA, VEN = VIN, CIN = COUT
= 2.2 µF, and CBIAS = 0.1 µF (unless otherwise noted)
0.69
0.68
0.67
0.66
0.65
0.64
0.63
0.62
0.61
0.6
0.605
0.595
0.585
0.575
0.565
0.555
0.545
0.535
0.525
0.515
VEN(LO)
VEN(HI)
VIN UVLO (Falling)
VIN UVLO (Rising)
0.59
0.58
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
Temperature (èC)
Figure 6-32. Enable High and Low Threshold vs Temperature
Figure 6-31. VUVLO(IN) Rising and Falling Threshold vs
Temperature
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7 Detailed Description
7.1 Overview
The TPS7A11 is a low-input, ultra-low dropout, and low quiescent current linear regulator that is optimized for
excellent transient performance. These characteristics make the device ideal for most battery-powered
applications. The implementation of the BIAS pin on the TPS7A11 vastly improves efficiency of low-voltage
output applications by allowing the use of a pre-regulated, low-voltage input supply that offers sub-band-gap
output voltages. This low-dropout regulator (LDO) offers foldback current limit, shutdown, thermal protection,
high output voltage accuracy of 1.5% over the recommended junction temperature range, and optional active
discharge.
7.2 Functional Block Diagram
Current
Limit
IN
BIAS
EN
OUT
Thermal
Shutdown
+
Global
UVLO
Active Discharge
P-Version Only
œ
Bandgap
GND
Internal
Controller
7.3 Feature Description
7.3.1 Excellent Transient Response
The TPS7A11 responds quickly to a transient on the input supply (line transient) or the output current (load
transient) resulting from the device high input impedance and low output impedance across frequency. This
same capability also means that the device has a high power-supply rejection ratio (PSRR) and low internal
noise floor (en). The LDO approximates an ideal power supply with outstanding line and load transient
performance.
The choice of external component values optimizes the small- and large-signal response; see the Input and
Output Capacitor Requirements section for proper capacitor selection.
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7.3.1.1 Global Undervoltage Lockout (UVLO)
The TPS7A11 uses two undervoltage lockout circuits: one on the BIAS pin and one on the IN pin to prevent the
device from turning on before either VBIAS and VIN rise above their lockout voltages. The two UVLO signals are
connected internally through an AND gate, as shown in Figure 7-1, that allows the device to be turned off when
either of these rails are below the lockout voltage.
UVLO(IN)
Global UVLO
UVLO(BIAS)
Figure 7-1. Global UVLO circuit
7.3.2 Active Discharge
The active discharge option has an internal pulldown MOSFET that connects a 120-Ω resistor to ground when
the device is disabled in order to actively discharge the output voltage. The active discharge circuit is activated
by driving the enable pin to logic low to disable the device, or when the device is in thermal shutdown.
The discharge time after disabling the device depends on the output capacitance (COUT) and the load resistance
(RL ) in parallel with the 120-Ω pulldown resistor. Equation 1 calculates this time:
120 · RL
t =
· COUT
120 + RL
(1)
Do not rely on the active discharge circuit for discharging a large amount of output capacitance after the input
supply has collapsed because reverse current can flow from the output to the input. This reverse current flow
can cause damage to the device. Limit reverse current to no more than 5% of the device-rated current.
7.3.3 Enable Pin
The enable pin for the device is active high. The output of the device is turned on when the enable pin voltage is
greater than the EN pin logic high voltage, and the output of the device is turned off when the enable pin voltage
is less than the EN pin logic low voltage. A voltage less than the EN pin logic low voltage on the enable pin
disables all internal circuits.
7.3.4 Sequencing Requirement
The IN, BIAS, and EN pin voltages can be sequenced in any order without causing damage to the device. The
start up is always monotonic regardless of the sequencing order or the ramp rates of the IN, BIAS, and EN pins.
For optimum device performance, VBIAS should be present before enabling the device because the device
internal circuitry is powered by VBIAS. For part numbers with an A following the voltage digits (example:
TPS7A11xxPA), the shutdown current is independent of sequencing. For part numbers without an A following the
voltage digits (example: TPS7A11xxP), the shutdown current into the BIAS input may increase by approximately
2 µA if the BIAS supply was present before the LDO was enabled and then disabled. This behavior can be
avoided with part numbers without an A by applying a logic high enable signal before applying the BIAS supply.
See the Recommended Operating Conditions table for proper voltage ranges of the IN, BIAS, and EN pins.
7.3.5 Internal Foldback Current Limit
The internal foldback current limit circuit is used to protect the LDO against high-load current faults or shorting
events. The foldback mechanism lowers the current limit as the output voltage decreases and limits power
dissipation during short-circuit events, while still allowing for the device to operate at the rated output current;
see Figure 6-12.
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For example, when VOUT is 90% of VOUT(nom), the current limit is ICL (typical); however, if VOUT is forced to 0 V,
the current limit is ISC (typical). In many LDOs, the foldback current limit can prevent start up into a constant-
current load or a negatively-biased output. A brick-wall current limit is when there is an abrupt current stop after
the current limit is reached. The foldback mechanism for this device goes into a brick-wall current limit when
VOUT is 90% of VOUT(nom), thus limiting current to ICL (typical). When VOUT is approximately 0 V, current is limited
to ISC (typical) in order to provide normal start up into a variety of loads. Thermal shutdown can be activated
during a current-limit event because of the high power dissipation typically found in these conditions. To provide
proper operation of the current limit, minimize the inductances to the input and load. Continuous operation in
current limit is not recommended.
7.3.6 Thermal Shutdown
The device contains a thermal shutdown protection circuit to disable the device when the thermal junction
temperature (TJ ) of the main pass-FET rises to the thermal shutdown temperature (TSD) for shutdown listed in
the Electrical Characteristics table. Thermal shutdown hysteresis ensures that the LDO resets again (turns on)
when the temperature falls to TSD for reset.
The thermal time constant of the semiconductor die is fairly short, and thus the device may cycle on and off
when thermal shutdown is reached until the power dissipation is reduced.
For reliable operation, limit the junction temperature to a maximum of 125°C. Operation above 125°C causes the
device to exceed the operational specifications. Although the internal protection circuitry of the device is
designed to protect against thermal overload conditions, this circuitry is not intended to replace proper heat
sinking. Continuously running the device into thermal shutdown or above a junction temperature of 125°C
reduces long-term reliability.
A fast start up when TJ > TSD for reset (typical, outside of the specified operation range) causes the device
thermal shutdown to assert at TSD for reset, and prevents the device from turning on until the junction
temperature is reduced below TSD for reset.
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7.4 Device Functional Modes
The device has the following modes of operation:
•
•
•
Normal operation: The device regulates to the nominal output voltage
Dropout operation: The pass element operates as a resistor and the output voltage is set as VIN – VDO
Disabled: The output of the device is disabled and the discharge circuit is activated
Table 7-1 shows the conditions that lead to the different modes of operation.
Table 7-1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN
VBIAS
VEN
IOUT
TJ
VIN > VOUT (nom) + VDO
and VIN > VIN(min)
TJ < TSD for
shutdown
Normal mode
Dropout mode
VBIAS > VOUT + VDO(BIAS)
VEN > VHI(EN)
IOUT < ICL
VIN(min) < VIN < VOUT
(nom) + VDO(IN)
TJ < TSD for
shutdown
VBIAS < VOUT + VDO(BIAS)
VEN > VHI(EN)
IOUT < ICL
Disabled mode
(any true condition
disables the device)
TJ > TSD for
shutdown
VIN < VUVLO(IN)
VBIAS < VBIAS(UVLO)
VEN < VLO(EN)
—
7.4.1 Normal Mode
The device regulates the output to the nominal output voltage when all normal mode conditions in Table 7-1 are
met.
7.4.2 Dropout Mode
The device is not in regulation, and the output voltage tracks the input voltage minus the voltage drop across the
pass element of the device. In this mode, the PSRR, noise, and transient performance of the device are
significantly degraded.
7.4.3 Disable Mode
In this mode the pass element is turned off, the internal circuits are shut down, and the output voltage is actively
discharged to ground by an internal resistor.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
Successfully implementing an LDO in an application depends on the application requirements. This section
discusses key device features and how to best implement them to achieve a reliable design.
8.1.1 Recommended Capacitor Types
The device is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input,
output, and bias pins. Multilayer ceramic capacitors are the industry standard for these types of applications, but
must be used with good judgment. Ceramic capacitors that use X7R-, X5R-, and COG-rated dielectric materials
provide relatively good capacitive stability across temperature. Avoid Y5V-rated capacitors because of large
variations in capacitance. Regardless of the ceramic capacitor type selected, ceramic capacitance varies with
operating voltage and temperature. As a rule of thumb, assume that effective capacitance decreases by as much
as 50%. The input, output, and bias capacitors recommended in the Recommended Operating Conditions table
account for an effective capacitance of approximately 50% of the nominal value.
8.1.2 Input and Output Capacitor Requirements
A minimum input ceramic capacitor is required for stability. A minimum output ceramic capacitor is also required
for stability, refer to the Recommended Operating Conditions table for the minimum capacitors values.
The input capacitor counteracts reactive input sources and improves transient response, input ripple, and PSRR.
A higher-value input capacitor may be necessary if large, fast rise-time load or line transients are anticipated, or
if the device is located several inches from the input power source. Dynamic performance of the device is
improved with the use of an output capacitor larger than the minimum value specified in the Recommended
Operating Conditions table.
Although a bias capacitor is not required, connect a 0.1-µF ceramic capacitor from BIAS to GND for best analog
design practice. This capacitor counteracts reactive bias sources if the source impedance is not sufficiently low.
Place the input, output, and bias capacitors as close as possible to the device to minimize trace parasitics.
8.1.3 Load Transient Response
The load-step transient response is the output voltage response by the LDO to a step in load current while
output voltage regulation is maintained. See Figure 6-20 to Figure 6-23 for typical load transient response. There
are two key transitions during a load transient response: the transition from a light to a heavy load, and the
transition from a heavy to a light load. The regions in Figure 8-1 are broken down as described in this section.
Regions A, E, and H are where the output voltage is in steady-state operation.
tAt
tCt
tDt
tEt
tGt
tHt
B
F
Figure 8-1. Load Transient Waveform
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During transitions from a light load to a heavy load, the:
•
Initial voltage dip is a result of the depletion of the output capacitor charge and parasitic impedance to the
output capacitor (region B)
•
Recovery from the dip results from the LDO increasing the sourcing current, and leads to output voltage
regulation (region C)
During transitions from a heavy load to a light load, the:
•
Initial voltage rise results from the LDO sourcing a large current, and leads to an increase in the output
capacitor charge (region F)
•
Recovery from the rise results from the LDO decreasing its sourcing current in combination with the load
discharging the output capacitor (region G)
A larger output capacitance reduces the peaks during a load transient but slows down the response time of the
device. A larger dc load also reduces the peaks because the amplitude of the transition is lowered and a higher
current discharge path is provided for the output capacitor.
8.1.4 Dropout Voltage
Generally, the dropout voltage often refers to the minimum voltage difference between the input and output
voltage (VDO = VIN – VOUT) that is required for regulation. When VIN – VOUT drops below the required VDO for the
given load current, the device functions as a resistive switch and does not regulate output voltage. Dropout
voltage is linearly proportional to the output current because the device is operating as a resistive switch, see
Figure 6-4 and Figure 6-5.
Dropout voltage is also affected by the drive strength for the gate of the pass element, which is nonlinear with
respect to VBIAS on this device because of the inherited nonlinearity of the pass element gate capacitance, see
Figure 6-7.
8.1.5 Behavior During Transition From Dropout Into Regulation
Some applications may have transients that place this device into dropout, especially when this device can be
powered from a battery with relatively high ESR. The load transient saturates the output stage of the error
amplifier when the pass element is driven fully on, making the pass element function like a resistor from VIN to
VOUT. The error amplifier response time to this load transient is limited because the error amplifier must first
recover from saturation and then places the pass element back into active mode. During this time, VOUT
overshoots because the pass element is functioning as a resistor from VIN to VOUT
.
When VIN ramps up slowly for start-up, the slow ramp-up voltage may place the device in dropout. As with many
other LDOs, the output can overshoot on recovery from this condition. However, this condition is easily avoided
through the use of the enable signal.
If operating under these conditions, apply a higher dc load or increase the output capacitance to reduce the
overshoot. These solutions provide a path to dissipate the excess charge.
8.1.6 Undervoltage Lockout Circuit Operation
The VIN UVLO circuit makes sure that the device remains disabled before the input supply reaches the minimum
operational voltage range. The VIN UVLO circuit also makes sure that the device shuts down when the input
supply collapses. Similarly, the VBIAS UVLO circuit makes sure that the device stays disabled before the bias
supply reaches the minimum operational voltage range. The VBIAS UVLO circuit also makes sure that the device
shuts down when the bias supply collapses.
Figure 8-2 depicts the UVLO circuit response to various input or bias voltage events. The diagram can be
separated into the following parts:
•
•
•
Region A: The device does not start until the input or bias voltage reaches the UVLO rising threshold
Region B: Normal operation, regulating device
Region C: Brownout event above the UVLO falling threshold (UVLO rising threshold – UVLO hystersis). The
output may fall out of regulation but the device is still enabled.
•
Region D: Normal operation, regulating device
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•
Region E: Brownout event below the UVLO falling threshold. The device is disabled in most cases and the
output falls as a result of the load and active discharge circuit. The device is re-enabled when the UVLO
rising threshold is reached and a normal start-up follows.
•
•
Region F: Normal operation followed by the input or bias falling to the UVLO falling threshold
Region G: The device is disabled when the input or bias voltages fall below the UVLO falling threshold to 0 V.
The output falls as a result of the load and active discharge circuit.
UVLO Rising Threshold
UVLO Hysteresis
VIN / VBIAS
C
VOUT
tAt
tBt
tDt
tEt
tFt
tGt
Figure 8-2. Typical VIN or VBIAS UVLO Circuit Operation
8.1.7 Power Dissipation (PD)
Circuit reliability demands that proper consideration be given to device power dissipation, location of the circuit
on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator
must be as free as possible of other heat-generating devices that cause added thermal stresses.
Equation 2 calculates the maximum allowable power dissipation for the device in a given package:
PD-MAX = [(TJ – TA) / RθJA
]
(2)
Equation 3 represents the actual power being dissipated in the device:
PD = (IGND + IOUT) × (VIN – VOUT
)
(3)
Power dissipation can be minimized, and thus greater efficiency achieved, by proper selection of the system
voltage rails. Proper selection allows the minimum input-to-output voltage differential to be obtained. The low
dropout of the TPS7A11 allows for maximum efficiency across a wide range of output voltages.
The main heat conduction path for the device depends on the ambient temperature and the thermal resistance
across the various interfaces between the die junction and ambient air.
The maximum power dissipation determines the maximum allowable junction temperature (TJ) for the device.
According to Equation 4, maximum power dissipation and junction temperature are most often related by the
junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of
the ambient air (TA). The equation is rearranged in Equation 5 for output current.
TJ = TA + (RθJA × PD)
(4)
(5)
IOUT = (TJ – TA) / [RθJA × (VIN – VOUT)]
Unfortunately, this thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the
particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the
planes. The RθJA recorded in the Electrical Characteristics table is determined by the JEDEC standard, PCB,
and copper-spreading area, and is only used as a relative measure of package thermal performance. For a well-
designed thermal layout, RθJA is actually the sum of the DRV package junction-to-case (bottom) thermal
resistance (RθJC(bot)) plus the thermal resistance contribution by the PCB copper.
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SBVS316B – SEPTEMBER 2018 – REVISED DECEMBER 2020
8.1.8 Estimating Junction Temperature
The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures
of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal
resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics
are determined to be significantly independent of the copper-spreading area. The key thermal metrics (ΨJT and
ΨJB) are used in accordance with Equation 6 and are given in the Electrical Characteristics table.
ΨJT : TJ = TT + ΨJT × PD and ΨJB : TJ = TB + ΨJB × PD
(6)
where:
•
•
•
PD is the power dissipated as explained in Equation 3
TT is the temperature at the center-top of the device package
TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge
8.1.9 Recommended Area for Continuous Operation
The operational area of an LDO is limited by the dropout voltage, output current, junction temperature, and input
voltage. The recommended area for continuous operation for a linear regulator is shown in Figure 8-3 and can
be separated into the following regions:
•
•
•
Dropout voltage limits the minimum differential voltage between the input and the output (VIN – VOUT) at a
given output current level; see the Dropout Voltage section for more details.
The rated output current limits the maximum recommended output current level. Exceeding this rating causes
the device to fall out of specification.
The rated junction temperature limits the maximum junction temperature of the device. Exceeding this rating
causes the device to fall out of specification and reduces long-term reliability.
– Equation 5 provides the shape of the slope. The slope is nonlinear because the maximum rated junction
temperature of the LDO is controlled by the power dissipation across the LDO, thus when VIN – VOUT
increases the output current must decrease.
•
The rated input voltage range governs both the minimum and maximum of VIN – VOUT
.
Output Current Limited
by Dropout
Rated Output
Current
Output Current Limited
by Thermals
Limited by
Minimum VIN
Limited by
Maximum VIN
VIN œ VOUT (V)
Figure 8-3. Continuous Operation Diagram With Description of Regions
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8.2 Typical Application
2.4 V ~ 5.5 V
CBIAS
1.2 V
CIN
1.0 V
COUT
BIAS
VOUT
IN
OUT
IN
OUT
Low Iq
DC/DC Converter
GND
Rechargeable
Battery
TPS7A11
EN
GND
Figure 8-4. High Efficiency Supply From a Rechargeable Battery
8.2.1 Design Requirements
Table 8-1 lists the parameters for this design example.
Table 8-1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
VIN
1.2 V
2.4 V (min)
VBIAS
VOUT
IOUT
1.0 V
150 mA (typical), 500 mA (peak)
8.2.2 Detailed Design Procedures
This design example is powered by a rechargeable battery that can be a building block in many portable
applications. Noise-sensitive portable electronics require an efficient small-size solution for their power supply.
Traditional LDOs are known for their low efficiency in contrast to the low-input, low-output voltage (LILO) LDOs
such as the TPS7A11. The use of a bias rail in the TPS7A11 allows the device to operate at a lower input
voltage, thus reducing the power dissipation across the die and maximizing device efficiency. Equation 7
calculates the efficiency for this design.
Efficiency = η = POUT/PIN ×100 % = (VOUT × IOUT) /(VIN × IIN + VBIAS × IBIAS) × 100 %
(7)
Equation 7 reduces to Equation 8 because the design example load current is much greater than the quiescent
current of the bias rail.
Efficiency = η = (VOUT × IOUT) / (VIN × IIN) × 100%
(8)
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8.2.3 Application Curve
Figure 8-5 shows a plot of the calculated efficiency.
100
80
60
40
20
0
0.001
0.01
0.1
1
Output Current (mA)
10
100
1000
VIN = VEN = 1.2 V, CIN = 2.2 µF, VOUT = 1.0 V, COUT = 2.2 µF, VBIAS = 2.4 V, CBIAS = 0.1 µF
Figure 8-5. TPS7A11 Output Efficiency at 1.2 VIN and 1.0 VOUT
9 Power Supply Recommendations
This device is designed to operate from an input supply voltage range of 0.75 V to 3.3 V and a bias supply
voltage range of 1.7 V to 5.5 V. The input and bias supplies must be well regulated and free of spurious noise. To
make sure that the output voltage is well regulated and dynamic performance is optimum, the input supply must
be at least VOUT(nom) + 0.5 V and VBIAS = VOUT(nom) + VDO(BIAS)
.
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10 Layout
10.1 Layout Guidelines
For correct printed circuit board (PCB) layout, follow these guidelines:
•
•
•
Place input, output, and bias capacitors as close to the device as possible
Use copper planes for device connections to optimize thermal performance
Place thermal vias around the device to distribute heat
10.2 Layout Examples
OUT
IN
CIN
COUT
A1
A3
GND
B2
C3
C1
CBIAS
BIAS
EN
Figure 10-1. Recommended Layout for YKA Package
Ground Plane
To Enable
Signal
To Bias Supply
4
5
BIAS
GND
EN
NC
3
2
1
CBIAS
COUT
CIN
6
IN
OUT
To Load
To Input Supply
Ground Plane
Figure 10-2. Recommended Layout for DRV Package
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Evaluation Module
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the
TPS7A11. The TPS720xxDRVEVM evaluation module (and related user guide) can be requested at the Texas
Instruments website through the product folders or purchased directly from the TI eStore.
11.1.2 Spice Model
Spice models for this device are available through the for the TPS7A11 product folder under the Tool and
Software tab.
11.1.3 Device Nomenclature
Table 11-1. Device Nomenclature (1) (2)
PRODUCT
VOUT
xx(x) is the nominal output voltage. For output voltages with a resolution of 50 mV, two digits are used in
the ordering number; otherwise, three digits are used (for example, 28 = 2.8 V; 125 = 1.25 V).
(P), when present, indicates the active discharge option.
(A), when present, indicates the BIAS shutdown current is independent of sequencing. See the
Sequencing Requirement section.
TPS7A11xx(x)(P)(A)yyyz
yyy is the package designator.
z is the package quantity. R is for reel (3000 pieces), T is for tape (250 pieces).
() indicates optional placeholders.
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder on www.ti.com.
(2) Output voltages from 0.5 V to 3.0 V in 50-mV increments are available. Contact the factory for details and availability.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
•
•
•
•
Texas Instruments, TPS720xxDRVEVM Evaluation Module user's guide
Texas Instruments, Using New Thermal Metrics application report
Texas Instruments, AN-1112 DSBGA Wafer Level Chip Scale Package application report
Texas Instruments, TIDA-01566 Light Load Efficient, Low Noise Power Supply Reference Design for
Wearables and IoT design guide
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
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11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2020 Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS7A1105PYKAR
TPS7A1106PDRVR
TPS7A1106PDRVT
TPS7A1106PYKAR
TPS7A11075PYKAR
TPS7A1108PDRVR
TPS7A1108PDRVT
TPS7A1109PYKAR
TPS7A11105PDRVR
TPS7A11105PDRVT
TPS7A11105PYKAR
TPS7A1110PDRVR
TPS7A1110PDRVT
TPS7A1110PYKAR
TPS7A1111PDRVR
TPS7A1111PDRVT
TPS7A1111PYKAR
TPS7A1112PDRVR
TPS7A1112PDRVT
TPS7A1112PYKAR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DSBGA
WSON
WSON
DSBGA
DSBGA
WSON
WSON
DSBGA
WSON
WSON
DSBGA
WSON
WSON
DSBGA
WSON
WSON
DSBGA
WSON
WSON
DSBGA
YKA
DRV
DRV
YKA
YKA
DRV
DRV
YKA
DRV
DRV
YKA
DRV
DRV
YKA
DRV
DRV
YKA
DRV
DRV
YKA
5
6
6
5
5
6
6
5
6
6
5
6
6
5
6
6
5
6
6
5
12000 RoHS & Green
3000 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
G
NIPDAU
NIPDAU
SNAGCU
SNAGCU
NIPDAU
NIPDAU
SNAGCU
NIPDAU
NIPDAU
SNAGCU
NIPDAU
NIPDAU
SNAGCU
NIPDAU
NIPDAU
SNAGCU
NIPDAU
NIPDAU
SNAGCU
1R6H
1R6H
H
250
RoHS & Green
12000 RoHS & Green
12000 RoHS & Green
3000 RoHS & Green
I
1R7H
1R7H
J
250
RoHS & Green
12000 RoHS & Green
3000 RoHS & Green
1R9H
1R9H
K
250
RoHS & Green
12000 RoHS & Green
3000 RoHS & Green
1R8H
1R8H
L
250
RoHS & Green
12000 RoHS & Green
3000 RoHS & Green
1RAH
1RAH
3
250
RoHS & Green
12000 RoHS & Green
3000 RoHS & Green
1RBH
1RBH
U
250
RoHS & Green
12000 RoHS & Green
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS7A1115PDRVR
TPS7A1115PDRVT
TPS7A1118PDRVR
TPS7A1118PDRVT
TPS7A1118PYKAR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WSON
WSON
WSON
WSON
DSBGA
DRV
DRV
DRV
DRV
YKA
6
6
6
6
5
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
1RCH
1RCH
1RDH
1RDH
M
NIPDAU
NIPDAU
NIPDAU
SNAGCU
12000 RoHS & Green
TPS7A1119PYKAR
TPS7A1125PDRVR
PREVIEW
ACTIVE
DSBGA
WSON
YKA
DRV
5
6
12000 RoHS & Green
3000 RoHS & Green
SNAGCU
NIPDAU
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
D
1REH
TPS7A1125PDRVT
TPS7A1128PDRVR
TPS7A1128PDRVT
TPS7A1128PYKAR
TPS7A1130PDRVR
TPS7A1130PDRVT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WSON
WSON
WSON
DSBGA
WSON
WSON
DRV
DRV
DRV
YKA
DRV
DRV
6
6
6
5
6
6
250
3000 RoHS & Green
250 RoHS & Green
RoHS & Green
NIPDAU
NIPDAU
NIPDAU
SNAGCU
NIPDAU
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
1REH
1RFH
1RFH
N
12000 RoHS & Green
3000 RoHS & Green
1RGH
1RGH
250
RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Nov-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS7A1105PYKAR
TPS7A1106PDRVR
TPS7A1106PDRVT
TPS7A1106PYKAR
TPS7A11075PYKAR
TPS7A1108PDRVR
TPS7A1108PDRVT
TPS7A1109PYKAR
TPS7A11105PDRVR
TPS7A11105PDRVT
TPS7A11105PYKAR
TPS7A1110PDRVR
TPS7A1110PDRVT
TPS7A1110PYKAR
TPS7A1111PDRVR
TPS7A1111PDRVT
TPS7A1111PYKAR
TPS7A1112PDRVR
DSBGA
WSON
WSON
DSBGA
DSBGA
WSON
WSON
DSBGA
WSON
WSON
DSBGA
WSON
WSON
DSBGA
WSON
WSON
DSBGA
WSON
YKA
DRV
DRV
YKA
YKA
DRV
DRV
YKA
DRV
DRV
YKA
DRV
DRV
YKA
DRV
DRV
YKA
DRV
5
6
6
5
5
6
6
5
6
6
5
6
6
5
6
6
5
6
12000
3000
250
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
0.9
2.3
2.3
0.9
0.9
2.3
2.3
0.9
2.3
2.3
0.9
2.3
2.3
0.9
2.3
2.3
0.9
2.3
1.25
2.3
0.48
1.15
1.15
0.48
0.48
1.15
1.15
0.48
1.15
1.15
0.48
1.15
1.15
0.48
1.15
1.15
0.48
1.15
2.0
4.0
4.0
2.0
2.0
4.0
4.0
2.0
4.0
4.0
2.0
4.0
4.0
2.0
4.0
4.0
2.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q1
Q2
Q2
Q1
Q1
Q2
Q2
Q1
Q2
Q2
Q1
Q2
Q2
Q1
Q2
Q2
Q1
Q2
2.3
12000
12000
3000
250
1.25
1.25
2.3
2.3
12000
3000
250
1.25
2.3
2.3
12000
3000
250
1.25
2.3
2.3
12000
3000
250
1.25
2.3
2.3
12000
3000
1.25
2.3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Nov-2020
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS7A1112PDRVT
TPS7A1112PYKAR
TPS7A1115PDRVR
TPS7A1115PDRVT
TPS7A1118PDRVR
TPS7A1118PDRVT
TPS7A1118PYKAR
TPS7A1125PDRVR
TPS7A1125PDRVT
TPS7A1128PDRVR
TPS7A1128PDRVT
TPS7A1128PYKAR
TPS7A1130PDRVR
TPS7A1130PDRVT
WSON
DSBGA
WSON
WSON
WSON
WSON
DSBGA
WSON
WSON
WSON
WSON
DSBGA
WSON
WSON
DRV
YKA
DRV
DRV
DRV
DRV
YKA
DRV
DRV
DRV
DRV
YKA
DRV
DRV
6
5
6
6
6
6
5
6
6
6
6
5
6
6
250
12000
3000
250
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
2.3
0.9
2.3
2.3
2.3
2.3
0.9
2.3
2.3
2.3
2.3
0.9
2.3
2.3
2.3
1.25
2.3
2.3
2.3
2.3
1.25
2.3
2.3
2.3
2.3
1.25
2.3
2.3
1.15
0.48
1.15
1.15
1.15
1.15
0.48
1.15
1.15
1.15
1.15
0.48
1.15
1.15
4.0
2.0
4.0
4.0
4.0
4.0
2.0
4.0
4.0
4.0
4.0
2.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q2
Q1
Q2
Q2
Q2
Q2
Q1
Q2
Q2
Q2
Q2
Q1
Q2
Q2
3000
250
12000
3000
250
3000
250
12000
3000
250
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS7A1105PYKAR
TPS7A1106PDRVR
TPS7A1106PDRVT
DSBGA
WSON
WSON
YKA
DRV
DRV
5
6
6
12000
3000
250
182.0
210.0
210.0
182.0
185.0
185.0
20.0
35.0
35.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Nov-2020
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS7A1106PYKAR
TPS7A11075PYKAR
TPS7A1108PDRVR
TPS7A1108PDRVT
TPS7A1109PYKAR
TPS7A11105PDRVR
TPS7A11105PDRVT
TPS7A11105PYKAR
TPS7A1110PDRVR
TPS7A1110PDRVT
TPS7A1110PYKAR
TPS7A1111PDRVR
TPS7A1111PDRVT
TPS7A1111PYKAR
TPS7A1112PDRVR
TPS7A1112PDRVT
TPS7A1112PYKAR
TPS7A1115PDRVR
TPS7A1115PDRVT
TPS7A1118PDRVR
TPS7A1118PDRVT
TPS7A1118PYKAR
TPS7A1125PDRVR
TPS7A1125PDRVT
TPS7A1128PDRVR
TPS7A1128PDRVT
TPS7A1128PYKAR
TPS7A1130PDRVR
TPS7A1130PDRVT
DSBGA
DSBGA
WSON
WSON
DSBGA
WSON
WSON
DSBGA
WSON
WSON
DSBGA
WSON
WSON
DSBGA
WSON
WSON
DSBGA
WSON
WSON
WSON
WSON
DSBGA
WSON
WSON
WSON
WSON
DSBGA
WSON
WSON
YKA
YKA
DRV
DRV
YKA
DRV
DRV
YKA
DRV
DRV
YKA
DRV
DRV
YKA
DRV
DRV
YKA
DRV
DRV
DRV
DRV
YKA
DRV
DRV
DRV
DRV
YKA
DRV
DRV
5
5
6
6
5
6
6
5
6
6
5
6
6
5
6
6
5
6
6
6
6
5
6
6
6
6
5
6
6
12000
12000
3000
250
182.0
182.0
210.0
210.0
182.0
210.0
210.0
182.0
210.0
210.0
182.0
210.0
210.0
182.0
210.0
210.0
182.0
210.0
210.0
210.0
210.0
182.0
210.0
210.0
210.0
210.0
182.0
210.0
210.0
182.0
182.0
185.0
185.0
182.0
185.0
185.0
182.0
185.0
185.0
182.0
185.0
185.0
182.0
185.0
185.0
182.0
185.0
185.0
185.0
185.0
182.0
185.0
185.0
185.0
185.0
182.0
185.0
185.0
20.0
20.0
35.0
35.0
20.0
35.0
35.0
20.0
35.0
35.0
20.0
35.0
35.0
20.0
35.0
35.0
20.0
35.0
35.0
35.0
35.0
20.0
35.0
35.0
35.0
35.0
20.0
35.0
35.0
12000
3000
250
12000
3000
250
12000
3000
250
12000
3000
250
12000
3000
250
3000
250
12000
3000
250
3000
250
12000
3000
250
Pack Materials-Page 3
GENERIC PACKAGE VIEW
DRV 6
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4206925/F
PACKAGE OUTLINE
DRV0006A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
A
B
PIN 1 INDEX AREA
2.1
1.9
0.8
0.7
C
SEATING PLANE
0.08 C
(0.2) TYP
0.05
0.00
1
0.1
EXPOSED
THERMAL PAD
3
4
6
2X
7
1.3
1.6 0.1
1
4X 0.65
0.35
0.25
6X
PIN 1 ID
(OPTIONAL)
0.3
0.2
6X
0.1
C A
C
B
0.05
4222173/B 04/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRV0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.45)
6X (0.3)
(1)
1
7
6
SYMM
(1.6)
(1.1)
4X (0.65)
4
3
SYMM
(1.95)
(R0.05) TYP
(
0.2) VIA
TYP
LAND PATTERN EXAMPLE
SCALE:25X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222173/B 04/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
www.ti.com
EXAMPLE STENCIL DESIGN
DRV0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
7
6X (0.45)
METAL
1
6
6X (0.3)
(0.45)
SYMM
4X (0.65)
(0.7)
4
3
(R0.05) TYP
(1)
(1.95)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD #7
88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:30X
4222173/B 04/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
YKA0005
DSBGA - 0.4 mm max height
SCALE 13.000
DIE SIZE BALL GRID ARRAY
A
B
E
BALL A1
INDEX AREA
D
0.4 MAX
C
SEATING PLANE
0.05 C
0.18
0.13
BALL
TYP
0.35
C
B
A
0.7
SYMM
D: Max = 1.12 mm, Min = 1.06 mm
E: Max = 0.77 mm, Min = 0.71 mm
0.35
0.24
5X
1
2
3
0.19
0.015
C A B
SYMM
4223737/B 05/2017
NanoFree Is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. NanoFreeTM package configuration.
www.ti.com
EXAMPLE BOARD LAYOUT
YKA0005
DSBGA - 0.4 mm max height
DIE SIZE BALL GRID ARRAY
(0.35)
2
5X ( 0.2)
1
3
A
B
(0.35)
SYMM
C
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:50X
(
0.2)
0.0325 MAX
0.0325 MIN
METAL
UNDER
METAL
SOLDER MASK
EXSPOSED
EXPOSED
METAL
SOLDER MASK
OPENING
(
0.2)
METAL
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4223737/B 05/2017
NOTES: (continued)
4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YKA0005
DSBGA - 0.4 mm max height
DIE SIZE BALL GRID ARRAY
(0.35)
2
5X ( 0.21)
(R0.05) TYP
1
3
A
B
(0.35)
SYMM
METAL
TYP
C
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.075 mm - 0.1 mm THICK STENCIL
SCALE:50X
4223737/B 05/2017
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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