TPS7A1413PYBKR [TI]

1A、低输入和输出电压、超低压降 (LDO) 稳压器 | YBK | 6 | -40 to 125;


型号：	TPS7A1413PYBKR
厂家：	TEXAS INSTRUMENTS
描述：	1A、低输入和输出电压、超低压降 (LDO) 稳压器 \| YBK \| 6 \| -40 to 125 稳压器
文件：	总34页 (文件大小：3140K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS7A14

ZHCSPG4B –DECEMBER 2021 –REVISED MAY 2022

TPS7A14 1A、低V_IN、低V_OUT、超低压降稳压器

1 特性

3 说明

• 超低输入电压范围：0.7V 至2.2V

• 高效率：

– 1A 时的压降电压为：70mV（最大值）

– 适用于V_IN= V_OUT+100mV

• 出色的负载瞬态响应：

TPS7A14 是一款小型超低压差稳压器 (LDO)，具有出

色的瞬态响应。该器件可提供 1A 电流，并具有出色的

交流性能（负载和线路瞬态响应）。输入电压范围为

0.7V 至 2.2V，输出范围为 0.5V 至 2.05V，且在负

载、线路和温度范围内具有1% 的超高精度。

– I_LOAD在20µs 内从3mA 变化到600mA 时为

主电源路径通过 IN 引脚，可连接至电压至少高于输出

电压 50mV 的电源。所有电气特性（包括出色的输出

电压容差、瞬态响应和 PSRR）均针对输入电压（比

输出电压高 100mV）进行规定，因此可实现高效率。

该稳压器使用一个为 LDO 内部电路供电的外部较高

20mV

• 在负载、线路和温度范围内的精度为：1%

• 高PSRR：

– 在1kHz 下为80dB（V_OUT= 0.8V，I_OUT

500mA）

_BIAS电压轨，支持很低的输入电压。例如，IN 引脚的

电源电压可以是高效直流/直流降压稳压器的输出，而

BIAS 引脚电源电压可来自可再充电电池。

• 可提供固定输出电压：

– 0.5V 至2.05V（阶跃为25mV）

• V_BIAS范围：2.2V 至5.5V

• 封装：

TPS7A14 配备了一个有源下拉电路，用于在输出处于

禁用状态时使其快速放电，并提供已知的启动状态。

– 6 引脚DSBGA：0.71mm × 1.16mm

• 有源输出放电

TPS7A14 可采用超小型 0.71mm × 1.16mm、6 凸点

DSBGA 封装，非常适合空间受限的应用。

2 应用

器件信息⁽¹⁾

• 摄像头模块

封装尺寸（标称值）

器件型号

TPS7A14

封装

DSBGA (6)

• 无线耳机和耳塞

• 智能手表和健身追踪器

• 智能手机和平板电脑

• 便携式医疗设备

• 固态硬盘(SSD)

0.71mm × 1.16mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

C_BIAS

BIAS

V_OUT

OUT

Standalone

OUT

C_IN

C_OUT

DC/DC Converter

Or PMU

TPS7A14

SENSE

GND

典型应用电路

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SBVS400

TPS7A14

www.ti.com.cn

ZHCSPG4B –DECEMBER 2021 –REVISED MAY 2022

Table of Contents

7.4 Device Functional Modes..........................................16

8 Application and Implementation..................................17

8.1 Application Information............................................. 17

8.2 Typical Application.................................................... 21

9 Power Supply Recommendations................................23

10 Layout...........................................................................23

10.1 Layout Guidelines................................................... 23

10.2 Layout Example...................................................... 24

11 Device and Documentation Support..........................25

11.1 Device Support........................................................25

11.2 Documentation Support.......................................... 25

11.3 接收文档更新通知................................................... 25

11.4 支持资源..................................................................25

11.5 Trademarks............................................................. 25

11.6 Electrostatic Discharge Caution..............................25

11.7 术语表..................................................................... 25

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................4

6.4 Thermal Information....................................................5

6.5 Electrical Characteristics.............................................5

6.6 Switching Characteristics............................................7

6.7 Typical Characteristics................................................8

7 Detailed Description......................................................13

7.1 Overview...................................................................13

7.2 Functional Block Diagram.........................................13

7.3 Feature Description...................................................14

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision A (January 2022) to Revision B (May 2022)

Page

• Changed Functional Block Diagram image...................................................................................................... 13

Changes from Revision * (December 2021) to Revision A (January 2022)

Page

• Changed PSRR vs Frequency and V_IN–V_OUTfigure legend to align with Electrical Characteristics ..............8

Submit Document Feedback

Product Folder Links: TPS7A14

TPS7A14

www.ti.com.cn

ZHCSPG4B –DECEMBER 2021 –REVISED MAY 2022

5 Pin Configuration and Functions

OUT

SENSE

GND

BIAS

Not to scale

图5-1. YBK Package, 6-Pin WCSP (Top View)

表5-1. Pin Functions

TYPE

DESCRIPTION

NO. NAME

Regulated output pin. A 2.2 µF or greater capacitance is required from OUT to ground for stability.

For best transient response, use an 8-µF (nominal) or larger ceramic capacitor from OUT to

ground. Place the output capacitor as close to OUT as possible.

OUT

Output

Input

Input pin. A 0.75 µF or greater capacitance is required from IN to ground for stability. Place the

input capacitor as close to IN as possible.

SENSE input. This pin is a feedback input to the regulator for SENSE connections. Connecting

SENSE to the load helps eliminate voltage errors resulting from trace resistance between OUT

and the load.

SENSE

Input

Enable pin. Driving this pin to logic high enables the LDO. Driving this pin to logic low disables the

LDO. If enable functionality is not required, EN must be connected to IN or BIAS.

Input

GND

Ground pin. This pin must be connected to ground.

—

BIAS pin. This pin enables operation in low-input voltage, low-output voltage (LILO) conditions.

For best performance, use 0.47-µF or larger ceramic capacitor from BIAS to ground. Place the

bias capacitor as close to BIAS as possible.

BIAS

Input

Submit Document Feedback

Product Folder Links: TPS7A14

TPS7A14

www.ti.com.cn

ZHCSPG4B –DECEMBER 2021 –REVISED MAY 2022

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range unless otherwise noted.⁽¹⁾

MIN

–0.3

MAX UNIT

Input, V_IN

2.4

6.0

Enable, V_EN

–0.3

Voltage

Bias, V_BIAS

6.0

V_IN+ 0.3 ⁽²⁾

–0.3

Sense, V_SENSE

Output, V_OUT

–0.3

Current

Maximum output

Operating junction, T_J

Storage, T_stg

Internally limited

–40

150

°C

Temperature

–65

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not

sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,

performance, and shorten the device lifetime.

(2) The absolute maximum rating is 2.4 V or (V_IN+ 0.3 V), whichever is less.

6.2 ESD Ratings

VALUE

±3000

±750

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

V_(ESD)

Electrostatic discharge

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating junction temperature range (unless otherwise noted).⁽¹⁾

MIN

NOM

MAX

UNIT

V_IN

Input voltage

Bias voltage

0.7

2.2

Greater of 2.2 or

V_OUT(NOM)+ 1.4

V_BIAS

5.5

V_OUT

I_OUT

C_IN

Output voltage

0.5

2.05

Peak output current

Input capacitance ⁽²⁾

0.75

µF

mΩ

C_BIAS

C_OUT

ESR

T_J

Bias capacitance ⁽³⁾

0.1

Output capacitance

2.2

100

125

Output capacitor series resistance

Operating junction temperature

–40

℃

(1) All voltages are with respect to GND.

(2) An input capacitor is required to counteract the effect of source resistance and inductance, which may in some cases cause symptoms

of system level instability such as ringing or oscillation, especially in the presence of load transients. A larger input capacitor may be

necessary depending on the source impedance and system requirements.

(3) A BIAS input capacitor is not required for LDO stability. However, a capacitor with a derated value of at least 0.1 µF is recommended to

maintain transient, PSRR, and noise performance.

Submit Document Feedback

Product Folder Links: TPS7A14

TPS7A14

www.ti.com.cn

ZHCSPG4B –DECEMBER 2021 –REVISED MAY 2022

6.4 Thermal Information

TPS7A14

THERMAL METRIC⁽¹⁾

DSBGA

6 PINS

136.7

1.1

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

38.1

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.5

ψ_JT

38.1

ψ_JB

R_θJC(bot)

n/a

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics

specified at T_J= –40°C to +85°C, V_IN= V_OUT(NOM)+ 0.1 V, V_BIAS= greater of 2.2 V or V_OUT(NOM)+ 1.4 V, I_OUT= 1 mA, V_EN

1.0 V, C_IN= 1 μF, C_OUT= 2.2 μF, and C_BIAS= 0.1 μF (unless otherwise noted); all typical values are at T_J= 25°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_OUT(NOM)+ 0.1 V ≤

TJ = –40°C to +125°C

–1.5

V_IN≤2.2 V,

Greater of 2.2 V or

V_OUT(NOM)+ 1.4 V ≤

Accuracy over temperature

TJ = –40°C to +85°C

–1

_BIAS≤5.5 V,

1 mA ≤I_OUT≤1 A

V_INline regulation

V_BIASline regulation

Load regulation

2.5

%/A

µA

ΔV_OUT/ ΔV_IN

ΔV_OUT/ ΔV_BIAS

ΔV_OUT/ ΔI_OUT

V_OUT(NOM)+ 0.1 V ≤V_IN≤2.2 V

V_OUT(NOM)+ 1.4 V ≤V_BIAS≤5.5 V

1 mA ≤I_OUT≤1 A

–2.5

±0.15

0.2

I_OUT= 0 mA

I_Q(BIAS)

Bias pin current

I_OUT= 1 A

µA

I_Q(IN)

Input pin current⁽¹⁾

I_OUT= 0 mA

5.7

620

3.8

9.2

I_GND

Ground pin current

V_BIASshutdown current

V_INshutdown current

I_OUT= 1 A

480

0.3

µA

I_SHDN(BIAS)

I_SHDN(IN)

µA

V_IN= 2.2 V, V_BIAS= 5.5 V, V_EN≤0.2 V

V_IN= 1.8 V, V_BIAS= 5.5 V, V_EN≤0.2 V

µA

V_OUT= 0.95 × V_OUT(NOM)

T_J= –40°C to +125°C

I_CL

I_SC

Output current limit

1.035

1.6

2.45

Short circuit current limit

V_OUT= 0 V

600

TJ = –40°C to + 125°C

TJ = –40°C to + 85°C

V_IN= 0.95 x V_OUT(NOM)

V_DO(IN)

V_INdropout voltage⁽²⁾

I_OUT= 1 A

V_BIAS= greater of 1.7V or V_OUT(nom) + 0.6 V,

V_SENSE= 0.95 x V_OUT(nom), I_OUT= 1 A,

T_J= –40°C to +125°C

V_DO(BIAS)

V_BIASdropout voltage⁽²⁾

1.1

Submit Document Feedback

Product Folder Links: TPS7A14

TPS7A14

www.ti.com.cn

ZHCSPG4B –DECEMBER 2021 –REVISED MAY 2022

6.5 Electrical Characteristics (continued)

specified at T_J= –40°C to +85°C, V_IN= V_OUT(NOM)+ 0.1 V, V_BIAS= greater of 2.2 V or V_OUT(NOM)+ 1.4 V, I_OUT= 1 mA, V_EN

1.0 V, C_IN= 1 μF, C_OUT= 2.2 μF, and C_BIAS= 0.1 μF (unless otherwise noted); all typical values are at T_J= 25°C

PARAMETER

TEST CONDITIONS

I_OUT= 3 mA

I_OUT= 500 mA

I_OUT= 1 A

MIN

TYP

MAX

UNIT

f = 100 Hz

f = 1 kHz

I_OUT= 3 mA

I_OUT= 500 mA

I_OUT= 1 A

I_OUT= 3 mA

I_OUT= 500 mA

I_OUT= 1 A

f = 10 kHz

f = 100 kHz

V_INpower-supply rejection

ratio

V_INPSRR

I_OUT= 3 mA

I_OUT= 500 mA

I_OUT= 1 A

I_OUT= 3 mA

I_OUT= 500 mA

I_OUT= 1 A

f = 1 MHz

f = 1 MHz,

I_OUT= 3 mA

I_OUT= 500 mA

V_IN= V_OUT+ 150 mV

I_OUT= 1 A

f = 1 kHz

V_BIASpower-supply rejection

ratio

V_BIASPSRR

f = 100 kHz

f = 1 MHz

I_OUT= 500 mA

Bandwidth = 10 Hz to 100 kHz,

V_OUT= 0.8 V, 5mA ≤I_OUT≤1 A

V_n

Output voltage noise

7.2

µV_RMS

V_BIASrising

1.15

1.0

1.42

1.3

1.7

V_UVLO(BIAS)

V_{UVLO_HYST(BIAS)}

V_UVLO(IN)

Bias supply UVLO

Bias supply hysteresis

Input supply UVLO

TJ = –40°C to + 125°C

V_BIASfalling

V_BIAShysteresis

V_INrising

1.63

100

603

552

584

530

623

566

TJ = –40°C to + 125°C

V_INfalling

V_{UVLO_HYST(IN)}

t_STR

Input supply hysteresis

Start-up time⁽³⁾

V_INhysteresis

µs

186

V_EN(HI)

EN pin logic high voltage⁽⁴⁾

EN pin logic low voltage⁽⁴⁾

EN pin current

0.6

0.25

T_J= –40°C to +125°C

EN = 5.5 V

V_EN(LOW)

I_EN

-20

V_IN= 0.9 V, V_OUT(nom)= 0.8 V, V_BIAS= 1 V,

V_EN= 0 V, P version only

R_PULLDOWN

Pulldown resistor

Shutdown, temperature rising

Reset, temperature falling

165

140

Thermal shutdown

temperature

T_SD

°C

(1) This is the current flowing from V_INto GND.

(2) Dropout is not measured for V_OUT< 0.6 V. V_BIASdropout applies only for V_BIASof 2.2 V or greater.

(3) Startup time = time from EN assertion to 0.95 × V_OUT(NOM).

(4) An input voltage within the minimum to maximum range is interpreted as the correct logic level.

Submit Document Feedback

Product Folder Links: TPS7A14

TPS7A14

www.ti.com.cn

ZHCSPG4B –DECEMBER 2021 –REVISED MAY 2022

6.6 Switching Characteristics

specified at T_J= –40°C to +125°C, V_IN= V_OUT(NOM)+ 0.1 V, V_BIAS= greater of 2.2 V or V_OUT(NOM)+ 1.4 V, I_OUT= 1 mA, V_EN

= 1.0 V, C_IN= 1 μF, C_OUT= 2.2 μF, and C_BIAS= 0.1 μF (unless otherwise noted); all typical values are at T_J= 25°C; all

transients values are over multiple load or line pulses with periods of 100µs on (high load) and 100µs off (low load)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_IN= (V_OUT(NOM)

0.1 V) to 2.1 V

Transition time, t_R= 1 V / µs

Line transient⁽¹⁾

% V_OUT

ΔV_OUT

V_IN= 2.1 V to

(V_OUT(NOM) + 0.1 V)

Transition time, t_F= 1 V / µs

–1

–2

I_OUT= 3 mA to 600 mA

I_OUT= 600 mA to 3 mA

Transition time, t_R= 20 µs, t_F= 20 µs, t_OFF

200 µs, t_ON= 1 ms, C_IN= 5 μF, C_OUT= 5 μF

Load transient⁽¹⁾

% V_OUT

ΔV_OUT

(1) This specification is verified by design.

Submit Document Feedback

Product Folder Links: TPS7A14

TPS7A14

www.ti.com.cn

ZHCSPG4B –DECEMBER 2021 –REVISED MAY 2022

6.7 Typical Characteristics

at operating temperature T_J= 25°C, V_OUT(NOM)= 0.8 V, V_IN= V_OUT(NOM)+ 0.1 V, V_BIAS= V_OUT(NOM)+ 1.4 V, I_OUT= 1 mA, V_EN

= V_IN, C_IN= 2.2 µF, C_OUT= 2.2 µF, and C_BIAS= 0.47 µF (unless otherwise noted)

图6-2. Output Voltage Accuracy vs V_BIAS

图6-1. Output Voltage Accuracy vs V_IN

图6-3. Output Voltage Accuracy vs I_OUT

图6-5. V_BIASDropout Voltage vs I_OUT

图6-4. V_INDropout Voltage vs I_OUT

图6-6. V_BIASInput Current vs V_BIAS

Submit Document Feedback

Product Folder Links: TPS7A14

TPS7A14

www.ti.com.cn

ZHCSPG4B –DECEMBER 2021 –REVISED MAY 2022

6.7 Typical Characteristics (continued)

at operating temperature T_J= 25°C, V_OUT(NOM)= 0.8 V, V_IN= V_OUT(NOM)+ 0.1 V, V_BIAS= V_OUT(NOM)+ 1.4 V, I_OUT= 1 mA, V_EN

= V_IN, C_IN= 2.2 µF, C_OUT= 2.2 µF, and C_BIAS= 0.47 µF (unless otherwise noted)

I_OUT= 1 A

I_OUT= 0 mA

图6-7. V_BIASInput Current vs V_BIAS

图6-8. V_INShutdown I_Qvs V_IN

I_OUT= 0 A, V_IN= 1 V

图6-10. V_OUTFoldback Current Limit vs Output Current

图6-9. V_BIASShutdown I_Qvs V_BIAS

图6-12. V_INUVLO vs Temperature

图6-11. Enable Threshold vs Temperature

Submit Document Feedback

Product Folder Links: TPS7A14

TPS7A14

www.ti.com.cn

ZHCSPG4B –DECEMBER 2021 –REVISED MAY 2022

6.7 Typical Characteristics (continued)

at operating temperature T_J= 25°C, V_OUT(NOM)= 0.8 V, V_IN= V_OUT(NOM)+ 0.1 V, V_BIAS= V_OUT(NOM)+ 1.4 V, I_OUT= 1 mA, V_EN

= V_IN, C_IN= 2.2 µF, C_OUT= 2.2 µF, and C_BIAS= 0.47 µF (unless otherwise noted)

t_r= 1 μs

图6-13. V_BIASUVLO vs Temperature

图6-14. Start-Up With V_BIASBefore V_IN

t_r= 1 μs

图6-15. Start-Up With V_INBefore V_BIASand V_EN

图6-16. Start-Up With V_INand V_BIASBefore V_EN

t_r= t_f= 10 μs, I_OUT= 1 mA

t_r= 1 μs

图6-18. Line Transient From 1 V to 2.2 V

图6-17. Start-Up With V_INand V_ENBefore V_BIAS

Submit Document Feedback

Product Folder Links: TPS7A14

TPS7A14

www.ti.com.cn

ZHCSPG4B –DECEMBER 2021 –REVISED MAY 2022

6.7 Typical Characteristics (continued)

at operating temperature T_J= 25°C, V_OUT(NOM)= 0.8 V, V_IN= V_OUT(NOM)+ 0.1 V, V_BIAS= V_OUT(NOM)+ 1.4 V, I_OUT= 1 mA, V_EN

= V_IN, C_IN= 2.2 µF, C_OUT= 2.2 µF, and C_BIAS= 0.47 µF (unless otherwise noted)

t_r= t_f= 10 μs, I_OUT= 500 mA

t_r= t_f= 10 μs, I_OUT= 1 A

图6-19. Line Transient From 1 V to 2.2 V

图6-20. Line Transient From 1 V to 2.2 V

t_r= t_f= 1 μs

t_r= t_f= 20 μs

图6-21. Load Transient From 100 μA to 1 A

图6-22. Load Transient From 100 μA to 1 A

C_BIAS= 0 μF, I_OUT= 1 A

图6-23. PSRR vs Frequency and V_IN–V_OUT

图6-24. PSRR vs Frequency and C_OUT

Submit Document Feedback

Product Folder Links: TPS7A14

TPS7A14

www.ti.com.cn

ZHCSPG4B –DECEMBER 2021 –REVISED MAY 2022

6.7 Typical Characteristics (continued)

at operating temperature T_J= 25°C, V_OUT(NOM)= 0.8 V, V_IN= V_OUT(NOM)+ 0.1 V, V_BIAS= V_OUT(NOM)+ 1.4 V, I_OUT= 1 mA, V_EN

= V_IN, C_IN= 2.2 µF, C_OUT= 2.2 µF, and C_BIAS= 0.47 µF (unless otherwise noted)

C_BIAS= 0 μF

图6-25. PSRR vs Frequency and I_OUT

图6-26. PSRR vs Frequency and V_BIAS–V_OUT

图6-27. Output Noise vs Frequency and I_OUT

Submit Document Feedback

Product Folder Links: TPS7A14

TPS7A14

www.ti.com.cn

ZHCSPG4B –DECEMBER 2021 –REVISED MAY 2022

7 Detailed Description

7.1 Overview

The TPS7A14 is a low-input, ultra-low dropout, low-quiescent-current linear regulator that is optimized for

excellent transient performance. These characteristics make the device designed for most battery-powered

applications. The low operating V_IN– V_OUT, combined with the BIAS pin, dramatically improve the efficiency of

low-voltage output applications by powering the voltage reference and control circuitry and allowing the use of a

pre-regulated, low-voltage input supply (IN) for the main power path. This low-dropout regulator (LDO) offers

foldback current limit, shutdown, thermal protection, and an optional active discharge.

7.2 Functional Block Diagram

Current

Limit

OUT

–

Overshoot

Pull-Down

BIAS

Bandgap

UVLO

SENSE

–

Active Discharge

P-Version Only

Internal

Controller

GND

Thermal

Shutdown

Submit Document Feedback

Product Folder Links: TPS7A14

TPS7A14

www.ti.com.cn

ZHCSPG4B –DECEMBER 2021 –REVISED MAY 2022

7.3 Feature Description

7.3.1 Excellent Transient Response

The TPS7A14 responds quickly to a change on the input supply (line transient) or the output current (load

transient) given the device high input impedance and low output impedance across frequency. This same

capability also means that this LDO has a high power-supply rejection ratio (PSRR) and, when coupled with a

low internal noise floor (e_n), the LDO can be used to create an excellent power supply with outstanding line and

load transient performance.

The choice of external component values optimizes the transient response; see the Input, Output, and Bias

Capacitor Requirements section for proper capacitor selection.

7.3.2 Global Undervoltage Lockout (UVLO)

The TPS7A14 uses two undervoltage lockout circuits: one on the BIAS pin and one on the IN pin to prevent the

device from turning on before both V_BIASand V_INrise above their lockout voltages. The two UVLO signals are

connected internally through an AND gate, as shown in 图 7-1, that turns off the device when the voltage on

either input is below their respective UVLO thresholds.

UVLO(IN)

Global UVLO

UVLO(BIAS)

图7-1. Global UVLO circuit

7.3.3 Enable Input

The enable input (EN) is active high. Applying a voltage greater than V_EN(HI)to EN enables the regulator output

voltage, and applying a voltage less than V_EN(LOW)to EN disables the regulator output. If independent control of

the output voltage is not needed, connect EN to either IN or BIAS.

7.3.4 Internal Foldback Current Limit

The device has an internal current limit circuit that protects the regulator during transient high-load current faults

or shorting events. The current limit is a hybrid brick-wall foldback scheme. The current limit transitions from a

brick-wall scheme to a foldback scheme at the foldback voltage (V_FOLDBACK). In a high-load current fault with the

output voltage above V_FOLDBACK, the brick-wall scheme limits the output current to the current limit (I_CL). When

the voltage drops below V_FOLDBACK, a foldback current limit activates that scales back the current as the output

voltage approaches GND. When the output is shorted, the device supplies a typical current called the short-

circuit current limit (I_SC). I_CLand I_SCare listed in the Electrical Characteristics table.

For this device, V_FOLDBACKis approximately 60% × V_OUT(nom)

The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the

device begins to heat up because of the increase in power dissipation. When the device is in brick-wall current

limit, the pass transistor dissipates power [(V_IN–V_OUT) × I_CL]. When the device output is shorted and the output

is below V_FOLDBACK, the pass transistor dissipates power [(V_IN– V_OUT) × I_SC]. If thermal shutdown is triggered,

the device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on.

If the output current fault condition continues, the device cycles between current limit and thermal shutdown. For

more information on current limits, see the Know Your Limits application report.

Submit Document Feedback

Product Folder Links: TPS7A14

TPS7A14

www.ti.com.cn

ZHCSPG4B –DECEMBER 2021 –REVISED MAY 2022

图7-2 shows a diagram of the foldback current limit.

V_OUT

Brickwall

V_OUT(NOM)

V_FOLDBACK

Foldback

0 V

I_OUT

I_RATED

0 mA

I_SC

I_CL

图7-2. Foldback Current Limit

7.3.5 Active Discharge

The active discharge function uses an internal MOSFET that connects a resistor (R_PULLDOWN) to ground when

the LDO is disabled in order to actively discharge the output voltage. The active discharge circuit is activated by

driving EN to logic low to disable the device, when the voltage at IN or BIAS is below the UVLO threshold, or

when the regulator is in thermal shutdown.

The discharge time after disabling the device depends on the output capacitance (C_OUT) and the load resistance

(R_L) in parallel with the pulldown resistor.

Do not rely on the active discharge circuit for discharging a large amount of output capacitance after the input

supply has collapsed because reverse current can flow from the output to the input. This reverse current flow

can cause damage to the device. Limit reverse current to no more than 5% of the rated output current for a short

period of time.

7.3.6 Thermal Shutdown

The internal thermal shutdown protection circuit disables the output when the thermal junction temperature (T_J)

of the pass transistor rises to the thermal shutdown temperature threshold, T_SD(shutdown)(typical). The thermal

shutdown circuit hysteresis ensures that the LDO resets (turns on) when the temperature falls to T_SD(reset)

(typical).

The thermal time constant of the semiconductor die is fairly short; thus, the device may cycle on and off when

thermal shutdown is reached until the power dissipation is reduced. Power dissipation during start up can be

high from large V_IN– V_OUTvoltage drops across the device or from high inrush currents charging large output

capacitors. Under some conditions, the thermal shutdown protection disables the device before start up

completes.

For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating

Conditions table. Operation above this maximum temperature causes the device to exceed its operational

specifications. Although the internal protection circuitry is designed to protect against thermal overload

conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the regulator into

thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability.

Submit Document Feedback

Product Folder Links: TPS7A14

TPS7A14

www.ti.com.cn

ZHCSPG4B –DECEMBER 2021 –REVISED MAY 2022

7.4 Device Functional Modes

表 7-1 shows the conditions that lead to the different modes of operation. See the Electrical Characteristics table

for parameter values.

表7-1. Device Functional Mode Comparison

PARAMETER

OPERATING MODE

V_IN

V_BIAS

V_EN

I_OUT

T_J

V_IN≥V_{OUT (nom)}+ V_DO

and V_IN≥V_IN(min)

T_J< T_SDfor

shutdown

_BIAS≥V_OUT+

V_DO(BIAS)

Normal mode

Dropout mode

I_OUT< I_CL

V_EN≥V_IH(EN)

V_IN(min)< V_IN< V_OUT

_(nom)+ V_DO(IN)

T_J< T_SDfor

shutdown

V_BIAS< V_OUT+ V_DO(BIAS)

V_EN> V_IH(EN)

I_OUT< I_CL

Disabled mode

(any true condition

disables the device)

T_J≥T_SDfor

shutdown

V_IN< V_UVLO(IN)

V_BIAS< V_BIAS(UVLO)

V_EN< V_IL(EN)

—

7.4.1 Normal Operation

The device regulates to the nominal output voltage when the following conditions are met:

• The input voltage is greater than the nominal output voltage plus the dropout voltage (V_OUT(nom)+ V_DO

• The bias voltage is greater than the nominal output voltage plus the dropout voltage (V_OUT(nom)+ V_DO

• The output current is less than the current limit (I_OUT< I_CL

• The device junction temperature is less than the thermal shutdown temperature ( T_J< T_SD(shutdown)

)

• The enable voltage has previously exceeded the enable rising threshold voltage and has not yet decreased

to less than the enable falling threshold

7.4.2 Dropout Operation

If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other

conditions are met for normal operation, the device operates in dropout mode. Similarly, if the bias voltage is

lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for

normal operation, the device operates in dropout mode as well. In this mode, the output voltage tracks the input

voltage. During this mode, the transient performance of the device becomes significantly degraded because the

pass transistor is in the ohmic or triode region, and acts as a switch. Line or load transients in dropout can result

in large output voltage deviations.

When the device is in a steady dropout state, defined as when the device is in dropout, (V_IN< V_OUT+ V_DOor

V_BIAS< V_OUT+ V_DOdirectly after being in normal regulation state, but not during start up), the pass transistor is

driven into the ohmic or triode region. When the input voltage returns to a value greater than or equal to the

nominal output voltage plus the dropout voltage (V_OUT(NOM)+ V_DO), the output voltage can overshoot for a short

time when the device pulls the pass transistor back into the linear region.

7.4.3 Disable Mode

The output of the device can be shutdown by forcing the voltage of the enable pin to less than V_IL(EN) (see the

Electrical Characteristics table). When disabled, the pass transistor is turned off, internal circuits are shutdown,

and the output voltage is actively discharged to ground by an internal discharge circuit from the output to ground.

Submit Document Feedback

Product Folder Links: TPS7A14

TPS7A14

www.ti.com.cn

ZHCSPG4B –DECEMBER 2021 –REVISED MAY 2022

8 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

8.1 Application Information

Successfully implementing an LDO in a system depends on the system requirements. This section discusses

key device features and how to best implement them to achieve a reliable design.

8.1.1 Recommended Capacitor Types

The regulator is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the

input, output, and bias pins. Multilayer ceramic capacitors are the industry standard for use with LDOs, but must

be used with good judgment. Ceramic capacitors that use X7R-, X5R-, and COG-rated dielectric materials

provide relatively good capacitive stability across temperature, whereas the use of Y5V-rated capacitors is

discouraged because of large variations in capacitance. Regardless of the ceramic capacitor type selected,

ceramic capacitance varies with operating voltage and temperature. Generally, assume that effective

capacitance decreases by as much as 50%. The input, output, and bias capacitors recommended in the

Recommended Operating Conditions table account for an effective capacitance of approximately 50% of the

nominal value.

8.1.2 Input, Output, and Bias Capacitor Requirements

A minimum input ceramic capacitor is required for stability. A minimum output ceramic capacitor is also required

for stability, see the Recommended Operating Conditions table for the minimum capacitors values.

The input capacitor counteracts reactive input sources and improves transient response, input ripple, and PSRR.

A higher-value input capacitor may be necessary if large, fast rise-time load or line transients are anticipated, or

if the device is located several inches from the input power source. Dynamic performance of the device is

improved with the use of an output capacitor larger than the minimum value specified in the Recommended

Operating Conditions table.

Although a bias capacitor is not required, good design practice is to connect a 0.1-µF ceramic capacitor from

BIAS to GND. This capacitor counteracts reactive bias source if the source impedance is not sufficiently low.

Place the input, output, and bias capacitors as close as possible to the device to minimize trace parasitics.

If the BIAS source is susceptible to fast voltage drops (for example, a 2-V drop in less than 1 µs) when the LDO

load current is near the maximum value, the BIAS voltage drop can cause the output voltage to fall briefly. In

such cases, use a BIAS capacitor large enough to slow the voltage ramp rate to less than 0.5 V/µs. For smaller

or slower BIAS transients, any output voltage dips must be less than 5% of the nominal voltage.

8.1.3 Dropout Voltage

Dropout voltage (V_DO) is defined as the input voltage minus the output voltage (V_IN– V_OUT) at the rated output

current (I_RATED), where the pass transistor is fully on. I_RATEDis the maximum I_OUTlisted in the Recommended

Operating Conditions table. The pass transistor is in the ohmic or triode region of operation, and acts as a

switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed

output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than

the nominal output regulation, then the output voltage falls as well.

For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (R_DS(ON)) of the

pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for

that current scales accordingly. Use 方程式1 to calculate the R_DS(ON)of the device.

V_DO

R_DS(ON)

I_RATED

(1)

Submit Document Feedback

Product Folder Links: TPS7A14

TPS7A14

www.ti.com.cn

ZHCSPG4B –DECEMBER 2021 –REVISED MAY 2022

The use of bias rail enables the TPS7A14 to achieve a lower dropout voltage between IN and OUT. However, a

minimum bias voltage above the nominal programmed output voltage must be maintained. 图 6-13 specifies the

minimum V_BIASheadroom required to maintain output regulation.

8.1.4 Behavior During Transition From Dropout Into Regulation

Some applications may have transients that place this device into dropout, especially when this device can be

powered from a battery with relatively high ESR. The load transient saturates the output stage of the error

amplifier when the pass element is driven fully on, making the pass element function like a resistor from V_INto

V_OUT. The error amplifier response time to this load transient is extended because the error amplifier must first

recover from saturation and then must place the pass element back into active mode. During this recovery

period, V_OUTovershoots because the pass element is functioning as a resistor from V_INto V_OUT

When V_INramps up slowly for start up, the slow ramp-up voltage may place the device in dropout. As with many

other LDOs, the output can overshoot on recovery from this condition. However, this condition is easily avoided

through the use of the enable signal.

If operating under these conditions, apply a higher dc load current or increase the output capacitance to reduce

the overshoot. These approaches provide a path to absorb the excess charge.

8.1.5 Device Enable Sequencing Requirement

The IN, BIAS, and EN pin voltages can be sequenced in any order without causing damage to the device. Start

up is always monotonic regardless of the sequencing order or the ramp rates of the IN, BIAS, and EN pins. See

the Recommended Operating Conditions table for proper voltage ranges of the IN, BIAS, and EN pins.

8.1.6 Load Transient Response

The load-step transient response is the output voltage response by the LDO to a step in load current while

output voltage regulation is maintained. See 图 6-21 and 图 6-22 for typical load transient response plots. There

are two key transitions during a load transient response: the transition from a light to a heavy load, and the

transition from a heavy to a light load. The regions in 图 8-1 are broken down as described in this section.

Regions A, E, and H are where the output voltage is in steady-state operation.

tAt

tCt

tDt

tEt

tGt

tHt

图8-1. Load Transient Waveform

During transitions from a light load to a heavy load, the following behavior can be observed:

• The initial voltage dip is a result of the depletion of the output capacitor charge and parasitic impedance to

the output capacitor (region B)

• Recovery from the dip results from the LDO increasing its sourcing current, and leads to output voltage

regulation (region C)

During transitions from a heavy load to a light load, the following behavior can be observed:

• The initial voltage rise results from the LDO sourcing a large current, and leads to an increase in the output

capacitor charge (region F)

• Recovery from the rise results from the LDO decreasing its sourcing current in combination with the load

discharging the output capacitor (region G)

A larger output capacitance reduces the peaks during a load transient but slows down the response time of the

device. A larger dc load also reduces the peaks because the amplitude of the transition is lowered and a higher

current discharge path is provided for the output capacitor.

Submit Document Feedback

Product Folder Links: TPS7A14

TPS7A14

www.ti.com.cn

ZHCSPG4B –DECEMBER 2021 –REVISED MAY 2022

8.1.7 Undervoltage Lockout Circuit Operation

The V_INUVLO circuit ensures that the regulator remains disabled when the input supply voltage is below the

minimum operational voltage range, and ensures that the regulator shuts down when the input supply collapses.

Similarly, the V_BIASUVLO circuit ensures that the regulator remains disabled when the bias supply voltage is

less than the minimum operational voltage range, and ensures that the regulator shuts down when the bias

supply collapses.

图 8-2 shows the UVLO circuit response to various input or bias voltage events. The diagram can be separated

into the following parts:

• Region A: The output remains off while the input or bias voltage is below the UVLO rising threshold

• Region B: Normal operation, regulating device

• Region C: Brownout event above the UVLO falling threshold (UVLO rising threshold –UVLO hysteresis).

The output may fall out of regulation but the device remains enabled.

• Region D: Normal operation, regulating device

• Region E: Brownout event below the UVLO falling threshold. The device is disabled in most cases and the

output falls as a result of the load and active discharge circuit. The device is re-enabled when the UVLO

rising threshold is reached and a normal start up follows.

• Region F: Normal operation followed by the input or bias falling to the UVLO falling threshold

• Region G: The device is disabled when the input or bias voltages fall below the UVLO falling threshold to 0 V.

The output falls as a result of the load and active discharge circuit.

UVLO Rising Threshold

UVLO Hysteresis

V_IN/ V_BIAS

V_OUT

tAt

tBt

tDt

tEt

tFt

tGt

图8-2. Typical V_INor V_BIASUVLO Circuit Operation

8.1.8 Power Dissipation (P_D)

Circuit reliability demands that proper consideration be given to device power dissipation, location of the circuit

on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator

must be as free as possible of other heat-generating devices that cause added thermal stresses.

方程式2 calculates the maximum allowable power dissipation for the device in a given package:

P_D-MAX= [(T_J–T_A) / R_θJA

]

(2)

(3)

(4)

方程式3 represents the actual power being dissipated in the device:

P_D= ((I_GND(IN)+ I_IN) × V_IN+ I_GND(BIAS)× V_BIAS) –(I_OUT× V_OUT

)

If the load current is much greater than I_GND(IN)and I_GND(BIAS)方程式3 can be simplified as:

P_D= (V_IN–V_OUT) × I_OUT

Power dissipation can be minimized, and thus greater efficiency achieved, by proper selection of the system

voltage rails. Proper selection allows the minimum input-to-output voltage differential to be obtained. The low

dropout of the TPS7A14 allows for maximum efficiency across a wide range of output voltages.

Submit Document Feedback

Product Folder Links: TPS7A14

TPS7A14

www.ti.com.cn

ZHCSPG4B –DECEMBER 2021 –REVISED MAY 2022

The main heat conduction path depends on the ambient temperature and the thermal resistance across the

various interfaces between the die junction and ambient air.

The maximum allowable junction temperature (T_J) determines the maximum power dissipation for the device.

According to 方程式 5, maximum power dissipation and junction temperature are most often related by the

junction-to-ambient thermal resistance (R_θJA) of the combined PCB and device package and the temperature of

the ambient air (T_A). The equation is rearranged in 方程式6 for output current.

T_J= T_A+ (R_θJA× P_D)

(5)

(6)

I_OUT= (T_J–T_A) / [R_θJA× (V_IN–V_OUT)]

Unfortunately, this thermal resistance (R_θJA) is highly dependent on the heat-spreading capability built into the

particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the

planes. The R_θJArecorded in the Electrical Characteristics table is determined by the JEDEC standard, PCB,

and copper-spreading area, and is only used as a relative measure of package thermal performance. For a well-

designed thermal layout, R_θJAis actually the sum of the YBK package junction-to-case (bottom) thermal

resistance (R_θJC(bot)) plus the thermal resistance contribution by the PCB copper.

8.1.9 Estimating Junction Temperature

The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures

of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal

resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics

are determined to be significantly independent of the copper-spreading area. The key thermal metrics (Ψ_JTand

Ψ_JB) are used in accordance with 方程式7 and are given in the Electrical Characteristics table.

Ψ_JT: T_J= T_T+ Ψ_JT× P_Dand Ψ_JB: T_J= T_B+ Ψ_JB× P_D

(7)

where:

• P_Dis the power dissipated as explained in 方程式3 and the Power Dissipation (P_D) section

• T_Tis the temperature at the center-top of the device package

• T_Bis the PCB surface temperature measured 1 mm from the device package and centered on the package

edge

8.1.10 Recommended Area for Continuous Operation

The operational area of an LDO is limited by the dropout voltage, output current, junction temperature, and input

voltage. The recommended area for continuous operation for a linear regulator is provided in 图 8-3 and can be

separated into the following regions:

• Dropout voltage limits the minimum differential voltage between the input and the output (V_IN–V_OUT) at a

given output current level; see the Dropout Operation section for more details.

• The rated output current limits the maximum recommended output current level. Exceeding this rating causes

the device to fall out of specification.

• The rated junction temperature limits the maximum junction temperature of the device. Exceeding this rating

causes the device to fall out of specification and reduces long-term reliability.

– 方程式6 provides the shape of the slope. The slope is nonlinear because the maximum rated junction

temperature of the LDO is controlled by the power dissipation across the LDO, thus when V_IN–V_OUT

increases the output current must decrease.

• The rated input voltage range governs both the minimum and maximum of V_IN–V_OUT

Submit Document Feedback

Product Folder Links: TPS7A14

TPS7A14

www.ti.com.cn

ZHCSPG4B –DECEMBER 2021 –REVISED MAY 2022

Output Current Limited

by Dropout

Rated Output

Current

Output Current Limited

by Thermals

Limited by

Minimum V_IN

Limited by

Maximum V_IN

V_INœ V_OUT(V)

图8-3. Continuous Operation Diagram With Description of Regions

8.2 Typical Application

C_BIAS

BIAS

TPS7A14

SENSE

V_OUT

OUT

C_IN

C_OUT

DC/DC Converter

Or PMU

GND

图8-4. High-Efficiency Supply From a Rechargeable Battery

8.2.1 Design Requirements

表8-1 lists the parameters for this design example.

表8-1. Design Parameters

DESIGN PARAMETER

EXAMPLE VALUE

V_IN

0.95 V

V_BIAS

V_OUT

I_OUT

2.4 V to 5.5 V

0.8 V

600 mA (typical), 900 mA (peak)

8.2.2 Detailed Design Procedure

This design example is powered by a rechargeable battery that can be a building block in many portable

applications. Noise-sensitive portable electronics require an efficient, small-size solution for their power supply.

Traditional LDOs are known for their low efficiency in contrast to low-input, low-output voltage (LILO) LDOs such

as the TPS7A14. The use of a bias rail in the TPS7A14 allows the main power path of the LDO to operate at a

lower input voltage, thus reducing the voltage drop across the pass transistor and maximizing device efficiency.

Because the voltage drop across the pass transistor can be so low, the efficiency of the TPS7A14 can

approximate that of a dc-dc converter. 方程式8 calculates the efficiency for this design.

Efficiency = η= P_OUT/ P_IN× 100 % = (V_OUT× I_OUT) / (V_IN× I_IN+ V_BIAS× I_BIAS) × 100 %

(8)

方程式 8 reduces to 方程式 9 because the design example load current is much greater than the quiescent

current of the bias rail.

Submit Document Feedback

Product Folder Links: TPS7A14

TPS7A14

www.ti.com.cn

ZHCSPG4B –DECEMBER 2021 –REVISED MAY 2022

Efficiency = η= (V_OUT× I_OUT) / (V_IN× I_IN) × 100%

(9)

Submit Document Feedback

Product Folder Links: TPS7A14

TPS7A14

www.ti.com.cn

ZHCSPG4B –DECEMBER 2021 –REVISED MAY 2022

8.2.3 Application Curve

V_BIAS= V_OUT(NOM)+ 1.4 V, V_EN= V_IN, C_IN= 2.2 µF, C_OUT= 2.2 µF, and C_BIAS= 0.47 µF

图8-5. V_INDropout Voltage vs I_OUT

9 Power Supply Recommendations

This device is designed to operate from an input supply voltage range of 0.6 V to 2.2 V and a bias supply voltage

range of 1.5 V to 5.5 V. The input and bias supplies must be well regulated and free of spurious noise. To make

sure that the output voltage is well regulated and dynamic performance is optimum, the input supply must be at

least V_OUT(nom)+ V_DOand V_BIAS= V_OUT(nom)+ V_DO(BIAS)

10 Layout

10.1 Layout Guidelines

For correct printed circuit board (PCB) layout, follow these guidelines:

• Place input, output, and bias capacitors as close to the device as possible

• Use copper planes for device connections to optimize thermal performance

• Place thermal vias around the device to distribute heat

Submit Document Feedback

Product Folder Links: TPS7A14

TPS7A14

www.ti.com.cn

ZHCSPG4B –DECEMBER 2021 –REVISED MAY 2022

10.2 Layout Example

图10-1. Recommended Layout

Submit Document Feedback

Product Folder Links: TPS7A14

TPS7A14

www.ti.com.cn

ZHCSPG4B –DECEMBER 2021 –REVISED MAY 2022

11 Device and Documentation Support

11.1 Device Support

11.1.1 Development Support

11.1.1.1 Evaluation Module

An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the

TPS7A14. The EVM can be requested at the Texas Instruments web site through the product folders or

purchased directly from the TI eStore

11.1.2 Device Nomenclature

表11-1. Device Nomenclature^{(1) (2)}

PRODUCT

DESCRIPTION

xx(x) is the nominal output voltage. Two or more digits are used in the ordering number (for example, 09

= 0.9 V, 95 = 0.95 V, 125 = 1.25 V).

TPS7A14xx(x)(P)yyyz

P indicates active pull down; if there is no P, then the device does not have the active pull down feature.

yyy is the package designator.

z is the package quantity. R is for reel (12000 pieces), T is for tape (250 pieces).

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the

device product folder on www.ti.com.

(2) Output voltages from 0.5 V to 2.05 V in 25-mV increments are available. Contact the factory for details and availability.

11.2 Documentation Support

11.2.1 Related Documentation

For related documentation see the following:

• Texas Instruments, Using New Thermal Metrics application report

• Texas Instruments, AN-1112 DSBGA Wafer Level Chip Scale Package application report

• Texas Instruments, TPS7A14EVM-058 Evaluation Module user guide

11.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

11.5 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

11.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

11.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

Submit Document Feedback

Product Folder Links: TPS7A14

TPS7A14

www.ti.com.cn

ZHCSPG4B –DECEMBER 2021 –REVISED MAY 2022

Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Submit Document Feedback

Product Folder Links: TPS7A14

PACKAGE OPTION ADDENDUM

www.ti.com

1-Jul-2022

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS7A1408PYBKR

TPS7A1409PYBKR

TPS7A1412PYBKR

TPS7A1413PYBKR

TPS7A1485PYBKR

ACTIVE

DSBGA

YBK

12000 RoHS & Green

SNAGCU

Level-1-260C-UNLIM

-40 to 125

Samples

SNAGCU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

1-Jul-2022

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

23-Jun-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS7A1408PYBKR

TPS7A1409PYBKR

TPS7A1412PYBKR

TPS7A1413PYBKR

TPS7A1485PYBKR

DSBGA

YBK

12000

180.0

8.4

0.8

1.26

0.36

2.0

8.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

23-Jun-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS7A1408PYBKR

TPS7A1409PYBKR

TPS7A1412PYBKR

TPS7A1413PYBKR

TPS7A1485PYBKR

DSBGA

YBK

12000

182.0

20.0

Pack Materials-Page 2

PACKAGE OUTLINE

YBK0006

DSBGA - 0.33 mm max height

SCALE 12.000

DIE SIZE BALL GRID ARRAY

BALL A1

CORNER

0.33 MAX

SEATING PLANE

0.05 C

0.115

0.065

0.4 TYP

SYMM

0.8 TYP

D: Max = 1.15 mm, Min = 1.09 mm

E: Max = 0.7 mm, Min = 0.64 mm

0.4 TYP

0.22

0.015

0.18

0.2 TYP

C A B

4226139/A 08/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

YBK0006

DSBGA - 0.33 mm max height

DIE SIZE BALL GRID ARRAY

(0.2) TYP

6X ( 0.2)

(0.4) TYP

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 50X

0.0375 MIN

0.0375 MAX

METAL UNDER

SOLDER MASK

(

0.2)

METAL

EXPOSED

METAL

(

0.2)

SOLDER MASK

OPENING

EXPOSED

METAL

SOLDER MASK

OPENING

SOLDER MASK

DEFINED

(PREFERRED)

NON-SOLDER MASK

DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4226139/A 08/2020

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).

www.ti.com

EXAMPLE STENCIL DESIGN

YBK0006

DSBGA - 0.33 mm max height

DIE SIZE BALL GRID ARRAY

(0.2) TYP

6X ( 0.21)

(R0.05) TYP

(0.4) TYP

SYMM

METAL

TYP

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.075 mm THICK STENCIL

SCALE: 50X

4226139/A 08/2020

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TPS7A1413PYBKR [TI]

相关型号：

TPS7A1485PYBKR

TPS7A15

TPS7A1508PYCKR

TPS7A1509PYCKR

TPS7A16

TPS7A16-Q1

TPS7A1601

TPS7A1601-Q1

TPS7A1601-Q1_15

TPS7A1601ADGNR

TPS7A1601AQDGNRQ1

TPS7A1601DGN