TPS7A1650AQDGNRQ1 [TI]
脱离电池 (60V) 运行、具有电源正常指示功能的汽车类 100mA、超低 IQ、低压降稳压器 | DGN | 8 | -40 to 125;
| 型号： | TPS7A1650AQDGNRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 脱离电池 (60V) 运行、具有电源正常指示功能的汽车类 100mA、超低 IQ、低压降稳压器 | DGN | 8 | -40 to 125 电池 稳压器 |
| 文件： | 总28页 (文件大小：1956K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS7A16A-Q1
ZHCSJD1A –FEBRUARY 2019–REVISED MARCH 2019
具有使能端和电源正常指示功能的
TPS7A16A-Q1 60V、5µA IQ、100mA、低压降稳压器
1 特性
3 说明
1
•
•
适用于汽车 应用
下列性能符合 AEC-Q100 标准：
TPS7A16A-Q1 超低功耗、低压降 (LDO) 稳压器具有
超低静态电流、高输入电压以及微型高热性能封装等诸
多优势。
–
器件温度 1 级：–40°C 至 125°C 的环境工作温
度范围
TPS7A16A-Q1 专为连续或断续（备用电源）电池供电
的 应用 而设计，超低静态电流在此类应用中对于延长
系统电池寿命至关重要。
–
–
器件 HBM ESD 分类等级 2
器件 CDM ESD 分类等级 C3B
•
•
•
•
•
•
•
宽输入电压范围：3V 至 60V
超低静态电流：5 µA
停机时静态电流：1µA
输出电流：100 mA
TPS7A16A-Q1 提供了一个与标准互补金属氧化物半导
体 (CMOS) 逻辑兼容的使能引脚 (EN) 以及一个具有用
户可编程延迟的集成开漏高电平有效电源正常输出
(PG)。这些引脚专用于需要进行电源轨排序、 基于 微
控制器的电池供电类应用。
低压差电压：电流为 20mA 时电压为 60mV
精度：2%
可提供：
此外，TPS7A16A-Q1 非常适合通过多节电池解决方案
生成低电压电源（从高电池节数电动工具组到汽车 应
用；TPS7A16A-Q1 器件不但能够提供一个稳压良好的
电压轨，还能够承受瞬态电压并在电压瞬态期间保持稳
压状态。这些 特性 意味着电涌保护电路更加简单且更
为经济高效。
–
–
固定输出电压：3.3V、5V
可调节输出电压：大约 1.2 至 18.5V
•
•
•
具有可编程延迟的电源正常指示功能
电流限制和热关断保护
与陶瓷输出电容器一起工作时保持稳定：
≥ 2.2µF
器件信息(1)
•
封装：高热性能 HVSSOP-8 PowerPAD™
器件型号
封装
HVSSOP (8)
封装尺寸（标称值）
TPS7A16A-Q1
3.00mm × 3.00mm
2 应用
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
•
•
•
•
紧急呼叫 (eCall)
电池管理系统 (BMS)
典型应用原理图
车载充电器 (OBC) 和无线充电器
直流/直流转换器
VIN
60 V
12 V
t
VOUT
VIN
OUT
VCC
mC2
IN
CIN
COUT
EN
RPG
TPS7A16A-Q1
VEN
EN
DELAY
PG
IO1
GND
VPG
CDELAY
IO3
mC1
IO2
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBVS342
TPS7A16A-Q1
ZHCSJD1A –FEBRUARY 2019–REVISED MARCH 2019
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 10
Application and Implementation ........................ 10
8.1 Application Information............................................ 10
8.2 Typical Applications ................................................ 11
Power Supply Recommendations...................... 15
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 6
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
7.3 Feature Description .................................................. 9
8
9
10 Layout................................................................... 15
10.1 Layout Guidelines ................................................. 15
10.2 Layout Examples................................................... 16
11 器件和文档支持 ..................................................... 18
11.1 接收文档更新通知 ................................................. 18
11.2 社区资源................................................................ 18
11.3 商标....................................................................... 18
11.4 静电放电警告......................................................... 18
11.5 术语表 ................................................................... 18
12 机械、封装和可订购信息....................................... 18
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (February 2019) to Revision A
Page
•
已更改 将状态从“预告信息”更改为“生产数据” ......................................................................................................................... 1
2
Copyright © 2019, Texas Instruments Incorporated
TPS7A16A-Q1
www.ti.com.cn
ZHCSJD1A –FEBRUARY 2019–REVISED MARCH 2019
5 Pin Configuration and Functions
DGN Package
8-Pin HVSSOP With Exposed Thermal Pad
Top View
OUT
FB/DNC
PG
1
2
3
4
8
7
6
5
IN
DELAY
NC
Thermal pad
GND
EN
Not to scale
NC – No internal connection
Pin Functions
PIN
NAME
I/O
DESCRIPTION
NO.
Delay pin. Connect a capacitor to GND to adjust the PG delay time; leave open if the reset function is not
needed.
DELAY
7
O
I
Enable pin. This pin turns the regulator on or off.
If VEN ≥ VEN_HI, the regulator is enabled.
If VEN ≤ VEN_LO, the regulator is disabled.
EN
5
If not used, the EN pin can be connected to IN. Make sure that VEN ≤ VIN at all times.
For the adjustable version, the feedback pin is the input to the control-loop error amplifier. This pin is used to
set the output voltage of the device when the regulator output voltage is set by external resistors.
For the fixed-voltage versions, do not connect to this pin. Do not route this pin to any electrical net, not even
to GND or IN.
FB/DNC
GND
IN
2
4
8
I
—
I
Ground pin
Regulator input supply pin. A capacitor > 0.1 µF must be tied from this pin to ground to assure stability. TI
recommends connecting a 10-µF ceramic capacitor from IN to GND (as close to the device as possible) to
reduce circuit sensitivity to printed-circuit-board (PCB) layout, especially when long input tracer or high source
impedances are encountered.
NC
6
1
---
O
This pin can be left open or tied to any voltage between GND and IN.
Regulator output pin. A capacitor > 2.2 µF must be tied from this pin to ground to assure stability. TI
recommends connecting a 10-µF ceramic capacitor from OUT to GND (as close to the device as possible) to
maximize ac performance.
OUT
Power-good pin. Open-collector output; leave open or connect to GND if the power-good function is not
needed.
PG
3
O
Thermal
pad
Solder to the printed circuit board (PCB) to enhance thermal performance. Although the thermal pad can be left
floating, TI highly recommends connecting the thermal pad to the GND plane.
Pad
---
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3
TPS7A16A-Q1
ZHCSJD1A –FEBRUARY 2019–REVISED MARCH 2019
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted)(1)
MIN
–0.3
MAX
UNIT
IN pin to GND pin
OUT pin to GND pin
OUT pin to IN pin
FB pin to GND pin
62
20
–0.3
–62
0.3
3
–0.3
Voltage
FB pin to IN pin
–62
0.3
0.3
62
V
EN pin to IN pin
–62
EN pin to GND pin
–0.3
PG pin to GND pin
–0.3
5.5
5.5
DELAY pin to GND pin
Peak output
Operating virtual junction, TJ, absolute maximum(2)
–0.3
Current
Internally limited
–40
150
150
Temperature
°C
Storage, TSTG
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Permanent damage does not occur to the part operating within this range, though electrical performance is not guaranteed outside the
operating ambient temperature range.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
Corner pins (OUT, GND, IN,
and EN)
V(ESD)
Electrostatic discharge
±750
±500
V
Charged-device model (CDM), per JEDEC
specification JESD22-C101(2)
Other pins
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
3
NOM
MAX
60
UNIT
V
VIN
Input voltage
VOUT
Output voltage
1.2
0
18.5
VIN
1.5
5
V
EN pin voltage
V
EN
EN pin slew-rate, voltage ramp-up
Delay pin voltage
V/µs
V
DELAY
PG
0
0
Power-good pin voltage
5
V
6.4 Thermal Information
TPS7A16A-Q1
THERMAL METRIC(1)
DGN (HVSSOP)
UNIT
8 PINS
52.5
72.2
24.1
2.3
RθJA
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
ψJB
24.0
10.1
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2019, Texas Instruments Incorporated
TPS7A16A-Q1
www.ti.com.cn
ZHCSJD1A –FEBRUARY 2019–REVISED MARCH 2019
6.5 Electrical Characteristics
at TA= –40°C to +125°C, VIN = VOUT(NOM) + 500 mV or VIN = 3 V (whichever is greater), VEN = VIN, IOUT = 10 µA, CIN = 2.2 μF,
COUT = 2.2 μF, and FB tied to OUT (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA = 25°C, VFB = VREF, VIN = 3 V, IOUT = 10 μA
VIN ≥ VOUT(NOM) + 0.5 V
MIN
TYP
MAX
UNIT
VIN
Input voltage range
3
60
V
V
V
V
VREF
VUVLO
VOUT
Internal reference
1.169
1.193
2
1.217
Undervoltage lockout threshold
Output voltage range
VREF
–2%
18.5
2%
VOUT(NOM) + 0.5 V ≤ VIN ≤ 60 V(1)
10 µA ≤ IOUT ≤ 100 mA
,
Overall VOUT accuracy
ΔVO(ΔVI)
ΔVO(ΔIO)
Line regulation
Load regulation
3 V ≤ VIN ≤ 60 V
±1
±1
%VOUT
%VOUT
10 µA ≤ IOUT ≤ 100 mA
VIN = 0.95xVOUT(NOM), IOUT = 20 mA
VIN = 0.95xVOUT(NOM), IOUT = 100 mA
VOUT = 90% VOUT(NOM), VIN = VOUT(NOM) + 1 V(2)
VOUT = 90% VOUT(NOM), VIN = 3 V(3)
3 V ≤ VIN ≤ 60 V, IOUT = 10 µA
60
VDO
Dropout voltage
Current limit
mV
mA
μA
265
225
225
5
500
400
400
15
101
101
ILIM
IGND
Ground current
IOUT = 100 mA, VOUT = 1.2 V
60
ISHDN
I FB
Shutdown supply current
Feedback current(4)
VEN = 0.4 V, VIN = 12 V
0.59
0.0
0.01
5.0
1
μA
µA
μA
V
–1
–1
IEN
Enable current
3 V ≤ VIN ≤ 12 V, VIN = VEN
1
VEN_HI
VEN_LO
Enable high-level voltage
Enable low-level voltage
1.2
0.3
95
93
V
OUT pin floating, VFB increasing, VIN ≥ VIN_MIN
OUT pin floating, VFB decreasing, VIN ≥ VIN_MIN
85
83
VIT
PG trip threshold
%VOUT
VHYS
PG trip hysteresis
PG output low voltage
PG leakage current
DELAY pin current
2.3
%VOUT
V
VPG, LO
IPG, LKG
IDELAY
OUT pin floating, VFB = 80% VREF, IPG = 100 µA
VPG = VOUT(NOM)
0.4
1
–1
μA
1
2
μA
VIN = 3 V, VOUT(NOM) = VREF, COUT = 10 μF,
f = 100 Hz
PSRR
TSD
Power-supply rejection ratio
50
dB
°C
Shutdown, temperature increasing
Reset, temperature decreasing
175
155
Thermal shutdown temperature
(1) Maximum input voltage is limited to 24 V because of the package power dissipation limitations at full load (P ≈ (VIN – VOUT) × IOUT
=
(24 V – VREF) × 50 mA ≈ 1.14 W). The device is capable of sourcing a maximum current of 50 mA at higher input voltages as long as
the power dissipated is within the thermal limits of the package plus any external heatsinking.
(2) For fixed output voltages only.
(3) For adjustable output only, where VOUT = 1.2 V
(4) IFB > 0 µA flows out of the device.
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5
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ZHCSJD1A –FEBRUARY 2019–REVISED MARCH 2019
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6.6 Typical Characteristics
at TA = –40°C to 125°C, VIN = VOUT(NOM) + 0.5 V or VIN = 3 V (whichever is greater), VEN = VIN, IOUT = 10 µA, CIN = 1 µF, COUT
= 2.2 µF, and FB tied to OUT (unless otherwise noted)
10
9
8
7
6
5
4
3
2
1
0
50
40
30
20
10
0
VEN = 0.4 V
IOUT = 0mA
− 40°C
+ 25°C
+ 85°C
+ 105°C
+ 125°C
− 40°C
+ 25°C
+ 85°C
+ 105°C
+ 125°C
0
0
0
10
20
30
40
50
60
0
10
20
30
40
50
60
Input Voltage (V)
Input Voltage (V)
图 2. Shutdown Current vs Input Voltage
图 1. Quiescent Current vs Input Voltage
1000
100
90
80
70
60
50
40
30
20
10
0
− 40°C
+ 25°C
+ 85°C
+ 105°C
+ 125°C
− 40°C
+ 25°C
+ 85°C
+ 105°C
+ 125°C
900
800
700
600
500
400
300
200
100
0
10
20
30
40
50
60
70
80
90 100
0
20
40
60
80
100
Output Current (mA)
Output Current (mA)
图 3. Quiescent Current vs Output Current
图 4. Dropout Voltage vs Output Current
1.294
1.244
1.194
1.144
1.094
10
− 40°C
+ 25°C
+ 85°C
+ 105°C
+ 125°C
− 40°C
+ 25°C
+ 85°C
+ 105°C
+ 125°C
7.5
5
2.5
0
−2.5
−5
−7.5
−10
10
20
30
Input Voltage (V)
40
50
60
0
10
20
30
Input Voltage (V)
40
50
60
图 5. Feedback Voltage vs Input Voltage
图 6. Line Regulation
6
版权 © 2019, Texas Instruments Incorporated
TPS7A16A-Q1
www.ti.com.cn
ZHCSJD1A –FEBRUARY 2019–REVISED MARCH 2019
Typical Characteristics (接下页)
at TA = –40°C to 125°C, VIN = VOUT(NOM) + 0.5 V or VIN = 3 V (whichever is greater), VEN = VIN, IOUT = 10 µA, CIN = 1 µF, COUT
= 2.2 µF, and FB tied to OUT (unless otherwise noted)
10
7.5
5
300
250
200
150
100
50
− 40°C
+ 25°C
+ 85°C
+ 105°C
+ 125°C
2.5
0
−2.5
−5
− 40°C
+ 25°C
+ 85°C
+ 105°C
+ 125°C
−7.5
−10
0
0
10
20
30
40
50
60
70
80
90 100
0
2
4
6
8
10
12
Output Current (mA)
Input Voltage (V)
图 7. Load Regulation
图 8. Current Limit vs Input Voltage
95
93
91
89
87
85
2.5
2
PG Rising
1.5
1
OFF−TO−ON
ON−TO−OFF
0.5
PG Falling
0
−40 −25 −10
5
20 35 50 65 80 95 110 125
Temperature (°C)
−40 −25 −10
5
20 35 50 65 80 95 110 125
Temperature (°C)
图 9. Power-Good Threshold Voltage vs Temperature
图 10. Enable Threshold Voltage vs Temperature
100
10
1
90
80
70
60
50
40
30
20
10
0
0.1
0.01
0.001
VIN = 3V
VOUT = ~1.2V
COUT = 10µF
VIN = 3V
VOUT = 1.2V
COUT = 2.2µF
10
100
1k
10k
100k
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
图 11. Power-Supply Rejection Ratio vs Frequency
图 12. Output Spectral Noise Density
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ZHCSJD1A –FEBRUARY 2019–REVISED MARCH 2019
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Typical Characteristics (接下页)
at TA = –40°C to 125°C, VIN = VOUT(NOM) + 0.5 V or VIN = 3 V (whichever is greater), VEN = VIN, IOUT = 10 µA, CIN = 1 µF, COUT
= 2.2 µF, and FB tied to OUT (unless otherwise noted)
VIN (2 V/div)
VPG (2 V/div)
VIN = 1 V ® 6.5 V
IOUT = 1 mA
VOUT (1 V/div)
COUT = 10 mF
CFF = 0 nF
Time (5 ms/div)
图 13. Power-Good Delay
8
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TPS7A16A-Q1
www.ti.com.cn
ZHCSJD1A –FEBRUARY 2019–REVISED MARCH 2019
7 Detailed Description
7.1 Overview
The TPS7A16A-Q1 is an ultra-low-power, low-dropout (LDO) voltage regulator that offers the benefits of ultra-low
quiescent current, high input voltage, and miniaturized, high thermal-performance packaging. The TPS7A16A-Q1
also offers an enable pin (EN) and an integrated open-drain, active-high, power-good output (PG) with a user-
programmable delay.
7.2 Functional Block Diagram
IN
OUT
UVLO
Pass
Device
Thermal
Shutdown
Current
Limit
Error
Amp
Enable
FB
EN
PG
Power
Good
Control
DELAY
7.3 Feature Description
7.3.1 Enable (EN)
The enable pin is a high-voltage-tolerant pin. A high input on EN actives the device and turns on the regulator.
For self-bias applications, connect this input to the IN pin. Ensure that VEN ≤ VIN at all times.
When the enable signal is comprised of pulse-width modulation (PWM) pulses, the slew rate of the rising and
falling edges must be less than 1.5 V/µs. Adding a 0.1-µF capacitor from the EN pin to GND is recommended.
7.3.2 Regulated Output (VOUT
)
The OUT pin is the regulated output based on the required voltage. The output has current limitation. During
initial power up, the regulator has a soft-start incorporated to control the initial current through the pass element.
In the event that the regulator drops out of regulation, the output tracks the input minus a drop based on the load
current. When the input voltage drops below the undervoltage lockout (UVLO) threshold, the regulator shuts
down until the input voltage recovers above the minimum start-up level.
7.3.3 PG Delay Timer (DELAY)
The power-good delay time (tDELAY) is defined as the time period from when VOUT exceeds the PG trip threshold
voltage (VIT) to when the PG output is high. This power-good delay time is set by an external capacitor (CDELAY
)
connected from the DELAY pin to GND; this capacitor is charged from 0 V to approximately 1.8 V by the DELAY
pin current (IDELAY) when VOUT exceeds the PG trip threshold (VIT).
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7.4 Device Functional Modes
7.4.1 Power-Good
The power-good (PG) pin is an open-drain output and can be connected to any 5.5-V or lower rail through an
external pullup resistor. When no CDELAY is used, the PG output is high-impedance when VOUT is greater than the
PG trip threshold (VIT). If VOUT drops below VIT, the open-drain output turns on and pulls the PG output low. If
output voltage monitoring is not needed, the PG pin can be left floating or connected to GND.
To ensure proper operation of the power-good feature, maintain VIN ≥ 3 V (VIN_MIN).
7.4.1.1 Power-Good Delay and Delay Capacitor
The power-good delay time (tDELAY) is defined as the time period from when VOUT exceeds the PG trip threshold
voltage (VIT) to when the PG output is high. This power-good delay time is set by an external capacitor (CDELAY
)
connected from the DELAY pin to GND; this capacitor is charged from 0 V to ap 1.8 V by the DELAY pin current
(IDELAY) once VOUT exceeds the PG trip threshold (VIT).
When CDELAY is used, the PG output is high-impedance when VOUT exceeds VIT, and VDELAY exceeds VREF
.
The power-good delay time can be calculated using: tDELAY = (CDELAY × VREF)/IDELAY. For example, when CDELAY
= 10 nF, the PG delay time is approximately 12 ms; that is, (10 nF × 1.193 V) / 1 µA = 11.93 ms.
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS7A16A-Q1 offers the benefit of ultra-low quiescent current, high input voltage, and miniaturized, high-
thermal-performance packaging.
The TPS7A16A-Q1 is designed for continuous or sporadic (power backup) battery-operated applications where
ultra-low quiescent current is critical to extending system battery life.
10
版权 © 2019, Texas Instruments Incorporated
TPS7A16A-Q1
www.ti.com.cn
ZHCSJD1A –FEBRUARY 2019–REVISED MARCH 2019
8.2 Typical Applications
8.2.1 TPS7A16A-Q1 Circuit as an Adjustable Regulator
VIN
VOUT
OUT
IN
COUT
CIN
R1
CFF
VOUT
TPS7A16A-Q1
Where: R1 = R2
- 1
RPG
VEN
EN
FB
VREF
R2
VPG
DELAY
PG
GND
CDELAY
图 14. The TPS7A16A-Q1 Circuit as an Adjustable Regulator Schematic
8.2.1.1 Design Requirements
表 1 lists the design parameters for this application.
表 1. Design Parameters
DESIGN PARAMETER
Input voltage range
Output voltage
EXAMPLE VALUE
5.5 V to 40 V
5 V
Output current rating
Output capacitor range
Delay capacitor range
100 mA
2.2 µF to 100 µF
100 pF to 100 nF
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Adjustable Voltage Operation
The TPS7A16A-Q1 has an output voltage range from 1.194 V to 20 V. As shown in 图 15, the nominal output of
the device is set by two external resistors.
VIN
IN
PG
CIN
RPG
0.1 mF
1 MW
VOUT
5 V
EN
OUT
COUT
R1
2.2 mF
3.4 MW
DELAY
CDELAY
FB
0.1 mF
R2
GND
1.07 MW
图 15. Adjustable Operation
公式 1 can calculate R1 and R2 for any output voltage range:
VOUT
R1 = R2
- 1
VREF
(1)
8.2.1.2.1.1 Resistor Selection
Use resistors in the order of MΩ to keep the overall quiescent current of the system as low as possible (by
making the current used by the resistor divider negligible compared to the quiescent current of the device).
If greater voltage accuracy is required, take into account the voltage offset contributions as a result of feedback
current and use 0.1% tolerance resistors.
版权 © 2019, Texas Instruments Incorporated
11
TPS7A16A-Q1
ZHCSJD1A –FEBRUARY 2019–REVISED MARCH 2019
www.ti.com.cn
表 2 shows the resistor combination to achieve an output for a few of the most common rails using commercially
available 0.1% tolerance resistors to maximize nominal voltage accuracy, while adhering to the formula shown in
公式 1.
表 2. Selected Resistor Combinations
VOUT
1.194 V
1.8 V
2..5 V
3.3 V
5 V
R1
R2
VOUT/(R1 + R2) « IQ
0 µA
NOMINAL ACCURACY
±2%
0 Ω
∞
1.18 MΩ
1.5 MΩ
2 MΩ
2.32 MΩ
1.37 MΩ
1.13 MΩ
1.07 MΩ
1.07 MΩ
1.58 MΩ
3.65 MΩ
1.15 MΩ
514 nA
±(2% + 0.14%)
±(2% + 0.16%)
±(2% + 0.35%)
±(2% + 0.39%)
±(2% + 0.42%)
±(2% + 0.18%)
±(2% + 0.19%)
±(2% + 0.26%)
871 nA
1056 nA
1115 nA
1115 nA
755 nA
3.4 MΩ
7.87 MΩ
14.3 MΩ
42.2 MΩ
16.2 MΩ
10 V
12 V
15 V
327 nA
18 V
1038 nA
Close attention must be paid to board contamination when using high-value resistors; board contaminants can
significantly impact voltage accuracy. If board cleaning measures cannot be ensured, consider using a fixed-
voltage version of the TPS7A16A-Q1 or using resistors in the order of hundreds or tens of kΩ.
8.2.1.2.2 Capacitor Recommendations
Use low equivalent-series-resistance (ESR) capacitors for the input, output, and feed-forward capacitors.
Ceramic capacitors with X7R and X5R dielectrics are preferred. These dielectrics offer more stable
characteristics. Ceramic X7R capacitors offer improved overtemperature performance, but ceramic X5R
capacitors are the most cost-effective and are available in higher values.
However, high-ESR capacitors can degrade PSRR.
8.2.1.2.3 Input and Output Capacitor Requirements
The TPS7A16A-Q1 ultra-low-power, high-voltage linear regulator achieves stability with a minimum input
capacitance of 0.1 µF and output capacitance of 2.2 µF; however, TI recommends using a 10-µF ceramic
capacitor to maximize ac performance.
8.2.1.2.4 Feed-Forward Capacitor (Only for Adjustable Version)
Although a feed-forward capacitor (CFF) from OUT to FB is not needed to achieve stability, TI recommends using
a 0.01-µF feed-forward capacitor to maximize ac performance.
8.2.1.2.5 Transient Response
As with any regulator, increasing the size of the output capacitor reduces over- and undershoot magnitude but
increases the duration of the transient response.
12
版权 © 2019, Texas Instruments Incorporated
TPS7A16A-Q1
www.ti.com.cn
ZHCSJD1A –FEBRUARY 2019–REVISED MARCH 2019
8.2.1.3 Application Curves
图 16. Channel 1 is VOUT, Channel 2 is PG, Channel 4 is
图 17. Channel1 is VOUT, Channel 2 is PG, Channel 3 is EN,
IOUT, VIN is 12 V and Ready Before EN
Channel4 is IOUT, VIN is 12 V Connected to EN
版权 © 2019, Texas Instruments Incorporated
13
TPS7A16A-Q1
ZHCSJD1A –FEBRUARY 2019–REVISED MARCH 2019
www.ti.com.cn
8.2.2 Automotive Applications
The TPS7A16A-Q1 maximum input voltage of 60 V makes the device ideal for use in automotive applications
where high-voltage transients are present.
Events such as load-dump overvoltage (where the battery is disconnected while the alternator is providing
current to a load) can cause voltage spikes from 25 V to 60 V. In order to prevent any damage to sensitive
circuitry, local transient voltage suppressors can be used to cap voltage spikes to lower, more manageable
voltages.
The TPS7A16A-Q1 can be used to simplify and lower costs in such cases. The very high voltage range allows
this regulator not only to withstand the voltages coming out of these local transient voltage suppressors, but even
replace them, thus lowering system cost and complexity. 图 18 shows a circuit diagram of an example
automotive application.
VIN
60 V
12 V
t
VOUT
VIN
OUT
VCC
mC2
IN
CIN
COUT
EN
RPG
TPS7A16A-Q1
VEN
EN
DELAY
PG
IO1
GND
VPG
CDELAY
IO3
mC1
IO2
图 18. Low-Power Microcontroller Rail Sequencing in Automotive Applications Subjected to Load-Dump
Transients
8.2.2.1 Design Requirements
表 3 lists the design parameters for this application.
表 3. Design Parameters
DESIGN PARAMETER
Input voltage range
Output voltage
EXAMPLE VALUE
5.5 V to 60 V
5 V
Output current rating
Output capacitor range
Delay capacitor range
100 mA
2.2 µF to 100 µF
100 pF to 100 nF
8.2.2.2 Detailed Design Procedure
See the Capacitor Recommendations and Input and Output Capacitor Requirements sections.
8.2.2.2.1 Device Recommendations
The output is fixed, so choose the TPS7A16A-Q1.
8.2.2.3 Application Curves
See 图 16 and 图 17.
14
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TPS7A16A-Q1
www.ti.com.cn
ZHCSJD1A –FEBRUARY 2019–REVISED MARCH 2019
9 Power Supply Recommendations
Design of the device is for operation from an input voltage supply with a range between 3 V and 60 V. This input
supply must be well regulated. The TPS7A16A-Q1 ultra-low-power, high-voltage linear regulator achieves
stability with a minimum input capacitance of 0.1 µF and output capacitance of 2.2 µF; however, TI recommends
using a 10-µF ceramic capacitor to maximize AC performance.
10 Layout
10.1 Layout Guidelines
To improve ac performance such as PSRR, output noise, and transient response, the board is recommended to
be designed with separate ground planes for IN and OUT, with each ground plane connected only at the GND
pin of the device. This grounding scheme is commonly referred to as star grounding. In addition, directly connect
the ground connection for the output capacitor to the GND pin of the device.
Equivalent series inductance (ESL) and ESR must be minimized in order to maximize performance and ensure
stability. Every capacitor must be placed as close as possible to the device and on the same side of the PCB as
the regulator itself.
Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. The use
of vias and long traces is strongly discouraged because they can impact system performance negatively and
even cause instability.
If possible, and to ensure the maximum performance denoted in this document, use the same layout pattern
used for the TPS7A16A-Q1 evaluation board, available at www.ti.com.
Layout is a critical part of good power-supply design. There are several signal paths that conduct fast-changing
currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade
the power-supply performance. To help eliminate these problems, bypass the IN pin to ground with a low-ESR
ceramic bypass capacitor with X5R or X7R dielectric.
Acceptable performance can be obtained with alternative PCB layouts; however, the layout and the schematic
have been shown to produce good results and are meant as a guideline.
图 19 illustrates the schematic for the suggested layout. 图 20 and 图 21 depict the top and bottom printed circuit
board (PCB) layers for the suggested layout, respectively.
10.1.1 Additional Layout Considerations
The high impedance of the FB pin makes the regulator sensitive to parasitic capacitances that can couple
undesirable signals from nearby components (especially from logic and digital devices, such as microcontrollers
and microprocessors); these capacitively-coupled signals can produce undesirable output voltage transients. In
these cases, use a fixed-voltage version of the TPS7A16A-Q1, or isolate the FB node by flooding the local PCB
area with ground-plane copper to minimize any undesirable signal coupling.
10.1.2 Power Dissipation
The ability to remove heat from the die is different for each package type, presenting different considerations in
the PCB layout. The PCB area around the device that is free of other components moves the heat from the
device to the ambient air. Using heavier copper increases the effectiveness of removing heat from the device.
The addition of plated through-holes to heat dissipating layers also improves the heatsink effectiveness.
Power dissipation depends on input voltage and load conditions. As 公式 2 shows, power dissipation (PD) is
equal to the product of the output current times the voltage drop across the output pass element:
PD = (VIN - VOUT) IOUT
(2)
版权 © 2019, Texas Instruments Incorporated
15
TPS7A16A-Q1
ZHCSJD1A –FEBRUARY 2019–REVISED MARCH 2019
www.ti.com.cn
Layout Guidelines (接下页)
10.1.3 Thermal Considerations
Thermal protection disables the output when the junction temperature rises to approximately 170°C, allowing the
device to cool. When the junction temperature cools to approximately 150°C, the output circuitry is enabled.
Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may
cycle on and off. This cycling limits the dissipation of the regulator, protecting the regulator from damage as a
result of overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heat-spreading area. For reliable operation, limit junction temperature to a maximum of 125°C at the worst-case
ambient temperature for a given application. To estimate the margin of safety in a complete design (including the
copper heat-spreading area), increase the ambient temperature until the thermal protection is triggered; use
worst-case loads and signal conditions. For good reliability, trigger thermal protection at least 45°C above the
maximum expected ambient condition of the particular application. This configuration produces a worst-case
junction temperature of 125°C at the highest expected ambient temperature and worst-case load.
The internal protection circuitry of the TPS7A16A-Q1 is designed to protect against overload conditions. This
circuitry is not intended to replace proper heatsinking. Continuously running the TPS7A16A-Q1 into thermal
shutdown degrades device reliability.
10.2 Layout Examples
TPS7A16A-Q1
图 19. Schematic for Suggested Layout
16
版权 © 2019, Texas Instruments Incorporated
TPS7A16A-Q1
www.ti.com.cn
ZHCSJD1A –FEBRUARY 2019–REVISED MARCH 2019
Layout Examples (接下页)
TPS7A16A
1300 mil
2200 mil
图 20. Suggested Layout: Top Layer
1300 mil
2200 mil
图 21. Suggested Layout: Bottom Layer
版权 © 2019, Texas Instruments Incorporated
17
TPS7A16A-Q1
ZHCSJD1A –FEBRUARY 2019–REVISED MARCH 2019
www.ti.com.cn
11 器件和文档支持
11.1 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.2 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 商标
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.5 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
18
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS7A1601AQDGNRQ1
TPS7A1633AQDGNRQ1
TPS7A1650AQDGNRQ1
ACTIVE
ACTIVE
ACTIVE
HVSSOP
HVSSOP
HVSSOP
DGN
DGN
DGN
8
8
8
2500 RoHS & Green
2500 RoHS & Green
2500 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
1NT1
1NU1
1NV1
NIPDAU
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS7A1601AQDGNRQ1 HVSSOP DGN
TPS7A1633AQDGNRQ1 HVSSOP DGN
TPS7A1650AQDGNRQ1 HVSSOP DGN
8
8
8
2500
2500
2500
330.0
330.0
330.0
12.4
12.4
12.4
5.3
5.3
5.3
3.3
3.3
3.3
1.3
1.3
1.3
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS7A1601AQDGNRQ1
TPS7A1633AQDGNRQ1
TPS7A1650AQDGNRQ1
HVSSOP
HVSSOP
HVSSOP
DGN
DGN
DGN
8
8
8
2500
2500
2500
367.0
367.0
367.0
367.0
367.0
367.0
38.0
38.0
38.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DGN 8
3 x 3, 0.65 mm pitch
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225482/A
www.ti.com
PACKAGE OUTLINE
DGN0008C
HVSSOP - 1.1 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE PACKAGE
C
5.05
4.75
TYP
A
0.1 C
SEATING
PLANE
PIN 1 INDEX AREA
6X 0.65
8
1
2X
3.1
2.9
1.95
NOTE 3
4
5
0.37
8X
0.26
0.1
C A B
3.1
2.9
B
NOTE 4
0.23
0.13
SEE DETAIL A
EXPOSED THERMAL PAD
4
5
0.25
GAGE PLANE
1.92
1.66
9
1.1 MAX
8
1
0.15
0.05
0.7
0.4
0 -8
A
20
DETAIL A
1.60
1.34
TYPICAL
4218838/A 11/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.
www.ti.com
EXAMPLE BOARD LAYOUT
DGN0008C
HVSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(2)
NOTE 9
METAL COVERED
BY SOLDER MASK
(1.6)
SOLDER MASK
DEFINED PAD
(R0.05) TYP
SYMM
8X (1.4)
8
8X (0.45)
1
(3)
NOTE 9
SYMM
9
(1.92)
(1.1)
6X (0.65)
4
5
(
0.2) TYP
VIA
SEE DETAILS
(0.55)
(4.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4218838/A 11/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
DGN0008C
HVSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(1.6)
BASED ON
0.125 THICK
STENCIL
SYMM
(R0.05) TYP
8X (1.4)
8
1
8X (0.45)
(1.92)
BASED ON
SYMM
0.125 THICK
STENCIL
6X (0.65)
5
4
METAL COVERED
BY SOLDER MASK
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
(4.4)
SOLDER PASTE EXAMPLE
EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
1.79 X 2.15
1.60 X 1.92 (SHOWN)
1.46 X 1.75
0.125
0.15
0.175
1.35 X 1.62
4218838/A 11/2017
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
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