TPS7A20_V07 [TI]
TPS7A20 300-mA, Ultra-Low-Noise, Low-IQ, High PSRR LDO;型号: | TPS7A20_V07 |
厂家: | TEXAS INSTRUMENTS |
描述: | TPS7A20 300-mA, Ultra-Low-Noise, Low-IQ, High PSRR LDO |
文件: | 总44页 (文件大小:8268K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TPS7A20
SBVS338B – MARCH 2020 – REVISED SEPTEMBER 2020
TPS7A20 300-mA, Ultra-Low-Noise, Low-IQ, High PSRR LDO
1 Features
3 Description
•
Low output voltage noise: 7 µVRMS
The TPS7A20 is an ultra-small, low-dropout (LDO)
linear regulator that can source 300 mA of output
current. The TPS7A20 is designed to provide low
noise, high PSRR, and excellent load and line
transient performance that can meet the requirements
of RF and other sensitive analog circuits. Using
innovative design techniques, the TPS7A20 offers an
ultra-low noise performance without the addition of a
noise bypass capacitor. The TPS7A20 also provides
the advantage of low quiescent current, which can be
ideal for battery-powered applications. With an input
voltage range of 1.6 V to 6.0 V and an output range of
0.8 V to 5.5 V, the TPS7A20 can be used for a wide
variety of applications. The device uses a precision
reference circuit to provide a maximum accuracy of
1.5% over load, line, and temperature variations.
– No noise-bypass capacitor required
High PSRR: 95 dB at 1 kHz
Very low IQ: 6.5 µA
Input voltage range: 1.6 V to 6.0 V
Output voltage range: 0.8 V to 5.5 V
Output voltage tolerance: ±1.5% (max)
Very low dropout:
– 140 mV (max) at 300 mA (VOUT = 3.3 V)
Low inrush current
Smart enable pulldown
•
•
•
•
•
•
•
•
•
Stable with 1-µF minimum ceramic output
capacitor
Packages:
•
– 1-mm × 1-mm X2SON
The TPS7A20 features an internal soft-start to lower
the inrush current, thus minimizing the input voltage
drop during start up. The device is stable with small
ceramic capacitors, allowing for a small overall
solution size.
– 0.603-mm × 0.603-mm DSBGA (preview)
– 2.90-mm × 1.60-mm SOT23-5 (preview)
2 Applications
•
•
•
•
•
•
Smartphones and tablets
IP network cameras
Portable medical equipment
Smart meters and field transmitters
Motor drives
The TPS7A20 has a smart enable input circuit with an
internally controlled pulldown resistor that keeps the
LDO disabled even when the EN pin is left floating
and helps eliminate the external components used to
pulldown the EN pin.
Wearables
Device Information (1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
1.00 mm × 1.00 mm
0.603 mm × 0.603 mm
2.90 mm × 1.60 mm
X2SON (4)
TPS7A20
DSBGA (4)(2)
SOT-23 (5)(2)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) Preview package.
VOUT
VIN
OUTPUT
INPUT
1 µF
1 µF
TPS7A20
VEN
ENABLE
GND
GND
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
TPS7A20
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SBVS338B – MARCH 2020 – REVISED SEPTEMBER 2020
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings ....................................... 5
6.2 ESD Ratings .............................................................. 5
6.3 Recommended Operating Conditions ........................5
6.4 Thermal Information ...................................................6
6.5 Electrical Characteristics ............................................6
6.6 Switching Characteristics ...........................................7
6.7 Typical Characteristics................................................8
7 Detailed Description......................................................20
7.1 Overview...................................................................20
7.2 Functional Block Diagram.........................................20
7.3 Feature Description...................................................21
7.4 Device Functional Modes..........................................23
8 Application and Implementation..................................24
8.1 Application Information............................................. 24
8.2 Typical Application.................................................... 28
9 Power Supply Recommendations................................29
10 Layout...........................................................................30
10.1 Layout Guidelines................................................... 30
10.2 Layout Examples.................................................... 30
11 Device and Documentation Support..........................31
11.1 Device Support........................................................31
11.2 Receiving Notification of Documentation Updates..31
11.3 Support Resources................................................. 31
11.4 Trademarks............................................................. 31
11.5 Electrostatic Discharge Caution..............................31
11.6 Glossary..................................................................31
12 Mechanical, Packaging, and Orderable
Information.................................................................... 31
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (March 2020) to Revision B (September 2020)
Page
•
Changed document status from advance information to production data.......................................................... 1
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SBVS338B – MARCH 2020 – REVISED SEPTEMBER 2020
5 Pin Configuration and Functions
1
2
1
2
A
IN
OUT
B
EN
GND
B
EN
GND
A
IN
OUT
Not to scale
Not to scale
Figure 5-1. YCK Package (Preview), 4-Pin DSBGA, Figure 5-2. YCK Package (Preview), 4-Pin DSBGA,
Top View Bottom View
Pin Functions: DSBGA
PIN
I/O
DESCRIPTION
NO.
NAME
Input voltage supply. For best transient response and to minimize input impedance, use the
nominal value or larger capacitor from IN to ground as listed in the Recommended
Operating Conditions table. Place the input capacitor as close to the IN and GND pins of the
device as possible.
A1
A2
IN
I
Regulated output voltage. A low equivalent series resistance (ESR) capacitor is required
from OUT to ground for stability. For best transient response, use the nominal
recommended value or larger capacitor listed in the Recommended Operating Conditions
table. Place the output capacitor as close to the OUT and GND pins of the device as
possible. An internal 150-Ω (typical) pulldown resistor prevents a charge from remaining on
VOUT when the regulator is in shutdown mode (VEN< VEN(LOW)).
OUT
O
Enable input. A low voltage (< VEN(LOW)) on this input turns the regulator off and discharges
the output pin to GND. A high voltage (> VEN(HI)) on this pin enables the regulator output.
This pin has an internal 500-kΩ pulldown resistor to hold the regulator off by default. When
VEN > VEN(HI), the 500-kΩ pulldown is disconnected to reduce input current.
B1
B2
EN
I
GND
—
Common ground.
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OUT
1
4
IN
IN
GND
EN
1
2
3
5
OUT
5
Thermal Pad
4
N/C
GND
2
3
EN
Not to scale
Not to scale
Figure 5-3. DQN Package, 4-Pin X2SON, Top View
Figure 5-4. DBV Package (Preview), 5-Pin SOT-23,
Top View
Pin Functions: X2SON, SOT-23
PIN
I/O
DESCRIPTION
NAME
X2SON
SOT-23
Input voltage supply. For best transient response and to minimize input
impedance, use the nominal value or larger capacitor from IN to ground as listed
in the Recommended Operating Conditions table. Place the input capacitor as
close to the IN and GND pins of the device as possible.
IN
4
1
1
I
Regulated output voltage. A low equivalent series resistance (ESR) capacitor is
required from OUT to ground for stability. For best transient response, use the
nominal recommended value or larger capacitor listed in the Recommended
Operating Conditions table. Place the output capacitor as close to the OUT and
GND pins of the device as possible. An internal 150-Ω (typical) pulldown resistor
prevents a charge from remaining on VOUT when the regulator is in shutdown
mode (VEN< VEN(LOW)).
OUT
5
O
Enable input. A low voltage (< VEN(LOW)) on this pin turns the regulator off and
discharges the output pin to GND. A high voltage (> VEN(HI)) on this pin enables
the regulator output. This pin has an internal 500-kΩ pulldown resistor to hold the
regulator off by default. When VEN > VEN(HI), the 500-kΩ pulldown is
disconnected to reduce input current.
EN
3
3
I
GND
N/C
2
2
4
—
—
Common ground.
—
No internal electrical connection.
Thermal pad for the X2SON package. Connect this pad to GND or leave floating.
Do not connect to any potential other than GND. Connect the thermal pad to a
large-area ground plane for best thermal performance.
Thermal Pad
5
—
—
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (3)
MIN
MAX
UNIT
VIN
–0.3
6.5
6.5 or VIN + 0.3
Voltage
VOUT
–0.3
–0.3
V
(2)
VEN
6.5
Current
Maximum output(4)
Operating junction, TJ
Storage, Tstg
Internally limited
A
–40
–65
125
150
°C
°C
Temperature
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 6.3 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The maximum value of VOUT is the lesser of 6.5 V or (VIN + 0.3 V).
(3) All voltages are with respect to the GND pin.
(4) Internal thermal shutdown circuitry protects the device from permanent damage.
6.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safemanufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safemanufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN
1.6
0
NOM
MAX
6.0
UNIT
V
VIN
Input supply voltage
VEN
VOUT
IOUT
CIN
Enable input voltage
6.0
V
Nominal output voltage range
Output current
0.8
0
5.5
V
300
mA
µF
µF
mΩ
°C
Input capacitor(2)
1
COUT
ESR
TJ
Output capacitor(3)
1
200
100
125
Output capacitor effective series resistance
Operating junction temperature
–40
(1) All voltages are with respect to GND.
(2) An input capacitor is not required for LDO stability. However, an input capacitor with an effective value of 0.47 μF minimum is
recommended to counteract the effect of source resistance and inductance, which may in some cases cause symptoms of system-
level instability such as ringing or oscillation, especially in the presence of load transients.
(3) Effective output capacitance of 0.47 μF minimum and 200 μF maximum is required for stability.
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UNIT
SBVS338B – MARCH 2020 – REVISED SEPTEMBER 2020
6.4 Thermal Information
TPS7A20
DQN
DBV
YCK
THERMAL METRIC(1)
(SOT-23) (X2SON) (DSBGA)
5 PINS
187.1
85.5
4 PINS
166.1
103.6
110.6
3.0
4 PINS
TBD
TBD
TBD
TBD
TBD
TBD
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
54.4
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
27.1
ψJB
54.1
103.3
98.8
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
at operating temperature range (TJ = –40℃ to +125℃), VIN = VOUT(NOM) + 0.3 V or 1.6V, whichever is greater,
VEN = 1.0 V, IOUT = 1 mA, CIN= 1 µF, COUT = 1 µF (unless otherwise noted); all typical values are at TJ = 25℃
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN = (VOUT(NOM) + 0.3 V) to 6.0 V,
IOUT = 1 mA to 300 mA,
VOUT ≥ 1.85 V
–1.5
1.5
%
ΔVOUT
Output voltage tolerance
VIN = (VOUT(NOM) + 0.5 V) to 6.0 V,
IOUT = 1 mA to 300 mA
VOUT < 1.85 V
–30
30
mV
VIN = (VOUT(NOM) + 0.3 V) to 6.0 V,
IOUT = 1 mA
ΔVOUT
ΔVOUT
Line regulation
Load regulation
0.03
%/V
mV
IOUT = 1 mA to 300 mA
13
TJ = 25°C
6.5
8.5
10
15
VEN = VIN = 6 V, IOUT = 0
TJ = –40°C to 85°C
TJ = –40°C to 125°C
mA
IGND
Quiescent ground current
µA
VEN = VIN = 6 V, IOUT = 300 mA
VEN = 0 V (disabled), VIN = 6.0 V, TJ = 25°C
VIN ≤ VOUT(NOM) , IOUT = 0 mA, VEN = VIN
0.8 V ≤ VOUT < 1.0 V(1)
2000
0.07
6.5
ISHDN
Shutdown ground current
IGND in dropout
0.2
15
µA
µA
IGND(DO)
690
490
355
200
140
1.0 V ≤ VOUT < 1.2 V(1)
IOUT = 300 mA,
VOUT = 95% x VOUT(NOM)
VDO
Dropout voltage
1.2 V ≤ VOUT < 1.5 V(1)
mV
1.5 V ≤ VOUT < 2.5 V
2.5 V ≤ VOUT < 5.5 V
VOUT = 0.9 x VOUT(NOM)
VIN = VOUT(NOM) + 0.5 V
,
VOUT < 1.5 V
VOUT ≥ 1.5 V
360
360
520
730
730
ICL
Output current limit
mA
mA
VOUT = 0.9 x VOUT(NOM)
,
520
160
VIN = VOUT(NOM) + 0.3 V
ISC
Short-circuit current limit
VOUT = 0 V
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at operating temperature range (TJ = –40℃ to +125℃), VIN = VOUT(NOM) + 0.3 V or 1.6V, whichever is greater,
VEN = 1.0 V, IOUT = 1 mA, CIN= 1 µF, COUT = 1 µF (unless otherwise noted); all typical values are at TJ = 25℃
PARAMETER
TEST CONDITIONS
MIN
TYP
95
95
75
75
45
65
92
75
60
40
7
MAX
UNIT
f = 100 Hz
f = 1 kHz
IOUT = 20 mA,
f = 10 kHz
VIN = VOUT + 1.0 V
f = 100 kHz
f = 1 MHz
PSRR
Power-supply rejection ratio
dB
f = 100 Hz
f = 1 kHz
IOUT = 300 mA,
VIN = VOUT + 1.0 V
f = 10 kHz
f = 100 kHz
f = 1 MHz
IOUT = 300 mA
IOUT = 1 mA
BW = 10 Hz to 100 kHz,
VOUT = 2.8 V
VN
Output noise voltage
µVRMS
10
Output automatic discharge
pulldown resistance
RPULLDOWN
VEN < VEN(LOW) (output disabled), VIN = 3.1 V
150
Ω
TJ rising
TJ falling
165
140
TSD
Thermal shutdown
°C
VIN = 1.6 V to 6.0 V,
VEN falling until the output is disabled
VEN(LOW)
VEN(HI)
Low input threshold
High input threshold
0.3
V
V
VIN = 1.6 V to 6.0 V
VEN rising until the output is enabled
0.9
VIN rising
VIN falling
1.17
1.11
1.35
1.3
50
1.59
1.55
VUVLO
UVLO threshold
V
VUVLO(HYST) UVLO hysteresis
mV
nA
IEN
EN input leakage current
VEN = 6.0 V and VIN = 6.0 V
90
250
REN(PULL-
Smart enable pulldown resistor VEN = 0.25 V
500
KΩ
DOWN)
(1) Design simulation data only
6.6 Switching Characteristics
at operating temperature range (TJ = –40℃ to +125℃), VIN = VOUT(NOM) + 0.3 V or 1.6V, whichever is greater,
VEN = 1.0 V, IOUT = 1 mA, CIN= 1 µF, COUT = 1 µF (unless otherwise noted); all typical values are at TJ = 25℃
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
From VEN > VEN(HI) to VOUT = 95% of VOUT(NOM)
,
tSTR
Start-up time
750
1150
µs
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6.7 Typical Characteristics
VIN = VOUT(NOM) + 0.3 V or 1.6 V (whichever is greater), VOUT = 2.8 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, and
TA = 25°C (unless otherwise noted)
3
2
9
6
TJ
TJ
-55°C
-40°C
0°C
25°C
85°C
125°C
150°C
-55°C
-40°C
0°C
25°C
85°C
125°C
150°C
1
3
0
0
-1
-2
-3
-4
-5
-6
-3
-6
-9
-12
-15
5.6
5.65
5.7
5.75
5.8
Input Voltage (V)
5.85
5.9
5.95
6
3.1 3.4 3.7
4
4.3 4.6 4.9 5.2 5.5 5.8
Input Voltage (V)
6
VOUT = 5.5 V, VEN = 1 V
VEN = 1 V
Figure 6-2. Line Regulation vs VIN
Figure 6-1. Line Regulation vs VIN
15
10
5
16
12
8
TJ
TJ
-55°C
-40°C
0°C
25°C
85°C
125°C
150°C
-55°C
-40°C
0°C
25°C
85°C
125°C
150°C
0
-5
4
-10
-15
-20
-25
0
-4
-8
0
25 50 75 100 125 150 175 200 225 250 275 300
Output Current (mA)
0
0.2 0.4 0.6 0.8
1
Output Current (mA)
1.2 1.4 1.6 1.8
2
VIN = 3.1 V, VEN = 1 V
VIN = 3.1 V, VEN = 1 V
Figure 6-3. Load Regulation vs IOUT
Figure 6-4. Load Regulation vs IOUT
15
10
5
15
TJ
TJ
-55°C
-40°C
0°C
25°C
85°C
125°C
150°C
-55°C
-40°C
0°C
25°C
85°C
125°C
150°C
10
5
0
-5
0
-10
-15
-20
-25
-30
-35
-5
-10
-15
-20
0
30
60
90 120 150 180 210 240 270 300
Output Current (mA)
0
0.2 0.4 0.6 0.8
1
Output Current (mA)
1.2 1.4 1.6 1.8
2
VOUT = 5.5 V, VEN = 1 V
VOUT = 5.5 V, VEN = 1 V
Figure 6-5. Load Regulation vs IOUT
Figure 6-6. Load Regulation vs IOUT
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0.6
0.4
0.2
0
0.6
0.5
0.4
0.3
0.2
0.1
0
TJ
TJ
-55°C
-40°C
0°C
25°C
85°C
125°C
150°C
-55°C
-40°C
0°C
25°C
85°C
125°C
150°C
-0.2
-0.4
-0.6
-0.8
-1
-0.1
-0.2
-0.3
0
0.2 0.4 0.6 0.8
1 1.2 1.4 1.6 1.8
Output Current (mA)
2
0
25 50 75 100 125 150 175 200 225 250 275 300
Output Current (mA)
D076
VEN = 1 V
VEN = 1 V
Figure 6-8. Output Voltage Accuracy vs IOUT
Figure 6-7. Output Voltage Accuracy vs IOUT
0.2
0.3
TJ
TJ
-55°C
-40°C
0°C
25°C
85°C
125°C
150°C
-55°C
-40°C
0°C
25°C
85°C
125°C
150°C
0.1
0
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.1
-0.2
-0.3
0
30
60
90 120 150 180 210 240 270 300
Output Current (mA)
0
0.2 0.4 0.6 0.8 1
Output Current (mA)
1.2 1.4 1.6 1.8
2
VOUT = 5.5 V, VEN = 1 V
VOUT = 5.5 V, VEN = 1 V
Figure 6-9. Output Voltage Accuracy vs IOUT
Figure 6-10. Output Voltage Accuracy vs IOUT
0.15
0.15
TJ
TJ
0.1
0.05
0
-55°C
-40°C
0°C
25°C
85°C
125°C
150°C
-55°C
-40°C
0°C
25°C
85°C
125°C
150°C
0.1
0.05
0
-0.05
-0.1
-0.15
-0.2
-0.25
-0.3
-0.05
-0.1
-0.15
-0.2
-0.25
3.1
3.6
4.1 4.6
Input Voltage (V)
5.1
5.6
6
5.6
5.65
5.7
5.75
5.8
Input Voltage (V)
5.85
5.9
5.95
6
VEN = 1 V, IOUT = 1 mA
VOUT = 5.5 V, VEN = 1 V
Figure 6-11. Output Voltage Accuracy vs VIN
Figure 6-12. Output Voltage Accuracy vs VIN
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130
90
85
80
75
70
65
60
55
TJ
TJ
-55°C
-40°C
0°C
25°C
85°C
125°C
150°C
-55°C
-40°C
0°C
25°C
85°C
125°C
150°C
120
110
100
90
80
70
60
50
0
30
60
90 120 150 180 210 240 270 300
Output Current (mA)
0
1
2
3
4
5
6
Output Current (mA)
7
8
9
10
VEN = 1 V
VEN = 1 V
Figure 6-13. Dropout Voltage vs IOUT
Figure 6-14. Dropout Voltage vs IOUT
160
150
95
90
85
80
75
70
65
60
55
TJ
TJ
-55°C
-40°C
0°C
25°C
85°C
125°C
150°C
-55°C
-40°C
0°C
25°C
85°C
125°C
150°C
140
130
120
110
100
90
80
70
60
0
30
60
90 120 150 180 210 240 270 300
Output Current (mA)
0
1
2
3
4
5
6
Output Current (mA)
7
8
9
10
D099
D100
VOUT = 1.8 V, VEN = 1 V
VOUT = 1.8 V, VEN = 1 V
Figure 6-15. Dropout Voltage vs IOUT
Figure 6-16. Dropout Voltage vs IOUT
180
170
160
150
140
130
120
110
100
90
14
TJ
0°C
25°C
TJ
13
12
11
10
9
-40°C
-20°C
50°C
85°C
125°C
-55°C
-40°C
0°C
25°C
85°C
125°C
150°C
8
7
6
5
4
1.6
1.5
2
2.5
3
3.5
4
Output Voltage ( V)
4.5
5
5.5
2.1
2.6
3.1
3.6
4.1
Input Voltage (V)
4.6
5.1
5.6
6
IOUT = 300 mA
VEN = 1 V, IOUT = 0 mA
Figure 6-17. Dropout Voltage vs VOUT
Figure 6-18. I GND vs VIN
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13
12
11
10
9
12
11
10
9
TJ
TJ
-55°C
-40°C
0°C
25°C
85°C
125°C
150°C
-55°C
-40°C
0°C
25°C
85°C
125°C
150°C
8
8
7
7
6
6
5
5
4
4
1.6
2.1
2.6
3.1
3.6
Input Voltage (V)
4.1
4.6
5.1 5.5
1.6
2.1
2.6
3.1
3.6
4.1
Input Voltage (V)
4.6
5.1
5.6
6
VOUT(NOM) = 5.5 V, VEN = 1 V, IOUT = 0 mA
VEN = VIN, IOUT = 0 mA
Figure 6-20. IGND vs VIN in the Dropout Region
Figure 6-19. IGND vs VIN
3250
12
11
10
9
TJ
TJ
3000
-55°C
-40°C
0°C
25°C
85°C
125°C
150°C
-55°C
-40°C
0°C
25°C
85°C
125°C
150°C
2750
2500
2250
2000
1750
1500
1250
1000
750
8
7
6
500
5
250
0
4
0
30
60
90 120 150 180 210 240 270 300
Output Current (mA)
1.6
2.1
2.6
3.1
3.6
Input Voltage (V)
4.1
4.6
5.1 5.5
VEN = 1 V
VOUT(NOM) = 5.5 V, VEN = VIN, IOUT = 0 mA
Figure 6-22. IGND vs IOUT
Figure 6-21. IGND vs VIN in the Dropout Region
4000
500
450
400
350
300
250
200
150
100
50
TJ
TJ
-55°C
-40°C
0°C
85°C
125°C
150°C
-55°C
-40°C
0°C
25°C
85°C
125°C
150°C
1000
100
25°C
10
2
0
0.001
0.01
0.1
Output Current (mA)
1
10
100 300
0
0.5
1
1.5
2
2.5
Output Current (mA)
3
3.5
4
4.5
5
D072
D073
VEN = 1 V
VEN = 1 V
Figure 6-23. IGND vs IOUT
Figure 6-24. IGND vs IOUT
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4000
3500
3000
2500
2000
1500
1000
500
45
TJ
125°C
TJ
-40°C
40
85°C
150°C
-55°C
0°C
25°C
35
30
25
20
15
10
5
0
0
1.6
-5
1.6
2.1
2.6
3.1
3.6
4.1
Input Voltage (V)
4.6
5.1
5.6
6
2.1
2.6
3.1
3.6
4.1
Input Voltage (V)
4.6
5.1
5.6
6
VEN = 0 V
VEN = 0 V
Figure 6-26. Shutdown Current vs VIN
Figure 6-25. Shutdown Current vs VIN
4500
4000
3500
3000
2500
2000
1500
1000
500
4.5
4
TJ
0°C
25°C
-55°C
-40°C
85°C
125°C
3.5
3
2.5
2
1.5
1
TJ
-55°C
-40°C
0°C
25°C
85°C
125°C
150°C
5.5
0.5
0
0
0
0.5
1
1.5
2
2.5
3
3.5
VEN - VIN (V)
4
4.5
5
6
0
50 100 150 200 250 300 350 400 450 500 550 600
Output Current (mA)
VEN = 6 V, IOUT = 0 mA
VEN = 1 V
Figure 6-27. Enable Pin Leakage Current vs
VEN - VIN
Figure 6-28. Current Limit
1.2
1.4
1.39
1.38
1.37
1.36
1.35
1.34
1.33
1.32
1.31
1.3
TJ
V
UVLO+ (VIN rising)
VUVLO- (V
-55°C
-40°C
0°C
25°C
85°C
125°C
150°C
IN falling)
1
0.8
0.6
0.4
0.2
0
0
50 100 150 200 250 300 350 400 450 500 550 600
Output Current (mA)
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature (°C)
D088
VOUT = 0.8 V, VEN = 1 V
VEN = 1 V
Figure 6-29. Current Limit
Figure 6-30. UVLO Threshold vs Temperature
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1
0.95
0.9
0.9
0.85
0.8
VIN
VIN
1.6 V ( Vout = 0.8 V )
2.1 V ( Vout = 1.8 V )
3.1 V ( Vout = 2.8 V )
5.8 V ( Vout = 5.5 V )
6.0 V ( Vout = 0.8 V - 5.5 V )
1.6 V ( Vout = 0.8 V )
2.1 V ( Vout = 1.8 V )
3.1 V ( Vout = 2.8 V )
5.8 V ( Vout = 5.5 V )
6.0 V ( Vout = 0.8 V - 5.5 V )
0.85
0.8
0.75
0.7
0.75
0.7
0.65
0.6
0.65
0.6
0.55
0.5
0.55
0.5
0.45
0.4
0.45
0.4
0.35
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature (°C)
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature (°C)
Figure 6-31. Enable Logic High Threshold vs
Temperature
Figure 6-32. Enable Logic Low Threshold Low vs
Temperature
400
540
VIN
1.6 V ( VOUT = 0.8 V )
2.1 V ( VOUT = 1.8 V )
3.1 V ( VOUT = 2.8 V )
6 V ( VOUT = 5.5 V )
VIN
1.6 V
2.4 V
3.4 V
4.4 V
5.4 V
520
350
300
250
200
150
100
500
6.0 V
480
460
440
420
-60
-30
0
30 60
Temperature (°C)
90
120
150
-60
-35
-10
15
40
65
Temperature (°C)
90
115 140 160
VEN = 0.25 V
VEN = 0.25 V
Figure 6-34. Smart Enable Pulldown Resistor vs
Temperature and VIN
Figure 6-33. Output Pulldown Resistor vs
Temperature
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
20
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
40
IOUT
VOUT
10
30
0
20
-10
-20
-30
-40
-50
-60
-70
-80
10
0
-10
-20
-30
-40
-50
-60
IOUT
VOUT
-0.1
0
2
4
6
8
10
Time (ms)
12
14
16
18
20
0
4
8
12
16
20
Time (µs)
24
28
32
36
40
D030
D033
IOUT = 1 mA to 300 mA, tRISING = 1 µs
IOUT = 300 mA to 1 mA, tFALLING = 1 µs
Figure 6-35. Load Transient
Figure 6-36. Load Transient
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1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
20
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
40
IOUT
VOUT
0
30
-20
-40
-60
-80
-100
-120
-140
-160
-180
20
10
0
-10
-20
-30
-40
-50
-60
IOUT
VOUT
-0.1
0
2
4
6
8
10
Time (ms)
12
14
16
18
20
0
10
20
30
40
50
Time (µs)
60
70
80
90 100
D031
D032
IOUT = 1 mA to 300 mA, tRISING = 200 ns
IOUT = 300 mA to 1 mA, tFALLING = 200 ns
Figure 6-37. Load Transient
Figure 6-38. Load Transient
0.9
40
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
30
IOUT
VOUT
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
20
-40
10
-80
0
-120
-160
-200
-240
-280
-320
-360
-10
-20
-30
-40
-50
-60
-70
IOUT
VOUT
-0.1
-0.1
0
2
4
6
8
10
Time (µs)
12
14
16
18
20
0
50 100 150 200 250 300 350 400 450 500
Time (µs)
D035
D037
IOUT = 0 mA to 300 mA, tRISING = 1 µs
IOUT = 300 mA to 0 mA, tFALLING = 1 µs
Figure 6-39. Load Transient
Figure 6-40. Load Transient
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
40
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
30
IOUT
VOUT
0
20
-40
10
-80
0
-120
-160
-200
-240
-280
-320
-360
-10
-20
-30
-40
-50
-60
-70
IOUT
VOUT
-0.1
-0.1
0
2
4
6
8
10
Time (µs)
12
14
16
18
20
0
50 100 150 200 250 300 350 400 450 500
Time (µs)
D034
D036
IOUT = 0 mA to 300 mA, tRISING = 200 ns
IOUT = 300 mA to 0 mA, tFALLING = 200 ns
Figure 6-41. Load Transient
Figure 6-42. Load Transient
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6
5
7
6
5
6
VOUT
VIN
VOUT
VIN
6
5
4
5
4
4
3
4
3
3
2
3
2
2
1
2
1
1
0
1
0
0
-1
-2
-3
-4
0
-1
-2
-3
-4
-1
-2
-3
-4
-1
-2
-3
0
10
20
30
40
50
Time (µs)
60
70
80
90 100
0
10
20
30
40
50
Time (ms)
60
70
80
90 100
D060
D061
VIN = 3.1 V → 4.1 V → 3.1 V, VIN tRISING = 5 µs, IOUT = 1 mA
VIN = 3.1 V → 4.1 V → 3.1 V, VIN tRISING = 5 µs, IOUT = 300 mA
Figure 6-43. Line Transient
Figure 6-44. Line Transient
120
120
VIN
VIN
110
110
3.10 V
3.30 V
3.80 V
3.1 V
3.3 V
3.8 V
100
100
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
10
0
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
D011
D00115
IOUT = 20 mA
IOUT = 300 mA
Figure 6-45. PSRR vs VIN vs Frequency and VIN
Figure 6-46. PSRR vs Frequency and VIN
120
110
100
90
120
COUT
110
1 mF
100
10 mF
200 mF
90
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
IOUT
100 mA
200 mA
20
10
0
0.01 mA
20 mA
300 mA
100k
10
100
1k
10k
1M
10M
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
Frequency (Hz)
D012
D00113
IOUT = 20 mA
Figure 6-47. PSRR vs Frequency and IOUT
Figure 6-48. PSRR vs Frequency and COUT
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2
2
1
IOUT
1 mA, RMS noise = 8.63 mVRMS
VIN
1
3.1 V, RMS Noise = 6.66 mVRMS
3.3 V, RMS Noise = 6.71 mVRMS
3.8 V, RMS Noise = 6.70 mVRMS
20 mA, RMS noise = 6.66 mVRMS
100 mA, RMS noise = 6.69 mVRMS
200 mA, RMS noise = 6.73 mVRMS
300 mA, RMS noise = 7.76 mVRMS
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
D002
D003
VRMS BW = 10 Hz to 100 kHz
IOUT = 20 mA, VRMS BW = 10 Hz to 100 kHz
Figure 6-49. Noise vs Frequency and IOUT
Figure 6-50. Noise vs Frequency and VIN
2
2
VIN
3.1 V, RMS Noise = 6.76 mVRMS
3.3 V, RMS Noise = 6.77 mVRMS
3.8 V, RMS Noise = 7.10 mVRMS
COUT
1 mF, RMS noise = 6.65 mVRMS
10 mF, RMS noise = 6.94 mVRMS
200 mF, RMS noise = 6.56 mVRMS
1
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
D004
D006
IOUT = 300 mA, VRMS BW = 10 Hz to 100 kHz
VIN = 3.8 V, IOUT = 20 mA, VRMS BW = 10 Hz to 100 kHz
Figure 6-51. Noise vs Frequency and VIN
Figure 6-52. Noise vs Frequency and COUT
2
2
COUT
1 mF, RMS noise = 7.14 mVRMS
10 mF, RMS noise = 7.14 mVRMS
200 mF, RMS noise = 6.87 mVRMS
IOUT
20 mA, RMS noise = 7.11 mVRMS
300 mA, RMS noise = 7.04 mVRMS
1
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
D007
D010
VIN = 3.8 V, IOUT = 300 mA, VRMS BW = 10 Hz to 100 kHz
VOUT = 0.8 V, VRMS BW = 10 Hz to 100 kHz
Figure 6-53. Noise vs Frequency and COUT
Figure 6-54. Noise vs Frequency and IOUT
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2
1
2
1
IOUT
20 mA, RMS noise = 7.09 mVRMS
300 mA, RMS noise = 7.19 mVRMS
IOUT
20 mA, RMS noise = 7.21 mVRMS
300 mA, RMS noise = 7.69 mVRMS
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
D009
D008
VOUT = 0.8 V, VIN = 1.8 V, VRMS BW = 10 Hz to 100 kHz
VOUT = 5.5 V, VIN = 6 V, VRMS BW = 10 Hz to 100 kHz
Figure 6-55. Noise vs Frequency and IOUT
Figure 6-56. Noise vs Frequency and IOUT
2
1.8
1.6
1.4
1.2
1
900
850
800
750
700
650
600
550
0.8
0.6
0.4
VIN
VEN
0.2
VOUT ( IOUT = 0 mA)
VOUT ( IOUT = 1 mA)
VOUT ( IOUT = 300 mA)
0
-0.2
-0.4
0
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Time (ms)
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature (°C)
D048
VOUT = 0.8 V, VIN = 0 V to 1.8 V, VEN = 0 V to 1.8 V, VEN rises
500 µs behind VIN, VIN and VEN slew rate = 1 V/µs
From VEN = VEN(HI) to VOUT = 95% of VOUT(NOM), IOUT = 0 mA
Figure 6-57. Startup Turnon Time
Figure 6-58. Startup
2
1.8
1.6
1.4
1.2
1
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.8
0.6
0.4
0.4
VIN
VEN
0.2
0.2
VIN / VEN
VOUT ( IOUT = 0 mA)
VOUT ( IOUT = 1 mA)
VOUT ( IOUT = 300 mA)
VOUT ( IOUT = 0 mA)
VOUT ( IOUT = 1 mA)
VOUT ( IOUT = 300 mA)
0
-0.2
-0.4
0
-0.2
-0.4
0
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Time (ms)
0
200 400 600 800 1000 1200 1400 1600 1800 2000
Time (ms)
D049
D050
VOUT = 0.8 V, VIN = 0 V to 1.8 V, VEN = 0 V to 1.8 V, VEN rises
500 µs ahead of VIN, VIN and VEN slew rate = 1 V/µs
VOUT = 0.8 V, VIN = 0 V to 1.8 V, VEN = VIN,
VIN slew rate = 1 V/µs
Figure 6-59. Startup
Figure 6-60. Startup
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4.5
4
4.5
4
3.5
3
3.5
3
2.5
2
2.5
2
1.5
1.5
1
1
0.5
0
VIN
VEN
VIN
VEN
0.5
0
VOUT ( IOUT = 0 mA)
VOUT ( IOUT = 1 mA)
VOUT ( IOUT = 300 mA)
VOUT ( IOUT = 0 mA)
VOUT ( IOUT = 1 mA)
VOUT ( IOUT = 300 mA)
-0.5
-0.5
0
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Time (ms)
0
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Time (ms)
D051
D052
VIN = 0 V to 3.8 V, VEN = 0 V to 3.8 V, VEN rises 500 µs behind
VIN, VIN and VEN slew rate = 1 V/µs
VIN = 0 V to 3.8 V, VEN = 0 V to 3.8 V, VEN rises 500 µs ahead
of VIN, VIN and VEN slew rate = 1 V/µs
Figure 6-61. Startup
Figure 6-62. Startup
4.5
4
6.5
6
5.5
5
3.5
3
4.5
4
2.5
2
3.5
3
2.5
2
1.5
1
VIN
VEN
1.5
1
VIN / VEN
VOUT ( IOUT = 0 mA)
VOUT ( IOUT = 1 mA)
VOUT ( IOUT = 300 mA)
0.5
VOUT ( IOUT = 0 mA)
VOUT ( IOUT = 1 mA)
VOUT ( IOUT = 300 mA)
0.5
0
0
-0.5
-0.5
0
200 400 600 800 1000 1200 1400 1600 1800 2000
Time (ms)
0
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Time (us)
D053
D054
VIN = 0 V to 3.8 V, VEN = 0 V to 3.8 V, VEN = VIN, VIN and slew
rate = 1 V/µs
VOUT = 5.5 V, VIN = 0 V to 6.0 V, VEN = 0 V to 6.0 V, VEN rises
500 µs behind VIN, VIN and VEN slew rate = 1 V/µs
Figure 6-63. Startup
Figure 6-64. Startup
6.5
6
6.5
6
5.5
5
5.5
5
4.5
4
4.5
4
3.5
3
3.5
3
2.5
2
2.5
2
VIN
VEN
1.5
1
1.5
VIN / VEN
VOUT ( IOUT = 0 mA)
VOUT ( IOUT = 1 mA)
VOUT ( IOUT = 300 mA)
1
VOUT ( IOUT = 0 mA)
VOUT ( IOUT = 1 mA)
VOUT ( IOUT = 300 mA)
0.5
0
0.5
0
-0.5
-0.5
0
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Time (ms)
0
200 400 600 800 1000 1200 1400 1600 1800 2000
Time (ms)
D055
D056
VOUT = 5.5 V, VIN = 0 V to 6.0 V, VEN = 0 V to 6.0 V, VEN rises
500 µs ahead of VIN, VIN and VEN slew rate = 1 V/µs
VOUT = 5.5 V, VIN = 0 V to 6 V, VEN = VIN, VIN slew rate = 1
V/µs
Figure 6-65. Startup
Figure 6-66. Startup
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18
16
14
12
10
8
2.5
2.25
2
300
270
240
210
180
150
120
90
5
IIN
VIN
VEN
VOUT
IIN
VIN
VEN
VOUT
4.5
4
1.75
1.5
1.25
1
3.5
3
2.5
2
6
0.75
0.5
0.25
0
1.5
1
4
60
2
30
0.5
0
0
0
0
120 240 360 480 600 720 840 960 1080 1200
Time (µs)
0
150 300 450 600 750 900 1050 1200 1350 1500
Time (µs)
D047
D043
VOUT = 0.8 V, VIN = 1.8 V, VEN = 0 V to 1.8 V,
VEN slew rate = 1 V/µs, COUT = 10 µF
VIN = 3.8 V, VEN = 0 V to 3.8 V, VEN slew rate = 1 V/µs,
COUT = 10 µF
Figure 6-67. Inrush Current
Figure 6-68. Inrush Current
800
720
640
560
480
400
320
240
160
80
8
IIN
VIN
VEN
VOUT
7.2
6.4
5.6
4.8
4
3.2
2.4
1.6
0.8
0
0
0
150 300 450 600 750 900 1050 1200 1350 1500
Time (µs)
D044
VOUT = 5.5 V, VIN = 6.0 V, VEN = 0 V to 6.0 V,
VEN slew rate = 1 V/µs, COUT = 10 µF
Figure 6-69. Inrush Current
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7 Detailed Description
7.1 Overview
Designed to meet the needs of sensitive RF and analog circuits, the TPS7A20 provides low noise, high PSRR,
low quiescent current, as well as low line and load transient response figures. Using innovative design
techniques, the TPS7A20 offers class-leading noise performance without the need for a separate noise filter
capacitor.
The TPS7A20 is designed to operate with a single 1-µF input capacitor and a single 1-µF ceramic output
capacitor.
7.2 Functional Block Diagram
Current
Limit
IN
OUT
Bandgap
+
Active Discharge
P-Version Only
œ
œ
Error
Amp
+
+
UVLO
Internal
Controller
Thermal
Shutdown
EN
500kΩ
GND
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7.3 Feature Description
7.3.1 Low Output Noise
Any internal noise at the TPS7A20 reference voltage is reduced by a first-order, low-pass RC filter before being
passed to the output buffer stage. The low-pass RC filter has a –3-dB cut-off frequency of approximately 0.1 Hz.
During start-up, the filter resistor is bypassed to reduce output rise time; the filter begins normal operation after
the output voltage reaches the correct value.
7.3.2 Smart Enable
The enable (EN) input polarity is active high. The output voltage is enabled when the voltage of the enable input
is greater than VEN(HI) and disabled when the enable input voltage is less than VEN(LOW). If independent control
of the output voltage is not needed, connect EN to IN.
This device has a smart enable circuit to reduce quiescent current. When the voltage on the enable pin is driven
above VEN(HI), as listed in the Electrical Characteristics table, the device is enabled and the smart enable internal
pulldown resistor (REN(PULLDOWN)) is disconnected. When the enable pin is floating, the REN(PULLDOWN) is
connected and pulls the enable pin low to disable the device. The REN(PULLDOWN) value is listed in the Electrical
Characteristics table.
7.3.3 Dropout Voltage
Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output
current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the Recommended
Operating Conditions table. The pass transistor is in the ohmic or triode region of operation, and acts as a
switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed
output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than
the value required to maintain output regulation, then the output voltage falls as well.
For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the
pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for
that current scales accordingly. Use Equation 1 to calculate the RDS(ON) of the device.
VDO
RDS(ON)
=
IRATED
(1)
7.3.4 Foldback Current Limit
The device has an internal current limit circuit that protects the regulator during transient high-load current faults
or shorting events. The current limit is a hybrid brickwall-foldback scheme. The current limit transitions from a
brickwall scheme to a foldback scheme at the foldback voltage (VFOLDBACK). In a high-load current fault with the
output voltage above VFOLDBACK, the brickwall scheme limits the output current to the current limit (ICL). When
the voltage drops below VFOLDBACK, a foldback current limit activates that scales back the current as the output
voltage approaches GND. When the output is shorted, the device supplies a typical current called the short-
circuit current limit (ISC). ICL and ISC are listed in the Electrical Characteristics table.
The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the
device begins to heat up because of the increase in power dissipation. When the device is in brickwall current
limit, the pass transistor dissipates power [(VIN – VOUT) × ICL]. When the device output is shorted and the output
is below VFOLDBACK, the pass transistor dissipates power [(VIN – VOUT) × ISC]. If thermal shutdown is triggered,
the device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on.
If the output current fault condition continues, the device cycles between current limit and thermal shutdown. For
more information on current limits, see the Know Your Limits application report.
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Figure 7-1 shows a diagram of the foldback current limit.
VOUT
Brickwall
VOUT(NOM)
VFOLDBACK
Foldback
0 V
IOUT
IRATED
0 mA
ISC
ICL
Figure 7-1. Foldback Current Limit
7.3.5 Undervoltage Lockout (UVLO)
The device has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a
controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input
drops during turn on, the UVLO has hysteresis as specified in the Electrical Characteristics table.
7.3.6 Thermal Shutdown
A thermal shutdown protection circuit disables the LDO when the junction temperature (TJ) of the pass transistor
rises to TSD(shutdown) (typical). Thermal shutdown hysteresis assures that the device resets (turns on) when the
temperature falls to TSD(reset) (typical).
The thermal time-constant of the semiconductor die is fairly short, thus the device may cycle on and off when
thermal shutdown is reached until power dissipation is reduced. Power dissipation during startup can be high
from large VIN – VOUT voltage drops across the device or from high inrush currents charging large output
capacitors. Under some conditions, the thermal shutdown protection disables the device before startup
completes.
For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating
Conditions table. Operation above this maximum temperature causes the device to exceed its operational
specifications. Although the internal protection circuitry of the device is designed to protect against thermal
overload conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device
into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability.
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7.3.7 Active Discharge
An internal pulldown MOSFET connects a resistor from OUT to ground when the device is disabled to actively
discharge the output capacitance. The active discharge circuit is activated by driving EN low or by the voltage on
IN falling below the undervoltage lockout (UVLO) threshold.
Do not rely on the active discharge circuit for discharging a large amount of output capacitance after the input
supply has collapsed because reverse current can possibly flow from the output to the input. This reverse current
flow can cause damage to the device. Limit reverse current to no more than 5% of the device rated current for a
short period of time.
7.4 Device Functional Modes
7.4.1 Device Functional Mode Comparison
The Device Functional Mode Comparison table shows the conditions that lead to the different modes of
operation. See the Electrical Characteristics table for parameter values.
Table 7-1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN
VEN
IOUT
TJ
Normal operation
Dropout operation
VIN > VOUT(nom) + VDO and VIN > VIN(min)
VIN(min) < VIN < VOUT(nom) + VDO
VEN > VEN(HI)
VEN > VEN(HI)
IOUT < IOUT(max)
IOUT < IOUT(max)
TJ < TSD(shutdown)
TJ < TSD(shutdown)
Disabled
(any true condition
disables the device)
VIN < VUVLO
VEN < VEN(LOW)
Not applicable
TJ > TSD(shutdown)
7.4.2 Normal Operation
The device regulates to the nominal output voltage when the following conditions are met:
•
•
•
The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO)
The output current is less than the current limit (IOUT < ICL)
The device junction temperature is less than the thermal shutdown temperature (TJ < TSD
)
•
The enable voltage has previously exceeded the enable rising threshold voltage and has not yet decreased
to less than the enable falling threshold
7.4.3 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage
tracks the input voltage. During this mode, the transient performance of the device becomes significantly
degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load
transients in dropout can result in large output-voltage deviations.
When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO
,
directly after being in a normal regulation state, but not during startup), the pass transistor is driven into the
ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output
voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time
while the device pulls the pass transistor back into the linear region.
7.4.4 Disabled
The output of the LDO can be shut down by driving EN to less than VEN(LOW) (see the Electrical Characteristics
table). When disabled, the pass transistor is turned off, internal circuits are shut down, and the output voltage is
actively discharged to ground by an internal discharge circuit between OUT and ground.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
8.1.1 Recommended Capacitor Types
The device is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input
and output. Multilayer ceramic capacitors have become the industry standard for these types of applications and
are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and
C0G-rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of
Y5V-rated capacitors is discouraged because of large variations in capacitance.
Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and
temperature. As a rule of thumb, expect the effective capacitance to decrease by as much as 50%. The input
and output capacitors recommended in the Recommended Operating Conditions table account for an effective
capacitance of approximately 50% of the nominal value.
8.1.2 Input and Output Capacitor Requirements
Although the LDO itself is stable without an input capacitor, good analog design practice is to connect a
capacitor from IN to GND, with a value at least equal to the nominal value specified in the Recommended
Operating Conditions table. The input capacitor counteracts reactive input sources and improves transient
response, input ripple, and PSRR, and is recommended if the source impedance is greater than 0.5 Ω. When the
source resistance and inductance are sufficiently high, especially in the presence of load transients, the overall
system may be susceptible to instability (including ringing and sustained oscillation) and other performance
degradation if there is insufficient capacitance between IN and GND. A capacitor with a value greater than the
minimum may be necessary if large, fast-rise-time load or line transients are anticipated or if the device is
located more than a few centimeters from the input power source.
An output capacitor of an appropriate value helps ensure stability and improve dynamic performance. Use an
output capacitor within the range specified in the Recommended Operating Conditions table.
8.1.3 Load Transient Response
The load-step transient response is the output voltage response by the LDO to a step in load current, whereby
output voltage regulation is maintained. There are two key transitions during a load transient response: the
transition from a light to a heavy load and the transition from a heavy to a light load. The regions shown in Figure
8-1 are broken down as follows. Regions A, E, and H are where the output voltage is in steady-state.
tAt
tCt
tDt
tEt
tGt
tHt
B
F
Figure 8-1. Load Transient Waveform
During transitions from a light load to a heavy load, the:
•
Initial voltage dip is a result of the depletion of the output capacitor charge and parasitic impedance to the
output capacitor (region B)
•
Recovery from the dip results from the LDO increasing its sourcing current, and leads to output voltage
regulation (region C)
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During transitions from a heavy load to a light load, the:
•
Initial voltage rise results from the LDO sourcing a large current, and leads to the output capacitor charge to
increase (region F)
•
Recovery from the rise results from the LDO decreasing its sourcing current in combination with the load
discharging the output capacitor (region G)
A larger output capacitance reduces the peaks during a load transient but slows down the response time of the
device. A larger DC load also reduces the peaks because the amplitude of the transition is lowered and a higher
current discharge path is provided for the output capacitor.
8.1.4 Undervoltage Lockout (UVLO) Operation
The UVLO circuit ensures that the device stays disabled before its input supply reaches the minimum
operational voltage range, and ensures that the device shuts down when the input supply collapses. Figure 8-2
shows the UVLO circuit response to various input voltage events. The diagram can be separated into the
following parts:
•
•
•
Region A: The device does not start until the input reaches the UVLO rising threshold.
Region B: Normal operation, regulating device.
Region C: Brownout event above the UVLO falling threshold (UVLO rising threshold – UVLO hysteresis). The
output may fall out of regulation but the device remains enabled.
•
•
Region D: Normal operation, regulating device.
Region E: Brownout event below the UVLO falling threshold. The device is disabled in most cases and the
output falls because of the load and active discharge circuit. The device is reenabled when the UVLO rising
threshold is reached by the input voltage and a normal start-up follows.
•
•
Region F: Normal operation followed by the input falling to the UVLO falling threshold.
Region G: The device is disabled when the input voltage falls below the UVLO falling threshold to 0 V. The
output falls because of the load and active discharge circuit.
UVLO Rising Threshold
UVLO Hysteresis
VIN
C
VOUT
tAt
tBt
tDt
tEt
tFt
tGt
Figure 8-2. Typical UVLO Operation
8.1.5 Power Dissipation (PD)
Circuit reliability demands that proper consideration be given to device power dissipation, location of the circuit
on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator
must be as free as possible of other heat-generating devices that cause added thermal stresses.
As a first-order approximation, power dissipation in the regulator depends on the input-to-output voltage
difference and load conditions. Use Equation 2 to approximate PD:
PD = (VIN – VOUT) × IOUT
(2)
Power dissipation can be minimized, and thus greater efficiency achieved, by proper selection of the system
voltage rails. Proper selection allows the minimum input-to-output voltage differential to be obtained. The low
dropout of the TPS7A20 allows for maximum efficiency across a wide range of output voltages.
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The main heat conduction path for the device is through the thermal pad on the package. As such, the thermal
pad must be soldered to a copper pad area under the device. This pad area contains an array of plated vias that
conduct heat to any inner plane areas or to a bottom-side copper plane.
The maximum power dissipation determines the maximum allowable junction temperature (TJ) for the device.
According to Equation 3, power dissipation and junction temperature are most often related by the junction-to-
ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of the ambient
air (TA). Equation 4 rearranges Equation 3 for output current.
TJ = TA + (RθJA × PD)
(3)
(4)
IOUT = (TJ – TA) / [RθJA × (VIN – VOUT)]
Unfortunately, this thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the
particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the
planes. The RθJA recorded in the Thermal Information table is determined by the JEDEC standard, PCB, and
copper-spreading area, and is only used as a relative measure of package thermal performance. For a well-
designed thermal layout, RθJA is actually the sum of the X2SON package junction-to-case (bottom) thermal
resistance (RθJC(bot)) plus the thermal resistance contribution by the PCB copper.
8.1.5.1 Estimating Junction Temperature
The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures
of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal
resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics
are determined to be significantly independent of the copper-spreading area. The key thermal metrics (ΨJT and
ΨJB) are used in accordance with Equation 5 and are given in the Thermal Information table.
ΨJT : TJ = TT + ΨJT × PD and ΨJB : TJ = TB + ΨJB × PD
(5)
where:
•
•
•
PD is the power dissipated as explained in Equation 2
TT is the temperature at the center-top of the device package
TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge
8.1.5.2 Recommended Area for Continuous Operation
The operational area of an LDO is limited by the dropout voltage, output current, junction temperature, and input
voltage. The recommended area for continuous operation for a linear regulator is given in Figure 8-3 and can be
separated into the following parts:
•
•
•
Dropout voltage limits the minimum differential voltage between the input and the output (VIN – VOUT) at a
given output current level. See Section 7.4.3 for more details.
The rated output currents limits the maximum recommended output current level. Exceeding this rating
causes the device to fall out of specification.
The rated junction temperature limits the maximum junction temperature of the device. Exceeding this rating
causes the device to fall out of specification and reduces long-term reliability.
– The shape of the slope is given by Equation 4. The slope is nonlinear because the maximum-rated
junction temperature of the LDO is controlled by the power dissipation across the LDO; thus when VIN
VOUT increases the output current must decrease.
–
•
The rated input voltage range governs both the minimum and maximum of VIN – VOUT.
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Figure 8-3 shows the recommended area of operation for this device on a JEDEC-standard high-K board with a
RθJA as given in the Thermal Information table.
Output current limited by
dropout
Rated output
current
Output current limited by thermals
Limited by
minimum VIN
Limited by
maximum VIN
VIN œ VOUT (V)
Figure 8-3. Region Description of Continuous Operation Regime
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8.2 Typical Application
Figure 8-4 shows the typical application circuit for the TPS7A20. Input and output capacitances may need to be
increased above the 1 µF minimum for some applications.
VOUT
VIN
OUTPUT
1.0 µF
INPUT
1.0 µF
TPS7A20
VEN
ENABLE
GND
GND
SVA-30180501
Figure 8-4. TPS7A20 Typical Application
8.2.1 Design Requirements
Table 8-1 summarizes the design requirements for Figure 8-4.
Table 8-1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
3.1 V to 3.6 V
2.8 V
Input voltage range
Output voltage
Output current
200 mA
Maximum ambient temperature
85°C
8.2.2 Detailed Design Procedure
For this design example, the 2.8-V output version (TPS7A2028) is selected. A nominal 3.3-V input supply is
assumed. A minimum 1.0-μF input capacitor is recommended to minimize the effect of resistance and
inductance between the 3.3-V source and the LDO input. A minimum 1.0-μF output capacitor is also
recommended for stability and good load transient response. The dropout voltage (VDO) is less than 140 mV
maximum at a 2.8-V output voltage and 300-mA output current, so there are no dropout issues with a minimum
input voltage of 3.0 V and a maximum output current of 200 mA.
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8.2.3 Application Curves
4.5
4
100
90
80
70
60
50
40
30
20
10
0
IOUT
200 mA
3.5
3
2.5
2
1.5
1
0.5
0
VIN / VEN
VOUT
-0.5
0
200 400 600 800 1000 1200 1400 1600 1800 2000
Time (us)
10 20
100
1000
10000 100000 1000000 1E+7
Frequency (Hz)
D064
D065
Figure 8-5. Start-Up
Figure 8-6. PSRR
9 Power Supply Recommendations
This device is designed to operate from an input supply voltage range of 1.6 V to 6.0 V. The input supply must
be well regulated and free of spurious noise. To ensure that the output voltage is well regulated and dynamic
performance is optimum, the input supply must be at least VOUT(nom) + 0.3 V or 1.6 V, whichever is greater. TI
highly recommends using a 1-µF or greater input capacitor to reduce the impedance of the input supply,
especially during transients.
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10 Layout
10.1 Layout Guidelines
•
•
•
•
Place input and output capacitors as close to the device as possible.
Use copper planes for device connections to optimize thermal performance.
Place thermal vias around the device to distribute the heat.
Do not place a thermal via directly beneath the thermal pad of the DQN package. A via can wick solder or
solder paste away from the thermal pad joint during the soldering process, leading to a compromised solder
joint on the thermal pad.
10.2 Layout Examples
V
V
OUT
IN
C
IN
OUT
5
C
1
2
3
OUT
IN
GND
GND
GND
EN
Enable
4
N/C
Figure 10-1. DBV Package (SOT-23) Typical Layout
TPS7A20
VOUT
VIN
1
2
4
3
COUT
CIN
Power Ground
VEN
Figure 10-2. DQN Package (X2SON) Typical Layout
VIN
VOUT
TPS7A20
A1
A2
B2
COUT
CIN
B1
Power Ground
VEN
Figure 10-3. YCK Package (DSBGA) Typical Layout
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Nomenclature
Table 11-1. Device Nomenclature
PRODUCT (1) (2)
VOUT
xx(x) is the nominal output voltage. For output voltages with a resolution of 100 mV, two digits are used
in the ordering number; otherwise, three digits are used (for example, 28 = 2.8 V; 125 = 1.25 V).
P indicates an active output discharge feature. All members of the TPS7A20 family actively discharge
the output when the device is disabled.
TPS7A20xx(x)Pyyyz
yyy is the package designator.
z is the package quantity. R is for reel (3000 pieces).
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder on www.ti.com.
(2) Output voltages from 0.8 V to 5.5 V in 25-mV increments are available. Contact the factory for details and availability.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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31
Product Folder Links: TPS7A20
PACKAGE OPTION ADDENDUM
www.ti.com
30-Oct-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PTPS7A2012PDBVR
PTPS7A2012PDQNR
PTPS7A201825PDQNR
PTPS7A2018PDBVR
PTPS7A2025PDBVR
PTPS7A2025PDQNR
PTPS7A2028PDBVR
PTPS7A2029PDQNR
PTPS7A2030PDBVR
PTPS7A2030PDQNR
PTPS7A2033PDBVR
PTPS7A2045PDQNR
PTPS7A2050PDBVR
TPS7A2012PDBVR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PREVIEW
SOT-23
X2SON
X2SON
SOT-23
SOT-23
X2SON
SOT-23
X2SON
SOT-23
X2SON
SOT-23
X2SON
SOT-23
SOT-23
DBV
DQN
DQN
DBV
DBV
DQN
DBV
DQN
DBV
DQN
DBV
DQN
DBV
DBV
5
4
4
5
5
4
5
4
5
4
5
4
5
5
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Green (RoHS
& no Sb/Br)
NIPDAU | SN
Level-1-260C-UNLIM
2ATF
TPS7A2012PDQNR
TPS7A2015PDBVR
TPS7A2015PDQNR
PREVIEW
PREVIEW
ACTIVE
X2SON
SOT-23
X2SON
DQN
DBV
DQN
4
5
4
3000
3000
3000
TBD
TBD
Call TI
Call TI
Call TI
Call TI
-40 to 125
-40 to 125
-40 to 125
Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
JD
TPS7A20185PDBVR
TPS7A20185PDQNR
PREVIEW
ACTIVE
SOT-23
X2SON
DBV
DQN
5
4
3000
3000
Green (RoHS
& no Sb/Br)
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
-40 to 125
2CBF
JE
Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Oct-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS7A2018PDBVR
TPS7A2018PDQNR
TPS7A2024PDBVR
TPS7A2025PDBVR
PREVIEW
SOT-23
X2SON
SOT-23
SOT-23
DBV
5
4
5
5
3000
3000
3000
3000
Green (RoHS
& no Sb/Br)
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
2AUF
JF
ACTIVE
PREVIEW
PREVIEW
DQN
Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
DBV
Green (RoHS
& no Sb/Br)
NIPDAU | SN
Level-1-260C-UNLIM
2CCF
2AVF
DBV
Green (RoHS
& no Sb/Br)
NIPDAU | SN
Level-1-260C-UNLIM
TPS7A2025PDQNR
TPS7A2028PDBVR
PREVIEW
PREVIEW
X2SON
SOT-23
DQN
DBV
4
5
3000
3000
TBD
Call TI
Call TI
-40 to 125
-40 to 125
Green (RoHS
& no Sb/Br)
NIPDAU | SN
Level-1-260C-UNLIM
2AWF
JH
TPS7A2028PDQNR
ACTIVE
X2SON
DQN
4
3000
Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
-40 to 125
TPS7A2029PDQNR
TPS7A2030PDBVR
PREVIEW
PREVIEW
X2SON
SOT-23
DQN
DBV
4
5
3000
3000
TBD
Call TI
Call TI
-40 to 125
-40 to 125
Green (RoHS
& no Sb/Br)
NIPDAU | SN
Level-1-260C-UNLIM
2AXF
TPS7A2030PDQNR
TPS7A2033PDBVR
PREVIEW
PREVIEW
X2SON
SOT-23
DQN
DBV
4
5
3000
3000
TBD
Call TI
Call TI
-40 to 125
-40 to 125
Green (RoHS
& no Sb/Br)
NIPDAU | SN
Level-1-260C-UNLIM
2AZF
JA
TPS7A2033PDQNR
ACTIVE
X2SON
DQN
4
3000
Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
-40 to 125
TPS7A2045PDQNR
TPS7A2050PDBVR
PREVIEW
PREVIEW
X2SON
SOT-23
DQN
DBV
4
5
3000
3000
TBD
Call TI
Call TI
-40 to 125
-40 to 125
Green (RoHS
& no Sb/Br)
NIPDAU | SN
Level-1-260C-UNLIM
2B1F
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
30-Oct-2020
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Sep-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS7A2015PDQNR
TPS7A2015PDQNR
TPS7A20185PDQNR
TPS7A20185PDQNR
TPS7A2018PDQNR
TPS7A2018PDQNR
TPS7A2028PDQNR
TPS7A2028PDQNR
TPS7A2033PDQNR
TPS7A2033PDQNR
X2SON
X2SON
X2SON
X2SON
X2SON
X2SON
X2SON
X2SON
X2SON
X2SON
DQN
DQN
DQN
DQN
DQN
DQN
DQN
DQN
DQN
DQN
4
4
4
4
4
4
4
4
4
4
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
180.0
178.0
180.0
178.0
180.0
178.0
178.0
180.0
178.0
180.0
9.5
8.4
9.5
8.4
9.5
8.4
8.4
9.5
8.4
9.5
1.16
1.13
1.16
1.13
1.16
1.13
1.13
1.16
1.13
1.16
1.16
1.13
1.16
1.13
1.16
1.13
1.13
1.16
1.13
1.16
0.5
0.53
0.5
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
0.53
0.5
0.53
0.53
0.5
0.53
0.5
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Sep-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS7A2015PDQNR
TPS7A2015PDQNR
TPS7A20185PDQNR
TPS7A20185PDQNR
TPS7A2018PDQNR
TPS7A2018PDQNR
TPS7A2028PDQNR
TPS7A2028PDQNR
TPS7A2033PDQNR
TPS7A2033PDQNR
X2SON
X2SON
X2SON
X2SON
X2SON
X2SON
X2SON
X2SON
X2SON
X2SON
DQN
DQN
DQN
DQN
DQN
DQN
DQN
DQN
DQN
DQN
4
4
4
4
4
4
4
4
4
4
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
184.0
205.0
184.0
205.0
184.0
205.0
205.0
184.0
205.0
184.0
184.0
200.0
184.0
200.0
184.0
200.0
200.0
184.0
200.0
184.0
19.0
33.0
19.0
33.0
19.0
33.0
33.0
19.0
33.0
19.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
2X 0.95
1.9
3.05
2.75
1.9
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
X2SON - 0.4 mm max height
DQN0004A
PLASTIC SMALL OUTLINE - NO LEAD
1.05
0.95
A
B
1
1.05
0.95
PIN 1
INDEX AREA
C
0.4 MAX
SEATING PLANE
0.08
NOTE 6
+0.12
-0.1
0.05
0.00
0.48
(0.05) TYP
NOTE 6
2
1
3
EXPOSED
THERMAL PAD
5
2X 0.65
(0.07) TYP
NOTE 5
4
0.28
PIN 1 ID
(OPTIONAL)
NOTE 4
4X
0.15
(0.11)
0.3
0.2
0.1
C A B
0.05
C
0.30
0.15
3X
4215302/E 12/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
4. Features may not exist. Recommend use of pin 1 marking on top of package for orientation purposes.
5. Shape of exposed side leads may differ.
6. Number and location of exposed tie bars may vary.
www.ti.com
EXAMPLE BOARD LAYOUT
X2SON - 0.4 mm max height
DQN0004A
PLASTIC SMALL OUTLINE - NO LEAD
(0.86)
SYMM
SEE DETAIL
4X
4X (0.36)
(0.03)
4
4X (0.21)
1
5
SYMM
(0.65)
4X (0.18)
2
3
(
0.48)
(0.22) TYP
EXPOSED METAL
CLEARANCE
LAND PATTERN EXAMPLE
SCALE: 40X
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
EXPOSED METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
SOLDER MASK DETAIL
4215302/E 12/2016
NOTES: (continued)
7. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271)
.
8. If any vias are implemented, it is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
X2SON - 0.4 mm max height
DQN0004A
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
SYMM
4X (0.4)
4X (0.03)
4
1
4X (0.21)
5
SYMM
(0.65)
SOLDER MASK
EDGE
4X (0.22)
2
3
(
0.45)
4X (0.235)
SOLDER PASTE EXAMPLE
BASED ON 0.075 - 0.1mm THICK STENCIL
EXPOSED PAD
88% PRINTED SOLDER COVERAGE BY AREA
SCALE: 60X
4215302/E 12/2016
NOTES: (continued)
9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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