TPS7A21345PYWDJ [TI]

500mA、低噪声、超低 IQ、高 PSRR、低压降 (LDO) 稳压器 | YWD | 4 | -40 to 125;


型号：	TPS7A21345PYWDJ
厂家：	TEXAS INSTRUMENTS
描述：	500mA、低噪声、超低 IQ、高 PSRR、低压降 (LDO) 稳压器 \| YWD \| 4 \| -40 to 125 稳压器
文件：	总37页 (文件大小：4772K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS7A21

ZHCSP35A –DECEMBER 2021 –REVISED SEPTEMBER 2022

TPS7A21 500mA、低噪声、低I_Q、高PSRR LDO

1 特性

3 说明

• 超低I_Q：6.5 μA

TPS7A21 是一款超小型低压降 (LDO) 线性稳压器，可

提供 500mA 的输出电流。该器件可提供低噪声、高

PSRR 和出色的负载和线路瞬态性能，符合射频和其

他敏感模拟电路的要求。采用创新的设计技术，无需添

加外部噪声旁路电容即可提供低噪声性能。TPS7A21

器件具有低静态电流，非常适合用于电池供电系统。输

入电压范围为 2.0V 至 6.0V，输出电压范围为 0.8V 至

5.5V，可满足各种系统要求。内部精密基准电路可实

现出色的精度，可在负载、线路和温度范围内提供高达

1.5% 的最大输出电压容差。

• 输入电压范围：2.0V 至6.0V

• 输出电压范围：0.8V 至5.5V（50mV 阶跃）

• 高PSRR：1kHz 时为91dB

• 低输出电压噪声：7.7μV_RMS

• 低压降：

– 在500mA 下为175mV（最大值）(2.5V V_OUT

• 智能EN 引脚下拉

• 输出电压容差：

– ±1.5%（线路、负载和温度范围）

• 支持多种陶瓷电容器：

– 1 µF 至200 µF

• 工作结温：–40°C 至+125°C

• 封装：

)

内部软启动电路可帮助控制浪涌电流，因此可在启动过

程中更大程度地降低输入电压降。该 LDO 在与小型陶

瓷电容器搭配使用时可保持稳定，因此可实现小尺寸的

总体解决方案。

– 出色的0.602mm × 0.602mm DSBGA 封装

借助具有内部控制下拉电阻器的智能使能输入电路，即

使在 EN 引脚未连接时也能让 LDO 保持禁用状态，有

助于省去原本需要用于下拉EN 输入的外部元件。

2 应用

• 手机和平板电脑

• 可穿戴设备

封装信息⁽¹⁾

• IP 摄像机

封装尺寸（标称值）

器件型号

TPS7A21

封装

• 便携式医疗设备

• 智能仪表和现场变送器

• RF、PLL、VCO 和时钟电源

• 电机驱动器

YWD（DSBGA，4）

0.602 mm × 0.602 mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

简化原理图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SBVS398

TPS7A21

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ZHCSP35A –DECEMBER 2021 –REVISED SEPTEMBER 2022

Table of Contents

8 Applications and Implementation................................18

8.1 Application Information............................................. 18

8.2 Typical Application.................................................... 22

8.3 Power Supply Recommendations.............................24

8.4 Layout....................................................................... 24

9 Device and Documentation Support............................26

9.1 Device Support......................................................... 26

9.2 Documentation Support............................................ 26

9.3 接收文档更新通知..................................................... 26

9.4 支持资源....................................................................26

9.5 Trademarks...............................................................26

9.6 Electrostatic Discharge Caution................................26

9.7 术语表....................................................................... 26

10 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................4

6.4 Thermal Information....................................................5

6.5 Electrical Characteristics.............................................5

6.6 Typical Characteristics................................................7

7 Detailed Description......................................................14

7.1 Overview...................................................................14

7.2 Functional Block Diagram.........................................14

7.3 Feature Description...................................................15

7.4 Device Functional Modes..........................................17

Information.................................................................... 26

10.1 Mechanical Data..................................................... 27

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision * (December 2021) to Revision A (September 2022)

Page

• 向特征部分中的输出电压容差要点添加了线路、负载和温度........................................................................... 1

• 更改了特征部分中的支持多种陶瓷电容器要点..................................................................................................1

• 更改了应用部分..................................................................................................................................................1

• Changed description of OUT pin in Pin Functions: DSBGA table...................................................................... 3

• Changed typical short-circuit current limit from 300 mA to 325 mA....................................................................5

• Changed typical value of smart enable pulldown resistor from 450 kΩto 440 kΩ............................................5

• Changed Output Voltage Accuracy vs I_OUTand I_Qvs V_INfigures in Typical Characteristics section..................7

• Deleted second I_GNDvs I_OUTfigure from Typical Characteristics section...........................................................7

• Added discussion regarding sources with limited current drive capability to Smart Enable (EN) section........ 15

• Added discussion that input voltage must be high enough to enable the active discharge to Active Discharge

section.............................................................................................................................................................. 15

• Added last sentence to Dropout Operation section.......................................................................................... 17

• Changed Input voltage and Output current parameters in Design Parameters table.......................................22

• Changed Detailed Design Procedure section...................................................................................................23

• Added Device Nomenclature section................................................................................................................26

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5 Pin Configuration and Functions

OUT

GND

OUT

TOP VIEW

BOTTOM VIEW

图5-1. YWD Package, 4-Pin DSBGA

表5-1. Pin Functions: DSBGA

I/O

DESCRIPTION

DSBGA

NAME

Input voltage supply. For best transient response and to minimize input impedance, use the

recommended value or larger capacitor from IN to GND, as listed in the Recommended

Operating Conditions table. Place the input capacitor as close to the IN and GND pins of the

device as possible.

Regulated output voltage. Connect a low-equivalent series resistance (ESR) capacitor to

this pin. For best transient response, use the nominal recommended value or larger

capacitor from OUT to GND. An internal 150-Ω(typical) pulldown resistor prevents a charge

from remaining on OUT when the regulator is in shutdown mode (V_EN< V_EN(LOW)).

OUT

Enable input. A low voltage (V_EN< V_EN(LOW)) on this pin turns the regulator off and

discharges the output pin to GND through an internal 150-Ωpulldown resistor. A high

voltage (V_EN> V_EN(HI)) on this pin enables the regulator output. This pin has an internal 450-

kΩpulldown resistor to hold the regulator off by default. When V_EN> V_EN(HI), the 450-kΩ

pulldown resistor is disconnected to reduce input current.

GND

Common ground.

—

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6 Specifications

6.1 Absolute Maximum Ratings

ratings apply over operating free-air temperature range (unless otherwise noted)^{(1) (3)}

MIN

–0.3

MAX

UNIT

V_IN

Input voltage

6.5

See⁽²⁾

6.5

V_OUT

V_EN

Output voltage

–0.3

Enable input voltage

Maximum output current⁽⁴⁾

Operating junction temperature

Storage temperature

–0.3

Internally limited

-40

T_J

150

°C

T_stg

–65

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not

sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,

performance, and shorten the device lifetime.

(2) Absolute maximum V_OUTis the lesser of V_IN+ 0.3 V, or 6.5 V.

(3) All voltages are with respect to the GND pin.

(4) Internal thermal shutdown circuitry helps protect the device from permanent damage.

6.2 ESD Ratings

VALUE

±2000

±750

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

V_(ESD)

Electrostatic discharge

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

conditions apply over the operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

2.0

NOM

MAX

6.0

UNIT

V_IN

Input supply voltage

V_EN

V_OUT

I_OUT

C_IN

Enable input voltage

6.0

Nominal output voltage range

Output current

0.8

5.5

500

µF

mΩ

°C

Input capacitor⁽²⁾

C_OUT

ESR

T_J

Output capacitor⁽³⁾

200

100

125

Output capacitor effective series resistance

Operating junction temperature

–40

(1) All voltages are with respect to the GND pin.

(2) An input capacitor is not required for LDO stability. However, an input capacitor with an effective value of 0.47 μF minimum

is recommended to counteract the effect of source resistance and inductance, which may in some cases cause symptoms of system-

level instability such as ringing or oscillation, especially in the presence of load transients.

(3) Effective output capacitance of 0.4 μF minimum and 200 μF maximum over all temperature and voltage conditions is required for

stability with ESR values as high as 100 mΩ. If the ESR is reduced to 20 mΩ or lower, stable operation can be achieved with effective

output capacitance as low as 0.3 μF.

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6.4 Thermal Information

TPS7A21

YWD

UNIT

THERMAL METRIC⁽¹⁾

(DSBGA)

4 PINS

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

197.1

2.9

°C/W

R_θJC(top)

R_θJB

Junction-to-board thermal resistance

52.4

1.5

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

ψ_JT

52.4

n/a

ψ_JB

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and ICPackage Thermal Metrics and An

empirical analysis of the impact of board layout on LDO thermal performance application notes.

6.5 Electrical Characteristics

specified over operating temperature range (T_J= –40℃to +125℃), V_IN= V_OUT(NOM)+ 0.3 V or 2 V, whichever is greater,

V_EN= 1.0 V, I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF (unless otherwise noted); all typical values are at T_J= 25℃

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_IN= (V_OUT(NOM)+ 0.3 V) to 6.0 V,

I_OUT= 1 mA to 500 mA,

_OUT≥1.85 V

1.5

–1.5

Output voltage tolerance

ΔV_OUT

V_IN= (V_OUT(NOM)+ 0.3 V) to 6.0 V,

I_OUT= 1 mA to 500 mA,

V_OUT< 1.85 V

–30

V_IN= (V_OUT(NOM)+ 0.3 V) to 6.0 V,

I_OUT= 1 mA

Line regulation

Load regulation

0.03

%/V

ΔV_OUT

I_OUT= 1 mA to 500 mA

0.001

6.5

%/mA

T_J= 25°C

V_EN= V_IN, V_IN= 6.0 V,

I_OUT= 0 mA

T_J= –40°C to 85°C

T_J= –40°C to 125°C

I_GND

Quiescent current

µA

V_EN= V_IN, V_IN= 6.0 V, I_OUT= 500 mA

V_EN= 0 V (disabled), V_IN= 6.0 V, T_J= 25°C

V_EN= 0 V (disabled), V_IN= 6.0 V, T_J= –40°C to 125°C

V_IN≤ V_OUT(NOM), I_OUT= 0 mA

2900

0.15

3500

I_SHTDWN

I_Q(DO)

Shutdown current

µA

Quiescent current in dropout

0.8 V ≤V_OUT< 1.0 V ⁽¹⁾

750

530

395

260

175

1500

1.0 V ≤V_OUT< 1.2 V ⁽¹⁾

I_OUT= 500 mA,

V_OUT= 95% ×

V_OUT(NOM)

1.2 V ≤V_OUT< 1.5 V ⁽¹⁾

1.5 V ≤V_OUT< 2.5 V

2.5 V ≤V_OUT≤5.5 V

V_DO

Dropout voltage

I_CL

I_SC

Output current limit

V_OUT= 0.9 × V_OUT(NOM)

V_OUT= 0V

740

1060

325

Short-circuit current limit

f = 100 Hz

f = 1 kHz

I_OUT= 20 mA,

V_IN= V_OUT+ 1.0 V

f = 10 kHz

f = 100 kHz

f = 1 MHz

f = 100 Hz

f = 1 kHz

PSRR

Power-supply rejection ratio

I_OUT= 500 mA,

V_IN= V_OUT+ 1.0 V

f = 10 kHz

f = 100 kHz

f = 1 MHz

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6.5 Electrical Characteristics (continued)

specified over operating temperature range (T_J= –40℃to +125℃), V_IN= V_OUT(NOM)+ 0.3 V or 2 V, whichever is greater,

V_EN= 1.0 V, I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF (unless otherwise noted); all typical values are at T_J= 25℃

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

BW = 10 Hz to

100 kHz,

V_OUT= 2.8 V

I_OUT= 500 mA

7.7

V_N

Output noise voltage

µV_RMS

I_OUT= 1 mA

Output automatic discharge

pulldown resistance

R_PULLDOWN

V_IN= 2 V, V_EN< V_IL(output disabled)

150

Thermal shutdown rising

Thermal shutdown falling

T_Jrising

T_Jfalling

165

140

T_SD

°C

V_IN= 2.0 V to 6.0 V,

V_ENfalling until the output is disabled

V_EN(LOW)

V_EN(HI)

Low input threshold

High input threshold

0.3

V_IN= 2.0 V to 6.0 V,

V_ENrising until the output is enabled

0.9

V_INrising

V_INfalling

1.11

1.05

1.32

1.27

1.63

1.57

V_UVLO

UVLO threshold

V_UVLO(HYST)

I_EN

UVLO hysteresis

EN pin leakage current

V_EN= 6.0 V and V_IN= 6.0 V

100

250

R_EN(PULL-

Smart enable pulldown resistor

Turnon time

440

200

kΩ

DOWN)

t_ON

From V_EN> V_IHto V_OUT= 95% of V_OUT(NOM)

120

280

µs

(1) Dropout voltages for V_OUTvalues below or very near the UVLO threshold cannot be measured directly. Values shown are verified by

simulation.

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6.6 Typical Characteristics

V_IN= 3.6 V, V_OUT= 3.3 V, I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF, and T_A= 25°C (unless otherwise noted)

V_EN= 1 V

图6-2. Output Voltage Accuracy vs I_OUT

图6-1. Output Voltage Accuracy vs I_OUT

V_EN= 1 V

图6-3. Output Voltage Accuracy vs V_IN

图6-4. Line Regulation vs V_IN

160

150

140

130

120

110

100

T_J

-55°C

-40°C

0°C

25°C

85°C

125°C

150°C

-55 °C

-40 °C

0 °C

85 °C

125 °C

150 °C

25 °C

50 100 150 200 250 300 350 400 450 500

Output Current (mA)

50 100 150 200 250 300 350 400 450 500

Output Current (mA)

Load

V_EN= 1 V

图6-5. Load Regulation vs I_OUT

图6-6. Dropout Voltage vs I_OUT

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6.6 Typical Characteristics (continued)

V_IN= 3.6 V, V_OUT= 3.3 V, I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF, and T_A= 25°C (unless otherwise noted)

T_J

-55°C

-40°C

0°C

25°C

85°C

125°C

150°C

0.2 0.4 0.6 0.8

1.2 1.4 1.6 1.8

Output Current (mA)

V_EN= 1 V

V_EN= V_IN

图6-7. Dropout Voltage vs I_OUT

图6-8. I_Qvs V_IN

V_EN= 1 V

图6-10. I_GNDvs I_OUT

图6-9. I_Qvs V_IN

T_J

-40°C

-55°C

0°C

25°C

-10

1.8

2.4

3.6

4.2

4.8

5.4

Input Voltage (V)

V_EN= 0 V, I_OUT= 0 mA

图6-12. Shutdown Current vs V_IN

V_EN= 1 V

图6-11. I_GNDvs I_OUT

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6.6 Typical Characteristics (continued)

V_IN= 3.6 V, V_OUT= 3.3 V, I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF, and T_A= 25°C (unless otherwise noted)

3000

2500

2000

1500

1000

500

4.5

T_J

125°C

T_J

85°C

150°C

-55°C

-40°C

0°C

25°C

85°C

125°C

150°C

3.5

2.5

1.5

0.5

1.8

2.4

3.6

4.2

4.8

5.4

200

400

600

800

1000

1200

1400

Input Voltage (V)

Output Current (mA)

V_EN= 0 V, I_OUT= 0 mA

图6-13. Shutdown Current vs V_IN

V_EN= 1 V

图6-14. Foldback Current Limit

5000

4500

4000

3500

3000

2500

2000

1500

1000

500

T_J

-55°C

-40°C

0°C

25°C

85°C

125°C

150°C

5.5

0.5

1.5

2.5

3.5

4.5

V_EN- V_IN(V)

V_EN= 6 V, I_OUT= 0 mA

图6-16. Enable Pin Leakage Current vs V_EN–V_IN

图6-15. Enable Logic Threshold vs Temperature

V_EN= 0.3 V

图6-18. Output Pulldown Resistance vs

图6-17. Smart Enable Pulldown Resistor vs Temperature and

Temperature and V_IN

V_IN

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6.6 Typical Characteristics (continued)

V_IN= 3.6 V, V_OUT= 3.3 V, I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF, and T_A= 25°C (unless otherwise noted)

V_EN= 1 V

V_IN= 0 V to 4.3 V, slew rate = 1 V/μs, I_OUT= 500 mA

图6-19. V_INUVLO Threshold vs Temperature

图6-20. Start-Up With V_ENBefore V_IN

V_IN= 0 V to 4.3 V, slew rate = 1 V/μs, I_OUT= 0 mA

图6-21. Start-Up With V_ENAfter V_IN

V_IN= 0 V to 4.3 V, slew rate = 1 V/μs, I_OUT= 500 mA

图6-22. Start-Up With V_ENAfter V_IN

V_IN= 4.3 V, V_EN= 0 V to 4.3 V, slew rate = 1 V/μs,

I_OUT= 0 mA, C_OUT= 1 μF

V_IN= 0 V to 4.3 V, slew rate = 1 V/μs, I_OUT= 500 mA

图6-23. Start-Up With V_EN= V_IN

图6-24. Start-Up Inrush Current

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6.6 Typical Characteristics (continued)

V_IN= 3.6 V, V_OUT= 3.3 V, I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF, and T_A= 25°C (unless otherwise noted)

V_IN= 4.3 V, V_EN= 0 V to 4.3 V, slew rate = 1 V/μs,

V_EN= V_EN(HI)to V_OUT= 95% of V_OUT(NOM), I_OUT= 0 mA

I_OUT= 0 mA, C_OUT= 10 μF

图6-25. Start-Up Inrush Current

图6-26. Start-Up Turn-On Time vs Temperature

-1

-2

-3

-1

-2

-3

-1

-2

-1

-2

V_OUT

V_IN

V_OUT

V_IN

90 100

Time (µs)

V_EN= V_IN, t_r= t_f= 5 μs, I_OUT= 500 mA

V_EN= V_IN, t_r= t_f= 5 μs, I_OUT= 1 mA

图6-27. Line Transient From 3.6 V to 4.6 V

图6-28. Line Transient From 3.6 V to 4.6 V

750

500

120

750

500

320

240

160

250

-250

-500

-750

-1000

-1250

-250

-500

-750

-1000

-1250

-30

-60

-90

-120

-80

-160

-240

-320

I_OUT

V_OUT

I_OUT

V_OUT

15 30 45 60 75 90 105 120 135 150 165 180

Time (µs)

V_EN= V_IN, t_r= t_f= 200 ns

V_EN= V_IN, t_r= t_f= 1 μs

图6-29. Load Transient From 1 mA to 500 mA

图6-30. Load Transient From 1 mA to 500 mA

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6.6 Typical Characteristics (continued)

V_IN= 3.6 V, V_OUT= 3.3 V, I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF, and T_A= 25°C (unless otherwise noted)

750

500

120

750

500

320

240

160

250

-250

-500

-750

-1000

-1250

-250

-500

-750

-1000

-1250

-30

-60

-90

-120

-80

-160

-240

-320

I_OUT

V_OUT

I_OUT

V_OUT

80 100 120 140 160 180 200

Time (µs)

V_EN= V_IN, t_r= t_f= 200 ns

V_EN= V_IN, t_r= t_f= 1 μs

图6-32. Load Transient From 0 mA to 500 mA

图6-31. Load Transient From 0 mA to 500 mA

V_EN= V_IN

V_EN= V_IN, I_OUT= 20 mA

图6-33. PSRR vs Frequency and I_OUT

图6-34. PSRR vs Frequency and V_IN

V_EN= V_IN, I_OUT= 500 mA

V_EN= V_IN, I_OUT= 20 mA

图6-35. PSRR vs Frequency and V_IN

图6-36. PSRR vs Frequency and C_OUT

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6.6 Typical Characteristics (continued)

V_IN= 3.6 V, V_OUT= 3.3 V, I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF, and T_A= 25°C (unless otherwise noted)

V_IN

3.6 V, RMS Noise = 6.73 ꢀV_RMS

4.75 V, RMS Noise = 6.70 ꢀV_RMS

6.0 V, RMS Noise = 6.65 ꢀV_RMS

0.5

0.2

0.1

0.05

0.02

0.01

0.005

0.002

0.001

100

10k

100k

10M

Frequency (Hz)

V_EN= V_IN, I_OUT= 20 mA

V_EN= V_IN, I_OUT= 500 mA

图6-38. Noise vs Frequency and V_IN

图6-37. PSRR vs Frequency and C_OUT

V_IN

3.6 V, RMS Noise = 6.90 ꢀV_RMS

4.75 V, RMS Noise = 7.32 ꢀV_RMS

6.0 V, RMS Noise = 11.54 ꢀV_RMS

0.5

0.2

0.1

0.05

0.02

0.01

0.005

0.002

0.001

100

10k

100k

10M

Frequency (Hz)

V_EN= V_IN, I_OUT= 500 mA

V_EN= V_IN

图6-39. Noise vs Frequency and V_IN

图6-40. Noise vs Frequency and I_OUT

C_OUT

0.5

0.47 µF, RMS Noise = 6.63 ꢀV_RMS

1.0 µF, RMS Noise = 6.71 ꢀV_RMS

10 µF, RMS Noise = 7.20 ꢀV_RMS

200 uF, RMS Noise = 7.69 ꢀV_RMS

0.47 µF, RMS Noise = 6.84 ꢀV_RMS

1.0 µF, RMS Noise = 6.96 ꢀV_RMS

10 µF, RMS Noise = 7.16 ꢀV_RMS

200 uF, RMS Noise = 8.74 ꢀV_RMS

0.3

0.2

0.3

0.2

0.1

0.05

0.03

0.02

0.03

0.02

0.01

0.005

0.003

0.002

0.003

0.002

0.001

100

10k

100k

10M

100

10k

100k

10M

Frequency (Hz)

V_EN= V_IN, I_OUT= 20 mA

图6-41. Noise vs Frequency and C_OUT

V_EN= V_IN, I_OUT= 500 mA

图6-42. Noise vs Frequency and C_OUT

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7 Detailed Description

7.1 Overview

Designed to meet the needs of sensitive RF and analog circuits, the TPS7A21 provides low noise, high PSRR,

and low quiescent current, as well as excellent line and load transient response. The TPS7A21 achieves

excellent noise performance without the need for a separate noise filter capacitor.

The TPS7A21 is designed to operate properly with a single 1-µF input capacitor and a single 1-µF ceramic

output capacitor. The effective output capacitance must be at least 0.4 µF across all operating voltage and

temperature conditions.

7.2 Functional Block Diagram

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7.3 Feature Description

7.3.1 Smart Enable (EN)

The enable pin (EN) is active high. The output is enabled when the voltage applied to EN is greater than V_EN(HI)

and disabled when the applied voltage is less than V_EN(LOW). If external control of the output voltage is not

needed, connect EN to IN. This device has a smart enable circuit to reduce quiescent current. When the voltage

on the enable pin is driven above V_EN(HI), the output is enabled and the smart enable internal pulldown resistor

(R_EN(PULLDOWN)) is disconnected. When the enable pin is floating, the R_EN(PULLDOWN)is connected and pulls the

enable pin low to disable the output. In addition to reducing quiescent current, the smart pulldown helps ensure

that the logic level is correct even when EN is driven from a source that has limited current drive capability. The

R_EN(PULLDOWN)value is listed in the Electrical Characteristics table.

7.3.2 Low Output Noise

Any internal noise at the TPS7A21 reference voltage is reduced by a first-order, low-pass RC filter before being

passed to the output buffer stage. The low-pass RC filter has a –3-dB cutoff frequency of approximately 0.1 Hz.

During start-up, the filter resistor is bypassed to reduce output rise time. The filter begins normal operation after

the output voltage reaches the nominal value.

7.3.3 Active Discharge

The regulator has an internal metal-oxide-semiconductor field-effect transistor (MOSFET) that connects a

pulldown resistor between the output and ground pins when the device is disabled to actively discharge the

output voltage. The voltage on IN must be high enough to turn on the pulldown MOSFET; when V_INis too low to

provide sufficient V_GSon the pulldown MOSFET, the pulldown circuit is not active. The active discharge circuit is

activated by the enable pin, or by the voltage on IN falling below the undervoltage lockout (UVLO) threshold.

Do not rely on the active discharge circuit for discharging a large amount of output capacitance after the input

supply has collapsed because reverse current can possibly flow from the output to the input. This reverse current

flow can cause damage to the device. Limit reverse current to no more than 5% of the device rated current for

only a short period of time.

7.3.4 Dropout Voltage

Dropout voltage (V_DO) is defined as the input voltage minus the output voltage (V_IN– V_OUT) at the rated output

current (I_RATED), when the pass transistor is fully on. I_RATEDis the maximum I_OUTlisted in the Recommended

Operating Conditions table. The pass transistor is in the ohmic or triode region of operation, and acts as a

switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed

output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than

the value required to support output regulation, then the output voltage falls as well.

For a CMOS regulator, the dropout voltage is determined by the drain-source, on-state resistance (R_DS(ON)) of

the pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage

for that current scales accordingly. 方程式1 calculates the R_DS(ON)of the device.

V_DO

R_DS(ON)

I_RATED

(1)

7.3.5 Foldback Current Limit

The TPS7A21 has an internal current limit circuit that protects the regulator during transient high-load current

faults or shorting events. The current limit is a hybrid brick-wall foldback scheme. The current limit transitions

from a brick-wall scheme to a foldback scheme at the foldback voltage (V_FOLDBACK).

In a high-load current fault with the output voltage above V_FOLDBACK, the brick-wall scheme limits the output

current to the current limit (I_CL). When the output voltage drops below V_FOLDBACK, a foldback current limit

activates that scales back the current when the output voltage approaches GND. When the output is shorted, the

device supplies a typical current called the short-circuit current limit (I_SC). I_CLand I_SCare listed in the Electrical

Characteristics table.

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The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the

regulator begins to heat up because of the increase in power dissipation. When the device is in brick-wall current

limit, the pass transistor dissipates power [(V_IN– V_OUT) × I_CL]. When the output is shorted and the output

voltage is less than V_FOLDBACK, the pass transistor dissipates power [(V_IN– V_OUT) × I_SC]. If thermal shutdown is

triggered, the device turns off. After the device cools down, the internal thermal shutdown circuit turns the device

back on. If the output current fault condition persists, the device cycles between current limit and thermal

shutdown. For more information on current limits, see the Know Your Limits application note.

图7-1 shows a diagram of the foldback current limit.

V_OUT

Brickwall

V_OUT(NOM)

V_FOLDBACK

Foldback

0 V

I_OUT

I_RATED

0 mA

I_SC

I_CL

图7-1. Foldback Current Limit

7.3.6 Undervoltage Lockout

An independent undervoltage lockout (UVLO) circuit monitors the input voltage, allowing a controlled and

consistent turn on and turn off of the output voltage. If the input voltage drops during load transients (when the

device output is enabled), the UVLO has built-in hysteresis to prevent unwanted turn off.

7.3.7 Thermal Overload Protection (T_SD

)

Thermal shutdown disables the output when the junction temperature T_Jrises to the shutdown temperature

threshold T_SD. The thermal shutdown circuit hysteresis requires the temperature to fall to a lower temperature

before turning on again. The thermal time constant of the semiconductor die is fairly short; thus, the device may

cycle on and off when thermal shutdown is reached until power dissipation is reduced.

Power dissipation during start up can be high from large V_IN– V_OUTvoltage drops across the device or from

high inrush currents charging large output capacitors. Under some conditions, the thermal shutdown protection

disables the device before start up completes.

For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating

Conditions table. Operation above this maximum temperature causes the regulator to exceed operational

specifications.

Although the thermal shutdown circuitry is designed to protect against temporary thermal overload conditions,

this circuitry is not intended to replace proper thermal design. Continuously running the regulator into thermal

shutdown or above the maximum recommended junction temperature reduces long-term reliability.

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7.4 Device Functional Modes

7.4.1 Device Functional Mode Comparison

表 7-1 shows the conditions that lead to the different modes of operation. See the Electrical Characteristics table

for parameter values.

表7-1. Device Functional Mode Comparison

PARAMETER

OPERATING MODE

V_IN

V_EN

I_OUT

T_J

Normal operation

Dropout operation

V_IN> V_OUT(nom)+ V_DOand V_IN> V_IN(min)

V_IN(min)< V_IN< V_OUT(nom)+ V_DO

I_OUT< I_OUT(max)

T_J< T_SD(shutdown)

V_EN≥V_EN(HI)

Disabled

(any true condition

disables the device)

V_IN< V_UVLO

Not applicable

V_EN≤V_EN(LOW)

T_J≥T_SD(shutdown)

7.4.2 Normal Operation

The device regulates to the nominal output voltage when the following conditions are met:

• The input voltage is greater than the nominal output voltage plus the dropout voltage (V_OUT(nom)+ V_DO

• The output current is less than the current limit (I_OUT< I_CL)

)

• The device junction temperature is less than the thermal shutdown temperature (T_J< T_SD

)

• The enable voltage has previously exceeded the enable rising threshold voltage and has not yet decreased

to less than the enable falling threshold

7.4.3 Dropout Operation

If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other

conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage

tracks the input voltage. During this mode, the transient performance of the device becomes significantly

degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load

transients in dropout can result in large output-voltage deviations.

When the device is in a steady dropout state (defined as when the device is in dropout, V_IN< V_OUT(NOM)+ V_DO

directly after being in a normal regulation state, but not during start up), the pass transistor is driven into the

ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output

voltage plus the dropout voltage (V_OUT(NOM)+ V_DO), the output voltage can overshoot for a short period of time

while the device pulls the pass transistor back into the linear region.

For output currents less than about 200 mA, the slope of the dropout voltage curve is lower than for higher

currents. This slope helps maintain better performance when the LDO is in dropout.

7.4.4 Disabled

The output of the device can be shut down by forcing the voltage of the enable pin to less than V_EN(LOW)). When

disabled, the pass transistor is turned off, internal circuits are shut down, and the output voltage is actively

discharged to ground by an internal discharge circuit from the output to ground.

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8 Applications and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

8.1 Application Information

8.1.1 Recommended Capacitor Types

The device is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input

and output. Multilayer ceramic capacitors have become the industry standard for many types of applications and

are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and

C0G-rated dielectric materials provide good capacitive stability across temperature, whereas the use of Y5V-

rated capacitors is discouraged because of large variations in capacitance.

Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and

temperature. Consult the manufacturer data sheet to verify performance. Generally, expect the effective

capacitance to decrease by as much as 50%. The input and output capacitors recommended in the

Recommended Operating Conditions table account for an effective capacitance of approximately 50% of the

nominal value.

8.1.2 Input and Output Capacitor Requirements

Although the LDO is stable without an input capacitor, good design practice is to connect a capacitor from IN to

GND, with a value at least equal to the nominal value specified in the Recommended Operating Conditions

table. The input capacitor counteracts reactive input sources and improves transient response, input ripple, and

PSRR, and is recommended if the source impedance is greater than 0.5 Ω. When the source resistance and

inductance are sufficiently high, the overall system can be susceptible to instability (including ringing and

sustained oscillation) and other performance degradation if there is insufficient capacitance between IN and

GND. A capacitor with a value greater than the minimum may be necessary if there are large fast-rise-time load

or line transients or if the LDO is located more than a few centimeters from the input power source.

An output capacitor of an appropriate value helps ensure stability and improve dynamic performance. Use an

output capacitor within the range specified in the Recommended Operating Conditions table.

8.1.3 Load Transient Response

The load-step transient response is the output voltage response by the LDO to a step in load current, whereby

output voltage regulation is maintained. There are two key transitions during a load transient response: the

transition from a light to a heavy load and the transition from a heavy to a light load. The regions shown in 图8-1

are broken down as follows. Regions A, E, and H are where the output voltage is in a steady state.

tAt

tCt

tDt

tEt

tGt

tHt

图8-1. Load Transient Waveform

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During transitions from a light load to a heavy load, the:

• Initial voltage dip is a result of the depletion of the output capacitor charge and parasitic impedance to the

output capacitor (region B)

• Recovery from the dip results from the LDO increasing the sourcing current, and leads to output voltage

regulation (region C)

During transitions from a heavy load to a light load, the:

• Initial voltage rise results from the LDO sourcing a large current, and leads to the output capacitor charge to

increase (region F)

• Recovery from the rise results from the LDO decreasing the sourcing current in combination with the load

discharging the output capacitor (region G)

A larger output capacitance reduces the peaks during a load transient but slows down the response time of the

device. A larger DC load also reduces the peaks because the amplitude of the transition is lowered and a higher

current discharge path is provided for the output capacitor.

8.1.4 Undervoltage Lockout (UVLO) Operation

The UVLO circuit verifies that the device stays disabled before the input supply reaches the minimum

operational voltage range, and makes sure that the device shuts down when the input supply collapses. 图 8-2

shows the UVLO circuit response to various input voltage events. The diagram can be separated into the

following parts:

• Region A: The device does not start until the input reaches the UVLO rising threshold.

• Region B: Normal operation, regulating device.

• Region C: Brownout event above the UVLO falling threshold (UVLO rising threshold –UVLO hysteresis).

The device remains enabled even if the output falls out of regulation.

• Region D: Normal operation, regulating device.

• Region E: Brownout event below the UVLO falling threshold. The device is disabled in most cases and the

output falls because of the load and active discharge circuit. The device is re-enabled when the UVLO rising

threshold is reached by the input voltage and a normal start-up follows.

• Region F: Normal operation followed by the input falling to the UVLO falling threshold.

• Region G: The device is disabled when the input voltage falls below the UVLO falling threshold to 0 V. The

output falls because of the load and active discharge circuit.

UVLO Rising Threshold

UVLO Hysteresis

V_IN

V_OUT

tAt

tBt

tDt

tEt

tFt

tGt

图8-2. Typical UVLO Operation

8.1.5 Power Dissipation (P_D)

Circuit reliability demands that proper consideration be given to device power dissipation, location of the circuit

on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator

must be as free as possible of other heat-generating devices that cause added thermal stresses.

As a first-order approximation, power dissipation in the regulator depends on the input-to-output voltage

difference and load conditions. Use 方程式2 to approximate P_D:

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P_D= (V_IN–V_OUT) × I_OUT

(2)

Power dissipation can be minimized, and thus greater efficiency achieved, by proper selection of the system

voltage rails. Proper selection allows the minimum input-to-output voltage differential to be obtained. The low

dropout of the TPS7A21 allows for maximum efficiency across a wide range of output voltages.

The main heat conduction path for the device is through the thermal pad on the package. As such, the thermal

pad must be soldered to a copper pad area under the device. This pad area contains an array of plated vias that

conduct heat to any inner plane areas or to a bottom-side copper plane.

The maximum allowable junction temperature (T_J) determines the maximum power dissipation for the device.

According to 方程式 3, power dissipation and junction temperature are most often related by the junction-to-

ambient thermal resistance (R_θJA) of the combined PCB and device package and the temperature of the

ambient air (T_A).

T_J= T_A+ (R_θJA× P_D)

(3)

方程式4 rearranges 方程式3 for output current.

I_OUT= (T_J–T_A) / [R_θJA× (V_IN–V_OUT)]

(4)

Unfortunately, this thermal resistance (R_θJA) is highly dependent on the heat-spreading capability built into the

particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the

planes. The R_θJArecorded in the Thermal Information table is determined by the JEDEC standard, PCB, and

copper-spreading area, and is only used as a relative measure of package thermal performance. For a well-

designed thermal layout, R_θJAis actually the sum of the package junction-to-case (bottom) thermal resistance

(R_θJC(bot)) plus the thermal resistance contribution by the PCB copper.

8.1.6 Estimating Junction Temperature

The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures

of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal

resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics

are determined to be significantly independent of the copper-spreading area. The key thermal metrics (Ψ_JTand

Ψ_JB) are used in accordance with 方程式5 and are given in the Thermal Information table.

Ψ_JT: T_J= T_T+ Ψ_JT× P_Dand Ψ_JB: T_J= T_B+ Ψ_JB× P_D

(5)

where:

• P_Dis the power dissipated as explained in the Power Dissipation (P_D) section

• T_Tis the temperature at the center-top of the device package

• T_Bis the PCB surface temperature measured 1 mm from the device package and centered on the package

edge

8.1.7 Recommended Area For Continuous Operation

The operational area of an LDO is limited by the dropout voltage, output current, junction temperature, and input

voltage. The recommended area for continuous operation for a linear regulator is given in 图 8-3 and can be

separated into the following parts:

• Dropout voltage limits the minimum differential voltage between the input and the output (V_IN–V_OUT) at a

given output current level. See the Dropout Operation section for more details.

• The rated output currents limits the maximum recommended output current level. Exceeding this rating

causes the device to fall out of specification.

• The rated junction temperature limits the maximum junction temperature of the device. Exceeding this rating

causes the device to fall out of specification and reduces long-term reliability.

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– The shape of the slope is depicted in the third region of 图8-3. The slope is nonlinear because the

maximum-rated junction temperature of the LDO is controlled by the power dissipation across the LDO.

Thus, when V_IN–V_OUTincreases the output current must decrease.

• The rated input voltage range governs both the minimum and maximum of V_IN–V_OUT

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图 8-3 shows the recommended area of operation for this device on a JEDEC-standard high-K board with a

_θJA, as given in the Thermal Information table.

Output current limited by

dropout

Rated output

current

Output current limited by thermals

Limited by

minimum V_IN

Limited by

maximum V_IN

V_INœ V_OUT(V)

图8-3. Region Description of Continuous Operation Regime

8.2 Typical Application

图 8-4 shows the typical application circuit for the TPS7A21. Input and output capacitances may need to be

increased above the 1 µF minimum value for some applications.

V_OUT

V_IN

OUTPUT

INPUT

1 µF

TPS7A21

V_EN

ENABLE

GND

图8-4. TPS7A21 Typical Application

8.2.1 Design Requirements

表8-1 summarizes the design requirements for the typical application circuit.

表8-1. Design Parameters

DESIGN PARAMETER

Input voltage

EXAMPLE VALUE

3.6 V

Output voltage

3.3 V

Output current

400 mA

85°C

Maximum ambient temperature

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8.2.2 Detailed Design Procedure

For this design example, the 3.3-V output version (TPS7A2133) is selected. A nominal 3.6-V input supply is

assumed. Use a minimum 1.0-μF input capacitor to minimize the effect of resistance and inductance between

the 3.6-V source and the LDO input. A minimum 1.0-μF output capacitor is also used for stability and good load

transient response. The dropout voltage (V_DO) is less than 150 mV maximum at a 3.3-V output voltage and 500-

mA output current, so there are no dropout issues with a minimum input voltage of 3.5 V and a maximum output

current of 400 mA.

With an ambient temperature of 85°C, an input voltage of 3.6 V and an output current of 400 mA, the die

temperature is 0.3 V × 0.4 A × 197.1°C/W + 85°C = 108.7°C.

8.2.2.1 Power Dissipation and Device Operation

The permissible power dissipation for any package is a measure of the capability of the device to pass heat from

the power source (the junctions of the device) to the ultimate heat sink of the ambient environment. Thus, power

dissipation is dependent on the ambient temperature and the thermal resistance across the various interfaces

between the die junction and ambient air.

方程式6 calculates the maximum allowable power dissipation for the device in a given package:

P_D-MAX= ((T_J-MAX–T_A) / R_θJA

)

(6)

方程式7 represents the actual power being dissipated in the device:

P_D= (V_IN–V_OUT) × I_OUT

(7)

These two equations establish the relationship between the maximum power dissipation allowed resulting from

thermal consideration, the voltage drop across the device, and the continuous current capability of the device.

Use these two equations to determine the optimum operating conditions for the device in the application.

In applications where lower power dissipation (P_D) or excellent package thermal resistance (R_θJA) is present,

the maximum ambient temperature (T_A-MAX) can be increased.

In applications where high power dissipation or poor package thermal resistance is present, the maximum

ambient temperature (T_A-MAX) may have to be derated. As given by 方程式 8, T_A-MAXis dependent on the

maximum operating junction temperature (T_J-MAX-OP= 125°C), the maximum allowable power dissipation in the

device package in the application (P_D-MAX), and the junction-to ambient thermal resistance of the device or

package in the application (R_θJA):

T_A-MAX= (T_J-MAX-OP–(R_θJA× P_D-MAX))

(8)

Alternately, if T_A-MAXcan not be derated, the P_Dvalue must be reduced. This reduction can be accomplished by

reducing V_INin the V_IN–V_OUTterm as long as the minimum V_INis met, or by reducing the I_OUTterm, or by some

combination of the two.

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8.2.3 Application Curves

V_EN= V_IN, I_OUT= 500 mA

V_IN= 0 V to 4.3 V, slew rate = 1 V/μs, I_OUT= 1 mA

图8-6. PSRR vs Frequency and V_IN

图8-5. Start-Up With V_ENAfter V_IN

8.3 Power Supply Recommendations

This LDO is designed to operate from an input supply voltage range of 2.0 V to 5.5 V. The input supply must be

well regulated and free of spurious noise. To ensure that the TPS7A21 output voltage is well regulated and

dynamic performance is optimum, the input supply must be at least V_OUT+ 0.3 V. A minimum capacitor value of

1 µF is required to be within 1 cm of the IN pin.

8.4 Layout

8.4.1 Layout Guidelines

The dynamic performance of the TPS7A21 is dependent on the layout of the PCB. PCB layout practices that are

adequate for typical LDOs may degrade the PSRR, noise, or transient performance of the TPS7A21.

Best performance is achieved by placing C_INand C_OUTon the same side of the PCB as the TPS7A21, and as

close to the package as practical. The ground connections for C_INand C_OUTmust be back to the TPS7A21

ground pin using as wide and short a copper trace as practical.

Connections using long trace lengths, narrow trace widths, or connections through vias must be avoided. These

connections add parasitic inductances and resistance that results in inferior performance, especially during

transient conditions.

8.4.1.1 DSBGA Mounting

The DSBGA package requires specific mounting techniques, which are detailed in the AN-1112 DSBGA Wafer

Level Chip Scale Package application note. For best results during assembly, alignment ordinals on the PCB can

be used to facilitate placement of the DSBGA device.

8.4.1.2 DSBGA Light Sensitivity

Exposing the DSBGA device to direct light may cause incorrect operation of the device. Light sources such as

halogen lamps can affect electrical performance if they are situated in proximity to the device. Light with

wavelengths in the red and infrared part of the spectrum have the most detrimental effect; thus, the fluorescent

lighting used inside most buildings has very little effect on performance.

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ZHCSP35A –DECEMBER 2021 –REVISED SEPTEMBER 2022

8.4.2 Layout Example

V_IN

V_OUT

C_OUT

C_IN

Power Ground

V_EN

图8-7. Typical DSBGA Layout

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ZHCSP35A –DECEMBER 2021 –REVISED SEPTEMBER 2022

9 Device and Documentation Support

9.1 Device Support

9.1.1 Device Nomenclature

表9-1. Device Nomenclature⁽¹⁾⁽²⁾

PRODUCT

V_OUT

xx(x) is the nominal output voltage. For output voltages with a resolution of 100 mV, two digits are

used in the ordering number; otherwise, three digits are used (for example, 28 = 2.8 V; 125 = 1.25

V).

TPS7A21xx(x)Pyyyz

P indicates an active output discharge feature. All members of the TPS7A21 family actively

discharge the output when the device is disabled.

yyy is the package designator.

z is the package quantity. J is for 12000-piece reel.

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the

device product folder at www.ti.com.

(2) Output voltages from 0.8 V to 5.5 V in 50-mV increments are available. Contact the factory for details and availability.

9.2 Documentation Support

9.2.1 Related Documentation

For related documentation see the following:

• Texas Instruments, AN-1112 DSBGA Wafer Level Chip Scale Package application report

• Texas Instruments, QFN/SON PCB Attachment application report

• Texas Instruments, TPS7A21EVM-059 Evaluation Module user guide

9.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

9.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

9.5 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

9.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

9.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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TPS7A21

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ZHCSP35A –DECEMBER 2021 –REVISED SEPTEMBER 2022

10.1 Mechanical Data

PACKAGE OUTLINE

YWD0004A-C01

PowerWCSP - 0.3 mm max height

POWER CHIP SCALE PACKAGE

0.622

0.582

PIN A1 INDEX

AREA

0.622

0.582

0.3 MAX

SEATING PLANE

0.05 C

0.10

0.07

0.35

SYMM

0.35

0.175

0.155

SYMM

0.015

C A B

4228730/A 05/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

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ZHCSP35A –DECEMBER 2021 –REVISED SEPTEMBER 2022

EXAMPLE BOARD LAYOUT

YWD0004A-C01

PowerWCSP - 0.3 mm max height

POWER CHIP SCALE PACKAGE

(0.35)

4X ( 0.165)

SYMM

(0.35)

SYMM

(R0.05) TYP

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 80X

0.0375 MAX

ALL AROUND

0.0375 MIN

ALL AROUND

METAL UNDER

SOLDER MASK

METAL EDGE

SOLDER MASK

OPENING

EXPOSED

METAL

SOLDER MASK

OPENING

EXPOSED METAL

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4228730/A 05/2022

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).

www.ti.com

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Product Folder Links: TPS7A21

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ZHCSP35A –DECEMBER 2021 –REVISED SEPTEMBER 2022

EXAMPLE STENCIL DESIGN

YWD0004A-C01

PowerWCSP - 0.3 mm max height

POWER CHIP SCALE PACKAGE

(0.385)

4X ( 0.2)

SYMM

(0.385)

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.075 mm THICK STENCIL

SCALE: 80X

4228730/A 05/2022

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may oﬀer better paste release.

www.ti.com

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PACKAGE OPTION ADDENDUM

www.ti.com

17-Mar-2023

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS7A2128PYWDJ

TPS7A2133BPYWDJ

TPS7A2133PYWDJ

TPS7A21345PYWDJ

ACTIVE

DSBGA

YWD

12000 RoHS & Green

Call TI

Level-1-260C-UNLIM

-40 to 125

Samples

Call TI

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

17-Mar-2023

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TPS7A21 :

Automotive : TPS7A21-Q1

•

NOTE: Qualified Version Definitions:

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

•

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

17-Mar-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS7A2128PYWDJ

TPS7A2133BPYWDJ

TPS7A2133PYWDJ

TPS7A21345PYWDJ

DSBGA

YWD

12000

180.0

8.4

0.69

0.37

2.0

8.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

17-Mar-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS7A2128PYWDJ

TPS7A2133BPYWDJ

TPS7A2133PYWDJ

TPS7A21345PYWDJ

DSBGA

YWD

12000

182.0

20.0

Pack Materials-Page 2

PACKAGE OUTLINE

YWD0004A

PowerWCSP - 0.3 mm max height

POWER CHIP SCALE PACKAGE

0.657

0.597

PIN A1 INDEX

AREA

0.657

0.597

0.3 MAX

SEATING PLANE

0.05 C

0.10

0.07

0.35

SYMM

0.35

D: Max = 0.592 mm, Min =0.532 mm

E: Max = 0.592 mm, Min =0.532 mm

0.175

0.155

0.015

C A B

SYMM

4225173/A 07/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

YWD0004A

PowerWCSP - 0.3 mm max height

POWER CHIP SCALE PACKAGE

(0.35)

4X ( 0.165)

SYMM

(0.35)

(R0.05) TYP

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 80X

0.0375 MAX

ALL AROUND

0.0375 MIN

ALL AROUND

METAL UNDER

SOLDER MASK

METAL EDGE

SOLDER MASK

OPENING

EXPOSED

METAL

SOLDER MASK

OPENING

EXPOSED METAL

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4225173/A 07/2019

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).

www.ti.com

EXAMPLE STENCIL DESIGN

YWD0004A

PowerWCSP - 0.3 mm max height

POWER CHIP SCALE PACKAGE

(0.385)

4X ( 0.2)

SYMM

(0.385)

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.075 mm THICK STENCIL

SCALE: 80X

4225173/A 07/2019

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

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TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TPS7A21345PYWDJ [TI]

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TPS7A2436DBVR

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