TPS7A24125DBVR [TI]

具有使能功能的 200mA、18V、超低 IQ、低压降 (LDO) 稳压器 | DBV | 5 | -40 to 125;


型号：	TPS7A24125DBVR
厂家：	TEXAS INSTRUMENTS
描述：	具有使能功能的 200mA、18V、超低 IQ、低压降 (LDO) 稳压器 \| DBV \| 5 \| -40 to 125 稳压器
文件：	总29页 (文件大小：1558K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS7A24

ZHCSK49E –AUGUST 2019 –REVISED SEPTEMBER 2022

TPS7A24 200mA、18V、超低I_Q低压降稳压器

1 特性

3 说明

• 超低I_Q：2.0μA

• 输入电压：2.4 V 至18 V

• 可用输出电压选项：

TPS7A24 低压降 (LDO) 线性稳压器支持 2.4V 至 18V

的输入电压范围，并具有超低的静态电流 (I_Q)。这些特

性能帮助现代电器满足日益严苛的能源要求，并有助于

延长便携式电源解决方案的电池寿命。

– 固定：1.25 V 至5.5 V

– 可调节：1.24 V 至17.75 V

• 在温度范围内的精度为1.25%

• 低压降：200 mA 时为250 mV（最大值）

• 主动过冲下拉保护

TPS7A24 有固定电压和可调节电压两种版本可供选

用。固定电压版本无需外部电阻器，可最大限度减小印

刷电路板 (PCB) 尺寸。为获得更大的灵活性或更高的

输出电压，可调节电压版本使用反馈电阻器将输出电压

设置为1.24V 到17.75V 之间。两种版本都具有1.25%

的输出调节精度，可对微控制器 (MCU) 基准电压进行

精密调节。

• 热关断保护和过流保护

• 工作结温：–40°C 至+125°C

• 与1µF 输出电容器一起工作时保持稳定

• 封装：5 引脚SOT-23 封装

在电流为 200mA 时，TPS7A24 LDO 的最大压降小于

250mV，因此它比标准线性稳压器的工作效率更高。

此最大压降使得在 3.55V 输入电压 (V_IN) 至 3.3V 输出

电压(V_OUT) 范围内的效率达到了92.8%。

2 应用

• 烟雾和热量探测器

• 恒温器

• 运动检测器（PIR、uWave 等）

• 无线电动工具

• 电器电池组

• 电表

• 水表

封装信息⁽¹⁾

封装尺寸（标称值）

器件型号

TPS7A24

封装

DBV（SOT-23，5)

2.90mm × 1.60mm

(1) 如需了解所有可用封装，请参阅产品说明书末尾的封装选项附

录。

典型应用电路

静态电流与输入电压

(V_OUT= 1.24V，I_OUT= 0A)

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SBVS386

TPS7A24

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ZHCSK49E –AUGUST 2019 –REVISED SEPTEMBER 2022

Table of Contents

7.4 Device Functional Modes..........................................13

8 Application and Implementation..................................14

8.1 Application Information............................................. 14

8.2 Typical Application.................................................... 17

8.3 Power Supply Recommendations.............................19

8.4 Layout....................................................................... 20

9 Device and Documentation Support............................21

9.1 Device Support......................................................... 21

9.2 接收文档更新通知..................................................... 21

9.3 支持资源....................................................................21

9.4 Trademarks...............................................................21

9.5 Electrostatic Discharge Caution................................21

9.6 术语表....................................................................... 21

10 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................5

6.4 Thermal Information....................................................5

6.5 Electrical Characteristics.............................................6

6.6 Typical Characteristics................................................7

7 Detailed Description......................................................10

7.1 Overview...................................................................10

7.2 Functional Block Diagrams....................................... 10

7.3 Feature Description...................................................11

Information.................................................................... 21

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision D (May 2022) to Revision E (September 2022)

Page

• Changed Dropout Voltage vs V_INand Dropout Voltage vs I_OUTfigures in Typical Characteristics section.........7

Changes from Revision C (January 2022) to Revision D (May 2022)

Page

•

Added Output voltage accuracy at 25 ℃to Electrical Characteristics table......................................................6

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5 Pin Configuration and Functions

GND

OUT

GND

OUT

Not to scale

图5-1. DBV Package (Adjustable),

图5-2. DBV Package (Fixed), 5-Pin SOT-23 (Top

5-Pin SOT-23 (Top View)

View)

表5-1. Pin Functions

I/O

DESCRIPTION

DBV

(Adjustable)

DBV

(Fixed)

NAME

Enable pin. Drive EN greater than V_EN(HI)to enable the regulator. Drive EN

less than V_EN(LOW)to put the regulator into low-current shutdown. Do not

float this pin. If not used, connect EN to IN.

Input

Feedback pin. Input to the control-loop error amplifier. This pin is used to set

the output voltage of the device with the use of external resistors. For

adjustable-voltage version devices only.

Input

—

GND

Ground pin.

—

Input pin. For best transient response and to minimize input impedance, use

the recommended value or larger capacitor from IN to ground as listed in the

Recommended Operating Conditions table. Place the input capacitor as

close to the IN and GND pins of the device as possible.

Input

No internal connection. For fixed-voltage version devices only. This pin can

be floated but the device has better thermal performance with this pin tied to

GND.

—

Output pin. A capacitor is required from OUT to ground for stability. For best

transient response, use the nominal recommended value or larger capacitor

from OUT to ground. Follow the recommended capacitor value as listed in

the Recommended Operating Conditions table. Place the output capacitor as

close to the OUT and GND pins of the device as possible.

OUT

Output

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

UNIT

V_IN

V_IN+ 0.3⁽³⁾

5.5

V_OUT

–0.3

Voltage⁽²⁾

V_FB

–0.3

V_EN

–0.3

Current

Maximum output

Operating junction, T_J

Storage, T_stg

Internally limited

–50

150

Temperature

°C

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) All voltages with respect to GND.

(3) V_IN+ 0.3 V or 20 V (whichever is smaller).

6.2 ESD Ratings

VALUE

±2000

±1000

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

(1) JEDEC document JEP155 states that 2-kV HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process.

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6.3 Recommended Operating Conditions

MIN

2.4

1.24

1.25

NOM

MAX

UNIT

V_IN

Input voltage

V_OUT

I_OUT

V_EN

Output voltage (adjustable version)

Output voltage (fixed version)

Output current

18 - V_DO

5.5

200

Enable voltage

(1)

C_IN

C_OUT

T_J

Input capacitor

μF

°C

(1)

Output capacitor

2.2

100

125

Operating junction temperature

–40

(1) All capacitor values are assumed to derate to 50% of the nominal capacitor value.

6.4 Thermal Information

TPS7A24

THERMAL METRIC⁽¹⁾

DBV (SOT23-5)

5 PINS

167.8

86.7

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

38.4

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

14.5

ψ_JT

38.1

ψ_JB

R_θJC(bot)

n/a

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

reports application report.

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6.5 Electrical Characteristics

specified at T_J= –40°C to + 125°C, V_IN= V_OUT(nom)+ 0.5 V or V_IN= 2.4 V (whichever is greater), FB tied to OUT, I_OUT= 1

mA, V_EN= 2 V, and C_IN= 1 μF, C_OUT= 2.2 μF ceramic (unless otherwise noted); typical values are at T_J= 25°C

PARAMETER

TEST CONDITIONS

Adjustable version, V_OUT= V_FB

Fixed output versions, T_J= -40℃to 125℃

Fixed output versions, T_J= 25 ℃

Adjustable version only

MIN

TYP

MAX

1.26

1.25

0.5

UNIT

1.22

1.24

V_OUT

Output voltage accuracy

–1.25

–0.5

V_OUT

Output voltage accuracy

Feedback voltage

Line regulation⁽¹⁾

V_FB

1.24

0.25

0.5

ΔV_OUT(ΔVIN)

ΔV_OUT(ΔIOUT)

(V_OUT(nom)+ 0.5 V or 2.4 V) ≤V_IN≤18 V

1 mA ≤I_OUT≤200 mA

–0.25

–0.5

Load regulation

I_OUT= 0 mA

4.5

I_GND

Ground pin current

µA

I_OUT= 1 mA

I_SHUTDOWN

Shutdown current

Output current limit

FB pin current

325

410

650

620

V_EN≤0.4 V, V_IN= 2.4 V, I_out= 0 mA

V_OUT= 0.9 × V_OUT(nom)

I_CL

I_FB

250

I_OUT= 100 mA

110

160

250

V_DO

Dropout voltage⁽²⁾

I_OUT= 200 mA

f = 10 Hz

Power-supply rejection

ratio

PSRR

f = 100 Hz

f = 1 kHz

V_n

Output noise voltage

UVLO threshold rising

UVLO hysteresis

BW = 10 Hz to 100 kHz, V_OUT= 1.24 V

V_INrising

300

2.15

μV_RMS

V_UVLO(RISING)

V_UVLO(HYS)

V_{UVLO(FALLING)}

1.95

2.35

2.25

UVLO threshold falling

V_INfalling

1.85

0.9

2.09

Enable pin high-level input

voltage

V_EN(HI)

Device enabled

Enable pin low-level input

voltage

V_EN(LOW)

I_EN

Device disabled

0.4

EN pin current

V_EN= 18 V

°C

Thermal shutdown

temperature

T_SD(shutdown)

Shutdown, temperature increasing

165

Thermal shutdown reset

temperature

T_SD(reset)

Reset, temperature decreasing

145

°C

(1) V_out(nom)+ 0.5 V or 2.4 V (whichever is greater).

(2) V_DOis measured with V_IN= 0.97 × V_OUT(nom)for fixed output voltage versions. V_DOis not measured for fixed output voltage versions

when V_OUT≤2.5 V. For the adjustable output device, V_DOis measured with V_FB= 0.97 × V_FB(nom).

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6.6 Typical Characteristics

at operating temperature T_J= 25°C, I_OUT= 1 mA, V_EN= 0.9 V, C_IN= 2.2 µF, C_OUT= 2.2 μF, and V_IN= V_OUT(typ)+ 0.8 V or

2.4 V (whichever is greater), unless otherwise noted; typical values are at T_J= 25°C

0.8

0.6

0.4

0.2

0.4

0.3

0.2

0.1

-50èC

-40èC

0èC

25èC

T_J

85èC

125èC

150èC

-50°C

-40°C

0°C

25°C

85°C

125°C

150°C

-0.1

-0.2

-0.3

-0.4

-0.5

-0.6

-0.2

-0.4

-0.6

-0.8

-1

0.025 0.05 0.075 0.1 0.125 0.15 0.175 0.2

Output Current (A)

Input Voltage (V)

D002

V_OUT= 1.24 V

I_OUT= 1 mA

图6-2. Load Regulation vs I_OUT

图6-1. Line Regulation vs V_IN

135

200

180

160

140

120

100

T_J

120

105

-50°C

-40°C

0°C

25°C

85°C

125°C

150°C

-50°C

-40°C

0°C

25°C

85°C

125°C

150°C

Input Voltage (V)

I_OUT= 100 mA

图6-4. Dropout Voltage vs V_IN

I_OUT= 10 mA

图6-3. Dropout Voltage vs V_IN

250

240

210

180

150

120

T_J

-50°C

225

200

175

150

125

100

-40°C

0°C

25°C

85°C

125°C

150°C

T_J

-50°C

-40°C

0°C

25°C

85°C

125°C

150°C

0.025 0.05 0.075 0.1 0.125 0.15 0.175 0.2

Output Current (A)

Input Voltage (V)

I_OUT= 200 mA

图6-5. Dropout Voltage vs V_IN

V_IN= 2.4 V

图6-6. Dropout Voltage vs I_OUT

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6.6 Typical Characteristics (continued)

at operating temperature T_J= 25°C, I_OUT= 1 mA, V_EN= 0.9 V, C_IN= 2.2 µF, C_OUT= 2.2 μF, and V_IN= V_OUT(typ)+ 0.8 V or

2.4 V (whichever is greater), unless otherwise noted; typical values are at T_J= 25°C

240

210

180

150

120

0.54

0.52

0.5

T_J

-50°C

-40°C

0°C

25°C

85°C

125°C

150°C

T_J

-50°C

-40°C

0°C

25°C

85°C

125°C

150°C

0.48

0.46

0.44

0.42

0.4

0.38

0.36

0.025 0.05 0.075 0.1 0.125 0.15 0.175 0.2

Output Current (A)

Input Voltage (V)

V_IN= 18 V

图6-7. Dropout Voltage vs I_OUT

图6-8. Current Limit vs V_IN

-50èC

-40èC

0èC

85èC

125èC

150èC

25èC

Input Voltage (V)

V_OUT= 1.24 V, I_OUT= 1 mA

V_OUT= 1.24 V, I_OUT= 0 A

图6-10. I_Qvs V_IN

图6-9. I_GNDvs V_IN

240

210

180

150

120

T_J

-50°C

-40°C

0°C

25°C

85°C

125°C

150°C

-50èC

-40èC

0èC

25èC

85èC

125èC

150èC

2.4

2.7

3.3

3.6 3.9

Input Voltage (V)

4.2

4.5

4.8

5.1

0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2

Output Current (A)

V_OUT= 3.3 V, I_OUT= 0 A

V_OUT= 1.24 V

图6-11. I_Qvs V_IN

图6-12. I_GNDvs I_OUT

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6.6 Typical Characteristics (continued)

at operating temperature T_J= 25°C, I_OUT= 1 mA, V_EN= 0.9 V, C_IN= 2.2 µF, C_OUT= 2.2 μF, and V_IN= V_OUT(typ)+ 0.8 V or

2.4 V (whichever is greater), unless otherwise noted; typical values are at T_J= 25°C

0.8

0.7

0.6

0.5

0.4

2.3

2.2

2.1

V_EN(LOW)

V_EN(HIGH)

V_UVLO-(V_INFalling)

V_UVLO+(V_INRising)

1.9

-50

-25

100

125

150

-50

-25

100

125

150

Temperature (èC)

V_OUT= 1.24 V, I_OUT= 1 mA

V_OUT= 1.24 V, 2.4 V ≤V_IN≤18 V

图6-13. V_ENvs Temperature

图6-14. UVLO Thresholds vs Temperature

100

I_OUT

10 mA

100 mA

200 mA

0.5

0.2

0.1

0.05

I_OUT

0.02

0.01

0.01A, RMS Noise = 280.2 mV_RMS

0.1A, RMS Noise = 283.2 mV_RMS

0.2 A, RMS Noise = 285.2 mV_RMS

0.005

100

10k

Frequency (Hz)

100k

10M

100

10k

Frequency (Hz)

100k

10M

V_OUT= 1.24 V, C_IN= 1 μF, C_OUT= 1 μF, C_FF= 10 nF, V_RMS

V_OUT= 1.24 V, C_IN= 0 μF, C_OUT= 1 μF

图6-15. PSRR vs Frequency and I_OUT

BW = 10 Hz to 100 kHz

图6-16. Output Noise (V_n) vs Frequency and I_OUT

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7 Detailed Description

7.1 Overview

The TPS7A24 is an 18-V, low quiescent current, low-dropout (LDO) linear regulator. The low I_Qperformance

makes the TPS7A24 an excellent choice for battery-powered or line-power applications that are expected to

meet increasingly stringent standby-power standards. The fixed-output versions have the advantage of providing

better accuracy with fewer external components, whereas the adjustable version has the flexibility for a far wider

output voltage range.

The 1.25% accuracy over temperature makes this device an excellent choice for meeting a wide range of

microcontroller power requirements.

For increased reliability, the TPS7A24 also incorporates overcurrent, overshoot pulldown, and thermal shutdown

protection. The operating junction temperature is –40°C to +125°C, and adds margin for applications concerned

with higher working ambient temperatures.

7.2 Functional Block Diagrams

TPS7A2401

(Adjustable Version)

OUT

Current

Limit

Thermal

Shutdown

UVLO

Band-Gap

Reference

GND

Logic

图7-1. Adjustable Version Block Diagram

TPS7A24

(Fixed Version)

OUT

Current

Limit

Thermal

Shutdown

R₁

UVLO

R₂

Band-Gap

Reference

GND

Logic

图7-2. Fixed Version Block Diagram

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7.3 Feature Description

7.3.1 Output Enable

The enable pin for the device is an active-high pin. The output voltage is enabled when the voltage of the enable

pin is greater than the high-level input voltage of the EN pin and disabled with the enable pin voltage is less than

the low-level input voltage of the EN pin. If independent control of the output voltage is not needed, connect the

enable pin to the input of the device.

7.3.2 Dropout Voltage

Dropout voltage (V_DO) is defined as the input voltage minus the output voltage (V_IN– V_OUT) at the rated output

current (I_RATED), where the pass transistor is fully on. I_RATEDis the maximum I_OUTlisted in the Recommended

Operating Conditions table. The pass transistor is in the ohmic or triode region of operation, and acts as a

switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed

output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than

the nominal output regulation, then the output voltage falls as well.

For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (R_DS(ON)) of the

pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for

that current scales accordingly. The following equation calculates the R_DS(ON)of the device.

V_DO

R_DS(ON)

I_RATED

(1)

7.3.3 Current Limit

The device has an internal current limit circuit that protects the regulator during transient high-load current faults

or shorting events. The current limit is a brick-wall scheme. In a high-load current fault, the brick-wall scheme

limits the output current to the current limit (I_CL). I_CLis listed in the Electrical Characteristics table.

The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the

device begins to heat up because of the increase in power dissipation. When the device is in brick-wall current

limit, the pass transistor dissipates power [(V_IN– V_OUT) × I_CL]. If thermal shutdown is triggered, the device turns

off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If the output

current fault condition continues, the device cycles between current limit and thermal shutdown. For more

information on current limits, see the Know Your Limits application report.

图7-3 shows a diagram of the current limit.

V_OUT

Brickwall

V_OUT(NOM)

0 V

I_OUT

I_RATED

0 mA

I_CL

图7-3. Current Limit

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7.3.4 Undervoltage Lockout (UVLO)

The device has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a

controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input

drops during turn on, the UVLO has hysteresis as specified in the Electrical Characteristics table.

7.3.5 Thermal Shutdown

The device contains a thermal shutdown protection circuit to disable the device when the junction temperature

(T_J) of the pass transistor rises to T_SD(shutdown)(typical). Thermal shutdown hysteresis assures that the device

resets (turns on) when the temperature falls to T_SD(reset)(typical).

The thermal time-constant of the semiconductor die is fairly short, thus the device may cycle on and off when

thermal shutdown is reached until power dissipation is reduced. Power dissipation during start up can be high

from large V_IN– V_OUTvoltage drops across the device or from high inrush currents charging large output

capacitors. Under some conditions, the thermal shutdown protection disables the device before start up

completes.

When the thermal limit is triggered with load currents near the value of the current limit, the output may oscillate

prior to the output switching off.

For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating

Conditions table. Operation above this maximum temperature causes the device to exceed operational

specifications. Although the internal protection circuitry of the device is designed to protect against thermal

overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device

into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability.

7.3.6 Active Overshoot Pulldown Circuitry

This device has pulldown circuitry connected to V_OUT. This circuitry is a 100-μA current sink, in series with a

5.5-kΩ resistor, controlled by V_EN. When V_ENis below V_EN(LOW), the pulldown circuitry is disabled and the LDO

output is in high-impedance mode.

If the output voltage is more than 2% above nominal voltage when V_EN≥ V_EN(LOW), the pulldown circuitry turns

on and the output is pulled down until the output voltage is within 2% from the nominal voltage. This feature

helps reduce overshoot during the transient response.

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7.4 Device Functional Modes

7.4.1 Device Functional Mode Comparison

表 7-1 shows the conditions that lead to the different modes of operation. See the Electrical Characteristics table

for parameter values.

表7-1. Device Functional Mode Comparison

PARAMETER

OPERATING MODE

V_IN

V_EN

I_OUT

T_J

Normal operation

Dropout operation

V_IN> V_OUT(nom)+ V_DOand V_IN> V_IN(min)

V_IN(min)< V_IN< V_OUT(nom)+ V_DO

V_EN> V_EN(HI)

I_OUT< I_OUT(max)

T_J< T_SD(shutdown)

Disabled

(any true condition

disables the device)

V_IN< V_UVLO

V_EN< V_EN(LOW)

Not applicable

T_J> T_SD(shutdown)

7.4.2 Normal Operation

The device regulates to the nominal output voltage when the following conditions are met:

• The input voltage is greater than the nominal output voltage plus the dropout voltage (V_OUT(nom)+ V_DO

• The output current is less than the current limit (I_OUT< I_CL)

)

• The device junction temperature is less than the thermal shutdown temperature (T_J< T_SD

)

• The enable voltage has previously exceeded the enable rising threshold voltage and has not yet decreased

to less than the enable falling threshold

7.4.3 Dropout Operation

If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other

conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage

tracks the input voltage. During this mode, the transient performance of the device becomes significantly

degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load

transients in dropout can result in large output-voltage deviations.

When the device is in a steady dropout state (defined as when the device is in dropout, V_IN< V_OUT(NOM)+ V_DO

directly after being in a normal regulation state, but not during start up), the pass transistor is driven into the

ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output

voltage plus the dropout voltage (V_OUT(NOM)+ V_DO), the output voltage can overshoot for a short period of time

while the device pulls the pass transistor back into the linear region.

7.4.4 Disabled

The output of the device can be shutdown by forcing the voltage of the enable pin to less than the maximum EN

pin low-level input voltage (see the Electrical Characteristics table). When disabled, the pass transistor is turned

off and internal circuits are shutdown.

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8 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

8.1 Application Information

8.1.1 Adjustable Device Feedback Resistors

The adjustable-version device requires external feedback divider resistors to set the output voltage. V_OUTis set

using the feedback divider resistors, R₁and R₂, according to the following equation:

V_OUT= V_FB× (1 + R₁/ R₂)

(2)

To ignore the FB pin current error term in the V_OUTequation, set the feedback divider current to 100x the FB pin

current listed in the Electrical Characteristics table. This setting provides the maximum feedback divider series

resistance, as shown in the following equation:

R₁+ R₂≤V_OUT/ (I_FB× 100)

(3)

8.1.2 Recommended Capacitor Types

The device is designed to be stable using low equivalent series resistance (ESR) capacitors at the input and

output. Multilayer ceramic capacitors have become the industry standard for these types of applications and are

recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and C0G-

rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of Y5V-

rated capacitors is discouraged because of large variations in capacitance.

Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and

temperature. As a rule of thumb, expect the effective capacitance to decrease by as much as 50%. The input

and output capacitors recommended in the Recommended Operating Conditions table account for an effective

capacitance of approximately 50% of the nominal value.

8.1.3 Input and Output Capacitor Requirements

Although an input capacitor is not required for stability, good analog design practice is to connect a capacitor

from IN to GND. This capacitor counteracts reactive input sources and improves transient response, input ripple,

and PSRR. An input capacitor is recommended if the source impedance is more than 0.5 Ω. A higher value

capacitor may be necessary if large, fast load transient or line transients are anticipated or if the device is

located several inches from the input power source.

Dynamic performance of the device is improved with the use of an output capacitor. Use an output capacitor

within the range specified in the Recommended Operating Conditions table for stability.

The effective output capacitance value is recommended to not exceed 50 µF.

8.1.4 Reverse Current

Excessive reverse current can damage this device. Reverse current flows through the intrinsic body diode of the

pass transistor instead of the normal conducting channel. At high magnitudes, this current flow degrades the

long-term reliability of the device.

Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute

maximum rating of V_OUT≤V_IN+ 0.3 V.

• If the device has a large C_OUTand the input supply collapses with little or no load current

• The output is biased when the input supply is not established

• The output is biased above the input supply

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If reverse current flow is expected in the application, external protection is recommended to protect the device.

Reverse current is not limited in the device, so external limiting is required if extended reverse voltage operation

is anticipated.

图8-1 shows one approach for protecting the device.

Schottky Diode

Internal Body Diode

OUT

Device

C_OUT

C_IN

GND

图8-1. Example Circuit for Reverse Current Protection Using a Schottky Diode

图8-2 shows another, more commonly used, approach in high input voltage applications.

OUT

Device

C_OUT

C_IN

GND

图8-2. Reverse Current Prevention Using a Diode Before the LDO

8.1.5 Feed-Forward Capacitor (C_FF)

For the adjustable-voltage version device, a feed-forward capacitor (C_FF) can be connected from the OUT pin to

the FB pin. C_FFimproves transient, noise, and PSRR performance, but is not required for regulator stability.

Recommended C_FFvalues are listed in the Recommended Operating Conditions table. A higher capacitance

C_FFcan be used; however, the start-up time increases. For a detailed description of C_FFtradeoffs, see the Pros

and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator application report.

8.1.6 Power Dissipation (P_D)

Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed

circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few

or no other heat-generating devices that cause added thermal stress.

To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference

and load conditions. 方程式4 calculates power dissipation (P_D).

P_D= (V_IN–V_OUT) × I_OUT

(4)

备注

Power dissipation can be minimized, and therefore greater efficiency can be achieved, by correct

selection of the system voltage rails. For the lowest power dissipation use the minimum input voltage

required for correct output regulation.

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For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal

pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an

array of plated vias that conduct heat to additional copper planes for increased heat dissipation.

The maximum power dissipation determines the maximum allowable ambient temperature (T_A) for the device.

According to 方程式 5, power dissipation and junction temperature are most often related by the junction-to-

ambient thermal resistance (R_θJA) of the combined PCB and device package and the temperature of the

ambient air (T_A).

T_J= T_A+ (R_θJA× P_D)

(5)

Thermal resistance (R_θJA) is highly dependent on the heat-spreading capability built into the particular PCB

design, and therefore varies according to the total copper area, copper weight, and location of the planes. The

junction-to-ambient thermal resistance listed in the Thermal Information table is determined by the JEDEC

standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance.

8.1.7 Estimating Junction Temperature

The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures

of the linear regulator when in-circuit on a typical PCB board application. These metrics are not thermal

resistance parameters and instead offer a practical and relative way to estimate junction temperature. These psi

metrics are determined to be significantly independent of the copper area available for heat-spreading. The

Thermal Information table lists the primary thermal metrics, which are the junction-to-top characterization

parameter (ψ_JT) and junction-to-board characterization parameter (ψ_JB). These parameters provide two

methods for calculating the junction temperature (T_J). As described in 方程式 6, use the junction-to-top

characterization parameter (ψ_JT) with the temperature at the center-top of device package (T_T) to calculate the

junction temperature. As described in 方程式 7, use the junction-to-board characterization parameter (ψ_JB) with

the PCB surface temperature 1 mm from the device package (T_B) to calculate the junction temperature.

T_J= T_T+ ψ_JT× P_D

(6)

where:

• P_Dis the dissipated power

• T_Tis the temperature at the center-top of the device package

T_J= T_B+ ψ_JB× P_D

(7)

where

• T_Bis the PCB surface temperature measured 1 mm from the device package and centered on the package

edge

For detailed information on the thermal metrics and how to use them, see the Semiconductor and IC Package

Thermal Metrics application report.

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8.1.8 Special Consideration for Line Transients

During a line transient, the response of this LDO to a very large or fast input voltage change can cause a brief

shutdown lasting up to a few hundred microseconds from the voltage transition. This shutdown can be avoided

by reducing the voltage step size, increasing the transition time, or a combination of both. 图 8-3 provides a

boundary to follow to avoid this behavior. If necessary, reduce slew rate and the voltage step size to stay below

the curve.

1.8

1.6

1.4

1.2

0.8

0.6

0.4

0.2

V_INDelta

Input Voltage Step Size (V)

10 11 12 13 14 15

图8-3. Recommended Input Voltage Step and Slew Rate in a Line Transient

8.2 Typical Application

图8-4. Generating a 3.3-V Rail From a Multicell Power Bank

8.2.1 Design Requirements

表8-1 summarizes the design requirements for 图8-4.

表8-1. Design Parameters

PARAMETER

DESIGN VALUES

5.3 V

V_IN

V_OUT

3.3 V ±1.25%

< 5 μA

I_(IN)(no load)

I_OUT(max)

T_A

200 mA

57.88°C (max)

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8.2.2 Detailed Design Procedure

Select a 3.3-V output, fixed or adjustable device to generate the 3.3-V rail. The fixed-version LDO has internal

feedback divider resistors, and thus has lower quiescent current. The adjustable-version LDO requires external

feedback divider resistors, and is described in the Selecting Feedback Divider Resistors section.

8.2.2.1 Transient Response

As with any regulator, increasing the output capacitor value reduces over- and undershoot magnitude, but

increases transient response duration.

8.2.2.2 Selecting Feedback Divider Resistors

For this design example, V_OUTis set to 5 V. The following equations set the output voltage:

V_OUT= V_FB× (1 + R₁/ R₂)

(8)

(9)

R₁+ R₂≤V_OUT/ (I_FB× 100)

For improved output accuracy, use 方程式 9 and I_FB(TYP)= 10 nA as listed in the Electrical Characteristics table

to calculate the upper limit for series feedback resistance, R₁+ R₂≤5 MΩ.

The control-loop error amplifier drives the FB pin to the same voltage as the internal reference (V_FB= 1.24 V as

listed in the Electrical Characteristics table). Use 方程式 8 to determine the ratio of R₁/ R₂= 1.66. Use this ratio

and solve 方程式 9 for R₂. Now calculate the upper limit for R₂≤ 1.24 MΩ. Select a standard value resistor of

R₂= 1.18 MΩ.

Reference 方程式8 and solve for R₁:

R₁= (V_OUT/ V_FB–1) × R₂

(10)

From 方程式10, R₁= 1.96 MΩcan be determined. From 方程式8, select V_OUT= 3.299 V.

8.2.2.3 Thermal Dissipation

Junction temperature can be determined using the junction-to-ambient thermal resistance (R_θJA) and the total

power dissipation (P_D). Use 方程式 11 to calculate the power dissipation. Multiply P_Dby R_θJAand add the

ambient temperature (T_A), as 方程式12 shows, to calculate the junction temperature (T_J).

P_D= (I_GND+ I_OUT) × (V_IN–V_OUT

)

(11)

(12)

T_J= R_θJA× P_D+ T_A

方程式 13 calculates the maximum ambient temperature. 方程式 14 calculates the maximum ambient

temperature for typical design applications.

T_A(MAX)= T_J(MAX)–(R_θJA× P_D)

(13)

(14)

T_A(MAX)= 125°C –[167.8°C/W × (5.3 V –3.3 V) × 0.2A] = 57.88°C

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8.2.3 Application Curve

-10

-20

-30

-40

-50

-60

-70

-80

V_OUT

V_IN

-450 -300 -150

150 300 450 600 750 900 1050

Time (µsec)

图8-5. Line Transient (4.3 V to 5.3 V)

8.3 Power Supply Recommendations

The device is designed to operate with an input supply range of 2.4 V to 18 V. If the input supply is noisy,

additional input capacitors with low ESR can help improve output noise performance. Connect a low output

impedance power supply to the input pin of the TPS7A24. In order to optimize regulation, see the Feature

Description section for more information on operation modes and performance features.

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8.4 Layout

8.4.1 Layout Guidelines

• Place input and output capacitors as close to the device pins as possible

• Use copper planes for device connections to optimize thermal performance

• Place thermal vias around the device to distribute heat

8.4.2 Layout Examples

GND

V_IN

V_OUT

PLANE

C_OUT

C_IN

R₁

R₂

GND

PLANE

图8-6. Adjustable Version Layout Example

V_OUT

V_IN

C_IN

C_OUT

GND PLANE

Represents via used for

application specific connections

图8-7. Fixed Version Layout Example

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9 Device and Documentation Support

9.1 Device Support

9.1.1 Device Nomenclature

表9-1. Device Nomenclature⁽¹⁾

PRODUCT

V_OUT

xx(x) is the nominal output voltage. For output voltages with a resolution of 100 mV, two digits are

used in the ordering number; for output voltages with a resolution of 50 mV, three digits are used

(for example, 28 = 2.8 V; 125 = 1.25 V). 01 indicates adjustable output version.

yyy is the package designator.

TPS7A24xx(x)yyyz

z is the package quantity. R is for large quantity reel

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the

device product folder at www.ti.com.

9.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

9.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

9.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

9.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

9.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

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11-Dec-2022

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS7A2401DBVR

TPS7A24125DBVR

TPS7A2418DBVR

TPS7A2425DBVR

TPS7A2430DBVR

TPS7A2433DBVR

TPS7A2436DBVR

TPS7A2450DBVR

ACTIVE

SOT-23

DBV

3000 RoHS & Green

NIPDAU | SN

Level-1-260C-UNLIM

-40 to 125

1XFF

1XTF

1XLF

1XKF

1XJF

1XHF

1XIF

Samples

NIPDAU | SN

1XGF

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

11-Dec-2022

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

2-Jul-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS7A2401DBVR

TPS7A24125DBVR

TPS7A2418DBVR

TPS7A2425DBVR

TPS7A2430DBVR

TPS7A2433DBVR

TPS7A2436DBVR

TPS7A2450DBVR

SOT-23

DBV

3000

180.0

8.4

3.2

1.4

4.0

8.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

2-Jul-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS7A2401DBVR

TPS7A24125DBVR

TPS7A2418DBVR

TPS7A2425DBVR

TPS7A2430DBVR

TPS7A2433DBVR

TPS7A2436DBVR

TPS7A2450DBVR

SOT-23

DBV

3000

210.0

185.0

35.0

Pack Materials-Page 2

PACKAGE OUTLINE

DBV0005A

SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR

3.0

2.6

0.1 C

1.75

1.45

0.90

PIN 1

INDEX AREA

(0.1)

2X 0.95

1.9

3.05

2.75

1.9

(0.15)

0.5

0.3

0.15

0.00

(1.1)

TYP

0.2

C A B

NOTE 5

0.25

GAGE PLANE

0.22

0.08

TYP

0.6

0.3

TYP

SEATING PLANE

4214839/G 03/2023

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Refernce JEDEC MO-178.

4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.25 mm per side.

5. Support pin may differ or may not be present.

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EXAMPLE BOARD LAYOUT

DBV0005A

SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR

PKG

5X (1.1)

5X (0.6)

SYMM

(1.9)

2X (0.95)

(R0.05) TYP

(2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

EXPOSED METAL

0.07 MIN

ARROUND

0.07 MAX

ARROUND

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4214839/G 03/2023

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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EXAMPLE STENCIL DESIGN

DBV0005A

SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR

PKG

5X (1.1)

5X (0.6)

SYMM

(1.9)

2X(0.95)

(R0.05) TYP

(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

4214839/G 03/2023

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

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重要声明和免责声明

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