TPS7A25125DRVR [TI]

具有电源正常指示功能的 300mA、18V、超低 IQ、高精度、可调节低压降稳压器 | DRV | 6 | -40 to 125;


型号：	TPS7A25125DRVR
厂家：	TEXAS INSTRUMENTS
描述：	具有电源正常指示功能的 300mA、18V、超低 IQ、高精度、可调节低压降稳压器 \| DRV \| 6 \| -40 to 125 稳压器
文件：	总37页 (文件大小：3883K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS7A25

ZHCSJ50C –DECEMBER 2018 –REVISED DECEMBER 2022

TPS7A25 具有电源正常状态指示功能的300mA、18V、超低I_Q、低压降线性稳

压器

1 特性

3 说明

• 超低I_Q：2μA

• 输入电压：2.4V 至18V

• 可用输出电压选项：

– 固定：1.25V 至5.0V

– 可调节：1.24 V 至17.66 V

• 在温度范围内的精度为1%

• 低压降：300 mA 时为340 mV（最大值）

• 开漏电源正常状态输出

TPS7A25 低压降 (LDO) 线性稳压器集 2.4V 至 18V 输

入电压范围和极低静态电流 (I_Q) 特性于一体。这些特

性能帮助现代电器满足日益严苛的能源要求，并有助于

延长便携式电源解决方案的电池寿命。

TPS7A25 有固定电压和可调节电压两种版本可供选

用。为获得更大的灵活性或更高的输出电压，可调节电

压版本使用反馈电阻器将输出电压设置为 1.24 V 到

17.64V 之间。两种版本都具有 1% 的输出调节精度，

可对微控制器(MCU) 基准电压进行精密调节。

• 热关断保护和过流保护

• 有源过冲下拉

在电流为 300mA 时，TPS7A25 LDO 的最大压降小于

340mV，因此它比标准线性稳压器的工作效率更高。

此最大压降使得在5.4V 输入电压 (V_IN) 至5.0V 输出电

压(V_OUT) 范围内的效率达到了92.5%。

• 工作结温：–40°C 至+125°C

• 与1µF 输出电容器一起工作时保持稳定

• 封装：6 引脚WSON

2 应用

电源正常状态 (PG) 指示灯可以用来将 MCU 保持在复

位状态，直到电源正常，或用于电源定序。PG 引脚为

开漏输出；因此，该引脚很容易进行电平位移，以便通

过 V_OUT以外的导轨进行监控。内置电流限制和热关断

有助于在发生负载短路或故障时保护稳压器。

• 家庭和楼宇自动化

• 多节电池移动电源

• 智能电网和计量

• 便携式电动工具

• 电机驱动器

• 白色家电

• 便携式电器

如需更高的输出电流选项，请考虑TPS7A26。

封装信息⁽¹⁾

封装尺寸（NOM）

器件型号

TPS7A25

封装

DRV（WSON，6） 2.00mm x 2.00mm

(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。

V_PG

R_PG

V_IN

V_OUT

OUT

TPS7A25

R₁

C_IN

C_OUT

GND

R₂

典型应用电路

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SBVS372

TPS7A25

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ZHCSJ50C –DECEMBER 2018 –REVISED DECEMBER 2022

Table of Contents

8.2 Functional Block Diagrams....................................... 13

8.3 Feature Description...................................................14

8.4 Device Functional Modes..........................................17

9 Device and Documentation Support............................25

9.1 Device Support......................................................... 25

9.2 Documentation Support............................................ 25

9.3 接收文档更新通知..................................................... 25

9.4 支持资源....................................................................25

9.5 Trademarks...............................................................25

9.6 Electrostatic Discharge Caution................................25

9.7 术语表....................................................................... 25

10 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................5

6.4 Thermal Information....................................................5

6.5 Electrical Characteristics.............................................6

7 Typical Characteristics................................................... 7

8 Detailed Description......................................................13

8.1 Overview...................................................................13

Information.................................................................... 25

10.1 Mechanical Data..................................................... 26

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision B (August 2019) to Revision C (December 2022)

Page

• 更改了输出电压选项要点中的最大值：将固定电压从5.5V 更改为5V.............................................................. 1

• Added Vout abs max ratings for fixed version.................................................................................................... 4

Changes from Revision A (March 2019) to Revision B (August 2019)

Page

• 更改了输出电压选项要点中的最大值：将固定电压从5V 更改为5.5V，并将可调节电压从17.64V 更改为

17.66V................................................................................................................................................................ 1

• 更改了“说明”部分：删除了第二段中有关固定电压的描述，将360mV 更改为340mV，并添加了最后一段.. 1

• Added fixed version to Pin Configuration and Functions section........................................................................3

• Added accuracy for fixed output options.............................................................................................................6

• Added Fixed Version image to Functional Block Diagrams section..................................................................13

• Added Active to Active Overshoot Pulldown Circuitry section title................................................................... 16

• Added Fixed Version Layout Example figure....................................................................................................24

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ZHCSJ50C –DECEMBER 2018 –REVISED DECEMBER 2022

5 Pin Configuration and Functions

OUT

Thermal

Pad

Thermal

Pad

GND

Not to scale

图5-1. TPS7A25: DRV Package (Adjustable), 6-Pin

图5-2. TPS7A25: DRV Package (Fixed), 6-Pin

WSON (Top View)

表5-1. Pin Functions

I/O

DESCRIPTION

DRV

(Adjustable)

DRV

(Fixed)

NAME

Enable pin. Drive EN greater than V_EN(HI)to enable the regulator. Drive EN

less than V_EN(LOW)to put the regulator into low-current shutdown. Do not

float this pin. If not used, connect EN to IN.

Input

Feedback pin. Input to the control-loop error amplifier. This pin is used to set

the output voltage of the device with the use of external resistors. For

adjustable-voltage version devices only.

Input

—

GND

Ground pin.

—

Input pin. For best transient response and to minimize input impedance, use

the recommended value or larger capacitor from IN to ground as listed in the

Recommended Operating Conditions table. Place the input capacitor as

close to the IN and GND pins of the device as possible.

Input

No internal connection. For fixed-voltage version devices only. This pin can

be floated but the device will have better thermal performance with this pin

tied to GND.

—

Output pin. A capacitor is required from OUT to ground for stability. For best

transient response, use the nominal recommended value or larger capacitor

from OUT to ground. Follow the recommended capacitor value as listed in

the Recommended Operating Conditions table. Place the output capacitor as

close to the OUT and GND pins of the device as possible.

OUT

Output

Power-good pin; open-collector output. Pullup externally to the OUT pin or

another voltage rail. The PG pin goes high when V_OUT> V_{IT(PG,RISING)}in the

Electrical Characteristics table. The PG pin is driven low when V_OUT

Output

V_{IT(PG,FALLING)}in the Electrical Characteristics table. If not used this pin can

be floated but the device will have better thermal performance with this pin

tied to GND.

Exposed pad of the package. Connect this pad to ground or leave floating.

Connect the thermal pad to a large-area ground plane for best thermal

performance.

Thermal pad

Pad

—

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

UNIT

V_IN

V_OUT(adjustable version)

V_IN+ 0.3⁽³⁾

–0.3

V_OUT(fixed version)

5.5

–0.3

Voltage⁽²⁾

V_FB

–0.3

V_EN

V_PG

–0.3

Current

Maximum output

Operating junction, T_J

Storage, T_stg

Internally limited

–50

150

Temperature

°C

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) All voltages with respect to GND.

(3) V_IN+ 0.3 V or 20 V (whichever is smaller).

6.2 ESD Ratings

VALUE

±2000

±1000

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

(1) JEDEC document JEP155 states that 2-kV HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process.

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6.3 Recommended Operating Conditions

MIN

2.4

1.24

1.25

NOM

MAX

UNIT

V_IN

Input voltage

V_OUT

I_OUT

V_EN

Output voltage (adjustable version)

Output voltage (fixed version)

Output current

18 - V_DO

5.0

300

Enable voltage

(1)

V_PG

C_IN

Power-good voltage

Input capacitor

(2)

μF

°C

(2)

C_OUT

T_J

Output capacitor

2.2

100

125

Operating junction temperature

–40

(1) Select pullup resistor to limit PG pin sink current when PG output is driven low. See the Power Good section for details.

(2) All capacitor values are assumed to derate to 50% of the nominal capacitor value.

6.4 Thermal Information

TPS7A25

THERMAL METRIC⁽¹⁾

DRV (WSON)

6 PINS

73.3

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

90.6

38.3

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

3.7

ψ_JT

38.4

ψ_JB

R_θJC(bot)

14.3

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

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6.5 Electrical Characteristics

specified at T_J= –40°C to + 125°C, V_IN= V_OUT(nom)+ 0.5 V or V_IN= 2.4 V (whichever is greater), FB tied to OUT, I_OUT= 1

mA, V_EN= 2 V, and C_IN= 1 μF, C_OUT= 2.2 μF ceramic (unless otherwise noted); typical values are at T_J= 25°C

PARAMETER

TEST CONDITIONS

MIN

TYP

2.15

MAX

UNIT

V_UVLO(RISING)

V_UVLO(HYS)

V_{UVLO(FALLING)}

V_FB

UVLO threshold rising

UVLO hysteresis

V_INrising

1.95

2.35

UVLO threshold falling

Feedback voltage

Output voltage accuracy

Line regulation⁽¹⁾

V_INfalling

1.85

2.09

1.24

2.25

Adjustable version only

Adjustable version, V_OUT= V_FB

Fixed output versions

V_OUT

1.228

–1

1.252

V_OUT

0.1

ΔV_OUT(ΔVIN)

ΔV_OUT(ΔIOUT)

(V_OUT(nom)+ 0.5 V or 2.4 V) ≤V_IN≤18 V

1 mA ≤I_OUT≤300 mA

I_OUT= 50 mA

–0.1

–0.5

Load regulation

0.5

120

210

510

105

180

340

720

4.5

V_DO

Dropout voltage⁽²⁾

I_OUT= 150 mA

I_OUT= 300 mA

I_CL

Output current limit

Ground pin current

V_OUT= 0.9 × V_OUT(nom)

I_OUT= 0 mA

325

µA

I_GND

I_OUT= 1 mA

I_SHUTDOWN

Shutdown current

FB pin current

EN pin current

325

600

V_EN≤0.4 V, V_IN= 2.4 V, I_out= 0 mA

I_FB

I_EN

V_EN= 18 V

Enable pin high-level input

voltage

V_EN(HI)

Device enabled

0.9

Enable pin low-level input

voltage

V_EN(LOW)

V_{IT(PG,RISING)}

Device disabled

0.4

R_PULLUP= 10 kΩ, V_OUTrising,

V_IN≥V_UVLO(RISING)

PG pin threshold rising

PG pin hysteresis

96.5

%V_OUT

R_PULLUP= 10 kΩ, V_OUTfalling,

V_IN≥V_UVLO(RISING)

V_HYS(PG)

%V_OUT

R_PULLUP= 10 kΩ, V_OUTfalling,

V_IN≥V_UVLO(RISING)

V_{IT(PG,FALLING)}

PG pin threshold falling

PG pin low level output

voltage

V_OL(PG)

I_LKG(PG)

V_OUT< V_{IT(PG,FALLING)}, I_PG-SINK= 500 µA

0.4

PG pin leakage current

V_OUT> V_{IT(PG,RISING)}, V_PG= 18 V

f = 10 Hz

300

Power-supply rejection

ratio

PSRR

f = 100 Hz

f = 1 kHz

V_n

Output noise voltage

BW = 10 Hz to 100 kHz, V_OUT= 1.2 V

300

μV_RMS

Thermal shutdown

temperature

T_SD(shutdown)

Shutdown, temperature increasing

Reset, temperature decreasing

165

145

°C

Thermal shutdown reset

temperature

T_SD(reset)

°C

(1) V_out(nom)+ 0.5 V or 2.4 V (whichever is greater).

(2) V_DOis measured with V_IN= 0.97 × V_OUT(nom)for fixed output voltage versions. V_DOis not measured for fixed output voltage versions

when V_OUT≤2.5 V. For the adjustable output device, V_DOis measured with V_FB= 0.97 × V_FB(nom).

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7 Typical Characteristics

at operating temperature T_J= 25°C, I_OUT= 1 mA, V_EN= 0.9 V, C_IN= 2.2 μF, C_OUT= 2.2 μF, and V_IN= V_OUT(typ)+ 0.5 V or

2.4 V (whichever is greater), unless otherwise noted; typical values are at T_J= 25°C

0.8

0.6

0.4

0.2

0.8

0.6

0.4

0.2

-50èC

-40èC

0èC

25èC

-50èC

-40èC

0èC

25èC

85èC

125èC

150èC

85èC

125èC

150èC

-0.2

-0.4

-0.6

-0.8

-1

-0.2

-0.4

-0.6

-0.8

-1

0.05

0.1

0.15

Output Current (A)

0.2

0.25

0.3

Input Voltage (V)

D002

V_OUT= 1.24 V

I_OUT= 1 mA

图7-2. Load Regulation vs I_OUT

图7-1. Line Regulation vs V_IN

250

200

150

100

400

350

300

250

200

150

100

-50èC

-40èC

0èC

85èC

125èC

150èC

-50èC

-40èC

0èC

85èC

125èC

150èC

25èC

8 10

Input Voltage (V)

D017

D016

I_OUT= 100 mA

I_OUT= 250 mA

图7-3. Dropout Voltage vs V_IN

图7-4. Dropout Voltage vs V_IN

500

450

400

350

300

250

200

150

100

400

300

200

100

-50èC

-40èC

0èC

25èC

85èC

125èC

150èC

-50èC

85èC

125èC

150èC

-40èC

0èC

25èC

0.05

0.1 0.15

Output Current (A)

0.2

0.25

0.3

8 12

Input Voltage (V)

D016

V_IN= 2.4 V

I_OUT= 300 mA

图7-5. Dropout Voltage vs V_IN

图7-6. Dropout Voltage vs I_IN

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7 Typical Characteristics (continued)

at operating temperature T_J= 25°C, I_OUT= 1 mA, V_EN= 0.9 V, C_IN= 2.2 μF, C_OUT= 2.2 μF, and V_IN= V_OUT(typ)+ 0.5 V or

2.4 V (whichever is greater), unless otherwise noted; typical values are at T_J= 25°C

400

300

200

100

0.9

0.8

0.7

0.6

-50èC

-40èC

0èC

25èC

85èC

125èC

150èC

-50èC

-40èC

0èC

25èC

85èC

125èC

150èC

0.05

0.1

0.15

Output Current (A)

0.2

0.25

0.3

Input Voltage (V)

D012

V_IN= 18 V

图7-7. Dropout Voltage vs I_OUT

图7-8. Current Limit vs V_IN

-50èC

-40èC

0èC

85èC

125èC

150èC

-50èC

-40èC

0èC

85èC

125èC

150èC

25èC

Input Voltage (V)

D005

V_OUT= 1.24 V, I_OUT= 1 mA

V_OUT= 1.24 V, I_OUT= 0 A

图7-9. I_GNDvs V_IN

图7-10. I_Qvs V_IN

200

-50èC

-40èC

0èC

25èC

85èC

125èC

150èC

180

160

140

120

100

-50èC

-40èC

0èC

85èC

125èC

150èC

25èC

0.5

1.5

2.5

Input Voltage (V)

3.5

0.05

0.1

0.15

Output Current (A)

0.2

0.25

0.3

D006

V_OUT= 1.24 V, I_OUT= 0 A

V_OUT= 1.24 V

图7-11. I_Qvs V_IN

图7-12. I_GNDvs I_OUT

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7 Typical Characteristics (continued)

at operating temperature T_J= 25°C, I_OUT= 1 mA, V_EN= 0.9 V, C_IN= 2.2 μF, C_OUT= 2.2 μF, and V_IN= V_OUT(typ)+ 0.5 V or

2.4 V (whichever is greater), unless otherwise noted; typical values are at T_J= 25°C

2.5

0.8

0.7

0.6

0.5

0.4

-50èC

-40èC

0èC

25èC

V_EN(LOW)

V_EN(HIGH)

85èC

125èC

150èC

1.5

0.5

-0.5

Input Voltage (V)

-50

-25

100

125

150

Temperature (èC)

V_OUT= 1.24 V

V_OUT= 1.24 V, 2.4 V ≤V_IN≤18 V

图7-14. V_ENThresholds vs Temperature

图7-13. Shutdown Current vs V_IN

2.3

100

V_UVLO-(V_INFalling)

V_UVLO+(V_INRising)

V_{IT(PG,FALLING)}

V_{IT(PG,RISING)}

2.2

2.1

1.9

-50

-25

100

125

150

-50

-25

100

125

150

Temperature (èC)

V_OUT= 1.24 V, I_OUT= 1 mA

图7-15. UVLO Thresholds vs Temperature

V_OUT= 1.24 V

图7-16. PG Thresholds vs Temperature

200

150

100

I_OUT

10 mA

100 mA

200 mA

300 mA

I_LKG(PG)

125 150

-50

-25

100

10k

Frequency (Hz)

100k

10M

Temperature (èC)

V_OUT= 1.24 V

V_OUT= 1.24 V, C_IN= 0 μF, C_OUT= 1 μF, C_FF= 10 nF

图7-18. PSRR vs Frequency and I_OUT

图7-17. PG Leakage Current vs Temperature

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7 Typical Characteristics (continued)

at operating temperature T_J= 25°C, I_OUT= 1 mA, V_EN= 0.9 V, C_IN= 2.2 μF, C_OUT= 2.2 μF, and V_IN= V_OUT(typ)+ 0.5 V or

2.4 V (whichever is greater), unless otherwise noted; typical values are at T_J= 25°C

100

I_OUT

V_IN

3.8 V

4.0 V

4.3 V

10 mA

100 mA

200 mA

300 mA

100

10k

Frequency (Hz)

100k

10M

100

10k

Frequency (Hz)

10k

100k

V_OUT= 3.3 V, V_IN= 4.3 V, C_IN= 0 μF, C_OUT= 1 μF,

V_OUT= 3.3 V, I_OUT= 0.3 A, C_IN= 0 μF, C_OUT= 1 μF,

C_FF= 10 nF

图7-19. PSRR vs Frequency and I_OUT

图7-20. PSRR vs Frequency and V_IN

100

C_OUT

1 uF

10 uF

47 uF

C_FF

1 nF

10 nF

100 nF

100

10k

Frequency (Hz)

100k

10M

100

10k

Frequency (Hz)

100k

10M

V_OUT= 3.3 V, V_IN= 4.3 V, I_OUT= 0.3 A, C_IN= 0 μF,

C_OUT= 1 μF

C_FF= 10 nF

图7-21. PSRR vs Frequency and C_OUT

图7-22. PSRR vs Frequency and C_FF

100

V_OUT

1.24 V

3.3 V

5 V

0.5

0.2

0.1

0.05

V_OUT

1.24 V, RMS Noise = 281.8 mV_RMS

3.3 V, RMS Noise = 334.7 mV_RMS

5 V, RMS Noise = 363.7 mV_RMS

0.02

0.01

0.005

100

10k

Frequency (Hz)

10k

100k

100

10k

Frequency (Hz)

100k

10M

V_IN= V_OUT+ 1 V or 2.4 V (whichever is greater), I_OUT= 0.3 A,

C_IN= 1 μF, C_OUT= 1 μF, C_FF= 10 nF, V_RMSBW = 10 Hz to

100 kHz

C_IN= 0 μF, C_OUT= 1 μF, C_FF= 10 nF

图7-23. PSRR vs Frequency and V_OUT

图7-24. Output Noise (V_n) vs Frequency and V_OUT

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7 Typical Characteristics (continued)

at operating temperature T_J= 25°C, I_OUT= 1 mA, V_EN= 0.9 V, C_IN= 2.2 μF, C_OUT= 2.2 μF, and V_IN= V_OUT(typ)+ 0.5 V or

2.4 V (whichever is greater), unless otherwise noted; typical values are at T_J= 25°C

0.5

0.2

0.1

0.2

0.1

0.05

I_OUT

C_OUT

0.01A, RMS Noise = 280.2 mV_RMS

0.1A, RMS Noise = 283.2 mV_RMS

0.2 A, RMS Noise = 285.2 mV_RMS

0.3 A RMS Noise = 281.8 mV_RMS

0.02

0.01

0.02

0.01

1 mF, RMS Noise = 281.8 mV_RMS

10 mF, RMS Noise = 309.3 mV_RMS

100 mF, RMS Noise = 244.3 mV_RMS

0.005

100

10k

Frequency (Hz)

100k

10M

100

10k 100k

Frequency (Hz)

10M

D013

V_OUT= 1.24 V, V_IN= 2.4 V, I_OUT= 0.3 A, C_IN= 1 μF,

V_OUT= 1.24 V, C_IN= 1 μF, C_OUT= 1 μF, C_FF= 10 nF,

C_FF= 10 nF, V_RMSBW = 10 Hz to 100 kHz

V_RMSBW = 10 Hz to 100 kHz

图7-26. Output Noise (V_n) vs Frequency and C_OUT

图7-25. Output Noise (V_n) vs Frequency and I_OUT

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

200

100

-100

-200

-300

-400

-500

-600

-700

-800

-900

-1000

0.5

0.2

0.1

0.05

C_FF

0 nF, RMS Noise = 545.7 mV_RMS

10 nF, RMS Noise = 340.6 mV_RMS

100 nF, RMS Noise = 295.4 mV_RMS

0.02

0.01

I_OUT

V_OUT

-0.1

-0.2

0.005

100

10k

Frequency (Hz)

100k

10M

-100

100

200

Time (µs)

300

400

500

600

V_OUT= 3.3 V, V_IN= 4.3 V, I_OUT= 0.3 A, C_IN= 1 μF,

C_OUT= 1 μF, V_RMSBW = 10 Hz to 100 kHz

I_OUT= 0.001 A to 0.3 A, slew rate = 0.5 A/μs, V_OUT= 3.3 V,

V_IN= 4.3 V, C_IN= 1 μF, C_OUT= 1 μF

图7-27. Output Noise (V_n) vs Frequency and C_FF

图7-28. Load Transient

400

I_OUT

V_OUT

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

300

200

100

-10

-20

-30

-40

-50

-60

-70

-80

-100

-200

-300

-400

-500

-600

-700

-800

V_OUT

V_IN

-0.1

-0.2

-100

100

200 300

Time (µsec)

400

500

600

-400

-200

200 400

Time (µsec)

600

800

1000

Exce

I_OUT= 0.3 A to 0.001 mA, slew rate = 0.5 A/μs, V_OUT= 3.3 V,

V_IN= 4.3 V, C_IN= 1 μF, C_OUT= 1 μF

V_IN= 5.3 V to 4.3 V, slew rate = 0.5 V/μs, V_OUT= 3.3 V,

I_OUT= 0.5 A, C_IN= 1 μF, C_OUT= 1 μF

图7-29. Load Transient

图7-30. Line Transient

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7 Typical Characteristics (continued)

at operating temperature T_J= 25°C, I_OUT= 1 mA, V_EN= 0.9 V, C_IN= 2.2 μF, C_OUT= 2.2 μF, and V_IN= V_OUT(typ)+ 0.5 V or

2.4 V (whichever is greater), unless otherwise noted; typical values are at T_J= 25°C

V_IN

V_EN

V_OUT

-10

-20

-30

-40

-50

-60

-70

-80

V_OUT

V_IN

-1

-450 -300 -150

150 300 450 600 750 900 1050

Time (µsec)

-100

100 200 300 400 500 600 700 800 900

Time (_ssec)

V_IN= 5 V, V_EN= 0 V to 2 V, V_OUT= 3.3 V, I_OUT= 0.3 A,

V_IN= 4.3 V to 5.3 V, slew rate = 0.5 V/μs, V_OUT= 3.3 V,

I_OUT= 0.5 A, C_IN= 1 μF, C_OUT= 1 μF

C_IN= 1 μF, C_OUT= 1 μF

图7-32. Start-Up With Enable

图7-31. Line Transient

V_VIN

V_OUT

-1

-2

-200

200

400

600

800

1000

1200

Time (msec)

V_IN= 0 V to 5 V, V_EN= V_IN, V_OUT= 3.3 V, I_OUT= 0.3 A,

C_IN= 1 μF, C_OUT= 1 μF

图7-33. Start-Up With Enable Pin Tied to Input

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8 Detailed Description

8.1 Overview

The TPS7A25 is an 18-V, low quiescent current, low-dropout (LDO) linear regulator. The low I_Qperformance

makes the TPS7A25 an excellent choice for battery-powered or line-power applications that are expected to

meet increasingly stringent standby-power standards.

The 1% accuracy over temperature and power-good indication make this device an excellent choice for meeting

a wide range of microcontroller power requirements. Additionally, the TPS7A25 has an internal soft-start to

minimize inrush current into the output capacitance.

For increased reliability, the TPS7A25 also incorporates overcurrent, overshoot pulldown, and thermal shutdown

protection. The operating junction temperature is –40°C to +125°C, and adds margin for applications concerned

with higher working ambient temperatures.

The TPS7A25 is available in a thermally enhanced WSON package.

8.2 Functional Block Diagrams

TPS7A2501

(Adjustable Version)

OUT

Current

Limit

Thermal

Shutdown

UVLO

Band-Gap

Reference

GND

Logic

Reference

图8-1. Adjustable Version

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TPS7A25

(Fixed Version)

OUT

Current

Limit

Thermal

Shutdown

R₁

UVLO

R₂

Band-Gap

Reference

GND

Logic

Reference

图8-2. Fixed Version

8.3 Feature Description

8.3.1 Output Enable

The enable pin for the device is an active-high pin. The output voltage is enabled when the voltage of the enable

pin is greater than the high-level input voltage of the EN pin and disabled with the enable pin voltage is less than

the low-level input voltage of the EN pin. If independent control of the output voltage is not needed, connect the

enable pin to the input of the device.

8.3.2 Dropout Voltage

Dropout voltage (V_DO) is defined as the input voltage minus the output voltage (V_IN– V_OUT) at the rated output

current (I_RATED), where the pass transistor is fully on. I_RATEDis the maximum I_OUTlisted in the Recommended

Operating Conditions table. The pass transistor is in the ohmic or triode region of operation, and acts as a

switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed

output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than

the nominal output regulation, then the output voltage falls as well.

For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (R_DS(ON)) of the

pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for

that current scales accordingly. Use 方程式1 to calculate the R_DS(ON)of the device.

V_DO

R_DS(ON)

I_RATED

(1)

8.3.3 Current Limit

The device has an internal current limit circuit that protects the regulator during transient high-load current faults

or shorting events. The current limit is a brick-wall scheme. In a high-load current fault, the brick-wall scheme

limits the output current to the current limit (I_CL). I_CLis listed in the Electrical Characteristics table.

The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the

device begins to heat up because of the increase in power dissipation. When the device is in brick-wall current

limit, the pass transistor dissipates power [(V_IN– V_OUT) × I_CL]. If thermal shutdown is triggered, the device turns

off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If the output

current fault condition continues, the device cycles between current limit and thermal shutdown. For more

information on current limits, see the Know Your Limits application note.

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图8-3 depicts a diagram of the current limit.

V_OUT

Brickwall

V_OUT(NOM)

0 V

I_OUT

I_RATED

0 mA

I_CL

图8-3. Current Limit

8.3.4 Undervoltage Lockout (UVLO)

The device has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a

controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input

drops during turn on, the UVLO has hysteresis as specified in the Electrical Characteristics table.

8.3.5 Thermal Shutdown

The device contains a thermal shutdown protection circuit to disable the device when the junction temperature

(T_J) of the pass transistor rises to T_SD(shutdown)(typical). Thermal shutdown hysteresis assures that the device

resets (turns on) when the temperature falls to T_SD(reset)(typical).

The thermal time-constant of the semiconductor die is fairly short, thus the device may cycle on and off when

thermal shutdown is reached until power dissipation is reduced. Power dissipation during start-up can be high

from large V_IN– V_OUTvoltage drops across the device or from high inrush currents charging large output

capacitors. Under some conditions, the thermal shutdown protection disables the device before start-up

completes.

When the thermal limit is triggered with the load current near the value of the current limit, the output may

oscillate prior to the output switching off.

For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating

Conditions table. Operation above this maximum temperature causes the device to exceed its operational

specifications. Although the internal protection circuitry of the device is designed to protect against thermal

overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device

into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability.

8.3.6 Power Good

The power-good (PG) pin is an open-drain output and can be connected to a regulated supply through an

external pullup resistor. The maximum pullup voltage is listed as V_PGin the Recommended Operating Conditions

table. For the PG pin to have a valid output, the voltage on the IN pin must be greater than V_UVLO(RISING), as

listed in the Electrical Characteristics table. When the V_OUTexceeds V_{IT(PG,RISING)}, the PG output is high

impedance and the PG pin voltage pulls up to the connected regulated supply. When the regulated output falls

below V_{IT(PG,FALLING)}, the open-drain output turns on and pulls the PG output low after a short deglitch time. If

output voltage monitoring is not needed, the PG pin can be left floating or connected to ground.

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The recommended maximum PG pin sink current (I_PG-SINK) and the leakage current into the PG pin (I_LKG(PG)) are

listed in the Electrical Characteristics table.

The PG pullup voltage (V_{PG_PULLUP}), the desired minimum power-good output voltage (V_PG(MIN)), and I_LKG(PG)

limit the maximum PG pin pullup resistor value (R_{PG_PULLUP}). V_{PG_PULLUP}, the PG pin low-level output voltage

(V_OL(PG)), and I_PG-SINKlimit the minimum R_{PG_PULLUP}. Maximum and minimum values for R_{PG_PULLUP}can be

calculated from the following equations:

R_{PG_PULLUP(MAX)}= (V_{PG_PULLUP}–V_PG(MIN)) / I_{LKG(PG)_MAX}

R_{PG_PULLUP(MIN)}= (V_{PG_PULLUP}–V_OL(PG)) / I_PG-SINK

(2)

(3)

For example, if the PG pin is connected to a pullup resistor with a 3.3-V external supply, from 方程式 2,

R_{PG_PULLUP(MAX)}is 11 MΩ. From 方程式3, R_{PG_PULLUP(MIN)}is 5.8 kΩ.

8.3.7 Active Overshoot Pulldown Circuitry

This device has pulldown circuitry connected to V_OUT. This circuitry is a 100-μA current sink, in series with a

5.5-kΩ resistor, controlled by V_EN. When V_ENis below V_EN(LOW), the pulldown circuitry is disabled and the LDO

output is in high-impedance mode.

If the output voltage is more than 60 mV above nominal voltage when V_EN≥ V_EN(LOW), the pulldown circuitry

turns on and the output is pulled down until the output voltage is within 60 mV from the nominal voltage. This

feature helps reduce overshoot during the transient response.

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8.4 Device Functional Modes

8.4.1 Device Functional Mode Comparison

表 8-1 shows the conditions that lead to the different modes of operation. See the Electrical Characteristics table

for parameter values.

表8-1. Device Functional Mode Comparison

PARAMETER

OPERATING MODE

V_IN

V_EN

I_OUT

T_J

Normal operation

Dropout operation

V_IN> V_OUT(nom)+ V_DOand V_IN> V_IN(min)

V_IN(min)< V_IN< V_OUT(nom)+ V_DO

V_EN> V_EN(HI)

I_OUT< I_OUT(max)

T_J< T_SD(shutdown)

Disabled

(any true condition

disables the device)

V_IN< V_UVLO

V_EN< V_EN(LOW)

Not applicable

T_J> T_SD(shutdown)

8.4.2 Normal Operation

The device regulates to the nominal output voltage when the following conditions are met:

• The input voltage is greater than the nominal output voltage plus the dropout voltage (V_OUT(nom)+ V_DO

• The output current is less than the current limit (I_OUT< I_CL)

)

• The device junction temperature is less than the thermal shutdown temperature (T_J< T_SD

)

• The enable voltage has previously exceeded the enable rising threshold voltage and has not yet decreased

to less than the enable falling threshold

8.4.3 Dropout Operation

If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other

conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage

tracks the input voltage. During this mode, the transient performance of the device becomes significantly

degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load

transients in dropout can result in large output-voltage deviations.

When the device is in a steady dropout state (defined as when the device is in dropout, V_IN< V_OUT(NOM)+ V_DO

directly after being in a normal regulation state, but not during start-up), the pass transistor is driven into the

ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output

voltage plus the dropout voltage (V_OUT(NOM)+ V_DO), the output voltage can overshoot for a short period of time

while the device pulls the pass transistor back into the linear region.

8.4.4 Disabled

The output of the device can be shutdown by forcing the voltage of the enable pin to less than the maximum EN

pin low-level input voltage (see the Electrical Characteristics table). When disabled, the pass transistor is turned

off and internal circuits are shutdown.

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Application and Implementation

备注

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

9.1 Application Information

9.1.1 Adjustable Device Feedback Resistors

The adjustable-version device requires external feedback divider resistors to set the output voltage. V_OUTis set

using the feedback divider resistors, R₁and R₂, according to the following equation:

V_OUT= V_FB× (1 + R₁/ R₂)

(4)

To ignore the FB pin current error term in the V_OUTequation, set the feedback divider current to 100 times the FB

pin current listed in the Electrical Characteristics table. This setting provides the maximum feedback divider

series resistance, as shown in the following equation:

R₁+ R₂≤V_OUT/ (I_FB× 100)

(5)

9.1.2 Recommended Capacitor Types

The device is designed to be stable using low equivalent series resistance (ESR) capacitors at the input and

output. Multilayer ceramic capacitors have become the industry standard for these types of applications and are

recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and C0G-

rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of Y5V-

rated capacitors is discouraged because of large variations in capacitance.

Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and

temperature. As a rule of thumb, expect the effective capacitance to decrease by as much as 50%. The input

and output capacitors recommended in the Recommended Operating Conditions table account for an effective

capacitance of approximately 50% of the nominal value.

9.1.3 Input and Output Capacitor Requirements

Although an input capacitor is not required for stability, good analog design practice is to connect a capacitor

from IN to GND. This capacitor counteracts reactive input sources and improves transient response, input ripple,

and PSRR. An input capacitor is recommended if the source impedance is more than 0.5 Ω. A higher value

capacitor may be necessary if large, fast transient load or line transients are anticipated or if the device is

located several inches from the input power source.

Dynamic performance of the device is improved with the use of an output capacitor. Use an output capacitor

within the range specified in the Recommended Operating Conditions table for stability.

The effective output capacitance is recommended to not exceed 50 μF.

9.1.4 Reverse Current

Excessive reverse current can damage this device. Reverse current flows through the intrinsic body diode of the

pass transistor instead of the normal conducting channel. At high magnitudes, this current flow degrades the

long-term reliability of the device.

Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute

maximum rating of V_OUT≤V_IN+ 0.3 V.

• If the device has a large C_OUTand the input supply collapses with little or no load current

• The output is biased when the input supply is not established

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• The output is biased above the input supply

If reverse current flow is expected in the application, external protection is recommended to protect the device.

Reverse current is not limited in the device, so external limiting is required if extended reverse voltage operation

is anticipated.

图9-1 shows one approach for protecting the device.

Schottky Diode

Internal Body Diode

OUT

Device

C_OUT

C_IN

GND

图9-1. Example Circuit for Reverse Current Protection Using a Schottky Diode

图9-2 shows another, more commonly used, approach in high input voltage applications.

OUT

Device

C_OUT

C_IN

GND

图9-2. Reverse Current Prevention Using A Diode Before the LDO

9.1.5 Feed-Forward Capacitor (C_FF)

For the adjustable-voltage version device, a feed-forward capacitor (C_FF) can be connected from the OUT pin to

the FB pin. C_FFimproves transient, noise, and PSRR performance, but is not required for regulator stability.

Common C_FFvalue choices range between 10 nF and 100 nF. A higher capacitance C_FFcan be used; however,

the start-up time increases. For a detailed description of C_FFtradeoffs, see the Pros and Cons of Using a

Feedforward Capacitor with a Low-Dropout Regulator application note.

9.1.6 Power Dissipation (P_D)

Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed

circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few

or no other heat-generating devices that cause added thermal stress.

To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference

and load conditions. The following equation calculates power dissipation (P_D).

P_D= (V_IN–V_OUT) × I_OUT

(6)

备注

Power dissipation can be minimized, and therefore greater efficiency can be achieved, by correct

selection of the system voltage rails. For the lowest power dissipation use the minimum input voltage

required for correct output regulation.

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For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal

pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an

array of plated vias that conduct heat to additional copper planes for increased heat dissipation.

The maximum power dissipation determines the maximum allowable ambient temperature (T_A) for the device.

According to the following equation, power dissipation and junction temperature are most often related by the

junction-to-ambient thermal resistance (R_θJA) of the combined PCB and device package and the temperature of

the ambient air (T_A).

T_J= T_A+ (R_θJA× P_D)

(7)

Thermal resistance (R_θJA) is highly dependent on the heat-spreading capability built into the particular PCB

design, and therefore varies according to the total copper area, copper weight, and location of the planes. The

junction-to-ambient thermal resistance listed in the Thermal Information table is determined by the JEDEC

standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance.

9.1.7 Estimating Junction Temperature

The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures

of the linear regulator when in-circuit on a typical PCB board application. These metrics are not thermal

resistance parameters and instead offer a practical and relative way to estimate junction temperature. These psi

metrics are determined to be significantly independent of the copper area available for heat-spreading. The

Thermal Information table lists the primary thermal metrics, which are the junction-to-top characterization

parameter (ψ_JT) and junction-to-board characterization parameter (ψ_JB). These parameters provide two

methods for calculating the junction temperature (T_J), as described in the following equations. Use the junction-

to-top characterization parameter (ψ_JT) with the temperature at the center-top of device package (T_T) to

calculate the junction temperature. Use the junction-to-board characterization parameter (ψ_JB) with the PCB

surface temperature 1 mm from the device package (T_B) to calculate the junction temperature.

T_J= T_T+ ψ_JT× P_D

(8)

where:

• P_Dis the dissipated power

• T_Tis the temperature at the center-top of the device package

T_J= T_B+ ψ_JB× P_D

(9)

where:

• T_Bis the PCB surface temperature measured 1 mm from the device package and centered on the package

edge

For detailed information on the thermal metrics and how to use them, see the Semiconductor and IC Package

Thermal Metrics application note.

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9.1.8 Special Consideration for Line Transients

During a line transient, the response of this LDO to a very large or fast input voltage change can cause a brief

shutdown lasting up to a few hundred microseconds from the voltage transition. This shutdown can be avoided

by reducing the voltage step size, increasing the transition time, or a combination of both. 图 9-3 provides a

boundary to follow to avoid this behavior. If necessary, reduce slew rate and the voltage step size to stay below

the curve.

1.8

1.6

1.4

1.2

0.8

0.6

0.4

0.2

V_INDelta

Input Voltage Step Size (V)

10 11 12 13 14 15

图9-3. Recommended Input Voltage Step and Slew Rate in a Line transient

9.2 Typical Application

V_PG

R_PG

V_IN

V_OUT

OUT

TPS7A25

R₁

C_IN

C_OUT

GND

R₂

图9-4. Generating a 5-V Rail From a Multicell Power Bank

9.2.1 Design Requirements

表9-1 summarizes the design requirements for 图9-4.

表9-1. Design Parameters

PARAMETER

DESIGN VALUES

8.4 V

V_IN

V_OUT

5 V ±1%

I_(IN)(no load)

I_OUT(max)

T_A

< 5 µA

220 mA

70°C (max)

9.2.2 Detailed Design Procedure

Select a 5-V output, fixed or adjustable device to generate the 5-V rail. The fixed-version LDO has internal

feedback divider resistors and thus has lower effective quiescent current. The adjustable-version LDO requires

external feedback divider resistors, and resistor selection is described in the Selecting Feedback Divider

Resistors section.

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9.2.2.1 Transient Response

As with any regulator, increasing the output capacitor value reduces over- and undershoot magnitude, but

increases transient response duration.

9.2.2.2 Selecting Feedback Divider Resistors

For this design example, V_OUTis set to 5 V. The following equations set the feedback divider resistors for the

desired output voltage:

V_OUT= V_FB× (1 + R₁/ R₂)

(10)

(11)

R₁+ R₂≤V_OUT/ (I_FB× 100)

For improved output accuracy, use 方程式 11 and I_FB(TYP)= 10 nA as listed in the Electrical Characteristics table

to calculate the upper limit for series feedback resistance, R₁+ R₂≤5 MΩ.

The control-loop error amplifier drives the FB pin to the same voltage as the internal reference (V_FB= 1.24 V as

listed in the Electrical Characteristics table). Use 方程式10 to determine the ratio of R₁/ R₂= 3.03. Use this ratio

and solve 方程式 11 for R₂. Now calculate the upper limit for R₂≤1.24 MΩ. Select a standard resistor value for

R₂= 1.18 MΩ.

Reference 方程式10 and solve for R₁:

R₁= (V_OUT/ V_FB–1) × R₂

(12)

From 方程式12, R₁= 3.64 MΩcan be determined. Select a standard resistor value for R₁= 3.6 MΩ. From 方程

式10, V_OUT= 5.023 V.

9.2.2.3 Thermal Dissipation

Junction temperature can be determined using the junction-to-ambient thermal resistance (R_θJA) and the total

power dissipation (P_D). Use 方程式 13 to calculate the power dissipation. Multiply P_Dby R_θJAand add the

ambient temperature (T_A), as 方程式14 shows, to calculate the junction temperature (T_J).

P_D= (I_GND+ I_OUT) × (V_IN–V_OUT

)

(13)

(14)

T_J= R_θJA× P_D+ T_A

方程式 15 calculates the maximum ambient temperature. 方程式 16 calculates the maximum ambient

temperature for this application.

T_A(MAX)= T_J(MAX)–(R_θJA× P_D)

(15)

(16)

T_A(MAX)= 125°C –[73.3°C/W × (8.4 V –5 V) × 0.22 A] = 70.2°C

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ZHCSJ50C –DECEMBER 2018 –REVISED DECEMBER 2022

9.2.3 Application Curve

1.8

1.6

1.4

1.2

1000

I_OUT

800

V_OUT

600

400

200

0.8

0.6

0.4

0.2

-200

-400

-600

-800

-1000

-1200

-1400

-0.2

-0.4

-500

500

1000 1500

Time (µsec)

2000

2500

3000

I_OUT= 1 mA to 0.22 A, slew rate = 0.5 A/μs, V_OUT= 5 V, V_IN= 8.4 V, C_IN= 1 μF, C_OUT= 1 μF, C_FF= 0 μF

图9-5. TPS7A25 Load Transient (1 mA to 220 mA)

9.3 Power Supply Recommendations

The device is designed to operate from an input supply voltage range of 2.4 V to 18 V. To ensure that the output

voltage is well regulated and dynamic performance is optimum, the input supply must be at least V_OUT(nom)

0.5 V. Connect a low output impedance power supply directly to the input pin of the TPS7A25.

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ZHCSJ50C –DECEMBER 2018 –REVISED DECEMBER 2022

9.4 Layout

9.4.1 Layout Guidelines

• Place input and output capacitors as close to the device pins as possible

• Use copper planes for device connections to optimize thermal performance

• Place thermal vias around the device and under the DRV thermal pad to distribute heat

9.4.2 Layout Examples

GND PLANE

C_OUT

V_IN

C_IN

V_OUT

GND

R_PG

GND PLANE

Represents via used for application-specific connections

图9-6. Adjustable Version Layout Example

V_OUT

V_IN

C_OUT

GND

C_IN

GND

R_PG

GND

PLANE

Represents via used for application-specific connections

图9-7. Fixed Version Layout Example

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ZHCSJ50C –DECEMBER 2018 –REVISED DECEMBER 2022

9 Device and Documentation Support

9.1 Device Support

9.1.1 Device Nomenclature

表9-1. Device Nomenclature⁽¹⁾

PRODUCT

V_OUT

xx(x) is the nominal output voltage. For output voltages with a resolution of 100 mV, two

digits are used in the ordering number; for output voltages with a resolution of 50 mV, three

digits are used (for example, 28 = 2.8 V; 125 = 1.25 V). 01 indicates adjustable output

version.

TPS7A25xx(x)yyyz

yyy is the package designator.

z is the package quantity. R is for large quantity reel, T is for small quantity reel.

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the

device product folder at www.ti.com.

9.2 Documentation Support

9.2.1 Related Documentation

For related documentation see the following:

Texas Instruments, TPS7A26 500-mA, 18-V, Ultra-Low I_Q, Low Dropout Linear Voltage Regulator With Power-

Good data sheet

9.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

9.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

9.5 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

9.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

9.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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TPS7A25

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ZHCSJ50C –DECEMBER 2018 –REVISED DECEMBER 2022

10.1 Mechanical Data

PACKAGE OUTLINE

DRV0006A

WSON - 0.8 mm max height

SCALE 5.500

PLASTIC SMALL OUTLINE - NO LEAD

2.1

1.9

PIN 1 INDEX AREA

2.1

1.9

0.8 MAX

SEATING PLANE

0.08 C

(0.2) TYP

0.05

0.00

1 0.1

EXPOSED

THERMAL PAD

1.3

1.6 0.1

4X 0.65

0.35

0.25

PIN 1 ID

(OPTIONAL)

0.3

0.2

0.1

C A

0.05

4222173/A 12/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

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TPS7A25

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ZHCSJ50C –DECEMBER 2018 –REVISED DECEMBER 2022

EXAMPLE BOARD LAYOUT

DRV0006A

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

6X (0.45)

6X (0.3)

(1)

SYMM

(1.6)

(1.1)

4X (0.65)

SYMM

(1.95)

(R0.05) TYP

(

0.2) VIA

TYP

LAND PATTERN EXAMPLE

SCALE:25X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4222173/A 12/2015

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.

www.ti.com

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TPS7A25

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ZHCSJ50C –DECEMBER 2018 –REVISED DECEMBER 2022

EXAMPLE STENCIL DESIGN

DRV0006A

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

SYMM

6X (0.45)

METAL

6X (0.3)

(0.45)

SYMM

4X (0.65)

(0.7)

(R0.05) TYP

(1)

(1.95)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD #7

88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:30X

4222173/A 12/2015

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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Product Folder Links: TPS7A25

PACKAGE OPTION ADDENDUM

www.ti.com

27-Sep-2022

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS7A2501DRVR

TPS7A2501DRVT

TPS7A25125DRVR

TPS7A2518DRVR

TPS7A2525DRVR

TPS7A2533DRVR

TPS7A2550DRVR

ACTIVE

WSON

DRV

3000 RoHS & Green

250 RoHS & Green

NIPDAU

Level-1-260C-UNLIM

-40 to 125

7A25

1XCP

1XBP

1XAP

Samples

NIPDAU

3000 RoHS & Green

1WSP

1WQP

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

27-Sep-2022

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

17-Apr-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS7A2501DRVR

TPS7A2501DRVT

TPS7A25125DRVR

TPS7A2518DRVR

TPS7A2525DRVR

TPS7A2533DRVR

TPS7A2550DRVR

WSON

DRV

3000

250

178.0

8.4

2.25

1.0

4.0

8.0

3000

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

17-Apr-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS7A2501DRVR

TPS7A2501DRVT

TPS7A25125DRVR

TPS7A2518DRVR

TPS7A2525DRVR

TPS7A2533DRVR

TPS7A2550DRVR

WSON

DRV

3000

250

205.0

200.0

33.0

3000

Pack Materials-Page 2

GENERIC PACKAGE VIEW

DRV 6

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4206925/F

PACKAGE OUTLINE

DRV0006A

WSON - 0.8 mm max height

SCALE 5.500

PLASTIC SMALL OUTLINE - NO LEAD

2.1

1.9

PIN 1 INDEX AREA

2.1

1.9

0.8

0.7

SEATING PLANE

0.08 C

(0.2) TYP

0.05

0.00

0.1

EXPOSED

THERMAL PAD

1.3

1.6 0.1

4X 0.65

0.35

0.25

PIN 1 ID

(OPTIONAL)

0.3

0.2

0.1

C A

0.05

4222173/B 04/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

DRV0006A

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

6X (0.45)

6X (0.3)

(1)

SYMM

(1.6)

(1.1)

4X (0.65)

SYMM

(1.95)

(R0.05) TYP

(

0.2) VIA

TYP

LAND PATTERN EXAMPLE

SCALE:25X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4222173/B 04/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.

www.ti.com

EXAMPLE STENCIL DESIGN

DRV0006A

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

SYMM

6X (0.45)

METAL

6X (0.3)

(0.45)

SYMM

4X (0.65)

(0.7)

(R0.05) TYP

(1)

(1.95)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD #7

88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:30X

4222173/B 04/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

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TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TPS7A25125DRVR [TI]

相关型号：

TPS7A2518DRVR

TPS7A2525DRVR

TPS7A2533DRVR

TPS7A2550DRVR

TPS7A26

TPS7A2601DRVR

TPS7A2601DRVT

TPS7A26125DRVR

TPS7A2618DRVR

TPS7A2625DRVR

TPS7A2633DRVR

TPS7A2650DRVR