TPS7A43 [TI]

TPS7A43 50-mA, 85-V, Low IQ, Dual Output Low-Dropout Linear Voltage Regulator With Precision Enable & Power-Good;


型号：	TPS7A43
厂家：	TEXAS INSTRUMENTS
描述：	TPS7A43 50-mA, 85-V, Low IQ, Dual Output Low-Dropout Linear Voltage Regulator With Precision Enable & Power-Good
文件：	总25页 (文件大小：1111K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS7A43

_{SBVS393 – DECE}T_MP_BS_ER7A₂₀4₂3₀

SBVS393 – DECEMBER 2020

www.ti.com

TPS7A43 50-mA, 85-V, Low I_Q, Dual Output Low-Dropout Linear Voltage Regulator

With Precision Enable & Power-Good

1 Features

3 Description

•

Input voltage: 4 V to 85 V

Ultra-low I_Q: 6.5 µA

Wide output voltage range:

– Adjustable: 1.24 V to 14.5 V

– Fixed: 1.25 V to 5.0 V

The TPS7A43 low-dropout (LDO) linear voltage

regulator introduces a combination of a 4-V to 85-V

input voltage range with very-low quiescent current

(I_Q).

This device can support a wide range of input

voltages (for example, a 15s battery and 24-V to

48-V line power) and withstand line transient voltages

up to 85 V. These features help modern appliances

meet increasingly stringent energy requirements, and

help extend battery life in portable-power solutions.

•

Intermediate output (MID_OUT): 10 V, 12 V, 15 V

Precision enable

1% accuracy over temperature

Power-good (PG) output (open-drain)

Thermal shutdown and overcurrent protection

Operating junction temperature: –40°C to +125°C

Package: HVSSOP-10 (R_θJA= 53.7°C/W)

The TPS7A43 is available in both fixed and adjustable

output versions. Fixed output options are available in

standard voltage options and the adjustable output

version uses external feedback resistors to set the

output voltage from 1.24 V to 14.5 V. The main output

(OUT) has a 1% output regulation accuracy that

provides precision regulation for most microcontroller

(MCU) references. The device also provides a second

intermediate output (MID_OUT) that can be used to

bias gate drivers in place of a discrete regulator. The

MID_OUT uses two logic pins (MVSEL1 and

MVSEL2) to adjust the intermediate output rail

between 10 V, 12 V, or 15 V.

2 Applications

•

Cordless power tools

DC motors and fans

Programmable logic controllers (PLCs)

Field transmitter and process sensors

Smoke and heat detectors

EV charging infrastructure

Battery packs

VOUT

COUT

VIN

OUT

VCC

VSS

CIN

The TPS7A43 features a precision enable input that

helps enable or disable the LDO at a fixed and

accurate threshold voltage using a resistor divider

from the input.

MCU

GND

VEN

FB/NC

GND

TPS7A43

VMID_OUT

MID_OUT

VMVSEL1

GND

MVSEL1

MVSEL2

Gate

Driver

GND

VPG

VMSELV2

The power-good (PG) output is used to monitor the

voltage at the feedback pin to indicate the status of

the output voltage. The EN input and PG output can

be used for sequencing multiple power sources in the

system. The built-in current limit and thermal

shutdown help protect the regulator in the event of a

load short or fault.

GND

R1 and R2 resistors are only for adjustable version.

Powering Cordless Power Tools

VIN

OUT

VOUT

CIN

COUT

GND

Device Information ⁽¹⁾

GND

TPS7A43

VMID_OUT

MID_OUT

PART NUMBER

PACKAGE

BODY SIZE (NOM)

MVSEL1

MVSEL2

GND

VIN

GND

TPS7A43

HVSSOP (10)

3.00 mm × 3.00 mm

GND

(1) For all available packages, see the package option

addendum at the end of the datasheet.

GND

Setting MID_OUT voltage to 12 V or 15 V using R3 and R4 resistors.

Powering the MCU for Battery Packs

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

Submit Document Feedback

intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change

Product Folder Links: TPS7A43

without notice.

TPS7A43

SBVS393 – DECEMBER 2020

www.ti.com

Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings ....................................... 4

6.2 ESD Ratings .............................................................. 4

6.3 Recommended Operating Conditions ........................5

6.4 Thermal Information ...................................................5

6.5 Electrical Characteristics ............................................6

6.6 Typical Characteristics................................................8

7 Detailed Description......................................................10

7.1 Overview...................................................................10

7.2 Functional Block Diagrams....................................... 10

7.3 Feature Description...................................................11

7.4 Device Functional Modes..........................................15

8 Application and Implementation..................................16

8.1 Application Information............................................. 16

8.2 Typical Application.................................................... 18

9 Power Supply Recommendations................................19

10 Layout...........................................................................19

10.1 Layout Guidelines................................................... 19

10.2 Layout Examples.................................................... 20

11 Device and Documentation Support..........................21

11.1 Device Support........................................................21

11.2 Receiving Notification of Documentation Updates..21

11.3 Support Resources................................................. 21

11.4 Trademarks............................................................. 21

11.5 Electrostatic Discharge Caution..............................21

11.6 Glossary..................................................................21

12 Mechanical, Packaging, and Orderable

Information.................................................................... 21

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

DATE

December 2020

REVISION

NOTES

Initial Release

Submit Document Feedback

Product Folder Links: TPS7A43

TPS7A43

SBVS393 – DECEMBER 2020

www.ti.com

5 Pin Configuration and Functions

OUT

NC/GND

Thermal pad

MID_OUT

MVSEL2

MID_OUT

MVSEL2

MVSEL1

GND

MVSEL1

GND

Not to scale

Figure 5-1. DGQ Package (Adjustable),

Top View

Figure 5-2. DGQ Package (Fixed), 10-Pin HVSSOP,

Top View

Table 5-1. Pin Functions

I/O

DESCRIPTION

DGQ

(Adjustable)

DGQ

(Fixed)

NAME

Precision enable pin. Driving this pin to logic high enables the device. Driving

this pin to logic low disables the device. This pin can be left floating to enable

the device because the device features an internal pullup resistor to the IN

pin. If this pin is tied to the IN pin then the input voltage must not exceed

18 V; see the Recommended Operating Conditions table.

Input

Feedback pin. Input to the control-loop error amplifier. This pin is used to set

the output voltage of the device with the use of external resistors. For

adjustable-voltage version devices only. This pin must not be left floating.

—

Input

—

GND

Ground pin.

Input pin. For best transient response and to minimize input impedance, use

the recommended value or larger ceramic capacitor from IN to ground; see

the Recommended Operating Conditions table. Place the input capacitor as

close to the IN and GND pins of the device as possible.

Input

MID output pin. A capacitor is required from MID_OUT to ground for stability.

For best transient response, use the nominal recommended value or larger

capacitor from MID_OUT to ground. Follow the recommended capacitor

value as listed in the Recommended Operating Conditions table. Place the

MID output capacitor as close to the MID_OUT and GND pins of the device

as possible.

MID_OUT

Output

Mid output voltage select pin. The MVSEL1 and MVSEL2 pins can be used

to set the MID_OUT output voltage; see the Electrical Characteristics table

for details on how to set the MID_OUT voltage using the MVSEL1 and

MVSEL2 pins.

MVSEL1

MVSEL2

Input

Mid output voltage select pin. The MVSEL2 and MVSEL1 pins can be used

to set the MID_OUT output voltage; see the Electrical Characteristics table

for details on how to set the MID_OUT voltage using the MVSEL1 and

MVSEL2 pins.

—

No internal connection. This pin must be left floating.

No internal connection. This pin can be left floating or tied to the GND plane

to improve thermal performance.

NC/GND

—

Output pin. A capacitor is required from OUT to ground for stability. For best

transient response, use the nominal recommended value or larger capacitor

from OUT to ground. Follow the recommended capacitor value as listed in

the Recommended Operating Conditions table. Place the output capacitor as

close to the OUT and GND pins of the device as possible.

OUT

Output

Power-good pin; an open-drain output indicates when the output voltage

reaches V_{IT(PG, RISING)}(typical). If not used, this pin can be left floating or tied

to the GND plane to improve thermal performance.

Submit Document Feedback

Product Folder Links: TPS7A43

TPS7A43

SBVS393 – DECEMBER 2020

www.ti.com

Table 5-1. Pin Functions (continued)

I/O

DESCRIPTION

DGQ

(Adjustable)

DGQ

(Fixed)

NAME

Exposed pad of the package. Connect this pad to ground or leave floating.

Connect the thermal pad to a large-area GND plane for improved thermal

performance.

Thermal pad

Pad

—

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

UNIT

V_IN

V_OUT⁽³⁾(adjustable version)

V_MID+ 0.3

V_OUT(fixed version)

5.5

V_IN+ 0.3

5.5

(4)

V_{MID_OUT}

Voltage⁽²⁾

V_FB

V_EN

V_MVSEL1

V_MVSEL2

V_PG

Maximum output

Maximum MID output

Operating junction, T_J

Storage, T_stg

Internally limited

–50

Current

150

Temperature

°C

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) All voltages with respect to GND.

(3) V_{MID_OUT}+ 0.3 V or 20 V (whichever is smaller).

(4) V_IN+ 0.3 V or 20 V (whichever is smaller).

6.2 ESD Ratings

VALUE

±2000

±750

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

(1) JEDEC document JEP155 states that 2-kV HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process.

Submit Document Feedback

Product Folder Links: TPS7A43

TPS7A43

SBVS393 – DECEMBER 2020

www.ti.com

6.3 Recommended Operating Conditions

MIN

NOM

MAX

UNIT

V_IN

Input voltage

V_{MID_OUT}

MID output voltage

V_{MID_OUT}

V_DO(OUT)

V_OUT

Output voltage (adjustable version)

1.24

V_OUT

Output voltage (fixed version)

Output current

1.25

5.5

I_OUT

50 - I_{MID_OUT}

I_{MID_OUT}

V_MVSEL1

V_MVSEL2

V_EN

MID rail output current

MID voltage select input voltage 1

MID voltage select input voltage 2

Enable voltage

(1)

V_PG

Power-good voltage

(2)

C_IN

Input capacitor

0.1

2.2

μF

°C

(2)

C_OUT

Output capacitor

3 x C_OUT

–40

100

125

(2) (3)

C_{MID_OUT}

T_J

MID output capacitor

Operating junction temperature

(1) Select pullup resistor to limit PG pin sink current when PG output is driven low. See Power Good section for details.

(2) All capacitor values are assumed to derate to 50% of the nominal capacitor value.

(3) Maintain a 3:1 ratio between C_{MID_OUT}vs C_OUTfor stability

6.4 Thermal Information

TPS7A43

THERMAL METRIC⁽¹⁾

HVSSOP (DGQ)

UNIT

8 PINS

53.7

76.6

26.8

3.6

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

Ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

Ψ_JB

26.7

9.6

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

Submit Document Feedback

Product Folder Links: TPS7A43

TPS7A43

SBVS393 – DECEMBER 2020

www.ti.com

6.5 Electrical Characteristics

specified at T_J= –40°C to +125°C, V_IN= V_OUT(nom)+ 1.5V or 4V, whiever is greater, FB tied to OUT (adjustable version only),

I_OUT= 1 mA, I_{MID_OUT}= open,V_EN= 2 V, V_MVSEL1= 0.9 V, V_MVSEL2= 0.9 V, C_IN= 1 μF, C_{MID_OUT}= 4.7 μF, and C_OUT= 1 μF

(unless otherwise noted); typical values are at T_J= 25°C

PARAMETER

TEST CONDITIONS

MIN

1.228

–0.5

–1

TYP

MAX

1.252

0.5

UNIT

ΔV_OUT

V_FB

Adjustable version, V_OUT= V_FB

1.24

Output voltage

accuracy

Fixed output version, T_J= 25℃

Fixed output version

Feedback voltage

Line regulation⁽¹⁾

Adjustable version only

1.24

(V_OUT(nom)+ 1 V or 4 V) ≤ V_IN≤ 85 V

V_{MID_OUT(nom)}+ 1.5 V ≤ V_IN≤ 85 V

–0.1

0.1

ΔV_OUT(ΔVIN)

–0.01

0.01

1 mA ≤ I_OUT≤ 50 mA,

I_{MID_OUT}= 0mA

ΔV_OUT(ΔIOUT)

Load regulation

–0.5

0.5

V_MVSEL1≤ V_MVSEL1(LOW)

V_MVSEL2≤ V_MVSEL2(LOW)

14.25

15.75

V_MVSEL1≤ V_MVSEL1(LOW)

or V_MVSEL1

V_MVSEL1(HIGH)

MID output voltage

accuracy

≥

ΔV_{MID_OUT}

V_IN= V_{MID_OUT}+ 1.5 V

11.4

12.6

V_MVSEL2≥ V_MVSEL2(HIGH)

V_MVSEL1≥ V_MVSEL1(HIGH)

V_MVSEL2≤ V_MVSEL2(LOW)

9.5

10.5

0.1

Line regulation of

MID output⁽¹⁾

(V_{MID_OUT(nom)}+ 1.5 V ≤ V_IN≤ 85 V,

I_{MID_OUT}= 1mA, I_OUT= 0 mA

ΔV_{MID_OUT(ΔVIN)}

–0.1

1 mA ≤ I_{MID_OUT}≤ 50 mA

V_IN= V_{MID_OUT}+ 1.5 V

I_OUT= 0mA

ΔV_{MID_OUT(Δ}

Load regulation of

MID output

–0.3

0.3

IOUT)

Dropout voltage of

V_{MID_OUT}to V_OUT

V_DO(OUT)

I_OUT= 50 mA

200

(2)

Dropout voltage of

V_INto V_{MID_OUT}

V_{DO(MID_OUT)}

I_CL(OUT)

I_{MID_OUT}= 50 mA

600

165

160

µA

(2)

Output current limit V_OUT= 0.9 × V_OUT(nom)

MID output current V_OUT= 0.9 × V_{MID_OUT(nom)}

100

125

5.5

I_{CL(MID_OUT)}

limit

V_IN= V_{MID_OUT}+ 1.5 V

T_J= 25°C

I_OUT= I_{MID_OUT}= 0 mA,

V_IN= V_{MID_OUT}+1.5 V

T_J= –40°C to +125°C

I_GND

Ground pin current

µA

I_OUT= 50 mA,

V_IN= V_{MID_OUT}+1.5 V

185

710

V_EN≤ V_EN(LOW)

V_{MID_OUT(nom)}+ 1.5 V ≤ V_IN≤ 85 V

I_OUT= I_{MID_OUT}= 0 mA

I_SHUTDOWN

Shutdown current

FB pin current

1900

I_FB

I_MVSEL1

I_MVSEL2

I_EN

MVSEL1 pin current V_MVSEL1= 17 V

MVSEL2 pin current V_MVSEL2= 17 V

EN pin current

V_EN= 17 V

MVSEL1 pin high-

level input voltage

V_MVSEL1(HIGH)

V_MVSEL1(LOW)

V_MVSEL2(HIGH)

V_MVSEL2(LOW)

V_EN(HI)

0.9

1.2

MVSEL1 pin low-

level input voltage

0.3

MVSEL2 pin high-

level input voltage

MVSEL2 pin low-

level input voltage

0.3

Enable rising

threshold

Device enabled

1.24

1.35

Submit Document Feedback

Product Folder Links: TPS7A43

TPS7A43

SBVS393 – DECEMBER 2020

www.ti.com

6.5 Electrical Characteristics (continued)

specified at T_J= –40°C to +125°C, V_IN= V_OUT(nom)+ 1.5V or 4V, whiever is greater, FB tied to OUT (adjustable version only),

I_OUT= 1 mA, I_{MID_OUT}= open,V_EN= 2 V, V_MVSEL1= 0.9 V, V_MVSEL2= 0.9 V, C_IN= 1 μF, C_{MID_OUT}= 4.7 μF, and C_OUT= 1 μF

(unless otherwise noted); typical values are at T_J= 25°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Enable falling

threshold

V_EN(LOW)

Device disabled

1.15

1.19

1.27

Enable pin

hysteresis

V_EN(HYST)

V_{IT(PG,RISING)}

V_HYS(PG)

%V_OUT

PG pin threshold

rising

R_PULLUP= 10 kΩ, V_OUTrising,

V_IN≥ V_UVLO(RISING)

96.5

R_PULLUP= 10 kΩ, V_OUTfalling,

V_IN≥ V_UVLO(RISING)

PG pin hysteresis

PG pin threshold

falling

R_PULLUP= 10 kΩ, V_OUTfalling,

V_IN≥ V_UVLO(RISING)

V_{IT(PG,FALLING)}

V_OL(PG)

PG pin low level

output voltage

V_OUT< V_{IT(PG,FALLING)}, I_PG-SINK= 500 µA

0.4

PG pin leakage

current

I_LKG(PG)

V_OUT> V_{IT(PG,RISING)}, V_PG= 18 V

f = 10 Hz

130

Power-supply

rejection ratio of

OUT rail

f = 100 Hz

I_OUT= 20mA

PSRR_(OUT)

f = 1 kHz

f = 100 kHz

f = 10 Hz

Power-supply

PSRR_{(MID_OUT)}rejection ratio of

MID_OUT rail

f = 100 Hz

I_{MID_OUT}= 20mA

f = 1 kHz

f = 100 kHz

Output noise

voltage

V_n

BW = 10 Hz to 100 kHz, V_OUT= 1.2 V

124

170

μV_RMS

°C

Thermal shutdown

T_SD(shutdown)

Shutdown, temperature increasing

temperature

(1) Line regulation from Input of the LDO to the final output of the LDO.

(2) V_DOis measured with V_IN= 0.97 × V_OUT(nom)for fixed output voltage versions. V_DOis not measured for fixed output voltage versions

when V_OUT≤ 2.5 V. For the adjustable output device, V_DOis measured with V_FB= 0.97 × V_FB(nom).

Submit Document Feedback

Product Folder Links: TPS7A43

TPS7A43

SBVS393 – DECEMBER 2020

www.ti.com

6.6 Typical Characteristics

at operating temperature T_J= 25°C, I_OUT= 1 mA, I_{MID_OUT}= open, V_EN= 2 V, V_MVSEL1= 0.9 V, V_MVSEL2= 0.9 V, C_IN= 1 μF,

C_{MID_OUT}= 4.7 μF, C_OUT= 1 μF, and V_IN= V_{MID_OUT}+ 1.5 V (unless otherwise noted); typical values are at T_J= 25°C

V_OUT

V_{MID_OUT}

V_PG

V_IN

V_OUT

V_{MID_OUT}

V_PG

V_IN

-1

-6

-1

-6

400

800

1,200

1,600

2,000

400

800

1,200

1,600

2,000

Time (ms)

V_MVSEL1= 0 V, V_MVSEL2= 0.9 V, V_INramp rate = 10 V/μs

V_MVSEL1= 0 V, V_MVSEL2= 0.9 V, V_INramp rate = 45 mV/μs

Figure 6-1. Fast Startup

Figure 6-2. Slow Startup

200

150

100

320

280

240

200

160

120

320

240

160

V_OUT

V_IN

V_OUT

V_{MID_OUT}

V_IN

-5

-50

-100

-150

-200

-10

-15

0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

Time (ms)

0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

Time (ms)

V_IN= 15 V to 85 V, V_INramp rate = 10 V/μs,V_MVSEL1= 0 V,

V_MVSEL2= 0.9 V, I_OUT= 1 mA, I_{MID_OUT}= open

V_IN= 15 V to 85 V, V_INramp rate = 10 V/μs,V_MVSEL1= 0 V,

V_MVSEL2= 0.9 V, I_OUT= 1 mA, I_{MID_OUT}= open

Figure 6-3. Line Transient

Figure 6-4. Line Transient (Zoom on V_OUT)

200

150

100

320

280

240

200

160

120

320

240

160

V_OUT

V_{MID_OUT}

V_IN

V_OUT

V_IN

-5

-50

-100

-150

-200

-10

-15

0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

Time (ms)

0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

Time (ms)

V_IN= 15 V to 85 V, V_INramp rate = 10 V/μs,V_MVSEL1= 0 V,

V_MVSEL2= 0.9 V, I_OUT= I_{MID_OUT}= 50 mA

V_IN= 15 V to 85 V, V_INramp rate = 10 V/μs,V_MVSEL1= 0 V,

V_MVSEL2= 0.9 V, I_OUT= I_{MID_OUT}= 50 mA

Figure 6-5. Line Transient

Figure 6-6. Line Transient (Zoom on V_OUT)

Submit Document Feedback

Product Folder Links: TPS7A43

TPS7A43

SBVS393 – DECEMBER 2020

www.ti.com

6.6 Typical Characteristics (continued)

at operating temperature T_J= 25°C, I_OUT= 1 mA, I_{MID_OUT}= open, V_EN= 2 V, V_MVSEL1= 0.9 V, V_MVSEL2= 0.9 V, C_IN= 1 μF,

C_{MID_OUT}= 4.7 μF, C_OUT= 1 μF, and V_IN= V_{MID_OUT}+ 1.5 V (unless otherwise noted); typical values are at T_J= 25°C

200

150

100

320

280

240

200

160

120

200

150

100

320

280

240

200

160

120

V_OUT

V_{MID_OUT}

V_IN

V_OUT

V_{MID_OUT}

V_IN

-50

-100

-150

-200

-100

-150

-200

80 100 120 140 160 180 200

Time (ms)

80 100 120 140 160 180 200

Time (ms)

V_IN= 15 V to 85 V, V_INramp rate = 10 V/μs,V_MVSEL1= 0 V,

V_MVSEL2= 0.9 V, I_OUT= I_{MID_OUT}= 50 mA

V_IN= 15 V to 85 V, V_INramp rate = 10 V/μs,V_MVSEL1= 0 V,

V_MVSEL2= 0.9 V, I_OUT= I_{MID_OUT}= 50 mA

Figure 6-7. Line Transient V_INRising Edge

Figure 6-8. Line Transient V_INFalling Edge

200

150

100

350

300

250

200

150

100

200

150

100

350

300

250

200

150

100

V_OUT

V_{MID_OUT}

I_OUT

V_OUT

V_{MID_OUT}

I_OUT

-50

-100

-150

-200

-100

-150

-200

-50

400

800

1,200

1,600

2,000

100

Time (ms)

V_IN= 50 V, V_MVSEL1= 0 V, V_MVSEL2= 0.9 V, I_{MID_OUT}= 1 mA,

I_OUTslew rate = 1 A/μs

V_IN= 50 V,V_MVSEL1= 0 V, V_MVSEL2= 0.9 V, I_{MID_OUT}= 1 mA,

I_OUTslew rate = 1 A/μs

Figure 6-9. Load Transient

Figure 6-10. Load Transient, I_OUTRising Edge

120

110

100

10k 100k

Frequency (Hz)

10M

100

10k

Frequency (Hz)

100k

10M

C_IN= open, C_OUT= 1 μF, V_{MID_OUT}= 12 V, C_{MID_OUT}= 3.3 μF,

I_{MID_OUT}= 20 mA, and I_OUT= open

C_IN= open, C_OUT= 1 μF, V_{MID_OUT}= 12 V, C_{MID_OUT}= 3.3 μF,

I_{MID_OUT}= open, and I_OUT= 20 mA

Figure 6-11. V_{MID_OUT}PSRR vs Frequency

Figure 6-12. V_OUTPSRR vs Frequency

Submit Document Feedback

Product Folder Links: TPS7A43

TPS7A43

SBVS393 – DECEMBER 2020

www.ti.com

7 Detailed Description

7.1 Overview

The TPS7A43 is an 85-V, low quiescent current, low-dropout (LDO) linear regulator. The low I_Qperformance

makes the device an excellent choice for battery-powered or line-power applications that are expected to meet

increasingly stringent standby-power standards.

The device high accuracy over temperature and power-good indication make this device an excellent choice for

meeting a wide range of microcontroller power requirements. The device features a selectable MID_OUT voltage

pin to provide a secondary voltage rail for various handheld power tool applications.

For increased reliability, the TPS7A43 also incorporates precision enable, output current limit, active discharge,

and thermal shutdown protection. The operating junction temperature is –40°C to +125°C, and adds margin for

applications concerned with higher working ambient temperatures.

7.2 Functional Block Diagrams

OUT

Current

Limit

Current

Limit

120 Ω

1.24-V

Bandgap

GND

MVSEL1

Internal

Controller

MVSEL2

Thermal

Shutdown

0.9 x 1.24-V Bandgap

GND

MID_OUT

Bandgap

GND

Figure 7-1. Adjustable Version

Submit Document Feedback

Product Folder Links: TPS7A43

TPS7A43

SBVS393 – DECEMBER 2020

www.ti.com

OUT

120 Ω

Current

Limit

Current

Limit

1.24-V

Bandgap

GND

MVSEL1

MVSEL2

550 kΩ

Internal

Controller

GND

Thermal

Shutdown

0.9 x 1.24-V Bandgap

GND

MID_OUT

Bandgap

GND

Figure 7-2. Fixed Version

7.3 Feature Description

7.3.1 MID_OUT Voltage Selection

The TPS7A43 features a MID_OUT voltage pin that provides a secondary output voltage supply in addtion to the

OUT pin, which is the main output voltage supply. The MID_OUT voltage can be set using the MVSEL1 and

MVSEL2 pins; see the MID_OUT Voltage Setting section for more details.

7.3.2 Precision Enable

The TPS7A43 features a precision enable circuit. The enable pin (EN) is active high; thus, enable the devcie by

forcing the voltage of the enable pin to exceed the minimum EN pin high-level voltage (see the Electrical

Characteristics table). Turn off the device by forcing the voltage of the enable pin to drop below the maximum EN

pin low-level input voltage (see the Electrical Characteristics table). This device has an internal pullup resisor to

the IN pin that enables the device when the EN pin is left floating.

If this pin is tied to the IN pin; the input voltage must not exceed 18 V; see the Recommended Operating

Conditions table.

Submit Document Feedback

Product Folder Links: TPS7A43

TPS7A43

SBVS393 – DECEMBER 2020

www.ti.com

As shown in Figure 7-3, an external resistor divider circuit can be used to enable the device using the input

voltage.

Internal

Controller

Bandgap

GND

Figure 7-3. Enable the Device Using the Input Voltage

The V_EN(HI)(maximum) threshold and the minimum input voltage to the application can be used to set the R₁to

R₂resistor divider ratio. The values of the R₂and R₁resistors then can be calcualted to minimize the leakeage

current throught the divider.

7.3.3 Dropout Voltage

Dropout voltage (V_DO) is defined as the input voltage minus the output voltage (V_IN– V_OUT) at the rated output

current (I_RATED), where the pass transistor is fully on. I_RATEDis the maximum I_OUTlisted in the Recommended

Operating Conditions table. The pass transistor is in the ohmic or triode region of operation, and acts as a

switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed

output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than

the nominal output regulation, then the output voltage falls as well.

For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (R_DS(ON)) of the

pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for

that current scales accordingly. The following equation calculates the R_DS(ON)of the device.

V_DO

R_DS(ON)

I_RATED

(1)

7.3.4 Current Limit

The device has an internal current limit circuit that protects the regulator during transient high-load current faults

or shorting events. The current limit is a brickwall scheme. In a high-load current fault, the brickwall scheme

limits the output current to the current limit (I_CL). I_CLis listed in the Electrical Characteristics table.

The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the

device begins to heat up because of the increase in power dissipation. When the device is in brickwall current

limit, the pass transistor dissipates power [(V_IN– V_OUT) × I_CL]. If thermal shutdown is triggered, the device turns

off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If the output

current fault condition continues, the device cycles between current limit and thermal shutdown. For more

information on current limits, see the Know Your Limits application report.

Submit Document Feedback

Product Folder Links: TPS7A43

TPS7A43

SBVS393 – DECEMBER 2020

www.ti.com

Figure 7-4 shows a diagram of the current limit.

V_OUT

Brickwall

V_OUT(NOM)

0 V

I_OUT

I_RATED

0 mA

I_CL

Figure 7-4. Current Limit

7.3.5 Thermal Shutdown

The device contains a thermal shutdown protection circuit to disable the device when the junction temperature

(T_J) of the pass transistor rises to T_SD(shutdown)(typical). Thermal shutdown hysteresis assures that the device

resets (turns on) when the temperature falls to T_SD(reset)(typical).

The thermal time-constant of the semiconductor die is fairly short, thus the device may cycle on and off when

thermal shutdown is reached until power dissipation is reduced. Power dissipation during startup can be high

from large V_IN– V_OUTvoltage drops across the device or from high inrush currents charging large output

capacitors. Under some conditions, the thermal shutdown protection disables the device before startup

completes.

When the thermal limit is triggered with the load current near the value of the current limit, the output may

oscillate prior to the output switching off.

For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating

Conditions table. Operation above this maximum temperature causes the device to exceed its operational

specifications. Although the internal protection circuitry of the device is designed to protect against thermal

overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device

into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability.

Submit Document Feedback

Product Folder Links: TPS7A43

TPS7A43

SBVS393 – DECEMBER 2020

www.ti.com

7.3.6 Power Good

The power-good (PG) pin is an open-drain output and can be connected to a regulated supply through an

external pullup resistor. The maximum pullup voltage is listed as V_PGin the Recommended Operating Conditions

table. For the PG pin to have a valid output, the voltage on the IN pin must be greater than V_UVLO(RISING), as

listed in the Electrical Characteristics table. When the V_OUTexceeds V_{IT(PG,RISING)}, the PG output is high

impedance and the PG pin voltage pulls up to the connected regulated supply. When the regulated output falls

below V_{IT(PG,FALLING)}, the open-drain output turns on and pulls the PG output low after a short deglitch time. If

output voltage monitoring is not needed, the PG pin can be left floating or connected to ground.

The recommended maximum PG pin sink current (I_PG-SINK) and the leakage current into the PG pin (I_LKG(PG)) are

listed in the Electrical Characteristics table.

The PG pullup voltage (V_{PG_PULLUP}), the desired minimum power-good output voltage (V_PG(MIN)), and I_LKG(PG)

limit the maximum PG pin pullup resistor value (R_{PG_PULLUP}). V_{PG_PULLUP}, the PG pin low-level output voltage

(V_OL(PG)), and I_PG-SINKlimit the minimum R_{PG_PULLUP}. Maximum and minimum values for R_{PG_PULLUP}can be

calculated from the following equations:

R_{PG_PULLUP(MAX)}= (V_{PG_PULLUP}– V_PG(MIN)) / I_{LKG(PG)_MAX}

R_{PG_PULLUP(MIN)}= (V_{PG_PULLUP}– V_OL(PG)) / I_PG-SINK

(2)

(3)

For example, if the PG pin is connected to a pullup resistor with a 3.3-V external supply, from the Electrical

Characteristics , R_{PG_PULLUP(MAX)}is 25 MΩ. From the Electrical Characteristics table, R_{PG_PULLUP(MIN)}is 6.6 kΩ.

Submit Document Feedback

Product Folder Links: TPS7A43

TPS7A43

SBVS393 – DECEMBER 2020

www.ti.com

7.4 Device Functional Modes

7.4.1 Device Functional Mode Comparison

The Device Functional Mode Comparison table shows the conditions that lead to the different modes of

operation. See the Electrical Characteristics table for parameter values.

Table 7-1. Device Functional Mode Comparison

PARAMETER

OPERATING MODE

V_IN

V_EN

I_OUT

T_J

Normal operation

Dropout operation

V_IN> V_OUT(nom)+ V_DOand V_IN> V_IN(min)

V_IN(min)< V_IN< V_OUT(nom)+ V_DO

V_EN> V_EN(HI)

I_OUT< I_OUT(max)

T_J< T_SD(shutdown)

Disabled

(any true condition

disables the device)

V_IN< V_UVLO

V_EN< V_EN(LOW)

Not applicable

T_J> T_SD(shutdown)

7.4.2 Normal Operation

The device regulates to the nominal output voltage when the following conditions are met:

•

The input voltage is greater than the nominal output voltage plus the dropout voltage (V_OUT(nom)+ V_DO)

The output current is less than the current limit (I_OUT< I_CL)

The device junction temperature is less than the thermal shutdown temperature (T_J< T_SD

)

•

The enable voltage has previously exceeded the enable rising threshold voltage and has not yet decreased

to less than the enable falling threshold

7.4.3 Dropout Operation

If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other

conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage

tracks the input voltage. During this mode, the transient performance of the device becomes significantly

degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load

transients in dropout can result in large output-voltage deviations.

When the device is in a steady dropout state (defined as when the device is in dropout, V_IN< V_OUT(NOM)+ V_DO

directly after being in a normal regulation state, but not during startup), the pass transistor is driven into the

ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output

voltage plus the dropout voltage (V_OUT(NOM)+ V_DO), the output voltage can overshoot for a short period of time

while the device pulls the pass transistor back into the linear region.

7.4.4 Disabled

The output of the device can be shutdown by forcing the voltage of the enable pin to less than the maximum EN

pin low-level input voltage (see the Electrical Characteristics table). When disabled, the pass transistor is turned

off and internal circuits are shutdown.

Submit Document Feedback

Product Folder Links: TPS7A43

TPS7A43

SBVS393 – DECEMBER 2020

www.ti.com

8 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

8.1 Application Information

8.1.1 MID_OUT Voltage Setting

The MID_OUT voltage has three different output voltage levels (10 V, 12 V, and 15 V), as listed in Table 8-1,

depending on the MVSEL1 and MVSEL2 pins voltage settings.

Table 8-1. MID_OUT Voltage Setting

SET V_MVSEL1

SET V_MVSEL2

MID_OUT

10 V

0.9 V ≤ V_MVSEL1≤ 17 V

0 V ≤ V_MVSEL1≤ 17 V

0 V ≤ V_MVSEL1≤ 0.4 V

0 V ≤ V_MVSEL2≤ 0.4 V

0.9 V ≤ V_MVSEL2≤ 17 V

0 V ≤ V_MVSEL2≤ 0.4 V

12 V

15 V

For adjustable voltage options of the TPS7A43, and to maintain voltage regulation on the MID_OUT and OUT

pins, the input voltage must be kept ≥ MID_OUT + V_{DO(MID_OUT)}. Additonally, to maintain regulation on the OUT

pin, the MID_OUT voltage must be set ≥ V_OUT(nom)+ V_DO(OUT)

TI recommends setting the MVSEL1 and MVSEL2 voltages for both the fixed and adjustable voltage options

before enabling the device to set the MID_OUT voltage level; however, the MID_OUT voltage setting can be

changed to a different level after the device had powered up.

8.1.2 Adjustable Device Feedback Resistors

The adjustable-version device requires external feedback divider resistors to set the output voltage. V_OUTis set

using the feedback divider resistors, R₁and R₂, according to the following equation:

V_OUT= V_FB× (1 + R₁/ R₂)

(4)

To ignore the FB pin current error term in the V_OUTequation, set the feedback divider current to 100x the FB pin

current listed in the Electrical Characteristics table. This setting provides the maximum feedback divider series

resistance, as shown in the following equation:

R₁+ R₂≤ V_OUT/ (I_FB× 100)

(5)

8.1.3 Recommended Capacitor Types

The device is designed to be stable using low equivalent series resistance (ESR) capacitors at the input and

output. Multilayer ceramic capacitors have become the industry standard for these types of applications and are

recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and C0G-

rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of Y5V-

rated capacitors is discouraged because of large variations in capacitance.

Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and

temperature. As a rule of thumb, expect the effective capacitance to decrease by as much as 50%. The input

and output capacitors recommended in the Recommended Operating Conditions table account for an effective

capacitance of approximately 50% of the nominal value.

Submit Document Feedback

Product Folder Links: TPS7A43

TPS7A43

SBVS393 – DECEMBER 2020

www.ti.com

8.1.4 Input and Output Capacitor Requirements

An input capacitor is not required for stability except when the device maximum current is sourced from the

MID_OUT pin. However, adding an input capacitor is always good analog design practice to counteract reactive

input sources and improve transient response, input ripple, and PSRR. Starting with the nominal input capacitor

value is required if large, fast transient load or line transients are anticipated on the MID_OUT pin or if the device

is located several inches from the input power source.

A minimum of a 3:1 capacitor ratio between C_{MID_OUT}and C_OUTis required for proper operation of the TPS7A43

LDO and TI recommends 4.7-μF capacitor to be connected from the MID_OUT pin to GND.

A minimum 1-μF output capacitor is required for V_OUTstability. A maximum 100-μF output capacitor can be used

as long as the 3:1 rato between C_{MID_OUT}and C_OUTis maintained.

8.1.5 Power Dissipation (P_D)

Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed

circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few

or no other heat-generating devices that cause added thermal stress.

To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference

and load conditions. The following equation calculates power dissipation (P_D).

P_D= (V_IN– V_OUT) × I_OUT

(6)

Note

Power dissipation can be minimized, and therefore greater efficiency can be achieved, by correct

selection of the system voltage rails. For the lowest power dissipation use the minimum input voltage

required for correct output regulation.

For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal

pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an

array of plated vias that conduct heat to additional copper planes for increased heat dissipation.

The maximum power dissipation determines the maximum allowable ambient temperature (T_A) for the device.

According to the following equation, power dissipation and junction temperature are most often related by the

junction-to-ambient thermal resistance (R_θJA) of the combined PCB and device package and the temperature of

the ambient air (T_A).

T_J= T_A+ (R_θJA× P_D)

(7)

Thermal resistance (R_θJA) is highly dependent on the heat-spreading capability built into the particular PCB

design, and therefore varies according to the total copper area, copper weight, and location of the planes. The

junction-to-ambient thermal resistance listed in the Thermal Information table is determined by the JEDEC

standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance.

8.1.6 Estimating Junction Temperature

The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures

of the linear regulator when in-circuit on a typical PCB board application. These metrics are not thermal

resistance parameters and instead offer a practical and relative way to estimate junction temperature. These psi

metrics are determined to be significantly independent of the copper area available for heat-spreading. The

Thermal Information table lists the primary thermal metrics, which are the junction-to-top characterization

parameter (ψ_JT) and junction-to-board characterization parameter (ψ_JB). These parameters provide two methods

for calculating the junction temperature (T_J), as described in the following equations. Use the junction-to-top

characterization parameter (ψ_JT) with the temperature at the center-top of device package (T_T) to calculate the

junction temperature. Use the junction-to-board characterization parameter (ψ_JB) with the PCB surface

temperature 1 mm from the device package (T_B) to calculate the junction temperature.

Submit Document Feedback

Product Folder Links: TPS7A43

TPS7A43

SBVS393 – DECEMBER 2020

www.ti.com

T_J= T_T+ ψ_JT× P_D

(8)

where:

•

P_Dis the dissipated power

T_Tis the temperature at the center-top of the device package

T_J= T_B+ ψ_JB× P_D

(9)

where

T_Bis the PCB surface temperature measured 1 mm from the device package and centered on the package

edge

•

For detailed information on the thermal metrics and how to use them, see the Semiconductor and IC Package

Thermal Metrics application report.

8.2 Typical Application

This section discusses the implementation of the TPS7A43 in cordless power tools application. Figure 8-1 shows

a typical circuit diagram for this appication.

VIN

VOUT

COUT

OUT

VCC

VSS

CIN

GND

MCU

VEN

GND

TPS7A4333

VMID_OUT

MID_OUT

MVSEL1

MVSEL2

GND

Gate

GND

VPG

VMSELV2

Driver

GND

Figure 8-1. Powering Cordless Power Tools

8.2.1 Design Requirements

Table 8-2 summarizes the design requirements for Figure 8-1.

Table 8-2. Design Parameters

PARAMETER

DESIGN VALUES

15 V (min), 85 V (transient max)

3.3 V ± 2 %

V_IN

V_OUT

V_{MID_OUT}

12 V ± 5 %

I_(IN)(no load)

I_OUT(tpyical), (max)

I_{MID_OUT}(tpyical), (max)

T_A

< 9 µA

20 mA, 50 mA

open , 1 mA

60 °C (max)

8.2.2 Detailed Design Procedure

A 3.3-V fixed output voltage devcie is slected for this application and the MVSEL1 pin is tied to GND to simplify

this design. The gate driver circuit is driven using the V_{MID_OUT}voltage by setting the MVSEL1 and MVSEL2 pins

by means of the MCU and GND refrence.

The input and output capacitors are selected in accordance with the Recommneded Operating Conditions table.

Submit Document Feedback

Product Folder Links: TPS7A43

TPS7A43

SBVS393 – DECEMBER 2020

www.ti.com

8.2.3 Application Curves

200

150

100

320

280

240

200

160

120

320

240

V_OUT

V_{MID_OUT}

V_IN

V_OUT

V_IN

-5

160

-50

-100

-150

-200

-10

-15

0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

Time (ms)

0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

Time (ms)

V_IN= 15 V to 85 V, V_INramp rate = 10 V/μs, V_MVSEL1= 0 V,

V_MVSEL2= 0.9 V, I_OUT= 50 mA, I_{MID_OUT}= open

V_IN= 15 V to 85 V, V_INramp rate = 10 V/μs, V_MVSEL1= 0 V,

V_MVSEL2= 0.9 V, I_OUT= 50 mA, I_{MID_OUT}= open

Figure 8-2. TPS7A43 Line Transient: 15 V to 85 V

Figure 8-3. TPS7A43 Line Transient: 15 V to 85 V

(Zoom on V_OUT

)

9 Power Supply Recommendations

The device is designed to operate from an input supply voltage range of 4 V to 85 V. To ensure that the output

voltage is well regulated and dynamic performance is optimum, the input supply must be at least V_{MID_OUT(nom)}

1.5 V. Connect a low output impedance power supply directly to the input pin of the TPS7A43.

10 Layout

10.1 Layout Guidelines

•

Place input and output capacitors as close to the device pins as possible.

Use copper planes for device connections to optimize thermal performance.

Place thermal vias around the device and under the thermal pad to distribute heat.

Only place tented thermal vias directly beneath the thermal pad of the DGQ package. An untented via can

wick solder or solder paste away from the thermal pad joint during the soldering process, leading to a

compromised solder joint on the thermal pad.

Submit Document Feedback

Product Folder Links: TPS7A43

TPS7A43

SBVS393 – DECEMBER 2020

www.ti.com

10.2 Layout Examples

CIN

COUT

OUT

GND Plane

OUT

MID_OUT

MVSEL2

Thermal Pad

CMID_OUT

R PG

MVSEL1

GND

GND Plane

Routing Via

Figure 10-1. Adjustable Version Layout Example

CIN

COUT

OUT

GND Plane

OUT

R PG

MVSEL1

GND

MID_OUT

MVSEL2

Thermal Pad

CMID_OUT

GND Plane

Routing Via

Figure 10-2. Fixed Version Layout Example

Submit Document Feedback

Product Folder Links: TPS7A43

TPS7A43

SBVS393 – DECEMBER 2020

www.ti.com

11 Device and Documentation Support

11.1 Device Support

11.1.1 Device Nomenclature

Table 11-1. Device Nomenclature ⁽¹⁾

PRODUCT

V_OUT

xx(x) is the nominal output voltage. For output voltages with a resolution of 100 mV, two

digits are used in the ordering number; for output voltages with a resolution of 50 mV, three

digits are used (for example, 28 = 2.8 V; 125 = 1.25 V). 01 indicates adjustable output

version.

TPS7A43xx(x) yyy z

yyy is the package designator.

z is the package quantity. R is for large quantity reel, T is for small quantity reel.

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the

device product folder at www.ti.com.

11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

11.3 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

11.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

11.6 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Submit Document Feedback

Product Folder Links: TPS7A43

PACKAGE OPTION ADDENDUM

www.ti.com

5-Feb-2021

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

PTPS7A4301DGQR

PTPS7A4333DGQR

PTPS7A4350DGQR

TPS7A4301DGQR

TPS7A4333DGQR

TPS7A4350DGQR

ACTIVE

HVSSOP

DGQ

2500 RoHS (In work)

& Non-Green

Call TI

-40 to 125

ACTIVE

DGQ

2500 RoHS (In work)

& Non-Green

Call TI

DGQ

2500 RoHS (In work)

& Non-Green

PREVIEW

DGQ

2500 RoHS (In work)

& Non-Green

DGQ

2500 RoHS (In work)

& Non-Green

DGQ

2500 RoHS (In work)

& Non-Green

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

5-Feb-2021

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

permission to use these resources only for development of an application that uses the TI products described in the resource. Other

reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party

intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,

costs, losses, and liabilities arising out of your use of these resources.

TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either

on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s

applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TPS7A43 [TI]

相关型号：

TPS7A4301DGQR

TPS7A4333DGQR

TPS7A4350DGQR

TPS7A44

TPS7A4401DGQR

TPS7A4433DGQR

TPS7A4450DGQR

TPS7A45

TPS7A4501

TPS7A4501-SP

TPS7A4501-SP_15

TPS7A4501DCQR