TPS7A4701RGWR [TI]
具有使能功能的 1A、36V、低噪声、高 PSRR、低压降稳压器 | RGW | 20 | -40 to 125;
| 型号： | TPS7A4701RGWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有使能功能的 1A、36V、低噪声、高 PSRR、低压降稳压器 | RGW | 20 | -40 to 125 稳压器 调节器 |
| 文件： | 总23页 (文件大小：906K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS7A47
www.ti.com
SBVS204A –JUNE 2012–REVISED JULY 2012
36-V, 1-A, 4.17-µV , RF LDO Voltage Regulator
RMS
1
FEATURES
DESCRIPTION
The TPS7A47 is a positive voltage (+36 V), ultralow-
23
•
Input Voltage Range: +3 V to +36 V
Output Voltage Noise
noise (4.17 µVRMS) linear regulator capable of
•
sourcing a 1-A load.
–
4.17 µVRMS (10 Hz, 100 kHz)
In addition, the TPS7A47 output voltage is fully user-
adjustable via a printed circuit board (PCB) layout
without the need of external resistors or feed-forward
capacitors, thus reducing overall component count.
•
•
Power-Supply Ripple Rejection:
–
–
82 dB (100 Hz)
≥ 55 dB (10 Hz, 10 MHz)
The TPS7A47 is designed with bipolar technology
ANY-OUT™ (User-Adjustable Output via
PCB Layout):
primarily
for
high-accuracy,
high-precision
instrumentation applications where clean voltage rails
are critical to maximize system performance. This
feature makes the device ideal for powering
operational amplifiers, analog-to-digital converters
(ADCs), digital-to-analog converters (DACs), and
other high-performance analog circuitry in critical
applications (such as medical, RF, and test-and-
measurement).
–
No External Resistors or Feed-Forward
Capacitors Required
–
Output Voltage Range: +1.4 V to +20.5 V
•
•
•
•
Output Current: 1 A
Dropout Voltage: 307 mV at 1 A
CMOS Logic Level-Compatible Enable Pin
Built-In Fixed Current Limit and
Thermal Shutdown
In addition, the TPS7A47 is ideal for post dc/dc
converter regulation. By filtering out the output
voltage ripple inherent to dc/dc switching
conversions, maximum system performance is
ensured in sensitive instrumentation, test-and-
measurement, audio, and RF applications.
•
•
Available in High Thermal Performance
Package:
–
5-mm × 5-mm QFN
Operating Temperature Range:
–40°C to +125°C
For applications where positive and negative low-
noise rails are required, consider TI's TPS7A33 family
of negative high-voltage, ultralow-noise linear
regulators.
APPLICATIONS
•
•
•
•
•
•
Voltage-Controlled Oscillators (VCO)
Frequency Synthesizers
TPS7A47
RF LDO
Test and Measurement Applications
Medical Applications
RX, TX, and PA Circuitry
Supply Rails for Operational Amplifiers,
DACs, ADCs, and Other High-Precision Analog
Circuitry
Amplifier
•
•
Audio Applications
Post DC/DC Converter Regulation and
Ripple Filtering
•
•
•
Industrial Instrumentation
Base Stations and Telecom Infrastructure
+12-V and +24-V Industrial Buses
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
ANY-OUT, PowerPAD are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
TPS7A47
SBVS204A –JUNE 2012–REVISED JULY 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
PACKAGE-
LEAD
PACKAGE
DESIGNATOR
SPECIFIED TEMPERATURE
RANGE
PRODUCT
TPS7A4700RGW
VQFN
RGW
–40°C ≤ TJ ≤ +125°C
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range, unless otherwise noted.(1)
VALUE
MIN
UNIT
MAX
IN pin to GND pin
–0.4
–0.4
–36
+36
V
V
V
V
V
V
V
V
V
V
V
V
V
V
EN pin to GND pin
EN pin to IN pin
+36
+0.4
OUT pin to GND pin
NR pin to GND pin
SENSE pin to GND pin
0P1V pin to GND pin
0P2V pin to GND pin
0P4V pin to GND pin
0P8V pin to GND pin
1P6V pin to GND pin
3P2V pin to GND pin
6P4V1 pin to GND pin
6P4V2 pin to GND pin
Peak output
–0.4
–0.4
–0.4
–0.4
–0.4
–0.4
–0.4
–0.4
–0.4
–0.4
–0.4
+36
+36
+36
+36
Voltage(2)
+36
+36
+36
+36
+36
+36
+36
Current
Internally limited
+125
Operating virtual junction, TJ
Storage, Tstg
–40
–65
°C
°C
Temperature
+150
Human body model (HBM)
QSS 009-105 (JESD22-A114A)
1000
500
V
V
Electrostatic discharge (ESD)
ratings(3)
Charge device model (CDM)
QSS 009-147 (JESD22-C101B.01)
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
(2) All voltages are with respect to network ground terminal.
(3) ESD testing is performed according to the respective JESD22 JEDEC standard.
2
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TPS7A47
www.ti.com
SBVS204A –JUNE 2012–REVISED JULY 2012
ELECTRICAL CHARACTERISTICS
At –40°C ≤ TJ ≤ +125°C; VIN = VOUT(NOM) + 1.0 V or VIN = 3.0 V (whichever is greater); VEN = VIN; IOUT = 0 mA; CIN =10 µF;
COUT = 10 µF; CNR = 10 nF; SENSE tied to OUT; and 0P1V, 0P2V, 0P4V, 0P8V, 1P6V, 3P2V, 6P4V1, 6P4V2 pins OPEN,
unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN
Input voltage range
3
35
V
VIN rising
VIN falling
2.67
V
VUVLO
Under-voltage lockout threshold
2.5
177
V
VUVLO_HYS
VNR
Under-voltage lockout hysteresis
Noise reduction pin voltage
mV
V
VOUT
V
IN ≥ VOUT(NOM) + 1.0 V or 3V (whichever is greater),
Output voltage range
Nominal accuracy
Overall accuracy
1.4
–1.0
–2.5
20.5
1.0
V
COUT = 20 µF
VOUT
TJ = +25°C, COUT = 20 µF
%VOUT
%VOUT
VOUT(NOM) + 1.0 V ≤ VIN ≤ 35 V, 0 mA ≤ IOUT ≤ 1 A,
COUT = 20 µF
2.5
ΔVOUT(ΔVIN)/
VOUT(NOM)
Line regulation
Load regulation
VOUT(NOM) + 1.0 V ≤ VIN ≤ 35 V
0 mA ≤ IOUT ≤ 1 A
0.092
0.3
%VOUT
%VOUT
ΔVOUT(ΔIOUT)/
VOUT(NOM)
VIN = 95% VOUT(NOM), IOUT = 0.5 A
VIN = 95% VOUT(NOM), IOUT = 1 A
VOUT = 90% VOUT(NOM)
IOUT = 0 mA
216
307
mV
mV
A
VDO
ICL
Dropout voltage
Current limit
450
1.0
1
1.26
0.58
6.1
mA
mA
µA
µA
µA
µA
V
IGND
Ground pin current
IOUT = 1 A
VEN = 0.4 V
2.55
3.04
0.78
0.81
8
60
2
ISHDN
Shutdown supply current
Enable pin current
VEN = 0.4 V, VIN = 35 V
VEN = VIN
IEN
VIN = VEN = 35 V
2
V+EN(HI)
V+EN(LO)
Enable high-level voltage
Enable low-level voltage
2.0
0.0
VIN
0.4
V
VIN = 3 V, VOUT(NOM) = 1.4 V, COUT = 50 µF,
CNR = 1 µF, BW = 10 Hz to 100 kHz
4.17
4.67
78
µVRMS
µVRMS
dB
VNOISE
Output noise voltage
VIN = 6 V, VOUT(NOM) = 5 V, COUT = 50 µF,
CNR = 1 µF, BW = 10 Hz to 100 kHz
VIN = 16 V, VOUT(NOM) = 15 V, COUT = 50 µF,
IOUT = 500 mA, CNR = 1 µF, f = 1 kHz
PSRR
TJ
Power-supply rejection ratio
Operating junction temperature
–40
+125
°C
°C
°C
Shutdown, temperature increasing
Reset, temperature decreasing
+170
+150
TSD
Thermal shutdown temperature
THERMAL INFORMATION
TPS7A47
RGW
20 PINS
32.5
THERMAL METRIC(1)
UNITS
θJA
Junction-to-ambient thermal resistance
θJCtop
θJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
27
11.9
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ψJB
11.9
θJCbot
1.7
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2012, Texas Instruments Incorporated
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TPS7A47
SBVS204A –JUNE 2012–REVISED JULY 2012
www.ti.com
PIN CONFIGURATIONS
RGW PACKAGE
5-mm × 5-mm QFN-20
(TOP VIEW)
1
2
3
4
5
15 IN
OUT
NC
14
13
12
11
NR
SENSE
6P4V2
6P4V1
EN
0P1V
0P2V
PIN DESCRIPTIONS
PIN
NAME
NO.
DESCRIPTION
When connected to GND, this pin adds 0.1 V to the nominal output voltage of the regulator.
Do not connect any voltage other than GND to this pin. If not used, leave this pin floating.
0P1V
12
When connected to GND, this pin adds 0.2 V to the nominal output voltage of the regulator.
Do not connect any voltage other than GND to this pin. If not used, leave this pin floating.
0P2V
0P4V
0P8V
1P6V
3P2V
6P4V1
6P4V2
11
10
9
When connected to GND, this pin adds 0.4 V to the nominal output voltage of the regulator.
Do not connect any voltage other than GND to this pin. If not used, leave this pin floating.
When connected to GND, this pin adds 0.8 V to the nominal output voltage of the regulator.
Do not connect any voltage other than GND to this pin. If not used, leave this pin floating.
When connected to GND, this pin adds 1.6 V to the nominal output voltage of the regulator.
Do not connect any voltage other than GND to this pin. If not used, leave this pin floating.
8
When connected to GND, this pin adds 3.2 V to the nominal output voltage of the regulator.
Do not connect any voltage other than GND to this pin. If not used, leave this pin floating.
6
When connected to GND, this pin adds 6.4 V to the nominal output voltage of the regulator.
Do not connect any voltage other than GND to this pin. If not used, leave this pin floating.
5
When connected to GND, this pin adds 6.4 V to the nominal output voltage of the regulator.
Do not connect any voltage other than GND to this pin. If not used, leave this pin floating.
4
EN
13
7
This pin turns the regulator on and off.
Ground
GND
Input supply. A capacitor greater than or equal to 1 µF must be tied from this pin to ground to assure stability.
A 10-µF capacitor is recommended to be connected from IN to GND (as close to the device as possible) to reduce
circuit sensitivity to printed-circuit-board (PCB) layout, especially when long input traces or high source
impedances are encountered.
IN
15, 16
NC
NR
2, 17-19 This pin can be left open or tied to any voltage between GND and IN.
Noise reduction pin. When a capacitor is connected from this pin to GND, RMS noise can be reduced to very low
levels. A capacitor greater than or equal to 10 nF must be tied from this pin to ground to assure stability. A 1-µF
capacitor is recommended to be connected from NR to GND (as close to the device as possible) to maximize ac
14
performance and minimize noise.
Regulator output. A capacitor greater than or equal to 10 µF must be tied from this pin to ground to assure
OUT
1, 20
3
stability. A 47-µF ceramic output capacitor is highly recommended to be connected from OUT to GND (as close to
the device as possible) to maximize ac performance.
Control-loop error amplifier input. This pin must be connected to OUT.
OUT is recommended to be connected at the point of load to maximize accuracy.
SENSE
4
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Copyright © 2012, Texas Instruments Incorporated
TPS7A47
www.ti.com
SBVS204A –JUNE 2012–REVISED JULY 2012
FUNCTIONAL BLOCK DIAGRAM
IN
IN
OUT
Thermal
Shutdown
UVLO
OUT
CIN
COUT
Current
Limit
100 kW
Band
Gap
265.5 kW
SENSE
3.2 MW
0P1V
0P2V
0P4V
0P8V
1.6 MW
800 kW
400 kW
1.572 MW
Fast
Charge
1P6V 3P2V 6P4V 6P4V
NR
CNR
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TPS7A47
SBVS204A –JUNE 2012–REVISED JULY 2012
www.ti.com
TYPICAL CHARACTERISTICS
At –40°C ≤ TJ ≤ +125°C; VIN = VOUT(NOM) + 1.0 V or VIN = 3.0 V (whichever is greater); VEN = VIN; IOUT = 0 mA; CIN =10 µF;
COUT = 10 µF; CNR = 1 µF; SENSE tied to OUT; and 0P1V, 0P2V, 0P4V, 0P8V, 1P6V, 3P2V, 6P4V1, 6P4V2 pins OPEN,
unless otherwise noted.
NOISE vs OUTPUT VOLTAGE
LINE REGULATION
100
10
4
3
VOUT = 1.4 V,VNOISE = 4.17 µVRMS
VOUT = 5 V,VNOISE = 4.67 µVRMS
VOUT = 10 V,VNOISE = 7.25 µVRMS
VOUT = 15 V,VNOISE = 12.28 µVRMS
−40°C
0°C
+25°C
+85°C
+125°C
2
1
IOUT = 500 mA
COUT = 50 µF
CNR = 1 µF
1
0
−1
−2
−3
−4
BWRMSNOISE (10 Hz, 100 kHz)
0.1
0.01
10
100
1k
10k
100k
1M
0
5
10
15
20
25
30
35
40
Frequency (Hz)
Input Voltage (V)
G020
G001
Figure 1.
Figure 2.
LOAD REGULATION
DROPOUT VOLTAGE vs OUTPUT CURRENT
4
3
1000
900
800
700
600
500
400
300
200
100
0
−40°C
0°C
+25°C
+85°C
−40°C
0°C
+25°C
+85°C
+125°C
2
+125°C
1
0
−1
−2
−3
−4
0
100 200 300 400 500 600 700 800 900 1000
0
100 200 300 400 500 600 700 800 900 1000
Output Current (mA)
Output Current (mA)
G002
G003
Figure 3.
Figure 4.
UVLO THRESHOLD vs TEMPERATURE
ENABLE VOLTAGE THRESHOLD vs TEMPERATURE
3
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2
3
UVLO Threshold Off
UVLO Threshold On
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
−40 −25 −10
5
20 35 50 65 80 95 110 125
Temperature (°C)
−40 −25 −10
5
20 35 50 65 80 95 110 125
Temperature (°C)
G004
G005
Figure 5.
Figure 6.
6
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TPS7A47
www.ti.com
SBVS204A –JUNE 2012–REVISED JULY 2012
TYPICAL CHARACTERISTICS (continued)
At –40°C ≤ TJ ≤ +125°C; VIN = VOUT(NOM) + 1.0 V or VIN = 3.0 V (whichever is greater); VEN = VIN; IOUT = 0 mA; CIN =10 µF;
COUT = 10 µF; CNR = 1 µF; SENSE tied to OUT; and 0P1V, 0P2V, 0P4V, 0P8V, 1P6V, 3P2V, 6P4V1, 6P4V2 pins OPEN,
unless otherwise noted.
QUIESCENT CURRENT vs INPUT VOLTAGE
GROUND CURRENT vs OUTPUT CURRENT
1000
800
600
400
200
0
10
1
−40°C
0°C
−40°C
0°C
+25°C
+85°C
+125°C
+25°C
+105°C
+125°C
IOUT = 0 µA
0.1
0
0
0
5
10
15
20
25
30
35
40
1
10
100
1000
Input Voltage (V)
Figure 7.
Output Current (mA)
Figure 8.
G006
G007
ENABLE CURRENT vs INPUT VOLTAGE
SHUTDOWN CURRENT vs INPUT VOLTAGE
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
10
9
8
7
6
5
4
3
2
1
0
−40°C
0°C
+25°C
+85°C
+125°C
−40°C
0°C
+25°C
+105°C
+125°C
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
Input Voltage (V)
Figure 9.
Input Voltage (V)
Figure 10.
G008
G009
CURRENT LIMIT vs INPUT VOLTAGE
POWER-SUPPLY REJECTION RATIO vs CNR
3
2.5
2
100
90
80
70
60
50
40
30
20
10
0
VOUT = 90% VOUT(NOM)
1.5
1
−40°C
0°C
+25°C
+85°C
+125°C
IOUT = 1 A
COUT = 50 µF
VIN = 3 V
CNR = 0.01 µF
CNR = 0.1 µF
CNR = 1 µF
0.5
0
VOUT = 1.4 V
CNR = 2.2 µF
4
8
12
16
20
10
100
1k
10k
100k
1M
10M
Input Voltage (V)
Frequency (Hz)
G010
G011
Figure 11.
Figure 12.
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TYPICAL CHARACTERISTICS (continued)
At –40°C ≤ TJ ≤ +125°C; VIN = VOUT(NOM) + 1.0 V or VIN = 3.0 V (whichever is greater); VEN = VIN; IOUT = 0 mA; CIN =10 µF;
COUT = 10 µF; CNR = 1 µF; SENSE tied to OUT; and 0P1V, 0P2V, 0P4V, 0P8V, 1P6V, 3P2V, 6P4V1, 6P4V2 pins OPEN,
unless otherwise noted.
POWER-SUPPLY REJECTION RATIO vs CNR
POWER-SUPPLY REJECTION RATIO vs IOUT
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
CNR = 0.01 µF
CNR = 0.1 µF
CNR = 1 µF
IOUT = 0.5 A
COUT = 50 µF
VIN = 3 V
CNR = 1 µF
COUT = 50 µF
VIN = 3 V
IOUT = 0 mA
IOUT = 50 mA
IOUT = 500 mA
IOUT = 1000 mA
CNR = 2.2 µF
VOUT = 1.4 V
VOUT = 1.4 V
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
G012
G013
Figure 13.
Figure 14.
POWER-SUPPLY REJECTION RATIO vs DROPOUT
POWER-SUPPLY REJECTION RATIO vs DROPOUT
100
100
90
80
70
60
50
40
30
20
10
0
VDO = 200 mV
VDO = 300 mV
VDO = 500 mV
VDO = 1 V
90
80
70
60
50
40
30
20
10
0
VOUT = 3.3 V,IOUT = 500 mA
CNR = 1 µF,COUT = 50 µF
VOUT = 3.3 V
CNR = 1 µF
COUT = 50 µF
IOUT = 50 mA
VDO = 200 mV
VDO = 300 mV
VDO = 500 mV
VDO = 1 V
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
G014
G015
Figure 15.
Figure 16.
POWER-SUPPLY REJECTION RATIO vs DROPOUT
POWER-SUPPLY REJECTION RATIO vs OUTPUT VOLTAGE
100
90
80
70
60
50
40
30
20
10
0
100
VDO = 200 mV
VDO = 300 mV
VDO = 500 mV
VDO = 1 V
90
80
70
60
50
VOUT = 3.3 V
CNR = 1 µF
COUT = 50 µF
IOUT = 1 A
40
VOUT = 1.4 V
VOUT = 3.3 V
VOUT = 5V
VOUT = 10V
VOUT = 15 V
30
CNR = 1 µF
COUT = 50 µF
IOUT = 500 mA
20
10
0
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
G016
G017
Figure 17.
Figure 18.
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TYPICAL CHARACTERISTICS (continued)
At –40°C ≤ TJ ≤ +125°C; VIN = VOUT(NOM) + 1.0 V or VIN = 3.0 V (whichever is greater); VEN = VIN; IOUT = 0 mA; CIN =10 µF;
COUT = 10 µF; CNR = 1 µF; SENSE tied to OUT; and 0P1V, 0P2V, 0P4V, 0P8V, 1P6V, 3P2V, 6P4V1, 6P4V2 pins OPEN,
unless otherwise noted.
POWER-SUPPLY REJECTION RATIO vs OUTPUT VOLTAGE
LOAD TRANSIENT
100
90
80
70
60
50
IOUT
(1 A/div)
40
VOUT = 1.4V
VOUT = 3.3V
30
VOUT
(10 mV/div)
VIN = 5 V
VOUT = 5V
VOUT = 10V
VOUT = 15V
CNR = 1µF
COUT = 50µF
IOUT = 1000mA
20
10
0
VOUT = 3.3 V
IOUT = 10 mA to 845 mA
10
100
1k
10k
100k
1M
10M
Time (500 ms/div)
G060
Frequency (Hz)
G018
Figure 19.
Figure 20.
STARTUP
LINE TRANSIENT
VIN = 5 V to 15 V
VOUT = 3.3 V
IOUT = 845 mA
VEN
(2 V/div)
VIN
VOUT
(10 V/div)
(2 V/div)
Startup Time = 65 ms
VIN = 6 V, VOUT = 5 V
IOUT
VOUT
(200 mA/div)
IOUT = 500 mA
CIN = 10 mF
(10 mV/div)
COUT = 50 mF
Time (5 ms/div)
Time (50 ms/div)
G061
G062
Figure 21.
Figure 22.
NOISE vs OUTPUT CURRENT
100
IOUT = 50 mA, VNOISE = 5 µVRMS
IOUT = 20 mA, VNOISE = 5.9 µVRMS
10
1
VOUT = 4.7 V
COUT = 10 µF
CNR = 1 µF
BWRMSNOISE [10 Hz, 100 kHz]
0.1
0.01
10
100
1k
10k
100k
1M
Frequency (Hz)
G019
Figure 23.
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APPLICATION INFORMATION
TYPICAL APPLICATION CIRCUIT
Output voltage is set by grounding the appropriate control pins, as shown in Figure 24. When grounded, all
control pins add a specific voltage on top of the internal reference voltage (VREF = 1.4 V). For example, when
grounding pins 0P1V, 0P2V, and 1P6V, the voltage values 0.1 V, 0.2 V, and 1.6 V are added to the 1.4-V
internal reference voltage for VOUT(NOM) equal to 3.3 V, as described in Equation 1.
VOUT(NOM) = VREF + 0.1 V + 0.2 V + 1.6 V = 1.4 V + 0.1 V + 0.2 V + 1.6 V = 3.3 V
(1)
VIN = 5 V
VOUT = 3.3 V
IN
OUT
10 mF
47 mF
EN
NR
SENSE
GND
Load
1 mF
0P1V
0P2V
0P4V 0P8V 1P6V 3P2V 6P4V1 6P4V2
Figure 24. Maximize PSRR Performance and Minimize RMS Noise
ANY-OUT PROGRAMMABLE OUTPUT VOLTAGE
The TPS7A4700 does not use external resistors to set output voltage, as is typical of low-dropout regulators
(LDOs), but uses device pins 4, 5, 6, 8, 9, 10, 11, and 12 to program the regulated output voltage. Each pin is
either connected to ground (active) or is left open, or floating, (inactive). The ANY-OUT programming is set by
Equation 2 as the sum of the internal reference voltage (VREF = 1.4 V) plus the accumulated sum of the
respective voltages assigned to each active pin. That is, 100 mV (pin 12), 200 mV (pin 11), 400 mV (pin 10), 800
mV (pin 9), 1.6 V (pin 8), 3.2 V (pin 6), 6.4 V (pin 5), or 6.4 V (pin 4). Table 1 summarizes these voltage values
associated with each active pin setting for reference. By leaving all program pins open, or floating, the output is
thereby programmed to the minimum possible output voltage equal to VREF
.
VOUT = VREF + (S ANY-OUT Pins to Ground)
(2)
Table 1. ANY-OUT Programmable Output Voltage
ANY-OUT PROGRAM PINS (Active Low)
ADDITIVE OUTPUT VOLTAGE LEVEL
Pin 4 (6P4V2)
Pin 5 (6P4V1)
Pin 6 (3P2)
6.4 V
6.4 V
3.2 V
Pin 8 (1P6)
1.6 V
Pin 9 (0P8)
800 mV
400 mV
200 mV
100 mV
Pin 10 (0P4)
Pin 11 (0P2)
Pin 12 (0P1)
There are several alternative ways to set the output voltage. The program pins can be driven using external
general-purpose input/output pins (GPIOs), manually connected to ground using 0-Ω resistors (or left open), or
hardwired by the given layout of the printed circuit board (PCB) to set the ANY-OUT voltage. The TPS7A4700
evaluation module (EVM), available for download from www.ti.com, allows the output voltage to be programmed
using jumpers.
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CAPACITOR RECOMMENDATION
The TPS7A4700 is designed to be stable using low equivalent series resistance (ESR), ceramic capacitors at the
input, output, and at the noise reduction pin (NR, pin 14). Multilayer ceramic capacitors have become the industry
standard for these types of applications and are recommended here, but must be used with good judgment.
Ceramic capacitors that employ X7R-, X5R-, and COG-rated dielectric materials provide relatively good
capacitive stability across temperature whereas the use of Y5V-rated capacitors is discouraged precisely
because the capacitance varies so widely. In all cases, ceramic capacitance varies a great deal with operating
voltage and the design engineer should be aware of these characteristics. As a rule of thumb, ceramic capacitors
are recommended to be derated by 50%. The input and output capacitors recommended herein account for a
capacitance derating of 50%.
Attention should be given to the input capacitance to minimize transient input droop during load current steps
because the TPS7A4700 has a very fast load transient response. Large input capacitances (greater than 10 µF)
have a good effect and do not affect stability. Note however that simply using large ceramic input capacitances
can also cause unwanted ringing at the output if the input capacitor, in combination with the wire lead
inductance, creates a high-Q peaking effect during transients. For example, a 5-nH lead inductance and a 10-µF
input capacitor form an LC filter with a resonance frequency of 712 kHz at the edge of the control loop
bandwidth. Short, well-designed interconnect leads to the up-stream supply minimize this effect without adding
damping. Damping of unwanted ringing can be accomplished by using a tantalum capacitor, with a few hundred
milliohms of ESR, in parallel with the ceramic input capacitor.
Input and Output Capacitor Requirements
The TPS7A4700 is designed and characterized for operation with ceramic capacitors of 10 µF or greater at the
input and output. Optimal noise performance is characterized using a total output capacitor value of 50 µF. Note
especially that input and output capacitances should be located as near as practical to the respective input and
output pins.
Noise Reduction Capacitor (CNR
)
The noise reduction capacitor, connected to the NR pin of the LDO, forms an RC filter for filtering out noise that
might ordinarily be amplified by the control loop and appear on the output voltage. Larger capacitances, up to 1
µF, affect noise reduction at lower frequencies while also tending to further reduce noise at higher frequencies.
Note that CNR also serves a secondary purpose in programming the turn-on rise time of the output voltage and
thereby controls the turn-on surge current.
INTERNAL CURRENT LIMIT (ICL)
The internal current limit circuit is used to protect the LDO against high-load current faults or shorting events. The
LDO is not designed to operate at a steady-state current limit. During a current-limit event, the LDO sources
constant current. Therefore, the output voltage falls while load impedance decreases. Note also that when a
current limit occurs while the resulting output voltage is low, excessive power may be dissipated across the LDO,
which results in a thermal shutdown of the output.
DROPOUT VOLTAGE (VDO)
Generally speaking, the dropout voltage often refers to the voltage difference between the input and output
voltage (VDO = VIN – VOUT). However, in the Electrical Characteristics VDO is defined as the VIN – VOUT voltage at
the rated current (IRATED), where the main current pass-FET is fully on in the Ohmic region of operation and is
characterized by the classic RDS(ON) of the FET. VDO indirectly specifies a minimum input voltage above the
nominal programmed output voltage at which the output voltage is expected to remain within its accuracy
boundary. If the input falls below this VDO limit (VIN < VOUT + VDO), then the output voltage decreases in order to
follow the input voltage.
Dropout voltage is always determined by the RDS(ON) of the main pass-FET. Therefore, if the LDO operates below
the rated current, then the VDO for that current scales accordingly. The RDS(ON) for the TPS7A4700 can be
calculated using Equation 3.
VDO
RDS(ON)
=
IRATED
(3)
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OUTPUT VOLTAGE ACCURACY
The output voltage accuracy specifies minimum and maximum output voltage error, relative to the expected
nominal output voltage stated as a percent. This accuracy error typically includes the errors introduced by the
internal reference and the load and line regulation across the full range of rated load and line operating
conditions over temperature, unless otherwise specified by the Electrical Characteristics. Output voltage
accuracy also accounts for all variations between manufacturing lots.
STARTUP
Enable (EN) and Under-Voltage Lockout (UVLO)
The TPS7A4700 only turns on when both EN and UVLO are above the respective voltage thresholds. The UVLO
circuit monitors input voltage (VIN) to prevent device turn-on before VIN rises above the lockout voltage. The
UVLO circuit also causes a shutdown when VIN falls below lockout. The EN signal allows independent logic-level
turn-on and shutdown of the LDO when the input voltage is present. EN can be connected directly to VIN if
independent turn-on is not needed.
Soft-Start and Inrush Current
Soft-start refers to the ramp-up characteristic of the output voltage during LDO turn-on after EN and UVLO have
achieved threshold voltage. The noise reduction capacitor serves a dual purpose of both governing output noise
reduction and programming the soft-start ramp during turn-on.
Inrush current is defined as the current through the LDO from IN to OUT during the time of the turn-on ramp up.
Inrush current then consists primarily of the sum of load and charge current to the output capacitor. This current
is difficult to measure because the input capacitor must be removed, which is not recommended. However, this
soft-start current can be estimated by Equation 4:
C
OUT ´ dVOUT(t)
VOUT(t)
RLOAD
IOUT(t)
=
+
dt
where:
VOUT(t) is the instantaneous output voltage of the turn-on ramp,
dVOUT(t)/dt is the slope of the VOUT ramp, and
RLOAD is the resistive load impedance.
(4)
AC PERFORMANCE
LDO ac performance is typically understood to include power-supply rejection ratio, load step transient response,
and output noise. These metrics are primarily a function of open-loop gain and bandwidth, phase margin, and
reference noise.
Power-Supply Rejection Ratio (PSRR)
PSRR is a measure of how well the LDO control loop rejects ripple noise from the input source to make the dc
output voltage as noise-free as possible across the frequency spectrum (usually 10 Hz to 10 MHz). Even though
PSRR is therefore a loss in noise signal amplitude (the output ripple relative to the input ripple), the PSRR
reciprocal is plotted in the Electrical Characteristics as a positive number in decibels (dB) for convenience.
Equation 5 gives the PSRR calculation as a function of frequency where input noise voltage [VS(IN)(f)] and output
noise voltage [VS(OUT)(f)] are understood to be purely ac signals.
VS(IN)(f)
PSRR (dB) = 20 Log10
VS(OUT)(f)
(5)
Noise that couples from the input to the internal reference voltage for the control loop is also a primary
contributor to reduced PSRR magnitude and bandwidth. This reference noise is greatly filtered by the noise
reduction capacitor at the NR pin of the LDO in combination with an internal filter resistor (RSS) for optimal
PSRR.
The LDO is often employed not only as a dc/dc regulator, but also to provide exceptionally clean power-supply
voltages that are free of noise and ripple to power-sensitive system components. This usage is especially true for
the TPS7A4700.
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Load Step Transient Response
The load step transient response is the output voltage response by the LDO to a step change in load current
whereby output voltage regulation is maintained. The worst-case response is characterized for a load step of
10 mA to 1 A (at 1 A per microsecond) and shows a classic critically-damped response of a very stable system.
The voltage response shows a small dip in the output voltage when charge is initially depleted from the output
capacitor and then the output recovers as the control loop adjusts itself. The depth of the charge depletion
immediately after the load step is directly proportional to the amount of output capacitance. However, to some
extent, the speed of recovery is inversely proportional to that same output capacitance. In other words, larger
output capacitances act to decrease any voltage dip or peak occurring during a load step but also decrease the
control-loop bandwidth, thereby slowing response.
The worst-case off-loading step characterization occurs when the current step transitions from 1 A to 0 mA.
Initially, the LDO loop cannot respond fast enough to prevent a small increase in output voltage charge on the
output capacitor. Because the LDO cannot sink charge current, the control loop must turn off the main pass-FET
to wait for the charge to deplete, thus giving the off-load step its typical monotonic decay (which appears
triangular in shape).
Noise
The TPS7A4700 is designed, in particular, for system applications where minimizing noise on the power-supply
rail is critical to system performance. This scenario is the case for phase-locked loop (PLL)-based clocking
circuits for instance, where minimum phase noise is all important, or in-test and measurement systems where
even small power-supply noise fluctuations can distort instantaneous measurement accuracy. Because the
TPS7A4700 is also designed for higher voltage industrial applications, the noise characteristic is well designed to
minimize any increase as a function of the output voltage.
LDO noise is defined as the internally-generated intrinsic noise created by the semiconductor circuits alone. This
noise is the sum of various types of noise (such as shot noise associated with current-through-pin junctions,
thermal noise caused by thermal agitation of charge carriers, flicker noise or 1/f noise that is a property of
resistors and dominates at lower frequencies as a function of 1/f, burst noise, and avalanche noise).
To calculate the LDO RMS output noise, a spectrum analyzer must first measure the spectral noise across the
bandwidth of choice (typically 10 Hz to 100 kHz in units of µV/√Hz). The RMS noise is then calculated in the
usual manner as the integrated square root of the squared spectral noise over the band, then averaged by the
bandwidth.
THERMAL INFORMATION
Thermal Protection
The TPS7A4700 contains a thermal shutdown protection circuit to turn off the output current when excessive
heat is dissipated in the LDO. Thermal shutdown occurs when the thermal junction temperature (TJ) of the main
pass-FET exceeds +170°C (typical). Thermal shutdown hysteresis assures that the LDO again resets (turns on)
when the temperature falls to +150°C (typical). Because the TPS7A4700 is capable of supporting high input
voltages, a great deal of power can be expected to be dissipated across the device at low output voltages which
may cause a thermal shutdown. The thermal time-constant of the semiconductor die is fairly short, and thus the
output oscillates on and off at a high rate when thermal shutdown is reached until power dissipation is reduced.
For reliable operation, the junction temperature should be limited to a maximum of +125°C. To estimate the
thermal margin in a given layout, increase the ambient temperature until the thermal protection shutdown is
triggered using worst-case load and highest input voltage conditions. For good reliability, thermal shutdown
should occur at least +45°C above the maximum expected ambient temperature condition for the application.
This configuration produces a worst-case junction temperature of +125°C at the highest expected ambient
temperature and worst-case load.
The internal protection circuitry of the TPS7A4700 is designed to protect against thermal overload conditions.
The circuitry is not intended to replace proper heat sinking. Continuously running the TPS7A4700 into thermal
shutdown degrades device reliability.
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Power Dissipation (PD)
Circuit reliability demands that due consideration be given to device power dissipation, location of the circuit on
the printed circuit board (PCB), and proper sizing of the thermal plane. The PCB area around the regulator
should be as free as possible of other heat-generating devices that can cause added thermal stresses.
Power dissipation in the regulator depends on the input to output voltage difference and load conditions. PD can
be calculated using Equation 6:
PD = (VOUT - VIN) ´ IOUT
(6)
It is important to note that power dissipation can be minimized, and thus greater efficiency achieved, by proper
selection of the system voltage rails. Proper selection allows the minimum input voltage necessary for output
regulation to be obtained.
The primary heat conduction path for the QFN (RGW) package is through the thermal pad to the PCB. The
thermal pad should be soldered to a copper pad area under the device. This pad area should then contain an
array of plated vias that conduct heat to any inner spreading plane areas or to a bottom-side copper plane.
The maximum power dissipation determines the maximum allowable junction temperature (TJ) for the device.
Power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance
(θJA) of the combined PCB and device package and the temperature of the ambient air (TA), according to
Equation 7.
TJ = TA + (qJA ´ PD)
(7)
Unfortunately, this thermal resistance (θJA) is highly dependant on the heat-spreading capability built into the
particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the
spreading planes. The θJA recorded in the Thermal Information table is determined by the JEDEC standard,
PCB, and copper-spreading area and is to be used only as a relative measure of package thermal performance.
Note that for a well-designed thermal layout, θJA is actually the sum of the QFN package junction-to-case
(bottom) thermal resistance (θJCbot) plus the thermal resistance contribution by the PCB copper. By knowing
θJCbot, the minimum amount of appropriate heat sinking can be used to estimate θJA with Figure 25. θJCbot can be
found in the Thermal Information table.
120
100
80
60
qJA (RGW)
40
20
0
0
1
2
3
4
5
6
7
8
9
10
Board Copper Area (in2)
NOTE: θJA value at a board size of 9-in2 (that is, 3-in × 3-in) is a JEDEC standard.
Figure 25. θJA vs Board Size
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Estimating Junction Temperature
The JEDEC standard now recommends the use of PSI thermal metrics to estimate the junction temperatures of
the LDO while in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal
resistances, but rather offer practical and relative means of estimating junction temperatures. These PSI metrics
are determined to be significantly independent of copper-spreading area. The key thermal metrics (ΨJT and ΨJB)
are given in the Thermal Information table and are used in accordance with Equation 8.
YJT: TJ = TT + YJT ´ PD
YJB: TJ = TB + YJB ´ PD
where:
PD is the power dissipated as explained in Equation 6,
TT is the temperature at the center-top of the device package, and
TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge.
(8)
BOARD LAYOUT
For best overall performance, all circuit components are recommended to be located on the same side of the
circuit board and as near as practical to the respective LDO pin connections. Ground return connections to the
input and output capacitor, and to the LDO ground pin should also be as close to each other as possible and
connected by a wide, component-side, copper surface. The use of vias and long traces to create LDO circuit
connections is strongly discouraged and negatively affects system performance. This grounding and layout
scheme minimizes inductive parasitics and thereby reduces load-current transients, minimizes noise, and
increases circuit stability.
A ground reference plane is also recommended and should be either embedded in the PCB itself or located on
the bottom side of the PCB opposite the components. This reference plane serves to assure accuracy of the
output voltage, shield noise, and behaves similar to a thermal plane to spread (or sink) heat from the LDO device
when connected to the PowerPAD™. In most applications, this ground plane is necessary to meet thermal
requirements.
Use the TPS7A4700EVM-094 evaluation module (EVM), available for download at www.ti.com, as a reference
for layout and application design.
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REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (June 2012) to Revision A
Page
•
Moved to full production data (changes throughout document) ........................................................................................... 1
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PACKAGE OPTION ADDENDUM
www.ti.com
20-Jul-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TPS7A4700RGWR
TPS7A4700RGWT
ACTIVE
ACTIVE
VQFN
VQFN
RGW
RGW
20
20
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS7A4700RGWR
TPS7A4700RGWT
VQFN
VQFN
RGW
RGW
20
20
3000
250
330.0
180.0
12.4
12.4
5.3
5.3
5.3
5.3
1.5
1.5
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS7A4700RGWR
TPS7A4700RGWT
VQFN
VQFN
RGW
RGW
20
20
3000
250
367.0
210.0
367.0
185.0
35.0
35.0
Pack Materials-Page 2
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