TPS7A4901DRBR [TI]
具有使能功能的 150mA、36V、低噪声、高 PSRR、可调节低压降稳压器 | DRB | 8 | -40 to 125;
| 型号： | TPS7A4901DRBR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有使能功能的 150mA、36V、低噪声、高 PSRR、可调节低压降稳压器 | DRB | 8 | -40 to 125 稳压器 |
| 文件： | 总23页 (文件大小：754K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS7A49xx
www.ti.com
SBVS121A –AUGUST 2010–REVISED SEPTEMBER 2010
+36V, +150mA, Ultralow-Noise, Positive LINEAR REGULATOR
1
FEATURES
DESCRIPTION
23
•
Input Voltage Range: +3V to +36V
The TPS7A49xx series of devices are positive,
high-voltage (+36V), ultralow noise (15.4mVRMS, 72dB
PSRR) linear regulators capable of sourcing a load of
150mA.
•
Noise:
–
–
12.7mVRMS (20Hz to 20kHz)
15.4mVRMS (10Hz to 100kHz)
These
logic-level-compatible
linear
regulators
include
a
pin
CMOS
and
•
Power-Supply Ripple Rejection:
enable
–
–
72dB (120Hz)
capacitor-programmable soft-start function that allows
for customized power-management schemes. Other
features available include built-in current limit and
thermal shutdown protection to safeguard the device
and system during fault conditions.
≥ 52dB (10Hz to 400kHz)
•
•
•
•
•
•
Adjustable Output: +1.194V to +33V
Output Current: 150mA
Dropout Voltage: 260mV at 100mA
Stable with Ceramic Capacitors ≥ 2.2mF
CMOS Logic-Level-Compatible Enable Pin
The TPS7A49xx family is designed using bipolar
technology, and is ideal for high-accuracy,
high-precision instrumentation applications where
clean voltage rails are critical to maximize system
performance. This design makes it an excellent
Built-In, Fixed, Current-Limit and Thermal
Shutdown Protection
choice
to
power
operational
amplifiers,
•
•
Available in High Thermal Performance
MSOP-8 PowerPAD™ Package
analog-to-digital converters (ADCs), digital-to-analog
converters (DACs), and other high-performance
analog circuitry.
Operating Tempature Range: –40°C to +125°C
In addition, the TPS7A49xx family of linear regulators
is suitable for post dc/dc converter regulation. By
filtering out the output voltage ripple inherent to dc/dc
switching conversion, maximum system performance
is provided in sensitive instrumentation, test and
measurement, audio, and RF applications.
APPLICATIONS
•
Supply Rails for Op Amps, DACs, ADCs, and
Other High-Precision Analog Circuitry
•
•
Audio
Post DC/DC Converter Regulation and Ripple
Filtering
For applications where both positive and negative
high-performance rails are required, consider TI’s
TPS7A30xx family of negative high-voltage,
ultralow-noise linear regulators as well.
•
•
•
•
Test and Measurement
RX, TX, and PA Circuitry
Industrial Instrumention
Base Stations and Telecom Infrastrucure
Typical Application
DGN PACKAGE
3mm ´ 5mm MSOP-8 PowerPAD
(TOP VIEW)
IN
OUT
+15V
1
2
3
4
+18V
OUT
FB
8
7
6
5
IN
TPS7A49
DNC
NR/SS
EN
EN
GND
NC
GND
-18V
IN
OUT
-15V
TPS7A30
EN GND
EVM
Post DC/DC Converter Regulation for
High-Performace Analog Circuitry
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
TPS7A49xx
SBVS121A –AUGUST 2010–REVISED SEPTEMBER 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
PRODUCT
VOUT
TPS7A49xx yyy z
XX is nominal output voltage (01 = Adjustable).(2)
YYY is package designator.
Z is package quantity.
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder on www.ti.com.
(2) For fixed -1.2V operation, tie FB to OUT.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range (unless otherwise noted).
VALUE
MIN
–0.3
–0.3
–36
MAX
UNIT
IN pin to GND pin
+36
V
V
V
V
V
OUT pin to GND pin
OUT pin to IN pin
+33
+0.3
FB pin to GND pin
FB pin to IN pin
–0.3
–36
+2
Voltage
+0.3
EN pin to IN pin
–36
0.3
EN pin to GND pin
NR/SS pin to IN pin
NR/SS pin to GND pin
Peak output
–0.3
–36
+36
V
V
V
+0.3
–0.3
+2
Internally limited
+125
Current
Operating virtual junction, TJ
Storage, Tstg
–40
–65
°C
°C
V
Temperature
+150
Human body model (HBM)
Charged device model (CDM)
500
Electrostatic discharge rating
500
V
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to
absolute-maximum rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION
TPS7A49xx
THERMAL METRIC(1)
DGN
8 PINS
55.09
8.47
—
UNITS
qJA
Junction-to-ambient thermal resistance
qJC(top)
qJB
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
°C/W
yJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
0.36
14.6
—
yJB
qJC(bottom)
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
DISSIPATION RATINGS
DERATING FACTOR
ABOVE TA = +25°C
T
A ≤ +25°C POWER
TA = +70°C POWER
RATING
TA = +85°C POWER
RATING
BOARD
PACKAGE
RqJA
RqJC
RATING
High-K(1)
DGN
55.9°C/W
8.47°C/W
16.6mW/°C
1.83W
1.08W
0.833W
(1) The JEDEC High-K (2s2p) board design used to derive this data was a 3-inch x 3-inch multilayer board with 2-ounce internal power and
ground planes and 2-ounce copper traces on top and bottom of the board.
2
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TPS7A49xx
www.ti.com
SBVS121A –AUGUST 2010–REVISED SEPTEMBER 2010
ELECTRICAL CHARACTERISTICS
At TJ = –40°C to +125°C, VIN = VOUT(NOM) + 1.0V or VIN = 3.0V (whichever is greater), VEN = VIN, IOUT = 1mA, CIN = 2.2mF, COUT = 2.2mF,
CNR/SS = 0nF, and the FB pin tied to OUT, unless otherwise noted.
TPS7A49xx
PARAMETER
Input voltage range
Internal reference
TEST CONDITIONS
MIN
3.0
TYP
MAX
35
UNIT
VIN
V
V
V
VREF
TJ = +25°C, VNR/SS = VREF
VIN ≥ VOUT(NOM) + 1.0V
1.176
VREF
–1.5
1.194
1.212
33.0
Output voltage range(1)
Nominal accuracy
TJ = +25°C, VIN = VOUT(NOM) + 0.5V
+1.5 %VOUT
VOUT
VOUT(NOM) + 1.0V ≤ VIN ≤ 35V
1mA ≤ IOUT ≤ 150mA
Overall accuracy
Line regulation
Load regulation
–2.5
+2.5 %VOUT
DVOUT(DVIN
)
TJ = +25°C, VOUT(NOM) + 1.0V ≤ VIN ≤ 35V
TJ = +25°C, 1mA ≤ IOUT ≤ 150mA
0.11
0.04
%VOUT
VOUT(NOM)
DVOUT(DIOUT
)
%VOUT
mV
VOUT(NOM)
VIN = 95% VOUT(NOM), IOUT = 100mA
VIN = 95% VOUT(NOM), IOUT = 150mA
VOUT = 90% VOUT(NOM)
IOUT = 0mA
260
333
309
61
VDO
ILIM
Dropout voltage
Current limit
600
500
100
mV
mA
mA
mA
mA
nA
mA
mA
V
220
IGND
Ground current
IOUT = 100mA
800
0.8
3
ISHDN
I FB
Shutdown supply current
Feedback current(2)
VEN = +0.4V
3.0
100
1.0
VEN = VIN = VOUT(NOM) + 1.0V
VEN = VIN = +35V
0.02
0.2
IEN
Enable current
1.0
VEN_HI
VEN_LO
Enable high-level voltage
Enable low- level voltage
+2.1
0
VIN
+0.4
V
VIN = +3V, VOUT(NOM) = VREF, COUT = 10mF,
CNR/SS = 10nF, BW = 10Hz to 100kHz
15.4
21.15
72
mVRMS
mVRMS
dB
VNOISE
Output noise voltage
VIN = +6.2V, VOUT(NOM) = +5V, COUT = 10mF,
CNR/SS = CBYP(3) = 10nF, BW = 10Hz to
100kHz
VIN = +6.2V, VOUT(NOM) = +5V, COUT = 10mF,
PSRR
TSD
TJ
Power-supply rejection ratio
CNR/SS = CBYP(3) = 10nF, f = 120Hz
Shutdown, temperature increasing
Reset, temperature decreasing
+170
+150
°C
°C
Thermal shutdown temperature
Operating junction temperature
range
–40
+125
°C
(1) To ensure stability at no load conditions, a current from the feedback resistive network equal to or greater than 5mA is required.
(2) IFB > 0 flows out of the device.
(3) CBYP refers to a bypass capacitor connected to the FB and OUT pins.
Copyright © 2010, Texas Instruments Incorporated
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TPS7A49xx
SBVS121A –AUGUST 2010–REVISED SEPTEMBER 2010
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DEVICE INFORMATION
FUNCTIONAL BLOCK DIAGRAM
IN
OUT
Pass
Device
UVLO
Current
Limit
Thermal
Shutdown
FB
Error
Amp
EN
Enable
VREF
NR/SS
GND
TYPICAL APPLICATION CIRCUIT
VIN
VOUT
OUT
IN
CBYP
CIN
VOUT
R1
³ 5mA, and
Where:
10nF
10mF
R1 + R2
EN TPS7A4901 FB
COUT
VOUT
VREF
10mF
R2
R1 = R2
- 1
NR/SS
CNR/SS
GND
10nF
Maximize PSRR Performance and Minimize RMS Noise
4
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TPS7A49xx
www.ti.com
SBVS121A –AUGUST 2010–REVISED SEPTEMBER 2010
PIN CONFIGURATION
DGN PACKAGE
MSOP-8
(TOP VIEW)
1
2
3
4
OUT
FB
8
7
6
5
IN
DNC
NR/SS
EN
NC
GND
PIN DESCRIPTIONS
TPS7A49xx
NAME
OUT
FB
NO.
1
DESCRIPTION
Regulator output. A capacitor ≥ 2.2mF must be tied from this pin to ground to assure stability.
This pin is the input to the control-loop error amplifier. It is used to set the output voltage of the device.
Not internally connected. This pin may either be left open or tied to GND.
Ground
2
NC
3
GND
4
This pin turns the regulator on or off. If VEN ≥ VEN_HI, the regulator is enabled.
If VEN_LO ≥ VEN, the regulator is disabled. The EN pin can be connected to IN, if not used. VEN ≤ VIN
EN
5
6
.
Noise reduction pin. Connecting an external capacitor to this pin bypasses noise generated by the internal bandgap.
This capacitor allows RMS noise to be reduced to very low levels and also controls the soft-start function.
NR/SS
DNC
IN
7
8
DO NOT CONNECT. Do not route this pin to any electrical net, not even GND or IN.
Input supply
PowerPAD
Must either be left open or tied to ground. Solder to printed circuit board (PCB) plane to enhance thermal performance.
Copyright © 2010, Texas Instruments Incorporated
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TPS7A49xx
SBVS121A –AUGUST 2010–REVISED SEPTEMBER 2010
www.ti.com
TYPICAL CHARACTERISTICS
At TJ = –40°C to +125°C, VIN = VOUT(NOM) + 1.0V or VIN = 3.0V (whichever is greater), VEN = VIN, IOUT = 1mA, CIN = 2.2mF, COUT
= 2.2mF, CNR/SS = 0nF, and the FB pin tied to OUT, unless otherwise noted.
FEEDBACK VOLTAGE vs INPUT VOLTAGE
FEEDBACK CURRENT vs TEMPERATURE
1.205
1.2
100
90
80
70
60
50
40
30
20
10
0
+125°C
+105°C
+85°C
+25°C
-40°C
1.195
1.19
1.185
0
5
10
15
20
25
30
35
40
-40 -25 -10
5
20 35 50 65 80 95 110 125
VIN (V)
Temperature (°C)
Figure 1.
GROUND CURRENT vs INPUT VOLTAGE
Figure 2.
GROUND CURRENT vs INPUT VOLTAGE
2500
2000
1500
1000
500
1200
1000
800
600
400
200
0
0mA
TJ = +25°C
10mA
50mA
100mA
150mA
+125°C
+105°C
+85°C
+25°C
-40°C
IOUT = 100mA
10
0
0
5
10
15
20
25
30
35
40
0
5
15
20
25
30
35
40
VIN (V)
VIN (V)
Figure 3.
GROUND CURRENT vs OUTPUT CURRENT
Figure 4.
ENABLE CURRENT vs ENABLE VOLTAGE
2500
2000
1500
1000
500
100
90
80
70
60
50
40
30
20
10
0
+125°C
+125°C
+105°C
+85°C
+25°C
-40°C
+105°C
+85°C
+25°C
-40°C
0
0
5
10
15
20
25
30
35
40
0
15
30
45
60
75
90 105 120 135 150
IOUT (mA)
VEN (V)
Figure 5.
Figure 6.
6
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TPS7A49xx
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SBVS121A –AUGUST 2010–REVISED SEPTEMBER 2010
TYPICAL CHARACTERISTICS (continued)
At TJ = –40°C to +125°C, VIN = VOUT(NOM) + 1.0V or VIN = 3.0V (whichever is greater), VEN = VIN, IOUT = 1mA, CIN = 2.2mF, COUT
= 2.2mF, CNR/SS = 0nF, and the FB pin tied to OUT, unless otherwise noted.
QUIESCENT CURRENT vs INPUT VOLTAGE
SHUTDOWN CURRENT vs INPUT VOLTAGE
100
90
80
70
60
50
40
30
20
10
0
3.5
3
+125°C
+105°C
+85°C
+25°C
-40°C
2.5
2
1.5
1
+125°C
+105°C
+85°C
+25°C
-40°C
0.5
0
IOUT = 0mA
VEN = 0.4V
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
VIN (V)
VIN (V)
Figure 7.
Figure 8.
DROPOUT VOLTAGE vs OUTPUT CURRENT
DROPOUT VOLTAGE vs TEMPERATURE
450
400
350
300
250
200
150
100
50
500
450
400
350
300
250
200
150
100
50
10mA
50mA
100mA
150mA
+125°C
+105°C
+85°C
+25°C
-40°C
0
0
0
15
30
45
60
75
90 105 120 135 150
-40 -25 -10
5
20 35 50 65 80 95 110 125
IOUT (mA)
Temperature (°C)
Figure 9.
CURRENT LIMIT vs INPUT VOLTAGE
Figure 10.
CURRENT LIMIT vs TEMPERATURE
450
400
350
300
250
200
150
100
50
500
450
400
350
300
250
200
VOUT = 90% VOUT(NOM)
VOUT = 90% VOUT(NOM)
+125°C
+105°C
+85°C
+25°C
-40°C
0
0
5
10
15
20
25
30
35
40
-25 -10
5
20 35 50 65 80 95 110 125
-40
VIN (V)
Temperature (°C)
Figure 11.
Figure 12.
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SBVS121A –AUGUST 2010–REVISED SEPTEMBER 2010
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TYPICAL CHARACTERISTICS (continued)
At TJ = –40°C to +125°C, VIN = VOUT(NOM) + 1.0V or VIN = 3.0V (whichever is greater), VEN = VIN, IOUT = 1mA, CIN = 2.2mF, COUT
= 2.2mF, CNR/SS = 0nF, and the FB pin tied to OUT, unless otherwise noted.
ENABLE THRESHOLD VOLTAGE vs TEMPERATURE
POWER-SUPPLY REJECTION RATIO vs COUT
2.5
90
80
70
60
50
40
30
COUT = 10mF
2
1.5
1
ON
OFF
COUT = 2.2mF
VOUT = 5V
VIN = 6.2V
20 IOUT = 150mA
0.5
0
CNR/SS = 10nF
10
CBYP = 10nF
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
10
100
1k
10k
100k
1M
10M
Temperature (°C)
Frequency (Hz)
Figure 13.
Figure 14.
LINE REGULATION
POWER-SUPPLY REJECTION RATIO vs CNR/SS
1
90
80
70
60
50
40
30
+125°C
+105°C
+85°C
+25°C
-40°C
0.8
0.6
CNR/SS = 10nF
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
VOUT = 1.2V
VIN = 3.2V
CNR/SS = 0nF
20 IOUT = 150mA
COUT = 10mF
10
CBYP = 0nF
0
0
5
10
15
20
25
30
35
40
10
100
1k
10k
100k
1M
10M
VIN (V)
Frequency (Hz)
Figure 15.
LOAD REGULATION
Figure 16.
POWER-SUPPLY REJECTION RATIO vs CBYP
1
0.8
90
80
70
60
50
40
30
+125°C
+105°C
+85°C
+25°C
-40°C
CBYP = 10nF
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
VOUT = 5V
VIN = 6.2V
CBYP = 0nF
20 IOUT = 150mA
COUT = 10mF
10
CNR/SS = 10nF
0
0
15
30
45
60
75
90 105 120 135 150
10
100
1k
10k
100k
1M
10M
IOUT (mA)
Frequency (Hz)
Figure 17.
Figure 18.
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TYPICAL CHARACTERISTICS (continued)
At TJ = –40°C to +125°C, VIN = VOUT(NOM) + 1.0V or VIN = 3.0V (whichever is greater), VEN = VIN, IOUT = 1mA, CIN = 2.2mF, COUT
= 2.2mF, CNR/SS = 0nF, and the FB pin tied to OUT, unless otherwise noted.
OUTPUT SPECTRAL NOISE DENSITY vs OUTPUT CURRENT
10
VOUT = 1.2V
VIN = 3V
RMS NOISE
IOUT
1mA
10Hz to 100kHz 100Hz to 100kHz
CIN = 2.2mF
CNR/SS = 10nF
COUT = 10mF
15.44
17.27
14.14
16.46
1
150mA
IOUT = 150mA
0.1
IOUT = 1mA
10k
0.01
10
100
1k
100k
Frequency (Hz)
Figure 19.
OUTPUT SPECTRAL NOISE DENSITY vs CNR/SS
10
VOUT = 1.2V
RMS NOISE
10Hz to 100kHz 100Hz to 100kHz
VIN = 3V
CNR/SS
IOUT = 150mA
CNR/SS = 0nF
69.04
16.58
67.87
15.86
0nF
CIN = 2.2mF
1
COUT = 10mF
10nF
0.1
0.01
CNR/SS = 10nF
10
100
1k
10k
100k
Frequency (Hz)
Figure 20.
OUTPUT SPECTRAL NOISE DENSITY vs VOUT(NOM)
10
IOUT = 1mA
RMS NOISE
10Hz to 100kHz 100Hz to 100kHz
CIN = 2.2mF
VOUT(NOM)
VOUT(NOM) = 5V
CNR = 10nF
21.15
15.44
14.74
14.14
5V
CBYP = 10nF
1
COUT = 10mF
1.2V
0.1
0.01
VOUT(NOM) = 1.2V
10
100
1k
10k
100k
Frequency (Hz)
Figure 21.
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TYPICAL CHARACTERISTICS (continued)
At TJ = –40°C to +125°C, VIN = VOUT(NOM) + 1.0V or VIN = 3.0V (whichever is greater), VEN = VIN, IOUT = 1mA, CIN = 2.2mF, COUT
= 2.2mF, CNR/SS = 0nF, and the FB pin tied to OUT, unless otherwise noted.
CAPACITOR-PROGRAMMABLE SOFT-START
CAPACITOR-PROGRAMMABLE SOFT-START
VEN
VEN
VOUT = 1.2V
VOUT = 1.2V
VIN = 3V
VIN = 3V
IOUT = 100mA
COUT = 10mF
CNR/SS = 10nF
VOUT
VOUT
IOUT = 100mA
COUT = 10mF
CNR/SS = 0nF
Time (50ms/div)
Time (5ms/div)
Figure 22.
Figure 23.
LINE TRANSIENT RESPONSE
LINE TRANSIENT RESPONSE
VOUT = 15V
VIN = 33V to 18V
IOUT = 100mA
COUT = 10mF
VIN
CNR/SS = 10nF
VOUT
VOUT
VOUT = 15V
VIN
VIN = 18V to 33V
IOUT = 100mA
COUT = 10mF
CNR/SS = 10nF
Time (10ms/div)
Time (10ms/div)
Figure 24.
Figure 25.
LOAD TRANSIENT RESPONSE
LOAD TRANSIENT RESPONSE
VOUT = 15V
VOUT = 15V
VIN = 18V
IOUT = 1mA to 120mA
COUT = 10mF
VIN = 18V
IOUT = 120mA to 1mA
COUT = 10mF
CNR/SS = 10nF
CNR/SS = 10nF
VOUT
VOUT
IOUT
IOUT
Time (100ms/div)
Time (100ms/div)
Figure 26.
Figure 27.
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THEORY OF OPERATION
GENERAL DESCRIPTION
CAPACITOR RECOMMENDATIONS
The TPS7A49xx belongs to
a family of new
generation linear regulators that use an innovative
bipolar process to achieve ultralow-noise and very
high PSRR levels at a wide input voltage range.
Low ESR capacitors should be used for the input,
output, noise reduction, and bypass capacitors.
Ceramic capacitors with X7R and X5R dielectrics are
preferred. These dielectrics offer more stable
characteristics. Ceramic X7R capacitors offer
improved over-temperature performance, while
ceramic X5R capacitors are the most cost-effective
and are available in higher values.
These features, combined with
a high thermal
performance MSOP-8 with PowerPAD package make
this device ideal for high-performance analog
applications.
ADJUSTABLE OPERATION
Note that high ESR capacitors may degrade PSRR.
To ensure stability, maximum ESR must be less than
200mΩ.
The TPS7A4901 has an output voltage range of
+1.194 to +33V. The nominal output voltage of the
device is set by two external resistors, as shown in
Figure 28.
INPUT AND OUTPUT CAPACITOR
REQUIREMENTS
VOUT
VIN
The TPS7A49xx family of positive, high-voltage linear
regulators achieve stability with a minimum input and
output capacitance of 2.2mF; however, it is highly
recommended to use a 10mF capacitor to maximize
ac performance.
OUT
IN
CBYP
10nF
CIN
10mF
R1
R2
EN TPS7A4901 FB
COUT
10mF
NR/SS
GND
CNR/SS
10nF
NOISE REDUCTION AND BYPASS
CAPACITOR REQUIREMENTS
Figure 28. Adjustable Operation for Maximum AC
Performance
Although noise reduction and bypass capacitors
(CNR/SS and CBYP, respectively) are not needed to
achieve stability, it is highly recommended to use
0.01mF capacitors to minimize noise and maximize ac
performance.
R1 and R2 can be calculated for any output voltage
range using the formula shown in Equation 1. To
ensure stability under no load conditions, this
resistive network must provide a current equal to or
greater than 5mA.
MAXIMUM AC PERFORMANCE
In order to maximize noise and PSRR performance, it
is recommended to include 10mF or higher input and
output capacitors, and 0.01mF noise reduction and
bypass capacitors, as shown in Figure 28. The
solution shown delivers minimum noise levels of
15.4mVRMS and power-supply rejection levels above
52dB from 10Hz to 400kHz; see Figure 18 and
Figure 19.
VOUT
VREF
VOUT
R1 = R2
- 1 , where
³ 5mA
R1 + R2
(1)
If greater voltage accuracy is required, take into
account the output voltage offset contributions
because of the feedback pin current and use 0.1%
tolerance resistors.
ENABLE PIN OPERATION
The TPS7A49xx provides an enable feature (EN) that
turns on the regulator when VEN > 2.1V.
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OUTPUT NOISE
Additionally, ac performance can be maximized by
adding a 0.01mF bypass capacitor (CBYP) from the FB
pin to the OUT pin. This capacitor greatly improves
power-supply rejection at lower frequencies, for the
band from 10Hz to 200kHz; see Figure 18.
The TPS7A49xx provides low output noise when a
noise reduction capacitor (CNR/SS) is used.
The noise reduction capacitor serves as a filter for the
internal reference. By using a 0.01mF noise reduction
capacitor, the output noise is reduced by almost 75%
(from 69mVRMS to 17mVRMS); see Figure 20.
The very high power-supply rejection of the
TPS7A49xx makes it a good choice for powering
high-performance
analog
circuitry,
such
as
operational amplifiers, ADCs, DACS, and audio
amplifiers.
TPS7A49xx low output voltage noise makes it an
ideal solution for powering noise-sensitive circuitry.
TRANSIENT RESPONSE
POWER-SUPPLY REJECTION
As with any regulator, increasing the size of the
output capacitor reduces over/undershoot magnitude
but increases duration of the transient response.
The 0.01mF noise reduction capacitor greatly
improves
TPS7A49xx
power-supply
rejection,
achieving up to 15dB of additional power-supply
rejection for frequencies between 110Hz and
200KHz.
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SBVS121A –AUGUST 2010–REVISED SEPTEMBER 2010
APPLICATION INFORMATION
POWER FOR PRECISION ANALOG
The TPS7A49xx offers a wide-bandwidth, very-high
power-supply rejection ratio. This specification makes
it ideal for post dc/dc converter filtering, as shown in
Figure 29. It is highly recommended to use the
maximum performance schematic shown in
Figure 28. Also, verify that the fundamental frequency
(and its first harmonic, if possible) is within the
bandwidth of the regulator PSRR, shown in
Figure 18.
One of the primary TPS7A49xx applications is to
provide
ultralow-noise
voltage
rails
to
high-performance analog circuitry in order to
maximize system accuracy and precision.
The TPS7A49xx family of positive high-voltage linear
regulators in conjunction with its negative counterpart
(the TPS7A30xx family of negative high-voltage linear
regulators), provide ultralow-noise, positive and
negative voltage rails for high-performance analog
circuitry, such as operational amplifiers, ADCs, DACs,
and audio amplifiers.
Because of the ultralow noise levels at high voltages,
analog circuitry with high-voltage input supplies can
be
used.
This
characteristic
allows
for
high-performance analog solutions to optimize the
voltage range, maximizing system accuracy.
IN
OUT
+18V
+15V
TPS7A49
POST DC/DC CONVERTER FILTERING
EN
GND
Most of the time, the voltage rails available in a
system do not match the voltage specifications
demanded by one or more of its circuits; these rails
must be stepped up or down, depending on specific
voltage requirements.
IN
OUT
-18V
-15V
TPS7A30
EN GND
DC/DC converters are the preferred solution to step
up or down a voltage rail when current consumption
is not negligible. They offer high efficiency with
minimum heat generation, but they have one primary
EVM
Figure 29. Post DC/DC Converter Regulation to
High-Performance Analog Circuitry
disadvantage: they introduce
a
high-frequency
component, and the associated harmonics, on top of
the dc output signal.
AUDIO APPLICATIONS
This high-frequency component, if not filtered
properly, degrades analog circuitry performance,
reducing overall system accuracy and precision.
Audio applications are extremely sensitive to any
distortion and noise in the audio band from 20Hz to
20kHz. This stringent requirement demands clean
voltage rails to power critical high-performance audio
systems.
The very-high power-supply rejection ratio (> 55dB)
and low noise at the audio band of the TPS7A49xx
maximize performance for audio applications; see
Figure 18.
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TPS7A49xx
SBVS121A –AUGUST 2010–REVISED SEPTEMBER 2010
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LAYOUT
PACKAGE MOUNTING
at least +35°C above the maximum expected ambient
condition of your particular application. This
Solder pad footprint recommendations for the
TPS7A49xx are available at the end of this product
datasheet and at www.ti.com.
configuration produces
a
worst-case junction
temperature of +125°C at the highest expected
ambient temperature and worst-case load.
The internal protection circuitry of the TPS7A49xx
has been designed to protect against overload
conditions. It was not intended to replace proper
heatsinking. Continuously running the TPS7A49xx
into thermal shutdown degrades device reliability.
BOARD LAYOUT RECOMMENDATIONS TO
IMPROVE PSRR AND NOISE PERFORMANCE
To improve ac performance such as PSRR, output
noise, and transient response, it is recommended that
the board be designed with separate ground planes
for IN and OUT, with each ground plane connected
only at the GND pin of the device. In addition, the
ground connection for the output capacitor should
connect directly to the GND pin of the device.
POWER DISSIPATION
The ability to remove heat from the die is different for
each
package
type,
presenting
different
considerations in the PCB layout. The PCB area
around the device that is free of other components
moves the heat from the device to the ambient air.
Performance data or JEDEC low- and high-K boards
are given in the Dissipation Ratings Table. Using
heavier copper increases the effectiveness in
removing heat from the device. The addition of plated
through-holes to heat dissipating layers also improves
the heatsink effectiveness.
Equivalent series inductance (ESL) and equivalent
series resistance (ESR) must be minimized to
maximize performance and ensure stability. Every
capacitor (CIN, COUT, CNR/SS, CBYP) must be placed as
close as possible to the device and on the same side
of the printed circuit board (PCB) as the regulator
itself.
Do not place any of the capacitors on the opposite
side of the PCB from where the regulator is installed.
The use of vias and long traces is strongly
discouraged because they may impact system
performance negatively and even cause instability.
Power dissipation depends on input voltage and load
conditions. Power dissipation (PD) is equal to the
product of the output current times the voltage drop
across the output pass element, as shown in
Equation 2:
If possible, and to ensure the maximum performance
denoted in this product datasheet, use the same
layout pattern used for TPS7A49 evaluation board,
available at www.ti.com.
PD = (VIN - VOUT) IOUT
(2)
SUGGESTED LAYOUT AND SCHEMATIC
THERMAL PROTECTION
Layout is a critical part of good power-supply design.
There are several signal paths that conduct
fast-changing currents or voltages that can interact
with stray inductance or parasitic capacitance to
generate noise or degrade the power-supply
performance. To help eliminate these problems, the
IN pin should be bypassed to ground with a low ESR
Thermal protection disables the output when the
junction temperature rises to approximately +170°C,
allowing the device to cool. When the junction
temperature cools to approximately +150°C, the
output circuitry is enabled. Depending on power
dissipation, thermal resistance, and ambient
temperature, the thermal protection circuit may cycle
on and off. This cycling limits the dissipation of the
regulator, protecting it from damage as a result of
overheating.
ceramic bypass capacitor with
dielectric.
a X5R or X7R
The GND pin should be tied directly to the PowerPAD
under the IC. The PowerPAD should be connected to
any internal PCB ground planes using multiple vias
directly under the IC.
Any tendency to activate the thermal protection circuit
indicates excessive power dissipation or an
inadequate heatsink. For reliable operation, junction
temperature should be limited to a maximum of
+125°C. To estimate the margin of safety in a
complete design (including heatsink), increase the
ambient temperature until the thermal protection is
triggered; use worst-case loads and signal conditions.
For good reliability, thermal protection should trigger
It may be possible to obtain acceptable performance
with alternate PCB layouts; however, the layout
shown in Figure 30 and the schematic shown in
Figure 31 have been shown to produce good results
and are meant as a guideline.
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TPS7A49xx
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SBVS121A –AUGUST 2010–REVISED SEPTEMBER 2010
Figure 30. PCB Layout Example
U1 TPS7A49XXDGN
J1
4
3
2
1
5
6
7
8
EN
GND
NC
NR/SS
DNC
IN
C4
FB
OUT
Vin J1
C1
R1
J4
9
J7 GND
C2
C3
R3
Figure 31. Schematic for PCB Layout Example
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TPS7A49xx
SBVS121A –AUGUST 2010–REVISED SEPTEMBER 2010
www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (August, 2010) to Revision A
Page
•
•
•
Revised Features list ............................................................................................................................................................ 1
Changed Description text (paragraph 1) to remove description of maximum load .............................................................. 1
Revised shutdown supply current, feedback current, and enable current specifications; rounded typical performance
values .................................................................................................................................................................................... 3
•
•
•
Revised Functional Block Diagram for clarification .............................................................................................................. 4
Changed description of NC pin (pin 3) in Pin Descriptions table ......................................................................................... 5
Updated Figure 1 to show correct device performance ........................................................................................................ 6
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PACKAGE OPTION ADDENDUM
www.ti.com
25-Aug-2010
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TPS7A4901DGNR
TPS7A4901DGNT
ACTIVE
ACTIVE
MSOP-
PowerPAD
DGN
DGN
8
8
2500
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Request Free Samples
MSOP-
PowerPAD
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Request Free Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Aug-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
2500
250
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS7A4901DGNR
TPS7A4901DGNT
MSOP-
Power
PAD
DGN
DGN
8
8
330.0
180.0
12.4
12.4
5.3
5.3
3.4
3.4
1.4
1.4
8.0
8.0
12.0
12.0
Q1
Q1
MSOP-
Power
PAD
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Aug-2010
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS7A4901DGNR
TPS7A4901DGNT
MSOP-PowerPAD
MSOP-PowerPAD
DGN
DGN
8
8
2500
250
346.0
190.5
346.0
212.7
29.0
31.8
Pack Materials-Page 2
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