TPS7A53-Q1 [TI]

汽车类 3A、低输入电压 (1.1V)、低噪声、高精度、超低压降 (LDO) 稳压器;


型号：	TPS7A53-Q1
厂家：	TEXAS INSTRUMENTS
描述：	汽车类 3A、低输入电压 (1.1V)、低噪声、高精度、超低压降 (LDO) 稳压器稳压器
文件：	总42页 (文件大小：2993K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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TPS7A53-Q1

ZHCSHB7B –SEPTEMBER 2017–REVISED JULY 2018

TPS7A53-Q1 3A 高精度汽车级低噪声 LDO 稳压器

1 特性

3 说明

•

符合汽车类应用的要求

符合面向汽车应用的 AEC-Q100 标准

TPS7A53-Q1 器件是一款低噪声 (4.4µV_RMS)、低压降

线性稳压器 (LDO)，可提供 3A 电流，同时最大压降仅

为 180mV。该器件的输出电压可通过外部电阻分压器

进行调节，范围为 0.8V 至 5.15V。

–

温度等级 1：–40°C ≤ T_A≤ +125°C

HBM ESD 分类等级 2

CDM ESD 分类等级 C4A

TPS7A53-Q1 集低噪声 (4.4µV_RMS)、高 PSRR 和高输

出电流能力等特性于一体，因此非常适合为雷达功率和

信息娱乐等应用中的噪声敏感型组件供电。此器件的

优秀性能可抑制电源产生的相位噪声和时钟抖动，因此

非常适合为射频放大器、雷达传感器和芯片组供电。射

频放大器尤其受益于该器件的高性能和 5.0V 输出能

力。

•

扩展结温 (T_J) 范围：–40°C 至 +150°C

输入电压范围：

–

无偏置：1.4V 至 6.5V

有偏置：1.1V 至 6.5V

•

可调输出电压范围：0.8V 至 5.15V

低压降：3A 电流时为 180mV（最大值）（带偏

置）

对于需要以低输入和低输出 (LILO) 电压运行的数字负

载，例如专用集成电路 (ASIC)、现场可编程门阵列

(FPGA) 和数字信号处理器 (DSP)，TPS7A53-Q1 所具

备的极高的精度（在负载和温度范围内可达 1%）、遥

感功能、出色的瞬态性能和软启动能力可确保实现出色

的系统性能。

•

输出电压噪声：4.4µV_RMS

线路、负载和温度范围内的偏置精度最大值为 1%

电源纹波抑制：

–

500kHz 时为 40dB

•

可调软启动浪涌控制

开漏电源正常 (PG) 输出

封装：

TPS7A53-Q1 器件的多功能性使其非常适合许多严苛

的应用。

–

3.5mm × 3.5mm 20 引脚 VQFN

具有可湿性侧面和高 CTE (12ppm/ºC) 塑封料的

4mm × 4mm 20 引脚 VQFNP

器件信息⁽¹⁾

器件型号

封装

封装尺寸（标称值）

超薄四方扁平无引线

封装 (VQFN) (20)

2 应用

3.50mm x 3.50mm

TPS7A53-Q1

•

远程信息处理控制单元

VQFNP (20)

（具有可湿性侧面）

4.00mm x 4.00mm

信息娱乐系统和仪表组

高速接口（PLL 和 VCO）

(1) 如需了解所有可用封装，请参阅产品说明书末尾的封装选项附

录。

为射频组件供电

输出电压噪声与

频率和输出电压间的关系

Bias Supply

V_OUT= 5.0 V, 11.7 mV_RMS

BIAS

Input Supply

EN Signal

V_OUT= 3.3 V, 8.3 mV_RMS

V_OUT= 1.5 V, 5.4 mV_RMS

V_OUT= 0.8 V, 4.5 mV_RMS

0.5

OUT

TPS7A53-Q1

0.2

0.1

0.05

V_CC

0.02

0.01

Radar

Sensor System

0.005

0.002

0.001

1x10¹

1x10²

1x10³

1x10⁴

1x10⁵

1x10⁶5x10⁶

Frequency (Hz)

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SBVS298

TPS7A53-Q1

ZHCSHB7B –SEPTEMBER 2017–REVISED JULY 2018

www.ti.com.cn

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 5

6.6 Typical Characteristics.............................................. 7

Detailed Description ............................................ 14

7.1 Overview ................................................................. 14

7.2 Functional Block Diagram ....................................... 14

7.3 Feature Description................................................. 15

7.4 Device Functional Modes........................................ 19

Application and Implementation ........................ 20

8.1 Application Information............................................ 20

8.2 Typical Application .................................................. 28

Power Supply Recommendations...................... 29

10 Layout................................................................... 29

10.1 Layout Guidelines ................................................. 29

10.2 Layout Example .................................................... 30

11 器件和文档支持 ..................................................... 31

11.1 器件支持................................................................ 31

11.2 文档支持................................................................ 31

11.3 接收文档更新通知 ................................................. 31

11.4 社区资源................................................................ 31

11.5 商标....................................................................... 31

11.6 静电放电警告......................................................... 31

11.7 术语表 ................................................................... 31

12 机械、封装和可订购信息....................................... 32

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision A (February 2018) to Revision B

Page

•

已添加添加了新的 RTK 封装（具有可湿性侧面的 VQFNP）................................................................................................ 1

Changes from Original (September 2017) to Revision A

Page

•

将“产品预览”更改成了“生产数据”（有效）.............................................................................................................................. 1

TPS7A53-Q1

www.ti.com.cn

ZHCSHB7B –SEPTEMBER 2017–REVISED JULY 2018

5 Pin Configuration and Functions

RGR Package

3.5-mm × 3.5-mm, 20-Pin VQFN

Top View

RTK Package

4-mm × 4-mm, 20-Pin VQFNP

Top View

OUT

Thermal

Pad

Thermal pad

NR/SS

BIAS

NR/SS

BIAS

DNC

Not to scale

Pin Functions

NAME

NO.

I/O

DESCRIPTION

BIAS supply voltage. This pin enables the use of low-input voltage, low-output (LILO) voltage conditions

(that is, V_IN= 1.2 V, V_OUT= 1 V) to reduce power dissipation across the die. The use of a BIAS voltage

improves dc and ac performance for V_IN≤ 2.2 V. A 10-µF capacitor or larger must be connected between

this pin and ground. If not used, this pin must be left floating or tied to ground.

BIAS

DNC

Do not connect. Leave this pin floating or connect this pin to ground.

Enable pin. Driving this pin to logic high enables the device; driving this pin to logic low disables the

device. If enable functionality is not required, this pin must be connected to IN or BIAS.

Feedback pin connected to the error amplifier. Although not required, a 10-nF feed-forward capacitor from

FB to OUT (as close to the device as possible) is recommended to maximize ac performance. The use of

a feed-forward capacitor can disrupt PG (power good) functionality.

Ground pin. These pins must be connected to ground, the thermal pad, and each other with a low-

impedance connection.

GND

8, 18

15-17

—

Input supply voltage pin. A 10-µF or larger ceramic capacitor (5 µF or greater of capacitance) from IN to

ground is recommended to reduce the impedance of the input supply. Place the input capacitor as close

to the input as possible.

2, 6, 7, 9,

10, 11

No internal connection

Noise-reduction and soft-start pin. Connecting an external capacitor between this pin and ground reduces

reference voltage noise and also enables the soft-start function. Although not required, a 10-nF or larger

capacitor is recommended to be connected from NR/SS to GND (as close to the pin as possible) to

maximize ac performance.

NR/SS

OUT

—

Regulated output pin. A 47-µF or larger ceramic capacitor (25 µF or greater of capacitance) from OUT to

ground is required for stability and must be placed as close to the output as possible. Minimize the

impedance from the OUT pin to the load.

1, 19, 20

Active-high, power-good pin. An open-drain output indicates when the output voltage reaches V_IT(PG)of

the target. The use of a feed-forward capacitor may disrupt PG (power good) functionality.

Thermal pad

—

Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND.

TPS7A53-Q1

ZHCSHB7B –SEPTEMBER 2017–REVISED JULY 2018

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

over junction temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

7.0

V_IN+ 0.3⁽²⁾

UNIT

IN, BIAS, PG, EN

Voltage

Current

OUT

NR/SS, FB

3.6

OUT

Internally limited

PG (sink current into device)

°C

Operating junction temperature, T_J

Storage temperature, T_stg

–55

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The absolute maximum rating is V_IN+ 0.3 V or 7.0 V, whichever is smaller.

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per AEC Q100-002(⁽¹⁾

Charged-device model (CDM), per AEC Q100-011

V_(ESD)

Electrostatic discharge

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over junction temperature range (unless otherwise noted)

MIN

1.1

3.0

NOM

MAX

6.5

UNIT

V_IN

Input supply voltage range⁽¹⁾

Bias supply voltage range⁽¹⁾

Enable voltage range

Output current

V_BIAS

V_EN

6.5

I_OUT

C_IN

Input capacitor

Output capacitor⁽²⁾

µF

kΩ

C_OUT

C_BIAS

R_PG

47 || 10 || 10

(3)

Bias capacitor

Power-good pullup resistance

NR/SS capacitor

100

C_NR/SS

C_FF

Feed-forward capacitor

Top resistor value in feedback network for

adjustable operation⁽⁴⁾

R₁

12.1

160

kΩ

Bottom resistor value in feedback network for

adjustable operation⁽⁵⁾

R₂

T_J

kΩ

Operating junction temperature

–40

150

°C

(1) BIAS supply is required when the V_INsupply is below 1.4 V. Conversely, no BIAS supply is required when the V_INsupply is higher than

or equal to 1.4 V. A BIAS supply helps improve dc and ac performance for V_IN≤ 2.2 V.

(2) The recommended output capacitors are selected to optimize PSRR for the frequency range of 400 kHz to 700 kHz. This frequency

range is a typical value for dc-dc supplies.

(3) If BIAS is used, a 10-µF capacitor is required. If BIAS is not used, a capacitor on the BIAS pin is not needed.

(4) The 12.1-kΩ resistor is selected to optimize PSRR and noise by matching the internal R₁value.

(5) The upper limit for the R₂resistor is to provide accuracy by making the current through the feedback network much larger than the

leakage current into the feedback node.

TPS7A53-Q1

www.ti.com.cn

ZHCSHB7B –SEPTEMBER 2017–REVISED JULY 2018

6.4 Thermal Information

TPS7A53-Q1

THERMAL METRIC⁽¹⁾

RGR (VQFN)

20 PINS

43.4

RTK (VQFNP)

20 PINS

39.9

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

36.8

32.1

17.6

16.9

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.8

0.4

ψ_JB

17.6

16.9

R_θJC(bot)

3.4

1.6

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics

over operating junction temperature range (T_J= –40°C to +150°C), V_IN= 1.4 V or V_IN= V_OUT(nom)+ 0.4 V (whichever is

greater), V_BIAS= open, V_OUT(nom)= 0.8 V⁽¹⁾, OUT connected to 50 Ω to GND⁽²⁾, V_EN= 1.1 V, C_IN= 10 µF, C_OUT= 47 µF, C_NR/SS

= C_FF= open, and PG pin pulled up to V_INwith 100 kΩ (unless otherwise noted); typical values are at T_J= 25°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

1.09

1.39

2.9

UNIT

V_FB

Feedback voltage

0.8

V_NR/SS

NR/SS pin voltage

0.8

V_UVLO1+(IN)

V_HYS1(IN)

V_UVLO1-(IN)

V_UVLO2+(IN)

V_HYS2(IN)

V_UVLO2-(IN)

V_UVLO+(BIAS)

V_UVLO-(BIAS)

V_HYS(BIAS)

Rising input supply UVLO with BIAS

V_UVLO1(IN)hysteresis

V_INrising with V_BIAS= 3.0 V

1.02

320

V_BIAS= 3.0 V

Falling input supply UVLO with BIAS

V_INfalling with V_BIAS= 3.0 V

0.55

0.711

1.31

253

Rising input supply UVLO without BIAS V_INrising

V_UVLO2(IN)hysteresis

Falling input supply UVLO without BIAS V_INfalling

0.65

2.45

1.064

2.83

2.531

290

Rising bias supply UVLO

Falling bias supply UVLO

V_UVLO(BIAS)hysteresis

V_BIASrising, V_IN= 1.1 V

V_BIASfalling, V_IN= 1.1 V

V_IN= 1.1 V

Using external resistors⁽³⁾

Range

0.8

5.15

0.8 V ≤ V_OUT≤ 5.15 V, 5 mA ≤ I_OUT≤ 3 A, over

V_IN, –40℃ < T_J< 150℃

Accuracy

–2%

Accuracy with

BIAS

V_IN= 1.1 V, 5 mA ≤ I_OUT≤ 3 A,3.0 V ≤ V_BIAS

6.5 V, –40℃ < T_J< 150℃

≤

–1.75%

–1%

0.75%

V_OUT

Output voltage

Accuracy

0.8 V ≤ V_OUT≤ 5.15 V, 5 mA ≤ I_OUT≤ 3 A, over

V_IN, –40℃ < T_J< 125℃

Accuracy with

BIAS

V_IN= 1.1 V, 5 mA ≤ I_OUT≤ 3 A,

3.0 V ≤ V_BIAS≤ 6.5 V, –40℃ < T_J< 125℃

–0.75%

0.75%

ΔV_OUT/ ΔV_IN

Line regulation

I_OUT= 5 mA, 1.4 V ≤ V_IN≤ 6.5 V

0.0035

0.07

mV/V

mV/A

5 mA ≤ I_OUT≤ 3 A, 3.0 V ≤ V_BIAS≤ 6.5 V,

V_IN= 1.1 V

ΔV_OUT/ ΔI_OUTLoad regulation

5 mA ≤ I_OUT≤ 3 A

0.08

0.04

5 mA ≤ I_OUT≤ 3 A, V_OUT= 5.0 V

(1) V_OUT(nom)is the expected V_OUTvalue set by the external feedback resistors.

(2) This 50-Ω load is disconnected when the test conditions specify an I_OUTvalue.

(3) When the device is connected to external feedback resistors at the FB pin, external resistor tolerances are not included.

TPS7A53-Q1

ZHCSHB7B –SEPTEMBER 2017–REVISED JULY 2018

www.ti.com.cn

Electrical Characteristics (continued)

over operating junction temperature range (T_J= –40°C to +150°C), V_IN= 1.4 V or V_IN= V_OUT(nom)+ 0.4 V (whichever is

greater), V_BIAS= open, V_OUT(nom)= 0.8 V⁽¹⁾, OUT connected to 50 Ω to GND⁽²⁾, V_EN= 1.1 V, C_IN= 10 µF, C_OUT= 47 µF, C_NR/SS

= C_FF= open, and PG pin pulled up to V_INwith 100 kΩ (unless otherwise noted); typical values are at T_J= 25°C

PARAMETER

TEST CONDITIONS

MIN

TYP

157

215

255

MAX

285

370

475

UNIT

V_IN= 1.4 V, I_OUT= 3 A, V_FB= 0.8 V – 3%

V_IN= 5.4 V, I_OUT= 3 A, V_FB= 0.8 V – 3%

V_IN= 5.6 V, I_OUT= 3 A, V_FB= 0.8 V – 3%

RGR package

RTK package

V_IN= 1.1 V, 3.0 V ≤ V_BIAS≤ 6.5 V,

I_OUT= 3 A, V_FB= 0.8 V – 3%

110

195

V_DO

Dropout voltage

V_IN= 1.4 V, I_OUT= 3 A, V_FB= 0.8 V – 3%

V_IN= 5.4 V, I_OUT= 3 A, V_FB= 0.8 V – 3%

V_IN= 5.6 V, I_OUT= 3 A, V_FB= 0.8 V – 3%

170

241

291

310

415

515

V_IN= 1.1 V, 3.0 V ≤ V_BIAS≤ 6.5 V,

I_OUT= 3 A, V_FB= 0.8 V – 3%

126

4.2

220

4.9

V_OUTforced at 0.9 × V_OUT(nom)

I_LIM

I_SC

Output current limit

3.55

–0.5

V_IN= V_OUT(nom)+ 0.4 V

Short-circuit current limit

GND pin current

R_LOAD= 20 mΩ

1.0

V_IN= 6.5 V, I_OUT= 5 mA

V_IN= 1.4 V, I_OUT= 3 A

5.5

I_GND

4.3

Shutdown, PG = open, V_IN= 6.5 V, V_EN= 0.5 V

V_IN= 6.5 V, V_EN= 0 V and 6.5 V

µA

I_EN

EN pin current

0.5

V_IN= 1.1 V, V_BIAS= 6.5 V,

V_OUT(nom)= 0.8 V, I_OUT= 3 A

I_BIAS

BIAS pin current

2.4

3.5

0.5

EN pin low-level input voltage

(disable device)

V_IL(EN)

V_IH(EN)

EN pin high-level input voltage

(enable device)

1.1

V_IT-(PG)

V_HYS(PG)

V_IT+(PG)

PG pin threshold

PG pin hysteresis

PG pin threshold

For falling V_OUT

For rising V_OUT

0.82V_OUT

0.88V_OUT

0.02V_OUT

0.90V_OUT

0.93V_OUT

0.84V_OUT

0.95V_OUT

0.4

V_OUT< V_IT(PG), I_PG= –1 mA

(current into device)

V_OL(PG)

PG pin low-level output voltage

I_lkg(PG)

I_NR/SS

I_FB

PG pin leakage current

NR/SS pin charging current

FB pin leakage current

V_OUT> V_IT(PG), V_PG= 6.5 V

V_NR/SS= GND, V_IN= 6.5 V

V_IN= 6.5 V

µA

4.0

6.5

–100

100

f = 10 kHz,

V_OUT= 0.8 V,

V_BIAS= 5.0 V

f = 500 kHz,

V_OUT= 0.8 V,

V_BIAS= 5.0 V

V_IN– V_{O UT}= 0.4 V,

I_OUT= 3 A, C_NR/SS= 100 nF,

PSRR

Power-supply ripple rejection

C_FF= 10 nF, C_OUT

47 µF || 10 µF || 10 µF

f = 10 kHz,

V_OUT= 5.0 V

f = 500 kHz,

V_OUT= 5.0 V

BW = 10 Hz to 100 kHz, V_IN= 1.1 V,

V_OUT= 0.8 V, V_BIAS= 5.0 V, I_OUT= 3 A,

C_NR/SS= 100 nF, C_FF= 10 nF,

4.4

C_OUT= 47 µF || 10 µF || 10 µF

V_n

Output noise voltage

µV_RMS

BW = 10 Hz to 100 kHz,

V_OUT= 5.0 V, I_OUT= 3 A, C_NR/SS= 100 nF,

C_FF= 10 nF, C_OUT= 47 µF || 10 µF || 10 µF

7.7

Shutdown, temperature increasing

Reset, temperature decreasing

160

140

T_SD

Thermal shutdown temperature

°C

TPS7A53-Q1

www.ti.com.cn

ZHCSHB7B –SEPTEMBER 2017–REVISED JULY 2018

6.6 Typical Characteristics

at T_A= 25°C, V_IN= 1.4 V or V_IN= V_OUT(NOM)+ 0.4 V (whichever is greater), V_BIAS= open, V_OUT(NOM)= 0.8 V, V_EN= 1.1 V, C_OUT

= 47 µF, C_NR/SS= 0 nF, C_FF= 0 nF, and PG pin pulled up to V_INwith 100 kΩ (unless otherwise noted)

100

I_OUT= 0.1 A

I_OUT= 0.5 A

I_OUT= 1.0 A

I_OUT= 2.0 A

I_OUT= 2.5 A

I_OUT= 3.0 A

V_IN= 1.10 V

V_IN= 1.15 V

V_IN= 1.20 V

V_IN= 1.25 V

V_IN= 1.30 V

V_IN= 1.35 V

V_IN= 1.40 V

1x10¹

1x10²

1x10³

1x10⁴

1x10⁵

1x10⁶

1x10⁷

1x10¹

1x10²

1x10³

1x10⁴

1x10⁵

1x10⁶

1x10⁷

Frequency (Hz)

V_IN= 1.1 V, V_BIAS= 5 V,

I_OUT= 3 A, V_BIAS= 5 V,

C_OUT= 47 µF || 10 µF || 10 µF, C_NR/SS= 10 nF, C_FF= 10 nF

图 1. PSRR vs Frequency and I_OUT

图 2. PSRR vs Frequency and V_INWith Bias

100

V_BIAS= 0 V

V_BIAS= 3.0 V

V_BIAS= 5.0 V

V_BIAS= 6.5 V

V_IN= 1.1 V, V_BIAS= 5 V

V_IN= 1.2 V, V_BIAS= 5 V

V_IN= 1.4 V, V_BIAS= 0 V

V_IN= 2.5 V, V_BIAS= 0 V

V_IN= 5.0 V, V_BIAS= 0 V

1x10¹

1x10²

1x10³

1x10⁴

1x10⁵

1x10⁶

1x10⁷

1x10¹

1x10²

1x10³

1x10⁴

1x10⁵

1x10⁶

1x10⁷

Frequency (Hz)

V_IN= 1.4 V, I_OUT= 1 A,

I_OUT= 1 A,

C_OUT= 47 µF || 10 µF || 10 µF, C_NR/SS= 10 nF, C_FF= 10 nF

图 3. PSRR vs Frequency and V_BIAS

图 4. PSRR vs Frequency and V_IN

100

V_OUT= 0.8 V

V_OUT= 0.9 V

V_IN= 3.60 V

V_IN= 3.65 V

V_OUT= 1.1 V

V_IN= 3.70 V

V_OUT= 1.2 V

V_OUT= 1.5 V

V_OUT= 1.8 V

V_IN= 3.75 V

V_IN= 3.80 V

V_IN= 3.85 V

V_OUT= 2.5 V

V_IN= 3.90 V

1x10¹

1x10²

1x10³

1x10⁴

1x10⁵

1x10⁶

1x10⁷

1x10¹

1x10²

1x10³

1x10⁴

1x10⁵

1x10⁶

1x10⁷

Frequency (Hz)

V_IN= V_OUT+ 0.3 V, V_BIAS= 5.0 V, I_OUT= 3 A,

C_OUT= 47 µF || 10 µF || 10 µF, C_NR/SS= 10 nF, C_FF= 10 nF

I_OUT= 3 A, C_OUT= 47 µF || 10 µF || 10 µF, C_NR/SS= 10 nF,

C_FF= 10 nF

图 5. PSRR vs Frequency and V_OUTWith Bias

图 6. PSRR vs Frequency and V_INfor V_OUT= 3.3 V

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Typical Characteristics (接下页)

at T_A= 25°C, V_IN= 1.4 V or V_IN= V_OUT(NOM)+ 0.4 V (whichever is greater), V_BIAS= open, V_OUT(NOM)= 0.8 V, V_EN= 1.1 V, C_OUT

= 47 µF, C_NR/SS= 0 nF, C_FF= 0 nF, and PG pin pulled up to V_INwith 100 kΩ (unless otherwise noted)

100

C_OUT= 47||10||10 mF

C_OUT= 47 mF

C_OUT= 100 mF

C_OUT= 200 mF

C_OUT= 500 mF

V_BIAS= 3.0 V

V_BIAS= 5.0 V

V_BIAS= 6.5 V

1x10¹

1x10²

1x10³

1x10⁴

1x10⁵

1x10⁶

1x10⁷

1x10¹

1x10²

1x10³

1x10⁴

1x10⁵

1x10⁶

1x10⁷

Frequency (Hz)

V_IN= V_OUT+ 0.3 V, V_OUT= 1 V, I_OUT= 3 A, C_NR/SS= 10 nF,

C_FF= 10 nF

V_IN= V_OUT+ 0.3 V, V_OUT= 1 V, I_OUT= 3 A,

C_OUT= 47 µF || 10 µF || 10 µF, C_NR/SS= 10 nF, C_FF= 10 nF

图 7. PSRR vs Frequency and C_OUT

图 8. V_BIASPSRR vs Frequency and V_BIAS

I_OUT= 1.0 A

I_OUT= 2.0 A

I_OUT= 3.0 A

V_OUT= 5.0 V, 11.7 mV_RMS

V_OUT= 3.3 V, 8.3 mV_RMS

V_OUT= 1.5 V, 5.4 mV_RMS

V_OUT= 0.8 V, 4.5 mV_RMS

0.5

0.2

0.1

0.05

0.02

0.01

0.005

0.002

0.001

0.6

1.2

1.8

2.4

3.6

4.2

4.8

5.4

1x10¹

1x10²

1x10³

1x10⁴

1x10⁵

1x10⁶5x10⁶

Output Voltage (V)

Frequency (Hz)

V_IN= V_OUT+ 0.3 V and V_BIAS= 5 V for V_OUT≤ 2.2 V,

C_OUT= 47 µF || 10 µF || 10 µF, C_NR/SS= 10 nF, C_FF= 10 nF,

RMS noise BW = 10 Hz to 100 kHz

V_IN= V_OUT+ 0.3 V and V_BIAS= 5 V for V_OUT≤ 2.2 V, I_OUT= 3 A,

C_OUT= 47 µF || 10 µF || 10 µF, C_NR/SS= 10 nF, C_FF= 10 nF,

RMS noise BW = 10 Hz to 100 kHz

图 10. Output Noise vs Frequency and V_OUT

图 9. Output Voltage Noise vs Output Voltage

V_IN= 1.4 V, V_BIAS= 5.0 V, 4.5 mV_RMS

V_IN= 1.4 V, 6.0 mV_RMS

C_NR/SS= 0 nF, 6.2 mV_RMS

C_NR/SS= 1 nF, 4.9 mV_RMS

V_IN= 1.5 V, 4.5 mV_RMS

V_IN= 1.8 V, 4.5 mV_RMS

V_IN= 2.5 V, 4.6 mV_RMS

V_IN= 5.0 V, 5.15 mV_RMS

C_NR/SS= 10 nF, 4.4 mV_RMS

C_NR/SS= 100 nF, 4.35 mV_RMS

0.5

0.2

0.1

0.2

0.1

0.05

0.02

0.01

0.02

0.01

0.005

0.002

0.001

0.002

0.001

1x10¹

1x10²

1x10³

1x10⁴

1x10⁵

1x10⁶4x10⁶

1x10¹

1x10²

1x10³

1x10⁴

1x10⁵

1x10⁶4x10⁶

Frequency (Hz)

I_OUT= 3 A, C_OUT= 47 µF || 10 µF || 10 µF, C_NR/SS= 10 nF,

C_FF= 10 nF, RMS noise BW = 10 Hz to 100 kHz

V_IN= V_OUT+ 0.3 V, V_BIAS= 5 V, I_OUT= 3 A, C_OUT= 47 µF ||

10 µF || 10 µF, C_FF= 10 nF, RMS noise BW = 10 Hz to 100 kHz

图 11. Output Noise vs Frequency and V_IN

图 12. Output Noise vs Frequency and C_NR/SS

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Typical Characteristics (接下页)

at T_A= 25°C, V_IN= 1.4 V or V_IN= V_OUT(NOM)+ 0.4 V (whichever is greater), V_BIAS= open, V_OUT(NOM)= 0.8 V, V_EN= 1.1 V, C_OUT

= 47 µF, C_NR/SS= 0 nF, C_FF= 0 nF, and PG pin pulled up to V_INwith 100 kΩ (unless otherwise noted)

C_FF= 0 nF, 6.2 mV_RMS

C_FF= 0.1 nF, 5.8 mV_RMS

C_FF= 1 nF, 4.9 mV_RMS

C_FF= 10 nF, 4.4 mV_RMS

C_FF= 100 nF, 4.35 mV_RMS

C_NR/SS= 10 nF, 11.7 mV_RMS

C_NR/SS= 100 nF, 7.7 mV_RMS

C_FF= C_NR/SS= 100 nF, 6.0 mV_RMS

0.5

0.2

0.1

0.2

0.1

0.05

0.02

0.01

0.02

0.01

0.005

0.002

0.001

0.002

0.001

1x10¹

1x10²

1x10³

1x10⁴

1x10⁵

1x10⁶4x10⁶

1x10¹

1x10²

1x10³

1x10⁴

1x10⁵

1x10⁶4x10⁶

Frequency (Hz)

V_IN= V_OUT+ 0.3 V, V_BIAS= 5 V, I_OUT= 3 A, sequencing with a dc-

dc converter and PG, C_OUT= 47 µF || 10 µF || 10 µF,

C_NR/SS= 10 nF, RMS noise BW = 10 Hz to 100 kHz

I_OUT= 3 A, C_OUT= 47 µF || 10 µF || 10 µF, C_FF= 10 nF,

RMS noise BW = 10 Hz to 100 kHz

图 13. Output Noise vs Frequency and C_FF

图 14. Output Noise at 5.0-V Output

1.2

Output Current

V_OUT= 0.9 V

V_OUT= 1.1 V

V_OUT= 1.2 V

V_OUT= 1.8 V

0.8

0.6

0.4

-10

-20

-30

-40

-50

V_EN

0.2

V_OUT, C_NR/SS= 0 nF

V_OUT, C_NR/SS= 10 nF

V_OUT, C_NR/SS= 47 nF

V_OUT, C_NR/SS= 100 nF

-0.2

0.25

0.5

0.75

1.25

1.5

1.75

Time (ms)

V_IN= 1.2 V, V_OUT= 0.9 V, V_BIAS= 5.0 V, I_OUT= 3 A,

C_OUT= 47 µF || 10 µF || 10 µF, C_FF= 10 nF

V_IN= V_OUT+ 0.3 V, V_BIAS= 5 V, I_{OUT, DC}= 100 mA, slew rate =

1 A/µs, C_NR/SS= C_FF= 10 nF, C_OUT= 47 µF || 10 µF || 10 µF

图 16. Load Transient vs Time and V_OUTWith Bias

图 15. Start-Up Waveform vs Time and C_NR/SS

Output Current

V_OUT= 0.9 V

V_OUT= 1.1 V

V_OUT, 0.5 A/ms

V_OUT, 1 A/ms

V_OUT, 2 A/ms

-10

-20

-30

-40

-50

-25

-50

0.2 0.4 0.6 0.8

1.2 1.4 1.6 1.8

0.4

0.8

1.2

1.6

Time (ms)

I_{OUT, DC}= 100 mA, C_OUT= 47 µF || 10 µF || 10 µF,

C_NR/SS= C_FF= 10 nF, slew rate = 1 A/µs

V_OUT= 5 V, I_{OUT, DC}= 100 mA, I_OUT= 100 mA to 3 A,

C_OUT= 47 µF || 10 µF || 10 µF, C_NR/SS= C_FF= 10 nF

图 17. Load Transient vs Time and V_OUTWithout Bias

图 18. Load Transient vs Time and Slew Rate

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Typical Characteristics (接下页)

at T_A= 25°C, V_IN= 1.4 V or V_IN= V_OUT(NOM)+ 0.4 V (whichever is greater), V_BIAS= open, V_OUT(NOM)= 0.8 V, V_EN= 1.1 V, C_OUT

= 47 µF, C_NR/SS= 0 nF, C_FF= 0 nF, and PG pin pulled up to V_INwith 100 kΩ (unless otherwise noted)

500

450

400

350

300

250

200

150

100

-40èC

0èC

25èC

85èC

125èC

150èC

V_OUT, 100 mA to 3 A

V_OUT, 500 mA to 3 A

-20

-40

1.5

2.5

3.5

4.5

5.5

Time (ms)

100

125

150

Input Voltage (V)

I_OUT= 3 A, V_BIAS= 0 V

V_IN= 1.2 V, V_BIAS= 5.0 V, C_OUT= 47 µF || 10 µF || 10 µF,

C_NR/SS= C_FF= 10 nF, slew rate = 1 A/µs

图 19. Load Transient vs Time and DC Load

图 20. Dropout Voltage vs Input Voltage Without Bias

(V_OUT= 0.9 V)

500

300

250

200

150

100

-40èC

0èC

25èC

85èC

125èC

150èC

-40èC

0èC

25èC

85èC

125èC

150èC

450

400

350

300

250

200

150

100

1.5

2.5

3.5

4.5

5.5

0.5

1.5

2.5

Input Voltage (V)

Output Current (A)

I_OUT= 3 A, V_BIAS= 6.5 V

图 21. Dropout Voltage vs Input Voltage With Bias

V_IN= 1.4 V, V_BIAS= 0 V

图 22. Dropout Voltage vs Output Current Without Bias

300

250

200

150

100

300

250

200

150

100

-40èC

0èC

25èC

85èC

125èC

150èC

-40èC

0èC

25èC

85èC

125èC

150èC

0.5

1.5

2.5

0.5

1.5

2.5

Output Current (A)

V_IN= 1.1 V, V_BIAS= 3 V

V_IN= 5.5 V

图 23. Dropout Voltage vs Output Current With Bias

图 24. Dropout Voltage vs Output Current (High V_IN)

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Typical Characteristics (接下页)

at T_A= 25°C, V_IN= 1.4 V or V_IN= V_OUT(NOM)+ 0.4 V (whichever is greater), V_BIAS= open, V_OUT(NOM)= 0.8 V, V_EN= 1.1 V, C_OUT

= 47 µF, C_NR/SS= 0 nF, C_FF= 0 nF, and PG pin pulled up to V_INwith 100 kΩ (unless otherwise noted)

1.5

1.2

0.9

0.6

0.3

0.8

0.6

0.4

0.2

-40èC

0èC

25èC

85èC

125èC

150èC

-40èC

0èC

25èC

85èC

125èC

150èC

-0.3

-0.6

-0.9

-1.2

-1.5

-0.2

-0.4

-0.6

-0.8

-1

0.5

1.5

2.5

1.5

2.5

3.5

4.5

5.5

6.5

Output Current (A)

Input Voltage (V)

V_IN= 1.4 V, V_BIAS= 0 V

V_OUT= 0.8 V, V_BIAS= 0 V, I_OUT= 5 mA

图 25. Load Regulation With Bias

图 26. Line Regulation Without Bias

-40èC

0èC

25èC

85èC

125èC

150èC

-40èC

0èC

25èC

85èC

125èC

150èC

3.75

3.5

3.25

3.75

3.5

3.25

2.75

2.5

2.25

2.75

2.5

2.25

3.5

4.5

5.5

6.5

Input Voltage (V)

Bias Voltage (V)

V_BIAS= 0 V, I_OUT= 5 mA

V_IN= 1.1 V, I_OUT= 5 mA

图 27. Quiescent Current vs Input Voltage

图 28. Quiescent Current vs Bias Voltage

-40èC

0èC

25èC

85èC

125èC

150èC

-40èC

0èC

25èC

85èC

125èC

150èC

3.5

4.5

5.5

6.5

Input Voltage (V)

Bias Voltage (V)

V_BIAS= 0 V

V_IN= 1.1 V

图 29. Shutdown Current vs Input Voltage

图 30. Shutdown Current vs Bias Voltage

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Typical Characteristics (接下页)

at T_A= 25°C, V_IN= 1.4 V or V_IN= V_OUT(NOM)+ 0.4 V (whichever is greater), V_BIAS= open, V_OUT(NOM)= 0.8 V, V_EN= 1.1 V, C_OUT

= 47 µF, C_NR/SS= 0 nF, C_FF= 0 nF, and PG pin pulled up to V_INwith 100 kΩ (unless otherwise noted)

8.5

1.5

1.25

7.5

0.75

0.5

0.25

6.5

V_UVLO2(IN)Rising

V_UVLO2(IN)Falling

V_UVLO1(IN)Rising

V_UVLO1(IN)Falling

5.5

-50

-25

100

125

150

-50

-25

100

125

150

Temperature (èC)

V_BIAS= 0 V

图 31. NR/SS Current vs Temperature

图 32. V_INUVLO vs Temperature

V_IL(EN)V_IH(EN)

2.9

2.8

2.7

2.6

2.5

2.4

2.3

2.2

1.1

0.9

0.8

0.7

0.6

0.5

0.4

V_UVLO(BIAS)Rising

V_UVLO(BIAS)Falling

-50

-25

100

125

-50

-25

100

125

Temperature (èC)

V_IN= 1.1 V

V_IN= 1.4 V, 6.5 V

图 33. V_BIASUVLO vs Temperature

图 34. Enable Threshold vs Temperature

600

500

400

300

200

100

600

500

400

300

200

100

Temperature

-40èC

0èC

25èC

85èC

125èC

150èC

-40èC

0èC

25èC

85èC

125èC

150èC

0.5

1.5

PG Current (mA)

2.5

0.5

1.5

2.5

PG Current (mA)

V_IN= 6.5 V

图 35. PG Voltage vs PG Current Sink

图 36. PG Voltage vs PG Current Sink

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Typical Characteristics (接下页)

at T_A= 25°C, V_IN= 1.4 V or V_IN= V_OUT(NOM)+ 0.4 V (whichever is greater), V_BIAS= open, V_OUT(NOM)= 0.8 V, V_EN= 1.1 V, C_OUT

= 47 µF, C_NR/SS= 0 nF, C_FF= 0 nF, and PG pin pulled up to V_INwith 100 kΩ (unless otherwise noted)

4.75

4.25

3.75

3.25

2.75

2.25

1.75

PG Falling

PG Rising

Temperature

25èC

-40èC

0èC

125èC

85èC

-50

-25

100

125

150

100

200

300

400

500

600

700

Temperature (èC)

Output Voltage (mV)

Temperature limited because of power dissipation

图 37. PG Threshold vs Temperature

图 38. Foldback Current Limit vs Output Voltage

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7 Detailed Description

7.1 Overview

The TPS7A53-Q1 is a high-current (3 A), low-noise (4.4 µV_RMS), high-accuracy (1%), low-dropout linear voltage

regulator with an input range of 1.1 V to 6.5 V and an output voltage range of 0.8 V to 5.15 V. The TPS7A53-Q1

has an integrated charge pump for ease of use, and an external bias rail to allow for the lowest dropout across

the entire output voltage range. 表 1 categorizes the functions shown in the Functional Block Diagram. These

features make the TPS7A53-Q1 a robust solution to solve many challenging problems by generating a clean,

accurate power supply in a variety of applications.

表 1. Device Features

VOLTAGE REGULATION

SYSTEM START-UP

INTERNAL PROTECTION

High accuracy

Programmable soft start

Foldback current limit

No sequencing requirement between BIAS,

IN, and EN

Low-noise, high-PSRR output

Fast transient response

Thermal shutdown

Power-good output

Start-up with negative bias on OUT

7.2 Functional Block Diagram

PSRR

Boost

Current

Limit

OUT

Charge

Pump

BIAS

Active

R_NR/SS= 250 kW

Discharge

0.8-V

V_REF

Error

Amp

I_NR/SS

NR/SS

200 pF

Internal

Controller

UVLO

Circuits

Thermal

Shutdown

0.88 x V_REF

GND

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7.3 Feature Description

7.3.1 Voltage Regulation Features

7.3.1.1 DC Regulation

An LDO, as shown in 图 39, functions as a class-B amplifier in which the input signal is the internal reference

voltage (V_REF). V_REFis designed to have a very low bandwidth at the input to the error amplifier through the use

of a low-pass filter (V_NR/SS).

As such, the reference can be considered as a pure dc input signal. The low output impedance of an LDO comes

from the combination of the output capacitor and pass element. The pass element also presents a high input

impedance to the source voltage when operating as a current source. A positive LDO can only source current

because of the class-B architecture.

This device achieves a maximum of 1% output voltage accuracy primarily because of the high-precision band-

gap voltage (V_BG) that creates V_REF. The low dropout voltage (V_DO) reduces the thermal power dissipation

required by the device to regulate the output voltage at a given current level, thereby improving system

efficiency. These features combine to make this device a good approximation of an ideal voltage source.

V_IN

To Load

R₁

V_REF

R₂

GND

NOTE: V_OUT= V_REF× (1 + R₁/ R₂).

图 39. Simplified Regulation Circuit

7.3.1.2 AC and Transient Response

The LDO responds quickly to a transient (large-signal response) on the input supply (line transient) or the output

current (load transient) resulting from the LDO high-input impedance and low output-impedance across

frequency. This same capability also means that the LDO has a high power-supply rejection ratio (PSRR) and,

when coupled with a low internal noise-floor (V_n), the LDO approximates an ideal power supply in ac (small-

signal) and large-signal conditions.

The choice of external component values optimizes the small- and large-signal response. The NR/SS capacitor

(C_NR/SS) and feed-forward capacitor (C_FF) easily reduce the device noise floor and improve PSRR.

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Feature Description (接下页)

7.3.2 System Start-Up Features

In many different applications, the power-supply output must turn on within a specific window of time to either

provide proper operation of the load or to minimize the loading on the input supply or other sequencing

requirements. The LDO start-up is well-controlled and user-adjustable, solving the demanding requirements

faced by many power-supply design engineers in a simple fashion.

7.3.2.1 Programmable Soft Start (NR/SS Pin)

Soft start directly controls the output start-up time and indirectly controls the output current during start-up (inrush

current).

The external capacitor at the NR/SS pin (C_NR/SS), as shown in 图 40, sets the output start-up time by setting the

rise time of the internal reference (V_NR/SS).

I_NR/SS

R_NR

V_REF

C_NR/SS

GND

V_FB

图 40. Simplified Soft-Start Circuit

7.3.2.2 Internal Sequencing

Controlling when a single power supply turns on can be difficult in a power distribution network (PDN) because of

the high power levels inherent in a PDN, and the variations between all of the supplies. As shown in 图 41 and 表

2, the LDO turnon and turnoff time is set by the enable circuit (EN) and undervoltage lockout circuits (UVLO_1,2(IN)

and UVLO_BIAS).

Internal Enable

UVLO_BIAS

Control

UVLO_1,2(IN)

图 41. Simplified Turnon Control

表 2. Internal Sequencing Functionality Table

ENABLE

STATUS

LDO

STATUS

ACTIVE

DISCHARGE

POWER

GOOD

INPUT VOLTAGE

BIAS VOLTAGE

PG = 1 when

EN = 1

EN = 0

Off

V_OUT≥ V_IT(PG)

V_BIAS≥ V_UVLO(BIAS)

V_IN≥ V_{UVLO_1,2(IN)}

Off

V_BIAS< V_UVLO(BIAS)+V_HYS(BIAS)

BIAS = don't care

PG = 0

(1)

V_IN< V_{UVLO_1,2(IN)}– V_HYS1,2(IN)

IN = don't care

EN = don't care

V_BIAS≥ V_UVLO(BIAS)

(1) The active discharge remains on as long as V_INor V_BIASprovide enough headroom for the discharge circuit to function.

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7.3.2.2.1 Enable (EN)

The enable signal (V_EN) is an active-high digital control that enables the LDO when the enable voltage is past the

rising threshold (V_EN≥ V_IH(EN)) and disables the LDO when the enable voltage is below the falling threshold (V_EN

≤ V_IL(EN)). The exact enable threshold is between V_IH(EN)and V_IL(EN)because EN is a digital control. Connect EN

to V_INif enable functionality is not desired.

7.3.2.2.2 Undervoltage Lockout (UVLO) Control

The UVLO circuits respond quickly to glitches on IN or BIAS and attempt to disable the output of the device if

either of these rails collapse.

7.3.2.2.3 Active Discharge

When either EN or UVLO are low, the device connects a resistor of several hundred ohms from V_OUTto GND,

discharging the output capacitance.

Do not rely on the active discharge circuit for discharging large output capacitors when the input voltage drops

below the targeted output voltage. Current flows from the output to the input (reverse current) when V_OUT> V_IN,

which can cause damage to the device (when V_OUT> V_IN+ 0.3 V).

7.3.2.3 Power-Good Output (PG)

The PG signal provides an easy solution to meet demanding sequencing requirements because PG signals

when the output nears its nominal value. PG can be used to signal other devices in a system when the output

voltage is near, at, or above the set output voltage (V_OUT(nom)). 图 42 shows a simplified schematic.

The PG signal is an open-drain digital output that requires a pullup resistor to a voltage source and is active high.

The PG circuit sets the PG pin into a high-impedance state to indicate that the power is good.

Using a large feed-forward capacitor (C_FF) delays the output voltage and, because the PG circuit monitors the FB

pin, the PG signal can indicate a false positive.

V_PG

V_BG

V_IN

V_FB

GND

UVLO_BIAS

UVLO_IN

GND

图 42. Simplified PG Circuit

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7.3.3 Internal Protection Features

In many applications, fault events can occur that damage devices in the system. Short circuits and excessive

heat are the most common fault events for power supplies. The TPS7A53-Q1 implements circuitry to protect the

device and its load during these events. Continuously operating in these fault conditions or above a junction

temperature of 140°C is not recommended because the long-term reliability of the device is reduced.

7.3.3.1 Foldback Current Limit (I_CL

)

The internal current limit circuit is used to protect the LDO against high load-current faults or shorting events.

During a current-limit event, the LDO sources constant current; therefore, the output voltage falls with decreased

load impedance. Thermal shutdown can activate during a current limit event because of the high power

dissipation typically found in these conditions. For proper operation of the current limit, minimize the inductances

to the input and load. Continuous operation in current limit is not recommended.

7.3.3.2 Thermal Protection (T_sd)

The thermal shutdown circuit protects the LDO against excessive heat in the system, either resulting from current

limit or high ambient temperature.

The output of the LDO turns off when the LDO temperature (junction temperature, T_J) exceeds the rising thermal

shutdown temperature. The output turns on again after T_Jdecreases below the falling thermal shutdown

temperature.

A high power dissipation across the device, combined with a high ambient temperature (T_A), can cause T_Jto be

greater than or equal to T_sd, triggering the thermal shutdown and causing the output to fall to 0 V. The LDO can

cycle on and off when thermal shutdown is reached under these conditions.

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7.4 Device Functional Modes

表 3 provides a quick comparison between the regulation and disabled operation.

表 3. Device Functional Modes Comparison

PARAMETER

OPERATING

MODE

V_IN

V_BIAS

I_OUT

I_OUT< I_CL

—

T_J

(2)

Regulation⁽¹⁾

Disabled⁽³⁾

V_IN> V_OUT(nom)+ V_DO

V_IN< V_{UVLO_1,2(IN)}

_BIAS≥ V_UVLO(BIAS)

V_EN> V_IH(EN)

V_EN< V_IL(EN)

T_J≤ T_J(maximum)

T_J> T_sd

V_BIAS< V_UVLO(BIAS)

(1) All table conditions must be met.

(2) V_BIASis only required for V_IN< 1.4 V.

(3) The device is disabled when any condition is met.

7.4.1 Regulation

The device regulates the output to the nominal output voltage when all the conditions in 表 3 are met.

7.4.2 Disabled

When disabled, the pass device is turned off, the internal circuits are shut down, and the output voltage is

actively discharged to ground by an internal resistor from the output to ground. See the Active Discharge section

for additional information.

7.4.3 Current Limit Operation

During a current-limit event, the LDO regulates the output current instead of the output voltage; therefore, the

output voltage falls with decreased load impedance.

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8 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

Successfully implementing an LDO in an application depends on the application requirements. This section

discusses key device features and how to best implement them to achieve a reliable design.

8.1.1 Recommended Capacitor Types

The TPS7A53-Q1 is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at

the input, output, and noise-reduction pin (NR, pin 13). Multilayer ceramic capacitors have become the industry

standard for these types of applications and are recommended, but must be used with good judgment. Ceramic

capacitors that employ X7R-, X5R-, and COG-rated dielectric materials provide relatively good capacitive stability

across temperature. The use of Y5V-rated capacitors is discouraged because of large variations in capacitance.

Regardless of the ceramic capacitor type selected, ceramic capacitance varies with operating voltage and

temperature. Make sure to derate ceramic capacitors by at least 50%. The input and output capacitors

recommended herein account for a capacitance derating of approximately 50%, but at high V_INand V_OUT

conditions (V_IN= 5.5 V to V_OUT= 5.0 V), the derating can be greater than 50%, and must be taken into

consideration.

8.1.1.1 Input and Output Capacitor Requirements (C_INand C_OUT

)

The TPS7A53-Q1 is designed and characterized for operation with ceramic capacitors of 47 µF or greater (22 µF

or greater of capacitance) at the output and 10 µF or greater (5 µF or greater of capacitance) at the input. Use at

least a 47-µF capacitor at the input to minimize input impedance. Place the input and output capacitors as near

as practical to the respective input and output pins in order to minimize trace parasitics. If the trace inductance

from the input supply to the TPS7A53-Q1 is high, a fast current transient can cause V_INto ring above the

absolute maximum voltage rating and damage the device. This situation can be mitigated by additional input

capacitors to dampen and keep the ringing below the device absolute maximum ratings.

A combination of multiple output capacitors boosts the high-frequency PSRR. The combination of one 0805-

sized, 47-µF ceramic capacitor in parallel with two 0805-sized, 10-µF ceramic capacitors with a sufficient voltage

rating, in conjunction with the PSRR boost circuit, optimizes PSRR for the frequency range of 400 kHz to

700 kHz, a typical range for dc-dc supply switching frequency. This 47-µF || 10-µF || 10-µF capacitor combination

also makes certain that at high input voltage and high output voltage configurations, the minimum effective

capacitance is met. Many 0805-sized, 47-µF ceramic capacitors have a voltage derating of approximately 60% to

80% at 5.0 V, so the addition of the two 10-µF capacitors makes sure that the capacitance is at or above 22 µF.

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Application Information (接下页)

8.1.1.2 Noise-Reduction and Soft-Start Capacitor (C_NR/SS

)

The TPS7A53-Q1 features a programmable, monotonic, voltage-controlled soft start that is set with an external

capacitor (C_NR/SS). Use an external C_NR/SSto minimize inrush current into the output capacitors. This soft-start

feature eliminates power-up initialization problems when powering field-programmable gate arrays (FPGAs),

digital signal processors (DSPs), or other processors. The controlled voltage ramp of the output also reduces

peak inrush current during start-up, minimizing start-up transients to the input power bus.

To achieve a monotonic start-up, the TPS7A53-Q1 error amplifier tracks the voltage ramp of the external soft-

start capacitor until the voltage approaches the internal reference. The soft-start ramp time depends on the soft-

start charging current (I_NR/SS), the soft-start capacitance (C_NR/SS), and the internal reference (V_NR/SS). 公式 1

calculates soft-start ramp time:

t_SS= (V_NR/SS× C_NR/SS) / I_NR/SS

(1)

I_NR/SSis provided in the Electrical Characteristics table and has a typical value of 6.2 µA.

The noise-reduction capacitor, in conjunction with the noise-reduction resistor, forms a low-pass filter (LPF) that

filters out the noise from the reference before being gained up with the error amplifier, thereby reducing the

device noise floor. The LPF is a single-pole filter and 公式 2 can calculate the cutoff frequency. The typical value

of R_NRis 250 kΩ. Increasing the C_NR/SScapacitor has a greater affect because the output voltage increases

when the noise from the reference is gained up even more at higher output voltages. For low-noise applications,

a 10-nF to 1-µF C_NR/SSis recommended.

f_cutoff= 1 / (2 × π × R_NR× C_NR/SS

)

(2)

8.1.1.3 Feed-Forward Capacitor (C_FF)

Although a feed-forward capacitor (C_FF) from the FB pin to the OUT pin is not required to achieve stability, a

10-nF external feed-forward capacitor optimizes the transient, noise, and PSRR performance. A higher

capacitance C_FFcan be used; however, the start-up time is longer and the power-good signal can incorrectly

indicate that the output voltage is settled. For a detailed description, see Pros and Cons of Using a Feed-

Forward Capacitor with a Low Dropout Regulator.

8.1.2 Soft Start and Inrush Current

Soft start refers to the ramp-up characteristic of the output voltage during LDO turnon after EN and UVLO

achieve threshold voltage. The noise-reduction capacitor serves a dual purpose of both governing output noise

reduction and programming the soft-start ramp during turnon.

Inrush current is defined as the current into the LDO at the IN pin during start-up. Inrush current then consists

primarily of the sum of load current and the current used to charge the output capacitor. This current is difficult to

measure because the input capacitor must be removed, which is not recommended. However, 公式 3 can

estimate this soft-start current:

_OUT´ dV_OUT(t)

V_OUT(t)

R_LOAD

I_OUT(t)

where:

•

V_OUT(t) is the instantaneous output voltage of the turnon ramp

dV_OUT(t) / dt is the slope of the V_OUTramp

R_LOADis the resistive load impedance

(3)

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Application Information (接下页)

8.1.3 Optimizing Noise and PSRR

Improve the ultra-low noise floor and PSRR of the device by careful selection of:

•

C_NR/SSfor the low-frequency range

C_FFin the midband frequency range

C_OUTfor the high-frequency range

V_IN– V_OUTfor all frequencies, and

V_BIASat lower input voltages

A larger noise-reduction capacitor improves low-frequency PSRR by filtering any noise coupling from the input

into the reference. To improve midband PSRR, use the feed-forward capacitor to place a pole-zero pair near the

edge of the loop bandwidth and push out the loop bandwidth. Use larger output capacitors to improve high-

frequency PSRR.

A higher input voltage improves the PSRR by giving the device more headroom to respond to noise on the input.

A bias rail also improves the PSRR at lower input voltages because greater headroom is provided for the internal

circuits.

The noise-reduction capacitor filters out low-frequency noise from the reference, and the feed-forward capacitor

reduces output voltage noise by filtering out the midband frequency noise. However, a large feed-forward

capacitor can create new issues that are discussed in Pros and Cons of Using a Feed-Forward Capacitor with a

Low Dropout Regulator.

Use a large output capacitor to reduce high-frequency output voltage noise. Additionally, a bias rail or higher

input voltage improves the noise because greater headroom is provided for the internal circuits.

表 4 lists the output voltage noise for the 10-Hz to 100-kHz band at a 5.0-V output for a variety of conditions with

an input voltage of 5.4 V, an R₁of 12.1 kΩ, and a load current of 3 A. The 5.0-V output is used because this

output is the worst-case condition for output voltage noise.

表 4. Output Noise Voltage at a 5.0-V Output

OUTPUT VOLTAGE NOISE

C_NR/SS

(nF)

C_FF

(nF)

C_OUT

(µF)

(µV_RMS

11.7

7.7

)

47 || 10 || 10

1000

100

7.4

5.8

100

1000

8.1.4 Charge Pump Noise

The device internal charge pump generates a minimal amount of noise. Use a bias rail to minimize the internal

charge pump noise when the internal voltage is clamped, thereby reducing the overall output noise floor.

The high-frequency components of the output voltage noise density curves are filtered out in most applications

by using 10-nF to 100-nF bypass capacitors close to the load. Using a ferrite bead between the LDO output and

the load input capacitors forms a pi-filter, further reducing the high-frequency noise contribution.

8.1.5 Current Sharing

Current sharing is possible through the use of external operational amplifiers. For more details, see TI Design,

Current-Sharing Dual LDOs, and verified reference design 6 A Current-Sharing Dual LDO.

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8.1.6 Adjustable Operation

As shown in 图 43, the output voltage of the TPS7A53-Q1 is set using external resistors.

Optional Bias

C_BIAS

Supply

BIAS

R_PG

Input

Supply

To Load

OUT

C_IN

C_FF

R₁

C_OUT

TI-Device™

NR/SS

R₂

C_NR/SS

GND

图 43. Adjustable Operation

Use 公式 4 to calculate R₁and R₂for any output voltage range. This resistive network must provide a current

equal to or greater than 5 µA for dc accuracy. To optimize the noise and PSRR, use an R₁of 12.1 kΩ.

V_OUT= V_NR/SS× (1 + R₁/ R₂)

(4)

表 5 shows the resistor combinations required to achieve several common rails using standard 1%-tolerance

resistors.

表 5. Recommended Feedback-Resistor Values

TARGETED OUTPUT

FEEDBACK RESISTOR VALUES⁽¹⁾

CALCULATED OUTPUT

VOLTAGE

(V)

VOLTAGE

(V)

R₁(kΩ)

R₂(kΩ)

0.9

12.4

12.1

12.4

12.1

11.8

12.1

11.8

12.4

100

66.5

49.9

33.2

24.9

14.3

0.899

0.949

0.999

1.099

1.198

1.494

1.798

1.89

0.95

1.00

1.10

1.20

1.50

1.80

1.90

2.50

2.85

3.00

3.30

3.60

4.5

8.87

5.9

2.48

4.75

4.42

3.74

3.48

2.55

2.37

2.838

2.990

3.324

3.582

4.502

4.985

5.00

(1) R₁is connected from OUT to FB; R₂is connected from FB to GND.

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8.1.7 Power-Good Operation

For proper operation of the power-good circuit, the pullup resistor value must be between 10 kΩ and 100 kΩ. The

lower limit of 10 kΩ results from the maximum pulldown strength of the power-good transistor, and the upper limit

of 100 kΩ results from the maximum leakage current at the power-good node. If the pullup resistor is outside of

this range, then the power-good signal may not read a valid digital logic level.

Using a large C_FFwith a small C_NR/SScauses the power-good signal to incorrectly indicate that the output voltage

has settled during turnon. The C_FFtime constant must be greater than the soft-start time constant for proper

operation of the PG during start-up. For a detailed description, see Pros and Cons of Using a Feed-Forward

Capacitor with a Low Dropout Regulator.

The state of PG is only valid when the device operates above the minimum supply voltage. During short UVLO

events and at light loads, power-good does not assert because the output voltage is sustained by the output

capacitance.

8.1.8 Undervoltage Lockout (UVLO) Operation

The UVLO circuit makes sure that the device remains disabled before the input or bias supplies reach the

minimum operational voltage range, and that the device shuts down when the input supply or bias supply falls

too low.

The UVLO circuit has a minimum response time of several microseconds to fully assert. During this time, a

downward line transient below approximately 0.8 V causes the UVLO to assert for a short time; however, the

UVLO circuit does not have enough stored energy to fully discharge the internal circuits inside of the device.

When the UVLO circuit does not fully discharge, the internal circuits of the output are not fully disabled.

The effect of the downward line transient can be mitigated by either using a larger input capacitor to limit the fall

time of the input supply when operating near the minimum V_IN, or by using a bias rail.

图 44 shows the UVLO circuit response to various input voltage events. The diagram can be separated into the

following regions:

•

Region A: The device does not turn on until the input reaches the UVLO rising threshold.

Region B: Normal operation with a regulated output.

Region C: Brownout event above the UVLO falling threshold (UVLO rising threshold – UVLO hysteresis). The

output may fall out of regulation but the device is still enabled.

•

Region D: Normal operation with a regulated output.

Region E: Brownout event below the UVLO falling threshold. The device is disabled in most cases and the

output falls because of the load and active discharge circuit. The device is reenabled when the UVLO rising

threshold is reached by the input voltage and a normal start-up then follows.

•

Region F: Normal operation followed by the input falling to the UVLO falling threshold.

Region G: The device is disabled when the input voltage falls below the UVLO falling threshold to 0 V. The

output falls because of the load and active discharge circuit.

UVLO Rising Threshold

UVLO Hysteresis

V_IN

V_OUT

tAt

tBt

tDt

tEt

tFt

tGt

图 44. Typical UVLO Operation

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8.1.9 Dropout Voltage (V_DO

)

Generally speaking, the dropout voltage often refers to the minimum voltage difference between the input and

output voltage (V_DO= V_IN– V_OUT) that is required for regulation. When V_INdrops below the required V_DOfor the

given load current, the device functions as a resistive switch and does not regulate output voltage. Dropout

voltage is proportional to the output current because the device is operating as a resistive switch.

Dropout voltage is affected by the drive strength for the gate of the pass element, which is nonlinear with respect

to V_INon this device because of the internal charge pump. The charge pump causes a higher dropout voltage at

lower input voltages when a bias rail is not used.

For this device, dropout voltage increases exponentially when the input voltage nears its maximum operating

voltage because the charge pump is internally clamped to 8.0 V.

8.1.10 Device Behavior During Transition From Dropout Into Regulation

Some applications have transients that place the device into dropout, especially with a device such as a high-

current linear regulator. A typical application with these transient conditions may require setting V_IN≤ (V_OUT

V_DO) in order to keep the device junction temperature within the specified operating range. A load transient or

line transient with these conditions can place the device into dropout; for example, a load transient from 1 A to 4

A at 1 A/µs when operating with a V_INof 5.4 V and a V_OUTof 5.0 V.

The load transient saturates the error amplifier output stage when the gate of the pass element is driven as high

as possible by the error amplifier, thus making the pass element function like a resistor from V_INto V_OUT. The

error amplifier response time to this load transient (I_OUT= 4 A to 1 A at 1 A/µs) is limited because the error

amplifier must first recover from saturation, and then place the pass element back into active mode. During the

recovery from the load transient, V_OUTovershoots because the pass element is functioning as a resistor from V_IN

to V_OUT. If operating under these conditions, apply a higher dc load or increase the output capacitance in order to

reduce the overshoot.

8.1.11 Load Transient Response

The load-step transient response is the output voltage response by the LDO to a step in load current, whereby

output voltage regulation is maintained. There are two key transitions during a load transient response: the

transition from a light to a heavy load, and the transition from a heavy to a light load. The regions shown in 图 45

are broken down in this section. Regions A, E, and H are where the output voltage is in steady-state regulation.

tAt

tCt

tDt

tEt

tGt

tHt

图 45. Load Transient Waveform

During transitions from a light load to a heavy load:

•

Initial voltage dip is a result of the depletion of the output capacitor charge and parasitic impedance to the

output capacitor (region B)

•

Recovery from the dip results from the LDO increasing its sourcing current, and leads to output voltage

regulation (region C)

During transitions from a heavy load to a light load:

•

Initial voltage rise results from the LDO sourcing a large current, and leads to the output capacitor charge to

increase (region F)

•

Recovery from the rise results from the LDO decreasing its sourcing current in combination with the load

discharging the output capacitor (region G)

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Transitions between current levels changes the internal power dissipation because the TPS7A53-Q1 is a high-

current device (region D). The change in power dissipation changes the die temperature during these transitions,

and leads to a slightly different voltage level. This different output voltage level shows up in the various load

transient responses.

A larger output capacitance reduces the peaks during a load transient but slows down the response time of the

device. A larger dc load also reduces the peaks because the amplitude of the transition is lowered and a higher

current discharge path is provided for the output capacitor.

8.1.12 Reverse Current Protection Considerations

As with most LDOs, this device can be damaged by excessive reverse current.

Conditions where excessive reverse current can occur are outlined in this section, all of which can exceed the

absolute maximum rating of V_OUT> V_IN+ 0.3 V:

•

If the device has a large C_OUT, then the input supply collapses quickly and the load current becomes very

small

•

The output is biased when the input supply is not established

The output is biased above the input supply

If an excessive reverse current flow is expected in the application, then external protection must be used to

protect the device. 图 46 shows one approach of protecting the device.

Schottky Diode

Internal Body Diode

OUT

Device

C_OUT

C_IN

GND

图 46. Example Circuit for Reverse Current Protection Using a Schottky Diode

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8.1.13 Power Dissipation (P_D)

Circuit reliability demands that proper consideration be given to device power dissipation, location of the circuit

on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator

must be as free as possible of other heat-generating devices that cause added thermal stresses.

As a first-order approximation, power dissipation in the regulator depends on the input-to-output voltage

difference and load conditions. Use 公式 5 to calculate P_D:

P_D= (V_OUT- V_IN) ´ I_OUT

(5)

注

Power dissipation can be minimized, and thus greater efficiency achieved, by proper

selection of the system voltage rails. Proper selection allows the minimum input-to-output

voltage differential to be obtained. The low dropout of the TPS7A53-Q1 allows for

maximum efficiency across a wide range of output voltages.

The primary heat conduction path for the package is through the thermal pad to the PCB. Solder the thermal pad

to a copper pad area under the device. This pad area contains an array of plated vias that conduct heat to any

inner plane areas or to a bottom-side copper plane.

The maximum power dissipation determines the maximum allowable junction temperature (T_J) for the device.

According to 公式 6, power dissipation and junction temperature are most often related by the junction-to-

ambient thermal resistance (R_θJA) of the combined PCB and device package and the temperature of the ambient

air (T_A). 公式 6 is rearranged in 公式 7 for output current.

T_J= T_A+ (R_θJA× P_D)

(6)

(7)

I_OUT= (T_J– T_A) / [R_θJA× (V_IN– V_OUT)]

Unfortunately, this thermal resistance (R_θJA) is highly dependent on the heat-spreading capability built into the

particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the

planes. The R_θJArecorded in the Electrical Characteristics table is determined by the JEDEC standard, PCB, and

copper-spreading area, and is only used as a relative measure of package thermal performance. For a well-

designed thermal layout, R_θJAis actually the sum of the VQFN package junction-to-case (bottom) thermal

resistance (R_θJC(bot)) plus the thermal resistance contribution by the PCB copper.

8.1.14 Estimating Junction Temperature

The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures

of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal

resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics

are determined to be significantly independent of the copper-spreading area. The key thermal metrics (Ψ_JTand

Ψ_JB) are used in accordance with 公式 8 and are given in the Electrical Characteristics table.

Y_JT: T_J= T_T+ Y_JT´ P_D

Y_JB: T_J= T_B+ Y_JB´ P_D

where:

•

P_Dis the power dissipated as explained in 公式 5

T_Tis the temperature at the center-top of the device package, and

T_Bis the PCB surface temperature measured 1 mm from the device package and centered on the package

edge

(8)

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8.2 Typical Application

This section discusses the implementation of the TPS7A53-Q1 using an adjustable feedback network to regulate

a 3-A load requiring good PSRR at high frequency with low-noise at an output voltage of 5.0 V. 图 47 provides a

schematic for this typical application circuit.

Optional Bias

C_BIAS

Supply

BIAS

R_PG

Input

Supply

To Load

OUT

C_IN

C_FF

R₁

C_OUT

TI-Device™

NR/SS

R₂

C_NR/SS

GND

图 47. Typical Application for a 5.0-V Rail

8.2.1 Design Requirements

For this design example, use the parameters listed in 表 6 as the input parameters.

表 6. Design Parameters

PARAMETER

Input voltage

DESIGN REQUIREMENT

5.50 V, ±1%, provided by the dc-dc converter switching at 500 kHz

Bias voltage

Not used because V_OUT≥ 2.20 V

Output voltage

5.0 V, ±1%

Output current

3.0 A (maximum), 10 mA (minimum)

RMS noise, 10 Hz to 100 kHz

PSRR at 500 kHz

Start-up time

< 10 µV_RMS

> 40 dB

< 25 ms

8.2.2 Detailed Design Procedure

At 3.0 A and 5.0 V_OUT, the dropout of the TPS7A53-Q1 has a 340-mV maximum dropout over temperature; thus,

a 500-mV headroom is sufficient for operation over both input and output voltage accuracy. At full load and high

temperature on some devices, the TPS7A53-Q1 can enter dropout if both the input and output supply are

beyond the edges of the respective accuracy specification.

For a 5.0-V output. use external adjustable resistors. See the resistor values in listed 表 5 for choosing resistors

for a 5.0-V output.

Input and output capacitors are selected in accordance with the Recommended Capacitor Types section.

Ceramic capacitances of 47 µF for the input and one 47-µF capacitor in parallel with two 10-µF capacitors for the

output are selected.

To satisfy the required start-up time and still maintain low noise performance, a 100-nF C_NR/SSis selected. 公式 9

calculates this value.

t_SS= (V_NR/SS× C_NR/SS) / I_NR/SS

(9)

At the 3.0-A maximum load, the internal power dissipation is 1.5 W and corresponds to a 53.1°C junction

temperature rise for the RGR package on a standard JEDEC board. With an 55°C maximum ambient

temperature, the junction temperature is at 108.1°C. To further minimize noise, a feed-forward capacitance (C_FF)

of 10 nF is selected.

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8.2.3 Application Curves

100

I_OUT= 0.1 A

I_OUT= 0.5 A

I_OUT= 1.0 A

I_OUT= 2.0 A

I_OUT= 2.5 A

I_OUT= 3.0 A

V_IN= 5.30 V

V_IN= 5.35 V

V_IN= 5.40 V

V_IN= 5.45 V

V_IN= 5.50 V

V_IN= 5.55 V

V_IN= 5.60 V

1x10¹

1x10²

1x10³

1x10⁴

1x10⁵

1x10⁶

1x10⁷

1x10¹

1x10²

1x10³

1x10⁴

1x10⁵

1x10⁶

1x10⁷

Frequency (Hz)

图 48. PSRR vs Frequency and I_OUTfor V_OUT= 5.0 V

图 49. PSRR vs Frequency and V_INfor V_OUT= 5.0 V at I_OUT

= 3.0 A

9 Power Supply Recommendations

The TPS7A53-Q1 is designed to operate from an input voltage supply range between 1.1 V and 6.5 V. If the

input supply is less than 1.4 V, then a bias rail of at least 3.0 V must be used. The input voltage range provides

adequate headroom in order for the device to have a regulated output. This input supply must be well regulated.

If the input supply is noisy, use additional input capacitors with low ESR to help improve output noise

performance.

10 Layout

10.1 Layout Guidelines

10.1.1 Board Layout

For best overall performance, place all circuit components on the same side of the circuit board and as near as

practical to the respective LDO pin connections. Place ground return connections to the input and output

capacitor, and to the LDO ground pin as close to each other as possible, connected by a wide, component-side,

copper surface. To avoid negative system performance, do not use of vias and long traces to the input and

output capacitors. The grounding and layout scheme illustrated in 图 50 minimizes inductive parasitics, and

thereby reduces load-current transients, minimizes noise, and increases circuit stability.

To improve performance, use a ground reference plane, either embedded in the PCB itself or placed on the

bottom side of the PCB opposite the components. This reference plane serves to provide accuracy of the output

voltage, shield noise, and behaves similar to a thermal plane to spread (or sink) heat from the LDO device when

connected to the thermal pad. In most applications, this ground plane is necessary to meet thermal requirements.

10.1.2 RTK Package — High CTE Mold Compound

The RTK package uses a mold compound with a high coefficient of thermal expansion (CTE) of 12 ppm/°C. This

mold compound allows for the CTE of the packaged IC to more closely match the CTE of a conventional FR4

PCB (~14 ppm/°C to 17 ppm/°C). This CTE match is important when considering the effects that temperature

swings can induce on a board with large differences in CTE values. Package and board combinations with widely

dissimilar CTEs can experience mechanical cracking or fracturing of the solder joints caused by frequent

changes in temperature, and the corresponding differences in expansion. Devices with normal mold compounds

in similar packages typically have CTE values that are 25% lower than values found with the RTK package.

TPS7A53-Q1

ZHCSHB7B –SEPTEMBER 2017–REVISED JULY 2018

www.ti.com.cn

10.2 Layout Example

Ground Plane for Thermal Relief and Signal

Ground

To PG Pullup Supply

PG Output

NC 11

DNC

C_BIAS

R_PG

To Bias Supply

To Signal Ground

Enable Signal

BIAS

Thermal Pad

R₂

NR/SS 13

To Signal Ground

To Load

C_NR/SS

EN 14

C_FFR₁

OUT

18 19 20

Input Power Plane

Output Power Plane

C_IN

C_OUT

Power Ground Plane

Vias used for application purposes.

图 50. Example Layout

TPS7A53-Q1

www.ti.com.cn

ZHCSHB7B –SEPTEMBER 2017–REVISED JULY 2018

11 器件和文档支持

11.1 器件支持

11.1.1 开发支持

11.1.1.1 参考设计

如需了解相关的 TI 参考设计，请参阅：

TI 设计 - 电流均流双路 LDO (TIDA-00270)。

11.1.2 器件命名规则

表 7. 订购信息⁽¹⁾

产品

说明

YYY 为封装标识符。

Z 为封装数量。

TPS7A5301QYYYZ Q1

(1) 欲获得最新的封装和订货信息，请参阅本文档末尾的封装选项附录，或者访问 www.ti.com.cn 查看器件产品文件夹。

11.2 文档支持

11.2.1 相关文档

请参阅如下相关文档：

•

TPS3702 高精度过压和欠压监视器

《使用前馈电容器和低压降稳压器的优缺点》

6A 电流均流双路 LDO

11.3 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.4 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

11.5 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.6 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

11.7 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、缩写和定义。

TPS7A53-Q1

ZHCSHB7B –SEPTEMBER 2017–REVISED JULY 2018

www.ti.com.cn

12 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此产品说明书的浏览器版本，请查阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS7A5301QRGRRQ1

TPS7A5301WQRTKRQ1

ACTIVE

VQFN

RGR

RTK

3000 RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 150

A5301

5301WQ

NIPDAUAG

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS7A5301QRGRRQ1

VQFN

RGR

RTK

3000

330.0

12.4

15.4

3.75

4.3

3.75

4.3

1.15

1.1

8.0

12.0

TPS7A5301WQRTKRQ1 VQFN

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS7A5301QRGRRQ1

TPS7A5301WQRTKRQ1

VQFN

RGR

RTK

3000

367.0

336.6

367.0

336.6

35.0

41.3

Pack Materials-Page 2

GENERIC PACKAGE VIEW

RGR 20

3.5 x 3.5, 0.5 mm pitch

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4228482/A

www.ti.com

PACKAGE OUTLINE

RGR0020A

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

3.65

3.35

PIN 1 INDEX AREA

3.65

3.35

SIDE WALL

METAL THICKNESS

DIM A

1.0

0.8

OPTION 1

0.1

OPTION 2

0.2

SEATING PLANE

0.08 C

0.05

0.00

2X 2

(DIM A) TYP

SYMM

EXPOSED

THERMAL PAD

SYMM

2X 2

2.05 0.1

16X 0.5

0.30

20X

PIN 1 ID

0.18

0.5

0.3

0.1

C A B

20X

0.05

4219031/B 04/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RGR0020A

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(2.05)

SYMM

SEE SOLDER MASK

DETAIL

20X (0.6)

20X (0.24)

16X (0.5)

(2.05)

SYMM

(3.3)

(0.775)

(R0.05) TYP

(

0.2) TYP

VIA

(0.775)

(3.3)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

METAL UNDER

SOLDER MASK

METAL EDGE

EXPOSED METAL

SOLDER MASK

OPENING

EXPOSED

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4219031/B 04/2022

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RGR0020A

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(0.56) TYP

20X (0.6)

20X (0.24)

16X (0.5)

(0.56) TYP

(3.3)

SYMM

4X (0.92)

(R0.05) TYP

4X (0.92)

SYMM

(3.3)

SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL

SCALE: 20X

EXPOSED PAD 21

81% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

4219031/B 04/2022

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TPS7A53-Q1 [TI]

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