TPS7A6301-Q1 [TI]
300-mA 40-V LOW-DROPOUT REGULATOR WITH ULTRALOW Iq; 300 - mA的40 -V低压差具有超低Iq的稳压器
| 型号： | TPS7A6301-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 300-mA 40-V LOW-DROPOUT REGULATOR WITH ULTRALOW Iq |
| 文件： | 总33页 (文件大小：1255K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS7A6301-Q1, TPS7A6333-Q1
TPS7A6350-Q1, TPS7A6401-Q1
www.ti.com
SLVSAB1D –JUNE 2011–REVISED JULY 2012
300-mA 40-V LOW-DROPOUT REGULATOR WITH ULTRALOW Iq
Check for Samples: TPS7A6301-Q1, TPS7A6333-Q1, TPS7A6350-Q1, TPS7A6401-Q1
1
FEATURES
•
•
Low Input-Voltage Tracking
Thermally Enhanced 14-pin TSSOP - PWP
Package and 10-pin VSON - DRK Package
•
•
Qualified for Automotive Applications
AEC-Q100 Test Guidance With the Following
Results:
APPLICATIONS
–
Device Temperature Grade 1: –40°C to
125°C Ambient Operating Temperature
•
•
•
Infotainment Systems With Sleep Mode
Body Control Modules
–
–
Device HBM ESD Classification Level H2
Device CDM ESD Classification Level C2
Always-On Battery Applications
–
–
–
Gateway Applications
Remote Keyless Entry Systems
Immobilizers
•
•
Low Dropout Voltage
300 mV at IOUT = 150 mA
–
4-V to 40-V Wide Input-Voltage Range
With up to 45-V Transients
DESCRIPTION
•
•
300-mA Maximum Output Current
Ultralow Quiescent Current
The TPS7A63xx-Q1 and TPS7A6401-Q1 are a family
of low-dropout linear voltage regulators designed for
low power consumption and quiescent current less
than 35 µA in light-load applications. These devices,
designed to achieve stable operation even with a low-
ESR ceramic output capacitor, feature an integrated
programmable window watchdog and overcurrent
protection. Designers can program the output voltage
using external resistors.
feature allows for a smaller input capacitor and can
possibly eliminate the need of using boost
converter during cold-crank conditions. The power-
on-reset delay is fixed (250 µs typical), or an external
capacitor can program the delay. Because of such
features, these devices are well-suited in power
supplies for various automotive applications.
–
–
IQUIESCENT = 35 µA (Typ.) at Light Loads
ISLEEP < 2 µA When EN = Low
•
Fixed (3.3-V and 5-V) and Adjustable (2.5-V to
7-V) Output Voltages
•
•
Integrated Watchdog With Fault/Flag
A low-voltage tracking
Stable With Low-ESR Ceramic Output
Capacitor
a
•
Integrated Power-On Reset
–
–
Programmable Delay
Open-Drain Reset Output
•
Integrated Fault Protection
–
–
Short-Circuit/Overcurrent Protection
Thermal Shutdown
TYPICAL APPLICATION SCHEMATIC
TPS7A6x01-Q1
TPS7A6333-Q1
VOUT
VOUT
COUT
VOUT
VOUT
COUT
VIN
VIN
VIN
or
TPS7A6350-Q1
VIN
CIN
CIN
R1
R2
FB
RRST
RDELAY
RDELAY
RRST
CDLY
CDLY
ROSC
GND
ROSC
GND
ROSC
ROSC
RESET
RESET
nRST
nRST
RFLT/FLAG
RFLT/FLAG
WD_FLT/
WD_FLG
WD_FLT/
WD_FLG
FAULT/
FLAG
FAULT/
FLAG
EN nWD_EN WD
EN nWD_EN WD
Figure 1. Fixed Output Voltage Option
Figure 2. Adjustable Output Voltage Option
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2012, Texas Instruments Incorporated
TPS7A6301-Q1, TPS7A6333-Q1
TPS7A6350-Q1, TPS7A6401-Q1
SLVSAB1D –JUNE 2011–REVISED JULY 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
DESCRIPTION
VALUE
UNIT
VIN, VEN
VOUT
Unregulated inputs(2)(3)
Regulated output
Sense voltage for error amplifier(2)
Constant-voltage reference(2)
45
7
V
V
V
V
FB
7
ROSC
7
nWD_EN, WD,
WD_FLAG,
WD_FLT
Watchdog inputs and outputs(2)
7
V
nRST
Open-drain reset output(2)
7
V
RDELAY
Reset delay timer output(2)
7
4.1
V
Thermal impedance junction to exposed pad TSSOP-PWP package
Thermal impedance junction to exposed pad VSON-DRK package
Thermal impedance junction to ambient TSSOP-PWP package(4)
Thermal impedance junction to ambient VSON-DRK package(4)
Electrostatic discharge(5)
°C/W
°C/W
°C/W
°C/W
kV
θJP
5.2
51
θJA
51.7
2
ESD
TA
Operating ambient temperature
125
°C
Tstg
Storage temperature range
–65 to 150
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to GND.
(2) Absolute negative voltage on these pins not to go below –0.3 V.
(3) Absolute maximum voltage for duration less than 480 ms.
(4) The thermal data is based on JEDEC standard high-K profile – JESD 51-5. The copper pad is soldered to the thermal land pattern. Also,
the correct attachment procedure must be incorporated.
(5) The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin.
2
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Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS7A6301-Q1 TPS7A6333-Q1 TPS7A6350-Q1 TPS7A6401-Q1
TPS7A6301-Q1, TPS7A6333-Q1
TPS7A6350-Q1, TPS7A6401-Q1
www.ti.com
SLVSAB1D –JUNE 2011–REVISED JULY 2012
DISSIPATION RATINGS
TA < 25°C POWER
RATING (W)
DERATING FACTOR ABOVE
TA = 85°C POWER
RATING (W)
JEDEC STANDARD
PACKAGE
TA = 25°C (°C/W)
JEDEC standard PCB,
high-K, JESD 51-5
14 pin
TSSOP-PWP
2.45
2.41
51
1.27
1.25
JEDEC Standard PCB
high-K, JESD 51-5
10 pin VSON-DRK
51.7
RECOMMENDED OPERATING CONDITIONS
DESCRIPTION
MIN
MAX UNIT
VIN, VEN
Unregulated input voltage
4
40
5.25
150
V
nRST, RDELAY, nWD_EN, WD_FLT(1)
,
Low voltage input or output
0
V
WD_FLAG(2), WD, FB
(3)
TJ
Operating junction temperature range
-40
°C
(1) Applicable for TPS7A63xx-Q1 only
(2) Applicable for TPS746401-Q1 only
(3) Applicable for TPS7A6301-Q1 and TPS7A6401-Q1 only
ELECTRICAL CHARACTERISTICS
VIN = 14 V, TJ = –40ºC to 150ºC (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Input Voltage (VIN Pin)
VOUT
0.3 V
+
VIN
Input voltage
VOUT = 2.5 V to 7 V, IOUT = 1 mA
40
3
V
VIN = 8.2 V to 18 V, VEN = 5 V,
IOUT = 0.01 mA to 0.75 mA
IQUIESCENT
ISLEEP
Quiescent current
Sleep or shutdown current
35
µA
µA
VIN = 8.2 V to 18 V, VEN < 0.8 V,
IOUT = 0 mA (no load), TA = 125°C
Undervoltage lockout
voltage
VIN-UVLO
Ramp VIN down until output is turned OFF
Ramp VIN up until output is turned ON
3.16
3.45
V
V
VIN(POWERUP)
Power-up voltage
Device Enable Input (EN Pin)
VIL
VIH
Logic-input low level
Logic-input high level
0
0.8
40
V
V
2.5
Regulated Output Voltage (VOUT Pin)
Fixed VOUT value (3.3 V, 5 V or a programmed value),
IOUT = 10 mA to 200 mA, VIN = VOUT + 1 V to 16V
VOUT
Regulated output voltage
Line regulation
–2%
2%
VIN = 6 V to 28 V, IOUT = 10 mA, VOUT = 5 V
VIN = 6 V to 28 V, IOUT = 10 mA, VOUT = 3.3 V
IOUT = 10 mA to 200 mA, VIN= 14 V, VOUT = 5 V
IOUT = 10 mA to 200 mA, VIN = 14 V, VOUT = 3.3 V
IOUT = 200 mA
15
20
mV
mV
mV
mV
mV
mV
Ω
ΔVLINE-REG
25
ΔVLOAD-REG
Load regulation
Dropout voltage
35
500
300
2
VDROPOUT
(VIN – VOUT
)
IOUT = 150 mA
(1)
RSW
Switch resistance
Output current
VIN to VOUT resistance
VOUT in regulation
[VOUT in regulation, VOUT = 3.3 V, VIN = 6 V](2)
0
0
200
300
1000
mA
mA
mA
IOUT
ICL
Output current limit
VOUT = 0 V (VOUT pin is shorted to ground)
350
(1) This test is done with VOUT in regulation, measuring the VIN – VOUT parameter when VOUT drops by 100 mV from the programmed value
(of VOUT) at specified loads.
(2) Design Information - not tested; specified by characterization.
Copyright © 2011–2012, Texas Instruments Incorporated
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TPS7A6301-Q1, TPS7A6333-Q1
TPS7A6350-Q1, TPS7A6401-Q1
SLVSAB1D –JUNE 2011–REVISED JULY 2012
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ELECTRICAL CHARACTERISTICS (continued)
VIN = 14 V, TJ = –40ºC to 150ºC (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VIN-RIPPLE = 0.5 Vpp, IOUT = 200 mA, frequency = 100
Hz, VOUT = 5 V and VOUT = 3.3 V
60
Power-supply ripple
rejection
PSRR(3)
dB
VIN-RIPPLE = 0.5 Vpp, IOUT = 200 mA, frequency = 150
kHz, VOUT = 5 V and VOUT = 3.3 V
30
Reset (nRST Pin)
VOL
IOH
Reset pulled low
IOL = 5 mA
0.4
1
V
Leakage current
Reset pulled to VOUT through a 5-kΩ resistor
µA
VOUT powered up above internally set tolerance,
VOUT = 5 V
4.5
4.5
4.65
3.07
4.65
3.07
4.77
VTH(POR)
Power-on-reset threshold
V
V
VOUT powered up above internally set tolerance,
VOUT = 3.3 V
VOUT falling below internally set tolerance,
VOUT = 5 V
4.77
UVTHRES
Reset threshold
VOUT falling below internally set tolerance,
VOUT = 3.3 V
CDLY = 100 pF
CDLY = 100 nF
300
300
µs
(2)
tPOR
Power-on-reset delay
ms
Internally preset
Power-on-reset delay
tPOR-PRESET
tDEGLITCH
CDLY not connected, VOUT = 5 V and VOUT = 3.3 V
250
5.5
µs
µs
Reset deglitch time
Reset Delay (RDELAY Pin)
Threshold to release nRST
VTH(RDELAY)
Voltage at RDELAY pin is ramped up
Voltage at RDELAY pin = 1 V
3
1
3.3
V
high
Delay capacitor
charging current
IDLY
0.75
5
1.25
µA
mA
Delay capacitor
discharging current
IOL
Current Voltage Reference (ROSC Pin)
VROSC Voltage reference
Watchdog Fault/ Flag Output ( WD_FLT/ WD_FLAG Pin)
0.95
1
1.05
V
VOL
Logic output low level
IOL= 5 mA
0.4
1
V
WD_FLT/WD_FLG pulled to VOUT through 5-kΩ
resistor
IOH
Leakage current
µA
Watchdog Enable Input (nWD_EN Pin)
VIL
VIH
Logic input low level
Logic input high level
0.8
0.8
V
5.25 V < VDD < 3 V
2.5
2.5
Watchdog Input Pulse (WD Pin)
VIL
VIH
Logic input low level
Logic input high level
V
5.25 V < VDD < 3 V
ROSC = 10 kΩ ± 1%
ROSC = 20kΩ ± 1%
10
20
tWD
Watchdog window duration
ms
Tolerance of watchdog
period using external
resistor
Excludes tolerance of ROSC
(external resistor connected to ROSC pin)
tWD-tol
–10%
108
10%
254
External resistor not connected, ROSC pin is floating
or open
tWD-DEFAULT
tWD-HOLD
Default watchdog period
164
ms
µs
Minimum pulse width for
resetting watch dog timer
1.65
(3) Specified by design - not tested.
4
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Product Folder Link(s): TPS7A6301-Q1 TPS7A6333-Q1 TPS7A6350-Q1 TPS7A6401-Q1
TPS7A6301-Q1, TPS7A6333-Q1
TPS7A6350-Q1, TPS7A6401-Q1
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SLVSAB1D –JUNE 2011–REVISED JULY 2012
ELECTRICAL CHARACTERISTICS (continued)
VIN = 14 V, TJ = –40ºC to 150ºC (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Operating Temperature Range
Operating junction
temperature
TJ
–40
150
ºC
ºC
ºC
Thermal shutdown trip
point
TSHUTDOWN
165
10
Thermal shutdown
hysteresis
THYST
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TPS7A6301-Q1, TPS7A6333-Q1
TPS7A6350-Q1, TPS7A6401-Q1
SLVSAB1D –JUNE 2011–REVISED JULY 2012
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DEVICE INFORMATION
TSSOP PWP PACKAGE (TOP VIEW)
Fixed Output Voltage Option
VSON DRK PACKAGE (TOP VIEW)
Fixed Output Voltage Option
1
2
3
4
5
6
7
14
13
12
11
10
9
VIN
nRST
NC
ROSC
NC
10 ROSC
1
2
3
4
5
VIN
nRST
GND
EN
nWD_EN
NC
WD
WD_FLT/FLAG
NC
9
8
7
6
nWD_EN
RDELAY
WD
GND
EN
RDELAY
VOUT
8
WD_FLT
VOUT
TSSOP PWP PACKAGE (TOP VIEW)
Adjustable Output Voltage Option
1
2
3
4
5
6
7
14
13
12
11
10
9
VIN
nRST
FB
ROSC
NC
nWD_EN
NC
WD
WD_FLT/FLAG
NC
GND
EN
RDELAY
VOUT
8
PIN FUNCTIONS
PIN NO.
PIN NAME
TYPE
DESCRIPTION
PWP DRK
Input voltage pin: The unregulated input voltage is supplied to this pin. A bypass capacitor connected between
the VIN pin and GND pin dampens line transients on the input.
1
2
1
2
VIN
I
nRST
FB
O
I
Reset pin: This is an open-drain reset output pin with an external pullup resistor connected to the VOUT pin.
Feedback pin (only applicable for TPS7A6x01-Q1): Sense voltage for error amplifier
Not connected (only applicable for TPS7A6333-Q1/6350-Q1)
3
4
–
3
NC
–
GND
I/O
Ground pin: This is signal ground pin of the IC.
Chip enable pin: This is a high-voltage-tolerant input pin with an internal pulldown. A high input to this pin
activates the device and turns the regulator ON. Connect this input to the VIN terminal for self-bias applications.
If this pin remains unconnected, the device stays disabled.
5
6
4
8
EN
I
RDELAY
O
Reset delay timer pin: This pin programs the reset delay timer using an external capacitor (CDLY) to ground.
Regulated output voltage pin: This is a regulated voltage output (VOUT = 3.3 V or 5 V or a programmed value) pin
with a limitation on maximum output current. For devices with adjustable output voltage (TPS7A6x01-Q1),
connecting an external resistor network programs the output voltage. In order to achieve stable operation and
prevent oscillation, connect an external output capacitor (COUT) with low ESR between this pin and GND pin.
7
8
5
–
VOUT
O
NC
–
Not connected
Watchdog fault pin (for TPS7A63xx-Q1 only): This is an active-low fault output pin with an external pullup
resistor connected to the VOUT pin.
WD_FLT
O
9
6
Watchdog flag pin (for TPS746401-Q1 only): This is an active-high latched fault (that is, flag) output pin with an
external pullup resistor connected to VOUT pin.
WD_FLAG
O
10
11
7
–
WD
NC
I
Watchdog service pin: This is an input pin to provide a service signal to the watchdog.
Not connected
–
Watchdog enable pin: A high input to this pin disables the watchdog, and vice versa. This is an active-low input
pin with an internal pulldown. Leaving this pin is unconnected and floating keeps the watchdog enabled. An
external microcontroller can pull this pin high momentarily to disable and reinitialize the watchdog.
12
9
nWD_EN
I
13
14
–
NC
–
Not connected
ROscillator pin: This pin programs the internal oscillator frequency (and hence the duration of the watchdog
window) by connecting an external resistor to ground.
10
ROSC
O
6
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Product Folder Link(s): TPS7A6301-Q1 TPS7A6333-Q1 TPS7A6350-Q1 TPS7A6401-Q1
TPS7A6301-Q1, TPS7A6333-Q1
TPS7A6350-Q1, TPS7A6401-Q1
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SLVSAB1D –JUNE 2011–REVISED JULY 2012
FUNCTIONAL BLOCK DIAGRAMS
VRef1
VIN
Band Gap
Temp. Sensor/
Thermal Shutdown
VIN
CIN
UVLO Comp.
with internal
reference
Q1
VRef1
Error
Regulator
Amp.
Control
Logic
Control
EN
VOUT
COUT
VOUT
Over
Current
Detection
RRST
RDELAY
Voltage
Supervisor with
Reset Delay
CDLY
Charge Pump
Oscillator
Q2
RESET
nRST
Current
Regulator
Watchdog
Oscillator
ROSC
ROSC
RFLT
Timer
WD_FLT
Q3
FAULT
GND
Watchdog
Fault Control
nWD_EN
WD
Figure 3. TPS7A6333-Q1 and TPS7A6350-Q1 (Fixed Output Voltage With FAULT Output)
VRef1
VIN
Band Gap
Temp. Sensor/
Thermal Shutdown
VIN
CIN
UVLO Comp.
with internal
reference
Q1
VRef1
Error
Regulator
Amp.
Control
Logic
Control
EN
VOUT
COUT
VOUT
FB
R1
R2
RRST
Over Current
Detection
RDELAY
Voltage
Supervisor with
Reset Delay
CDLY
Charge Pump
Oscillator
Q2
RESET
nRST
Current
Regulator
Watchdog
Oscillator
ROSC
RFLT
ROSC
Timer
WD_FLT
Q3
FAULT
GND
Watchdog
Fault Control
nWD_EN
WD
Figure 4. TPS7A6301 (Adjustable Output Voltage With FAULT Output)
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TPS7A6301-Q1, TPS7A6333-Q1
TPS7A6350-Q1, TPS7A6401-Q1
SLVSAB1D –JUNE 2011–REVISED JULY 2012
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VRef1
VIN
Band Gap
Temp. Sensor/
Thermal Shutdown
VIN
CIN
UVLO Comp.
with internal
reference
Q1
VRef1
Error
Regulator
Amp.
Control
Logic
Control
EN
VOUT
COUT
VOUT
FB
R1
R2
RRST
Over Current
Detection
RDELAY
Voltage
Supervisor with
Reset Delay
CDLY
Charge Pump
Oscillator
Q2
RESET
nRST
Current
Regulator
Watchdog
Oscillator
ROSC
ROSC
RFLAG
Timer
WD_FLAG
Q3
FLAG
GND
Watchdog
Fault Control
nWD_EN
WD
Figure 5. TPS7A6401-Q1 (Adjustable Output Voltage With FLAG Output)
8
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TPS7A6301-Q1, TPS7A6333-Q1
TPS7A6350-Q1, TPS7A6401-Q1
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SLVSAB1D –JUNE 2011–REVISED JULY 2012
TYPICAL CHARACTERISTICS
Graphs shown in the Typical Characteristics section for unreleased devices are for preview only.
55
50
45
40
35
30
25
20
15
60
50
40
30
20
10
IOUT = 1mA
VIN =14V
VOUT= 5V, 3.3V
VIN = 14V
TA= 25°C
VOUT = 5V, 3.3V
-50
0
50
100
150
0.1
1
10
100
TA (°C)
IOUT (mA)
Figure 6. Quiescent Current versus Load Current
Figure 7. Quiescent Current versus Ambient Air
Temperature
0.4
0.35
0.3
700
600
500
400
300
200
100
0
VOUT = 5V
VOUT = 5V, 3.3V
TA= 25°C
0.25
0.2
TA = 125°C
TA = 25°C
0.15
0.1
IOUT = 100mA
TA = -40°C
No Load
0.05
0
4
14
24
VIN (V)
34
40
0
50
100
IOUT (mA)
150
200
(1)
Figure 8. Quiescent Current versus Input Voltage
Figure 9. Dropout Voltage versus Load Current
(1) Measure dropout voltage when the output voltage drops by 100 mV from the regulated output-voltage level. (For example, for an output
voltage programmed to be 5 V, measure the dropout voltage when the output voltage drops down to 4.9 V from 5 V.)
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TPS7A6301-Q1, TPS7A6333-Q1
TPS7A6350-Q1, TPS7A6401-Q1
SLVSAB1D –JUNE 2011–REVISED JULY 2012
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TYPICAL CHARACTERISTICS (continued)
5.1
5.08
5.06
5.04
5.02
5
6
5
4
3
2
1
0
IOUT = 100mA
TA = 25°C
VIN = 14V
IOUT = 1mA
4.98
4.96
4.94
4.92
4.9
-50
0
50
100
150
2
3
4
5
6
7
TA (°C)
VIN (V)
Figure 10. Output Voltage versus Ambient Air Temperature
(VOUT Set to 5 V)
Figure 11. Output Voltage versus Input Voltage
(VOUT Set to 5 V)
0.12
750
700
650
600
550
500
450
VIN = 14V
ILOAD = 100mA
VOUT = 5V, 3.3V
VOUT = 5V, 3.3V
0.1
0.08
0.06
0.04
0.02
0
TA= 125°C
TA= 25°C
TA = -40°C
0
10
20
30
40
50
-50
0
50
TA (°C)
100
150
VIN (V)
Figure 12. Output Voltage versus Input Voltage
Figure 13. Output Current Limit versus Ambient Air
Temperature
12
11.5
11
3
VIN = 14V
IOUT = 10mA
VOUT = 5V, 3.3V
VIN
step from
8V to 28V
VOUT = 5V, 3.3V
IOUT step from
10mA to 200mA
2.5
2
1.5
1
10.5
10
9.5
9
0.5
8.5
8
-50
0
-50
0
50
100
150
0
50
100
150
TA (°C)
TA (°C)
Figure 14. Load Regulation versus Ambient Air
Temperature
Figure 15. Line Regulation versus Ambient Air Temperature
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TYPICAL CHARACTERISTICS (continued)
120
100
80
120
100
80
60
40
20
0
VIN = 14V
IOUT = 200mA
TA = 25°C
COUT = 10µF
VOUT = 5V, 3.3V
VIN = 14V
IOUT = 1mA
TA = 25°C
COUT = 10µF
VOUT = 5V, 3.3V
60
40
20
0
10
100
1k
10k
Frequency (Hz)
100k
1M
10
100
1k
10k
Frequency (Hz)
100k
1M
Figure 16. PSRR at Heavy Load Current
Figure 17. PSRR at Light Load Current
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DETAILED DESCRIPTION
TPS7A63xx-Q1/6401-Q1 is a family of monolithic low-
dropout linear voltage regulators with integrated
watchdog and reset functionality. These voltage
regulators are designed for low power consumption
and quiescent current less than 25 µA in light-load
applications. Because of an programmable reset
delay (also called power-on-reset delay), these
devices are well-suited in power supplies for
microprocessors and microcontrollers.
When starting up, and also when the output recovers
from a negative voltage spike due to a load step or a
dip in the input voltage for a specified duration, the
device implements reset delay to indicate that output
voltage is stable and in regulation.
When the output voltage reaches the power-on-reset
threshold (VTH(POR)) level, that is, 93% of regulated
output voltage (3.3 V or 5 V, or a programmed value),
a
constant output current charges an external
These devices are available in two fixed and
adjustable output-voltage versions as follows:
capacitor (CDLY) to an internal threshold (VTH(RDELAY)
)
voltage level. Then, nRST asserts high and CDLY
discharges through an internal load. This allows CDLY
to charge from approximately 0 V during the next
power cycle.
•
•
Fault (WD_FLT) output version: TPS7A63xx-Q1
Flag (WD_FLAG) output version: TPS7A6401-Q1
The following section describes the features of
TPS7A63xx-Q1/6401-Q1 voltage regulators in detail.
Program the reset delay time by connecting an
external capacitor (CDLY ,100 pF to 100 nF) to the
RDELAY pin. Equation 1 gives the delay time:
CDLY´3
Power Up, Reset Delay, and Reset Output
t
=
POR
-6
1´10
(1)
During power up, the regulator incorporates
a
protection scheme to limit the current through the
pass element and output capacitor. When the input
where,
tPOR = reset delay time in seconds
CDLY = reset delay capacitor value in farads
voltage exceeds a certain threshold (VIN(POWERUP)
)
level, the output voltage begins to ramp up as shown
in Figure 18.
VIN(POWERUP)
t < tDEGLITCH
VIN
t>tDEGLITCH
0
0
VIN
VTH(POR)
UVTHRES
VTH(POR)= 93% of VOUT
0
0
VOUT
VOUT
VTH(RDELAY)
VTH(RDELAY)
0
0
VRDELAY
VnRST
VRDELAY
VnRST
tPOR
tDEGLITCH
tPOR
0
0
Figure 18. Power Up and Conditions for Activation
of Reset
Figure 19. Reset Delay and Deglitch Filter
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As Figure 19 shows, if the regulated output voltage
falls below 93% of the set level, nRST asserts low
after a short de-glitch time of approximately 5.5 µs
(typical). In case of negative transients in the input
voltage (VIN), the reset signal asserts low only if the
output (VOUT) drops and stays below the reset
threshold level (VTH(POR)) for more than the deglitch
time (tDEGLITCH), as Figure 19 and Figure 22 illustrate.
While nRST is low, if the input voltage returns to the
nominal operating voltage, the normal power-up
sequence ensues. nRST asserts high only if the
output voltage exceeds the reset threshold voltage
(VTH(POR)) and the reset delay time (tPOR) has
elapsed.
Charge-Pump Operation
These devices have an internal charge pump which
turns on or off depending on the input voltage and the
output current. The charge pump switching circuitry
must not cause conducted emissions to exceed
required thresholds on the input voltage line. For a
given output current, the charge pump stays on at
lower input voltages and turns off at higher input
voltages. The charge-pump switching thresholds are
hysteretic. Figure 20 and Figure 21 show typical
switching thresholds for the charge pump at light (IOUT
< ~2 mA) and heavy (IOUT > ~2 mA) loads,
respectively.
Adjustable Output Voltage
ON
Program the regulated output voltage (VOUT) by
connecting external resistors to FB pin. Calculate the
feedback resistor values using Equation 2.
Hysteresis
R1
é
= V 1 +
REF
ù
V
OUT
ê
ú
R2
ë
û
(2)
OFF
where,
VOUT= desired output voltage
7.8
7.9
VIN (V)
VREF = reference voltage (VREF= 1.23 V, typically)
R1, R2 = feedback resistors (see Figure 5)
Figure 20. Charge-Pump Operation at Light
Loads
Equation
3 gives the overall tolerance of the
regulated output.
R1
é
ù
tol
= tol
+
tol + tol
é
R1 R2
ù
û
VOUT
VREF
ê
ú ë
ON
R1 + R2
ë
û
(3)
where,
tolVOUT = tolerance of the output voltage
Hysteresis
tolVREF = tolerance of the internal reference
voltage (tolVREF = ± 1.5% typically)
OFF
tolR1,tolR2 = tolerance of feedback resistors R1,
R2
9.2
9.6
VIN (V)
For a tighter tolerance on VOUT, select lower-value
feedback resistors. TI recommends to select
feedback resistors such that the sum of R1 and R2 is
between 20 kΩ and 200 kΩ.
Figure 21. Charge-Pump Operation at Heavy
Loads
Low-Power Mode
Chip Enable
At light loads and high input voltages (VIN
>
These devices have a high-voltage-tolerant EN pin
that an external microcontroller or a digital control
circuit can use to enable and disable them. A high
input to this pin activates the device and turns the
regulator on. For self bias applications, connect this
input to the VIN terminal . An internal pulldown
resistor is connected to this pin, and therefore if this
pin remains unconnected, the device stays disabled.
approximately 8 V, such that the charge pump is off),
the device operates in low-power mode and the
quiescent current consumption is reduced to 25 µA
(typical) as shown in Table 1.
Table 1. Typical Quiescent Current Consumption
IOUT
Charge Pump ON
Charge Pump OFF
IOUT
approximately 2
mA
<
35 µA
(Low-power mode)
250 µA
(Light load)
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Table 1. Typical Quiescent Current
Consumption (continued)
Integrated Fault Protection
These devices feature integrated fault protection to
make them ideal for use in automotive applications.
In order to remain in a safe area of operation during
certain fault conditions, the devices use internal
current-limit protection and current-limit foldback to
limit the maximum output current. This protects them
from excessive power dissipation. For example,
during a short-circuit condition on the output, fault
protection limits the current through the pass element
to ICL to protect the device from excessive power
dissipation.
IOUT
Charge Pump ON
Charge Pump OFF
IOUT
>
approximately 2
mA
280 µA
70 µA
(Heavy load)
Undervoltage Shutdown
These devices have an integrated undervoltage
lockout (UVLO) circuit to shut down the output if the
input voltage (VIN) falls below an internally fixed
UVLO threshold level (VIN-UVLO). This ensures that the
regulator does not latch into an unknown state during
low-input-voltage conditions. The regulator powers up
when the input voltage exceeds the VIN(POWERUP)
level, as Figure 22 shows.
Thermal Shutdown
These devices incorporate a thermal shutdown (TSD)
circuit as
continuous
a
protection from overheating. For
normal operation, the junction
temperature should not exceed the TSD trip point.
The junction temperature exceeding the TSD trip
point causes the output to turn off. When the junction
temperature falls below TSD trip point, the output
turns on again, as Figure 23 shows.
Low-Voltage Tracking
At low input voltages, the regulator drops out of
regulation, and the output voltage tracks the input
minus a voltage based on the load current (IOUT) and
switch resistance (RSW), as Figure 22 shows. This
feature allows for a smaller input capacitor and can
possibly eliminate the need of using
a boost
convertor during cold crank conditions, as Figure 22
shows.
Tracking
VIN-UVLO
VIN
0
UVTHRES
0
VOUT
0
VRDELAY
tDEGLITCH
VnRST
0
Figure 22. Low-Voltage Tracking and Undervoltage
Lockout
Figure 23. Thermal Cycling Waveform for
TPS7A6350-Q1 (VIN= 24 V, IOUT= 200 mA, VOUT= 5 V)
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INTEGRATED WINDOW WATCHDOG
Watchdog Enable
These devices have an integrated watchdog with fault
(WD_FLT) and flag (WD_FLAG) output options. Both
device options are available in fixed- and adjustable-
output versions. The watchdog operation, service
fault conditions, and difference between fault
(TPS7A63xx-Q1) and flag (TPS746401-Q1) output
versions are described as follows.
An external microcontroller or a digital circuit can
apply an appropriate signal to the nWD_EN pin to
enable or disable the watchdog. A low input to this
pin turns the watchdog on. Because of an internal
pulldown resistor connected to this pin, leaving the
pin unconnected keeps the watchdog enabled.
Watchdog Service Signal
Programmable-Window Watchdog
In order for the watchdog service signal (WD) to
service an open window correctly, the service signal
must stay high for a duration of at least tWD_HOLD. The
recommended value of tWD_HOLD is given by
Equation 7:
Program the duration of the watchdog window by
connecting an external resistor (ROSC) to ground at
the ROSC pin. The current through the resistor sets
the clock frequency of the internal oscillator. The user
can adjust the duration of the watchdog window (that
is, the watchdog timer period) by changing the
resistor value. The duration of the watchdog window
and the duration of the fault output are multiples of
the internal oscillator frequency and are given by the
following equations:
tWD_HOLD = 3 × tWD_OUT
(7)
Watchdog Fault Outputs
The WD_FLT pin and WD_FLAG pin are fault output
terminals for the TPS7A63xx-Q1 and TPS7A6401-Q1
devices, respectively. Typically, one pulls these fault
outputs high to a regulated output supply. In the case
of a watchdog fault condition, the TPS7A63xx-Q1
momentarily pulls WD_FLT low for a duration of
tWD_OUT, whereas the TPS746401-Q1 latches the
WD_FLAG high and momentarily pulls nRST low for
tWD = 10–6 × ROSC = 5000 × 1 / fOSC
tWD_OUT = 1 / fOSC
(4)
(5)
(6)
tCW = tOW = 1 / 2 tWD
where,
tWD = width of watchdog window
ROSC = resistor connected at ROSC pin
tWD_OUT = duration of fault output
fOSC = frequency of internal oscillator
tCW = duration of closed window
tOW = duration of open window
a duration of tWD_OUT
.
Watchdog Initialization
On power up and during normal operation, the
watchdog initializes under the conditions shown in
Table 2. The normal operation of the watchdog for
the WD_FLT and WD_FLAG output device options is
shown in Figure 25 and Figure 26, respectively.
As shown in Figure 24, each watchdog window
consists of an open window and a closed window,
each having a width approximately 50% of the
watchdog window. However, there is an exception to
this; the first open window after watchdog initialization
is eight times the duration of the watchdog window.
All open windows except the one after watchdog
initialization are one-half the width of the watchdog
window. On initialization, the watchdog must receive
service (by software, external microcontroller, and so
forth) only during an open window. A watchdog
serviced during a closed window, or not serviced
during a open window, creates a watchdog fault
condition.
Table 2. Conditions for Watchdog Initialization
TPS7A63xx TPS746401
What causes watchdog
to initialize?
-Q1
(FAULT
Option)
-Q1
(FLAG
Option)
Edge
Rising edge of nRST
(when VOUT exceeds
VTH(POR)) while the
watchdog is in the enabled
state, for example, during
soft power up
✓
✓
✓
✓
✓
X
Falling edge of nWD_EN
while the nRST is already
high, for example, when
the microprocessor
enables the watchdog after
the device is powered up
CLOSED
WINDOW
(must not be serviced
to prevent fault)
OPEN
WINDOW
OPEN WINDOW
After watchdog initialization
(must be serviced to prevent fault)
(must be serviced to
prevent fault)
Rising edge of WD_FLT
while the nRST is already
high and the watchdog is in
the enabled state, for
tCW=½ tWD
tOW=½ tWD
8 x tWD
Event causing
watchdog initialization
tWD = 5000 x tWD_OUT
example, right after a
closed window is serviced
Figure 24. Watchdog Window Duration
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Watchdog Operation
tPOR
tPOR
93% of VOUT
93% of VOUT
0
0
0
0
0
0
VOUT
VOUT
0
nRST
nRST
0
tWD_HOLD
tWD_HOLD
nWD_EN
nWD_EN
WD
0
WD
0
WD_FLT
WD_FLAG
WD
Window
Status
WD
Window
Status
OW
OW
NA
NA
CW
OW CW
<½ tWD
CW
OW CW
<½ tWD
WD Initialization
WD Initialization
½ tWD
½ tWD
<8 tWD
<8 tWD
Figure 25. Power Up, Initialization, and Normal
Operation for TPS7A63xx-Q1
Figure 26. Power Up, Initialization, and Normal
Operation for TPS7A6401-Q1
Figure 25 shows watchdog initialization and operation
for the TPS7A63xx-Q1. After output voltage is in
regulation and reset asserts high (clearly the chip-
enable pin is high), the watchdog becomes enabled
when an external signal pulls nWD_EN (the watchdog
enable pin) low. This causes the watchdog to initialize
and wait for a service signal during the first open
window for 8× the duration of tWD. A service signal
applied to the WD pin during the first open window
resets the watchdog counter and a closed window
starts. To prevent a fault condition from occurring,
watchdog service must not occur during the closed
window. Watchdog service must occur during the
following open window to prevent fault condition from
occurring. The fault output (WD_FLT), externally
pulled up to VOUT (typically), stays high as long as
the watchdog receives proper serviced and there is
no fault condition.
Figure 26 shows watchdog initialization and operation
for FLAG output version (TPS7A6401-Q1). The fault
output (WD_FLAG), externally pulled up to VOUT
(typically), stays low as long as the watchdog
receives proper service and there is no fault
condition.
Likewise, enabling the watchdog before powering the
device on (that is, pulling the nWD_EN pin low before
power up), the watchdog initializes as soon as the
output voltage is in regulation and reset asserts high
(see Table
Initialization).
2
for Conditions for Watchdog
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Watchdog Fault Conditions
0
0
0
0
0
0
VOUT
VOUT
0
tWD_OUT
tWD_OUT
nRST
nRST
0
nWD_EN
nWD_EN
WD
0
WD
0
tWD_OUT
tWD_OUT
tWD_OUT
tWD_OUT
WD_FLT
WD_FLAG
OW
OW
OW
WD Initialization
OW
WD Init.
WD
WD
FLT
FLT
FLT
NA
FLT
OW CW
CW
OW
OW CW
CW
OW
Init.
Init.
<½ tWD
½ tWD
½ tWD
<½ tWD
½ tWD
½ tWD
<8 tWD
<8 tWD
Figure 27. Watchdog Service Fault Conditions for
TPS7A63xx-Q1
Figure 28. Watchdog Service Fault Conditions for
TPS7A6401-Q1
For both device options, a watchdog fault condition
occurs in following (non-exhaustive) cases:
As shown in Figure 28, for TPS746401-Q1 the first
watchdog fault registers when watchdog receives
service during a closes window. This causes the
watchdog flag pin (WD_FLAG) to become high and
stay latched. At the same time, nRST pin goes low
temporarily for the duration of tWD_OUT. WD_FLAG
remains high until toggling the nWD_EN pin disables
and re-enables the watchdog or the watchdog
receives service properly (while nWD_EN is low and
nRST is high). The second fault registers when the
watchdog does not receive service during an open
i) When the watchdog receives service during a
closed window
ii) When watchdog does not rexceive serviced during
an open window (this open window could be the one
after watchdog initialization, or the one following a
closed window).
As shown in Figure 27, for TPS7A63xx-Q1 the first
watchdog fault registers when the watchdog receives
service during a closed window. This causes the
watchdog fault pin (WD_FLT) to go low temporarily
for a duration of tWD_OUT. Following the fault, the
watchdog reinitializes. Likewise, the second fault
registers when the watchdog does not receive service
during an open window (following a closed window).
Again, the fault pin (WD_FLT) is asserts low for a
window (following
WD_FLAG is high (i.e. during a fault condition), if the
watchdog stays enabled, and reset is high;
a
closed window). While
a
watchdog service signal can also bring WD_FLAG
low (about 5 µs after the watchdog receives service).
duration of tWD_OUT
.
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tPOR
tPOR
93% of VOUT
tDEGLITCH
93% of VOUT
tDEGLITCH
0
0
0
0
0
VOUT
VOUT
0
tWD_OUT
tWD_OUT
nRST
nRST
0
nWD_EN
nWD_EN
0
WD
WD
0
0
tWD_OUT
tWD_OUT
tWD_OUT
WD_FLT
WD_FLAG
F
L
T
F
L
T
N
A
N
OW
A
OW
WD Initialization
OW
WD Init.
OW
NA
WD Initialization
OW
WD Init.
OW
WD Initialization
OW
WD Init.
OW
WD Initialization
CW
FLT
FLT
WD Init.
<8 tWD
8 tWD
8 tWD
8 tWD
<8 tWD < ½tWD
8 tWD
Figure 29. Watchdog Fault During Initialization,
and Reinitialization During Reset for TPS7A63xx-
Q1
Figure 30. Watchdog Fault During Initialization,
and Reinitialization During Reset for TPS7A6401-
Q1
As shown in Figure 29 for the TPS7A6401-Q1, the
watchdog fault condition also occurs if the watchdog
does not receive service during the open window
after watchdog initialization. That is, if the watchdog
does not receive service during the first 8× tWD_OUT
period after initialization, a fault condition occurs. This
causes the watchdog fault pin (WD_FLT) to go low
temporarily for a duration of tWD_OUT. In case of a load
transient, if the regulated output voltage drops down
causing reset (nRST) to go low, the rising edge on
nRST causes the watchdog to reinitialize (that is,
when reset becomes high with the watchdog still
enabled). During a fault condition (that is, WD_FLT is
low) with the watchdog disabled, the fault output
continues to stay low until tWD_OUT is elapsed. A
falling edge on nWD_EN pin causes the watchdog to
reinitialize while nRST is still high.
As shown in Figure 30 for the TPS7A6401-Q1, the
watchdog fault condition also occurs if the watchdog
does not receive service during the open window
after watchdog initialization. That is, if the watchdog
does not receive service in first 8× tWD_OUT period
after initialization, a fault condition occurs. This
causes the watchdog flag pin (WD_FLAG) to become
high and stay latched. At the same time, the nRST
pin goes low temporarily for a duration of tWD_OUT. In
the case of a load transient, if the regulated output
voltage drops down causing the reset output to go
low, the WD_FLAG asserts low, and the rising edge
on nRST causes the watchdog to reinitialize (while
the watchdog remains enabled). During a fault
condition (that is, WD_FLAG is high), and with a
disabled watchdog, the flag output continues to stay
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high as long as the watchdog remains enabled or
receives proper service. However, nRST stays low
until tWD_OUT elapses. Re-enabling the watchdog
causes watchdog to reinitialize (while nRST is still
high).
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APPLICATION INFORMATION
Typical application circuits for TPS7A6401-Q1 and
TPS76333-Q1/6350-Q1 are shown in Figure 31 and
Figure 32. Depending on the end application, one
may use different values of external components.
Carefully select feedback resistors (R1 and R2), used
to program the output voltage. Using smaller resistors
results in higher current consumption, whereas using
very large resistors impacts the sensitivity of the
regulator. Therefore, TI recommends selecting
feedback resistors such that the sum of R1 and R2 is
between 20 kΩ and 200 kΩ.
Power Dissipation and Thermal
Considerations
Calculated the power dissipated in the device using
Equation 8.
PD = IOUT × (VIN – VOUT)) + IQUIESCENT × VIN
(8)
where,
PD = continuous power dissipation
IOUT = output current
VIN = input voltage
Example
VOUT = output voltage
IQUIESCENT = quiescent current
If the desired regulated output voltage is 5 V, after
selecting R2 then one can calculate R1 using (or vice
versa) Equation 2. Knowing VREF = 1.23 V (typical),
VOUT = 5 V, selecting R2 = 20 kΩ, the calculated
value of R1 is 61.3 kΩ.
As IQUIESCENT << IOUT, therefore, ignore the term
IQUIESCENT × VIN in Equation 8.
For a device in operation at a given ambient air
temperature (TA), calculate the junction temperature
(TJ) using Equation 9.
During fast load steps, an application may require a
larger output capacitor to prevent the output from
temporarily dropping down. TI recommends a low-
ESR ceramic capacitor with dielectric of type X5R or
X7R. One can also connect a bypass capacitor at the
output to decouple high-frequency noise as per the
end application.
TJ = TA + (θJA × PD)
(9)
where,
θJA = junction-to-ambient-air thermal impedance
Calculate the rise in junction temperature due to
power dissipation using Equation 10.
ΔT = TJ – TA = (θJA × PD)
TPS7A6333-Q1/
TPS7A6350-Q1
(10)
VIN
VOUT
VOUT
0.1μF
VIN
1μF
to
10μF
10μF
to
22μF
0.1μF
For a given maximum junction temperature (TJ-Max),
calculate the maximum ambient air temperature (TA-
at which the device can operate using
Equation 11.
1kΩ
to
5kΩ
RDELAY
ROSC
)
Max
100pF
to 100nF
RESET
nRST
10kΩ
to
200kΩ
TA-Max = TJ-Max – (θJA × PD)
(11)
1kΩ
to
5kΩ
WD_FLT/
WD_FLG
FAULT/
FLAG
GND
Example
EN nWD_EN WD
If IOUT = 100 mA, VOUT = 5 V, VIN = 14 V, IQUIESCENT
=
250 µA, and θJA= 50°C/W, the continuous power
dissipated in the device is 0.9 W. The rise in junction
temperature due to power dissipation is 45°C. For a
maximum junction temperature of 150°C, the
maximum ambient air temperature at which the
device can operate is 105°C.
Figure 31. Typical Application Schematic,
TPS7A6333-Q1/6350-Q1
TPS7A6401-Q1
VIN
VOUT
VOUT
0.1μF
VIN
10μF
to
22μF
1μF
to
10μF
0.1μF
R1
R2
1kΩ
to
5kΩ
FB
RDELAY
ROSC
100pF
to 100nF
10kΩ
to
200kΩ
RESET
nRST
1kΩ
to
5kΩ
GND
WD_FLT/
WD_FLG
FAULT/
FLAG
EN nWD_EN WD
Figure 32. Typical Application Schematic
TPS7A6401-Q1
20
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Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS7A6301-Q1 TPS7A6333-Q1 TPS7A6350-Q1 TPS7A6401-Q1
TPS7A6301-Q1, TPS7A6333-Q1
TPS7A6350-Q1, TPS7A6401-Q1
www.ti.com
SLVSAB1D –JUNE 2011–REVISED JULY 2012
For adequate heat dissipation, TI recommends
soldering the thermal pad (exposed heat sink) to the
thermal land pad on the PCB. Doing this provides a
heat conduction path from the die to the PCB and
reduces overall package thermal resistance. Power
derating curves for the TPS7A63xx-Q1/6401-Q1
PWP package and TPS7A6333-Q1 DRK are
comparable; see Figure 33.
For optimum thermal performance, TI recommends
using a high-K PCB with thermal vias between the
ground plane and solder pad or thermal land pad; see
Figure 34 (a) and (b). Further, use a thicker ground
plane and a thermal land pad with a larger surface
area to inprove considerably the heat-spreading
capabilities of a PCB. For a two-layer PCB, a bat
wing layout can enhance the heat-spreading
capabilities.
2.5
2
Thermal Via
Thermal Land Pad
PCB
1.5
1
Dedicated
Ground Plane
(a) Multilayer PCB with a dedicated ground plane
0.5
0
Thermal Via
0
25
50
75
100
125
150
Thermal Land Pad
PCB
Junction Temperature (°C)
Bat Wings
Figure 33. Power Derating Curve
Ground Plane
(b) Dual layer PCB with Bat wings for enhanced heat spreading
Figure 34. Using Multilayer PCB and Thermal
Vias for Adequate Heat Dissipation
Keeping other factors constant, surface area of the
thermal land pad contributes to heat dissipation only
to a certain extent.
Copyright © 2011–2012, Texas Instruments Incorporated
Submit Documentation Feedback
21
Product Folder Link(s): TPS7A6301-Q1 TPS7A6333-Q1 TPS7A6350-Q1 TPS7A6401-Q1
TPS7A6301-Q1, TPS7A6333-Q1
TPS7A6350-Q1, TPS7A6401-Q1
SLVSAB1D –JUNE 2011–REVISED JULY 2012
www.ti.com
REVISION HISTORY
Changes from Original (June 2011) to Revision A
Page
•
•
•
Deleted the Ordering Information Table ............................................................................................................................... 2
Changed values for VIL and VIH in the Watchdog Enable Input (nWD_EN pin) section ....................................................... 4
Changed values for VIL and VIH in the Watchdog Input Pulse (WD pin) section .................................................................. 4
Changes from Revision A (August 2011) to Revision B
Page
•
Deleted devices TPS7A64333-Q1 and TPSA6450-Q1 ........................................................................................................ 1
Changes from Revision B (December 2011) to Revision C
Page
•
Changed regulated output voltage (6.1), added text to the test conditions (10mA to 200mA, VIN = VOUT + 1V to 16V) ...... 3
Changes from Revision C (April 2012) to Revision D
Page
•
•
•
•
•
Added new bullets at top of Features list ............................................................................................................................. 1
Corrected part number in numerous locations throughout the data sheet ........................................................................... 1
Deleted the NO. column from the electrical tables ............................................................................................................... 2
............................................................................................................................................................................................... 9
Deleted two Typical Characteristics graphs .......................................................................................................................... 9
22
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Product Folder Link(s): TPS7A6301-Q1 TPS7A6333-Q1 TPS7A6350-Q1 TPS7A6401-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
26-Jun-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TPS7A6301QPWPRQ1
TPS7A6333QDRKRQ1
TPS7A6333QPWPRQ1
TPS7A6350QPWPRQ1
TPS7A6401QPWPRQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
HTSSOP
VSON
PWP
DRK
PWP
PWP
PWP
14
10
14
14
14
2000
3000
2000
2000
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
HTSSOP
HTSSOP
HTSSOP
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
26-Jun-2012
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS7A6301QPWPRQ1 HTSSOP PWP
TPS7A6333QDRKRQ1 VSON DRK
14
10
14
14
14
2000
3000
2000
2000
2000
330.0
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
12.4
6.9
3.3
6.9
6.9
6.9
5.6
4.3
5.6
5.6
5.6
1.6
1.1
1.6
1.6
1.6
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
Q1
Q2
Q1
Q1
Q1
TPS7A6333QPWPRQ1 HTSSOP PWP
TPS7A6350QPWPRQ1 HTSSOP PWP
TPS7A6401QPWPRQ1 HTSSOP PWP
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS7A6301QPWPRQ1
TPS7A6333QDRKRQ1
TPS7A6333QPWPRQ1
TPS7A6350QPWPRQ1
TPS7A6401QPWPRQ1
HTSSOP
VSON
PWP
DRK
PWP
PWP
PWP
14
10
14
14
14
2000
3000
2000
2000
2000
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
35.0
35.0
35.0
35.0
35.0
HTSSOP
HTSSOP
HTSSOP
Pack Materials-Page 2
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