TPS7A6550QKVURQ1 [TI]
300-mA 40-V LOW-DROPOUT REGULATOR WITH 25-μA QUIESCENT CURRENT; 300 - mA的40 -V低压降了25 μA静态电流稳压器
| 型号： | TPS7A6550QKVURQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 300-mA 40-V LOW-DROPOUT REGULATOR WITH 25-μA QUIESCENT CURRENT |
| 文件： | 总18页 (文件大小：813K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS7A6533-Q1
TPS7A6550-Q1
www.ti.com
SLVSA98C –MAY 2010–REVISED JULY 2012
300-mA 40-V LOW-DROPOUT REGULATOR WITH 25-µA QUIESCENT CURRENT
Check for Samples: TPS7A6533-Q1, TPS7A6550-Q1
1
FEATURES
DESCRIPTION
The TPS7A65xx-Q1 is a family of low-dropout linear
voltage regulators designed for low power
consumption and quiescent current less than 25 µA in
light-load applications. These devices feature
integrated overcurrent protection and a design to
achieve stable operation even with low-ESR ceramic
output capacitors. A low-voltage tracking feature
allows for a smaller input capacitor and can possibly
eliminate the need of using a boost converter during
cold crank conditions. Because of these features,
these devices are well-suited in power supplies for
various automotive applications.
•
Low Dropout Voltage
300 mV at IOUT = 150 mA
–
•
4-V to 40-V Wide Input Voltage Range
With up to 45-V Transients
•
•
300-mA Maximum Output Current
25-µA (Typ) Ultralow Quiescent Current at
Light Loads
•
3.3-V and 5-V Fixed Output Voltage With ±2%
Tolerance
•
•
Low-ESR Ceramic Output Stability Capacitor
Integrated Fault Protection
TYPICAL REGULATOR STABILITY
–
–
Short-Circuit and Overcurrent Protection
Thermal Shutdown
10
VIN = 14V
COUT = 10µF, 47µF
TA = 27°C
•
•
Low Input-Voltage Tracking
VOUT = 5V, 3.3V
Thermally Enhanced Power Package
1
–
3-Pin TO-252 (KVU /DPAK)
Stable Operation
Over Entire Region
APPLICATIONS
•
•
•
•
Qualified for Automotive Applications
Infotainment Systems With Sleep Mode
Body Control Modules
0.1
Always-On Battery Applications
0.01
0.01
0.1
1
10
100 300
–
–
–
Gateway Applications
Remote Keyless Entry Systems
Immobilizers
IOUT (mA)
Figure 1. ESR versus Load Current for
TPS7A6550-Q1
TYPICAL APPLICATION SCHEMATIC
TPS7A65xx
VIN
CIN
VIN
VOUT
VOUT
COUT
GND
Figure 2. Application Schematic
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2012, Texas Instruments Incorporated
TPS7A6533-Q1
TPS7A6550-Q1
SLVSA98C –MAY 2010–REVISED JULY 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION(1)
OUTPUT VOLTAGE
PACKAGE
TOP-SIDE MARKING
ORDERABLE PART NUMBER
TPS7A6550QKVUQ1
Tube of 70
7A6550Q1
5 V
3-pin KVU
3-pin KVU
Reel of 2500
Reel of 2500
7A6550Q1
TPS7A6550QKVURQ1
TPS7A6533QKVURQ1
3.3 V
7A6533Q1
(1) For the most-current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
NO.
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
DESCRIPTION
VALUE
UNIT
V
VIN
Unregulated input(2)(3)
Regulated output
45
VOUT
θJP
7
1.2
V
Thermal impedance junction to exposed pad KVU (DPAK) package
Thermal impedance junction to ambient KVU (DPAK) package(4)
Thermal impedance junction to ambient KVU (DPAK) package(5)
Electrostatic discharge(6)
°C/W
°C/W
°C/W
kV
θJA
29.3
38.6
2
θJA
ESD
TA
Operating ambient temperature
125
°C
Tstg
Storage temperature range
–65 to 150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to GND.
(2) Absolute negative voltage on these pins not to go below –0.3 V.
(3) Absolute maximum voltage for duration less than 480 ms.
(4) The thermal data is based on JEDEC standard high-K profile – JESD 51-5. The copper pad is soldered to the thermal land pattern. Also
correct attachment procedure must be incorporated.
(5) The thermal data is based on JEDEC standard low-K profile – JESD 51-3. The copper pad is soldered to the thermal land pattern. Also
correct attachment procedure must be incorporated.
(6) The human-body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin.
DISSIPATION RATINGS
DERATING FACTOR
ABOVE TA = 25°C
(°C/W)
TA < 25°C POWER
RATING (W)
TA = 85°C POWER
RATING (W)
NO.
JEDEC STANDARD
PACKAGE
JEDEC Standard PCB -
low K, JESD 51-3
2.1
2.2
3 pin KVU
3 pin KVU
3.24
4.27
38.6
29.3
1.68
2.22
JEDEC Standard PCB -
high K, JESD 51-5
RECOMMENDED OPERATING CONDITIONS
NO.
3.1
3.2
DESCRIPTION
MIN
4
MAX UNIT
VIN
TJ
Unregulated input voltage
40
V
Operating junction temperature range
–40
150
°C
2
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SLVSA98C –MAY 2010–REVISED JULY 2012
ELECTRICAL CHARACTERISTICS
VIN = 14V, TJ = –40ºC to 150ºC (unless otherwise noted)
NO.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
4. Input Voltage (VIN pin)
Fixed 5-V output, IOUT = 1 mA
5.3
3.6
40
V
4.1
VIN
Input voltage
Fixed 3.3-V output, IOUT = 1 mA
40
4.2
4.3
4.4
IQUIESCENT
VIN-UVLO
Quiescent current
VIN = 8.2 V to 18 V, IOUT = 0.01 mA to 0.75 mA
25
3.16
3.45
40
µA
V
Undervoltage lockout
voltage
Ramp VIN down until output is turned OFF
Ramp VIN up until output is turned ON
VIN(POWERUP) Power-up voltage
V
5. Regulated Output Voltage (VOUT pin)
Fixed VOUT value (3.3 V or 5 V as applicable),
IOUT = 10 mA, 10 mA to 300 mA,
VIN = VOUT + 1 V to 16 V
5.1
VOUT
Regulated output voltage
Line regulation
–2%
2%
VIN = 6 V to 28 V, IOUT = 10 mA, VOUT = 5 V
VIN = 6 V to 28 V, IOUT = 10 mA, VOUT = 3.3 V
IOUT = 10 mA to 300 mA, VIN= 14 V, VOUT = 5 V
IOUT = 10 mA to 300 mA,VIN = 14 V, VOUT = 3.3 V
IOUT = 250 mA
15
20
mV
mV
mV
mV
mV
mV
Ω
5.2
5.3
5.4
∆VLINE-REG
25
∆VLOAD-REG
Load regulation
Dropout voltage
35
500
300
2
(1)
VDROPOUT
(VIN – VOUT
)
IOUT = 150 mA
(2)
5.5
5.6
5.7
RSW
Switch resistance
Output current
VIN to VOUT resistance
IOUT
ICL
VOUT in regulation
0
300
1000
mA
mA
Output current limit
VOUT = 0 V (VOUT pin is shorted to ground)
350
VIN-RIPPLE = 0.5 Vpp, IOUT = 300 mA,
frequency = 100 Hz, VOUT = 5 V, and
VOUT = 3.3 V
60
30
Power-supply ripple
rejection
5.8
PSRR(2)
dB
VIN-RIPPLE = 0.5 Vpp, IOUT = 300 mA,
frequency = 150 kHz, VOUT = 5 V, and
VOUT = 3.3 V
6. Operating Temperature Range
Operating junction
temperature
6.1
6.2
6.3
TJ
-40
150
ºC
ºC
ºC
Thermal shutdown trip
point
TSHUTDOWN
THYST
165
10
Thermal shutdown
hysteresis
(1) This test is done with VOUT in regulation and VIN – VOUT parameter is measured when VOUT (3.3 V or 5 V) drops by 100 mV at specified
loads.
(2) Specified by design – not tested
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DEVICE INFORMATION
KVU PACKAGE
(TOP VIEW)
3
1
2
GND
VIN
VOUT
TERMINAL FUNCTIONS
NO.
1
NAME
VIN
TYPE
DESCRIPTION
Input voltage pin: The unregulated input voltage is supplied to this pin. A bypass capacitor is connected
between VIN pin and GND pin to dampen input line transients.
I
2
GND
I/O
Ground pin: This is signal ground pin of the IC.
Regulated output voltage pin: This is a regulated voltage output (VOUT = 3.3 V or 5 V, as applicable) pin
with a limitation on maximum output current. In order to achieve stable operation and prevent oscillation,
an external output capacitor (COUT) with low ESR is connected between this pin and the GND pin.
3
VOUT
O
FUNCTIONAL BLOCK DIAGRAM
VRef1
Temperature Sensor/
Thermal Shutdown
Band Gap
Q1
UVLO
Comp. with
VRef1
VIN
Error
Amp
Regulator
Control
Internal
Reference
VIN
CIN
Logic
Control
VOUT
VOUT
COUT
Over Current Detection
Oscillator
Charge
Pump
GND
Figure 3. TPS7A65xx-Q1 Functional Block Diagram
4
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SLVSA98C –MAY 2010–REVISED JULY 2012
TYPICAL CHARACTERISTICS
ESR
vs
ESR
vs
LOAD CURRENT
LOAD CURRENT
10
10
VIN = 14V
VIN = 14V
COUT = 1µF
TA = 27°C
VOUT = 5V
COUT = 1µF
TA = 27°C
VOUT = 3.3V
1
1
Stable Operation
Stable Operation
0.1
0.06
0.03
0.1
Unstable
Operation
0.06
Unstable
Operation
0.03
0.01
0.01
0.01
0.01
0.1
1
10
30
100 300
0.1
1
IOUT (mA)
10
30
100 300
IOUT (mA)
QUIESCENT CURRENT
vs
QUIESCENT CURRENT
vs
LOAD CURRENT
AMBIENT AIR TEMPERATURE
VIN =14V
VOUT=5V, 3.3V
55
50
45
40
35
30
25
20
15
80
70
60
50
40
30
20
10
VIN = 14V
TA= 25°C
VOUT = 5V, 3.3V
IOUT = 250mA
IOUT = 1mA
0
0.001
-50
0
50
100
150
0.01
0.1
1
10
100
1000
TA (°C)
IOUT (mA)
(1)
QUIESCENT CURRENT
vs
DROPOUT VOLTAGE
vs
INPUT VOLTAGE
LOAD CURRENT
0.4
0.35
0.3
700
600
500
400
300
200
100
VOUT = 5V
VOUT = 5V, 3.3V
TA= 25°C
TA = 125°C
TA = 25°C
0.25
0.2
TA = -40°C
0.15
0.1
IOUT = 100mA
No Load
0.05
0
0
4
14
24
VIN (V)
34
40
0
50
100
150
IOUT (mA)
200
250
300
(1) Dropout voltage is measured when the output voltage drops by 100mV from the regulated output voltage level. (For example, the drop
out voltage for TPS7A6550 is measured when the output voltage drops down to 4.9V from 5V.)
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TYPICAL CHARACTERISTICS (continued)
OUTPUT VOLTAGE
OUTPUT VOLTAGE
vs
vs
AMBIENT AIR TEMPERATURE
INPUT VOLTAGE
5.1
5.08
5.06
5.04
5.02
5
6
5
4
3
2
1
0
IOUT = 100mA
TA = 25°C
VIN = 14V
IOUT = 1mA
4.98
4.96
4.94
4.92
4.9
-50
0
50
100
150
2
3
4
5
6
7
TA (°C)
VIN (V)
OUTPUT CURRENT
vs
OUTPUT CURRENT LIMIT
vs
INPUT VOLTAGE
AMBIENT AIR TEMPERATURE
0.12
0.1
750
700
650
600
550
500
450
VIN = 14V
VOUT = 5V, 3.3V
ILOAD = 100mA
VOUT = 5V, 3.3V
0.08
0.06
0.04
0.02
0
TA= 125°C
TA= 25°C
TA = -40°C
0
10
20
30
40
50
-50
0
50
TA (°C)
100
150
VIN (V)
LOAD REGULATION
vs
LINE REGULATION
vs
AMBIENT AIR TEMPERATURE
AMBIENT AIR TEMPERATURE
12
11.5
11
3
VIN = 14V
IOUT = 10mA
VOUT = 5V, 3.3V
VIN
VOUT = 5V, 3.3V
IOUT step from
10mA to 300mA
2.5
step from
8V to 28V
2
1.5
1
10.5
10
9.5
9
0.5
8.5
8
-50
0
-50
0
50
100
150
0
50
100
150
TA (°C)
TA (°C)
6
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SLVSA98C –MAY 2010–REVISED JULY 2012
TYPICAL CHARACTERISTICS (continued)
PSRR AT HEAVY LOAD CURRENT
PSRR AT LIGHT LOAD CURRENT
120
100
80
120
100
80
60
40
20
0
VIN = 14V
IOUT = 250mA
TA = 25°C
COUT = 10µF
VOUT = 5V, 3.3V
VIN = 14V
IOUT = 1mA
TA = 25°C
COUT = 10µF
VOUT = 5V, 3.3V
60
40
20
0
10
100
1k
10k
Frequency (Hz)
100k
1M
10
100
1k
10k
Frequency (Hz)
100k
1M
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DETAILED DESCRIPTION
voltages. The charge-pump switching thresholds are
hysteretic. Figure 5 and Figure 6 show typical
switching thresholds for the charge pump at light (IOUT
TPS7A65xx-Q1 is a family of monolithic low-dropout
linear voltage regulators designed for low power
consumption and quiescent current less than 25 µA in
light-load applications. Because of an integrated fault
protection, these devices are well-suited in power
supplies for various automotive applications.
<
approximately
approximately 2 mA) loads, respectively.
2
mA) and heavy (IOUT
>
These devices are available in two fixed-output-
voltage versions as follows:
ON
•
•
5-V output version (TPS7A6550-Q1)
3.3-V output version (TPS7A6533-Q1)
Hysteresis
The following section describes the features of
TPS7A65xx-Q1 voltage regulators in detail.
OFF
7.8
7.9
Power Up
VIN (V)
During power up, the regulator incorporates
protection scheme to limit the current through the
pass element and output capacitor. When the input
a
Figure 5. Charge-Pump Operation at Light Loads
voltage exceeds a certain threshold (VIN(POWERUP)
)
level, the output voltage begins to ramp up; see
Figure 4.
ON
VIN
Hysteresis
OFF
VIN(POWERUP)
9.2
9.6
VIN (V)
0
VOUT
Figure 6. Charge-Pump Operation at Heavy
Loads
5V or 3.3V
Low-Power Mode
0
At light loads and high input voltages (VIN
>
approximately 8 V such that charge pump is off) the
device operates in the low-power mode and the
quiescent current consumption decreases to 25 µA
(typical) as shown in Table 1.
Figure 4. Power-Up Sequence
Charge-Pump Operation
Table 1. Typical Quiescent Current Consumption
IOUT
Charge Pump ON
Charge Pump OFF
These devices have an internal charge pump which
turns on or off depending on the input voltage and the
output current. The charge pump switching circuitry
does not cause conducted emissions to exceed
required thresholds on the input voltage line. For a
given output current, the charge pump stays on at
lower input voltages and turns off at higher input
IOUT
approximately 2
mA
<
25 µA
(low-power mode)
250 µA
(light load)
IOUT
>
approximately 2
mA
(heavy load)
280 µA
70 µA
8
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Undervoltage Shutdown
Integrated Fault Protection
These devices have an integrated undervoltage
lockout (UVLO) circuit to shut down the output if the
input voltage (VIN) falls below an internally fixed
UVLO threshold level (VIN-UVLO) as shown in Figure 7.
This ensures that the regulator does not latch into an
unknown state during low input-voltage conditions.
The regulator normally powers up when the input
voltage exceeds the VIN(POWERUP) threshold.
These devices feature integrated fault protection to
make them ideal for use in automotive applications.
In order to keep them in a safe area of operation
during certain fault conditions, they use internal
current-limit protection and current-limit foldback to
limit the maximum output current. This protects them
from excessive power dissipation. For example,
during a short-circuit condition on the output; limiting
current through the pass element to ICL protects the
device from excessive power dissipation.
Low-Voltage Tracking
At low input voltages, the regulator drops out of
regulation, and the output voltage tracks input minus
a voltage based on the load current (IOUT) and switch
resistance (RSW) as shown in Figure 7. This allows for
a smaller input capacitor and can possibly eliminate
the need of using a boost convertor during cold crank
conditions.
Thermal Shutdown
These devices incorporate a thermal shutdown (TSD)
circuit as
continuous
a
protection from overheating. For
normal operation, the junction
temperature should not exceed the TSD trip point. If
the junction temperature exceeds the TSD trip point,
the output turns off. When the junction temperature
falls below the TSD trip point, the output turns on
again. Figure 8 shows this.
VIN-UVLO
VIN
0
5V or 3.3V
VOUT
0
Tracking
Figure 7. Undervoltage Shutdown and Low-
Voltage Tracking
Figure 8. Thermal Cycling Waveform for
TPS7A6550-Q1 (VIN = 24 V, IOUT = 300 mA, VOUT = 5
V)
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APPLICATION INFORMATION
A typical application circuit for TPS7A65xx-Q1 is
Figure 9. Depending on the end application, one may
use different values of external components. An
application may require a larger output capacitor
during fast load steps to prevent the output from
temporarily dropping down. TI recommends a low-
ESR ceramic capacitor with dielectric of type X5R or
X7R. The user can additionally connect a bypass
capacitor at the output to decouple high-frequency
noise as per the end application.
For a given maximum junction temperature (TJ-Max),
calculate the maximum ambient air temperature (TA-
)
Max
at which the device can operate using
Equation 4.
TA-Max = TJ-Max – (θJA × PD)
(4)
Example
If IOUT = 100 mA, VOUT = 5 V, VIN = 14 V, IQUIESCENT
=
250 µA and θJA= 30˚C/W, the continuous power
dissipated in the device is 0.9 W. The rise in junction
temperature due to power dissipation is 27˚C. For a
maximum junction temperature of 150˚C, maximum
ambient air temperature at which the device can
operate is 123˚C.
TPS7A65xx
VIN
0.1µF
VOUT
0.1µF
VIN
VOUT
1µF
to
10µF
10µF
to
22µF
For adequate heat dissipation, TI recommends
soldering the power pad (exposed heat sink) to the
thermal land pad on the PCB. Doing this provides a
heat conduction path from the die to the PCB and
reduces overall package thermal resistance.
Figure 10 shows power derating curves for the
TPS7A65xx-Q1 family of devices in the KVU (DPAK)
package.
GND
Figure 9. Typical Application Schematic
4
3.5
3
Power Dissipation and Thermal
Considerations
Calculate the power dissipated in the device using
Equation 1.
JESD 51-5 (KVU)
2.5
JESD 51-3 (KVU)
2
PD = IOUT × (VIN - VOUT)) + IQUIESCENT × VIN
(1)
where,
1.5
1
PD = continuous power dissipation
IOUT = output current
VIN = input voltage
VOUT = output voltage
IQUIESCENT = quiescent current
0.5
0
0
25
50
75
100
125
150
Ambient Air Temperature (°C)
IQUIESCENT << IOUT
IQUIESCENT × VIN in Equation 1.
; therefore, ignore the term
Figure 10. Power Derating Curves
For a device under operation at a given ambient air
temperature (TA), calculate the junction temperature
(TJ) using Equation 2.
For optimum thermal performance, TI recommends
using a high-K PCB with thermal vias between the
ground plane and solder pad or thermal land pad.
Figure 11 (a) and (b) show this. Further, a design can
improve the heat-spreading capabilities of a PCB
considerably by using a thicker ground plane and a
thermal land pad with a larger surface area.
TJ = TA + (θJA × PD)
(2)
where,
θJA = junction-to-ambient air thermal impedance
Calculate the rise in junction temperature due to
power dissipation using Equation 3.
ΔT = TJ – TA = (θJA × PD)
(3)
10
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Keeping other factors constant, the surface area of
the thermal land pad contributes to heat dissipation
only to a certain extent. Figure 12 shows the variation
of θJA with surface area of the thermal land pad
(soldered to the exposed pad) for the KVU package.
Exposed Tab
55
Thermal Via
Thermal Land Pad
50
PCB
Ground Plane
45
KVU (DPAK) (JESD 51-3)
(a) Before soldering
40
35
30
(b) After soldering
0
200
400
600
800
1000
Thermal Pad Area (sq. mm)
Figure 11. Using a Multilayer PCB and Thermal
Vias For Adequate Heat Dissipation
Figure 12. θJA versus Thermal Pad Area
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Product Folder Link(s): TPS7A6533-Q1 TPS7A6550-Q1
TPS7A6533-Q1
TPS7A6550-Q1
SLVSA98C –MAY 2010–REVISED JULY 2012
www.ti.com
REVISION HISTORY
Changes from Original (May 2010) to Revision A
Page
•
Removed all KKT information. .............................................................................................................................................. 2
Changes from Revision A (November 2011) to Revision B
Page
•
Changed the θJP value in the Abs Max Table From: 12.7 To: 1.2°C/W ............................................................................... 2
Changes from Revision B (November 2011) to Revision C
Page
•
•
Deleted the TPS7A6533-Q1 device ...................................................................................................................................... 1
Changed the Regulated Output Voltage (5.1). Added to Test Conditions "10mA to 300mA, VIN = VOUT + 1V to 16V" ....... 3
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Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS7A6533-Q1 TPS7A6550-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
16-May-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TPS7A6533QKVURQ1
TPS7A6550QKVURQ1
ACTIVE
ACTIVE
PFM
PFM
KVU
KVU
3
3
2500
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
Level-3-260C-168 HR
Green (RoHS
& no Sb/Br)
CU SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS7A6533QKVURQ1
TPS7A6550QKVURQ1
PFM
PFM
KVU
KVU
3
3
2500
2500
330.0
330.0
16.4
16.4
6.9
6.9
10.5
10.5
2.7
2.7
8.0
8.0
16.0
16.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS7A6533QKVURQ1
TPS7A6550QKVURQ1
PFM
PFM
KVU
KVU
3
3
2500
2500
340.0
340.0
340.0
340.0
38.0
38.0
Pack Materials-Page 2
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