TPS7A6633QDGNRQ1 [TI]
High-Voltage Ultralow-Iq Low-Dropout Regulator; 高电压超低Iq的低压差稳压器
| 型号： | TPS7A6633QDGNRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High-Voltage Ultralow-Iq Low-Dropout Regulator |
| 文件： | 总26页 (文件大小：7427K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS7A6601-Q1, TPS7A6633-Q1
TPS7A6650-Q1, TPS7A6933-Q1
TPS7A6950-Q1
www.ti.com
SLVSBL0B –DECEMBER 2012–REVISED AUGUST 2013
High-Voltage Ultralow-Iq Low-Dropout Regulator
Check for Samples: TPS7A6601-Q1, TPS7A6633-Q1, TPS7A6650-Q1, TPS7A6933-Q1, TPS7A6950-Q1
1
FEATURES
•
•
Low Input Voltage Tracking
Integrated Power-On Reset
•
•
Qualified for Automotive Applications
–
–
Programmable Reset-Pulse Delay
Open-Drain Reset Output
AEC-Q100 Qualified With the Following
Results
–
Device Temperature Grade 1: –40°C to
125°C Ambient Operating Temperature
Range
•
Integrated Fault Protection
–
–
Thermal Shutdown
Short-Circuit Protection
–
–
Device HBM ESD Classification Level H2
Device CDM ESD Classification Level C3B
•
•
Input Voltage Sense Comparator
(TPS7A69xx-Q1 Only)
•
4-V to 40-V Wide Vin Input Voltage Range With
up to 45-V Transient
Packages
–
–
8-Pin SOIC-D for TPS7A69xxQ1
•
•
Output Current 150 mA
8-Pin MSOP-DGN for TPS7A66xx-Q1
Low Quiescent Current Iq:
–
–
2 µA when EN = Low (Shutdown Mode)
12 µA Typical at Light Loads
APPLICATIONS
•
•
•
•
Qualified for Automotive Applications
Infotainment Systems With Sleep Mode
Body Control Modules
•
•
•
Low ESR Ceramic Output Stability Capacitor
(2.2 µF–100 µF)
300-mV Dropout Voltage at 150 mA
(Typical, VIN = 4 V)
Always-On Battery Applications
–
–
–
Gateway Applications
Remote Keyless Entry Systems
Immobilizers
Fixed (3.3-V and 5-V) and Adjustable
(1.5-V to 5-V) Output Voltages
(Adjustable for TPS7A66xx-Q1 Only)
DESCRIPTION
The TPS7A66xx and TPS7A69xx are low-dropout linear regulators designed for up to 40-V Vin operations. With
only 12-µA quiescent current at no load, they are quite suitable for standby micro control unit systems, especially
in automotive applications.
The devices feature integrated short-circuit and overcurrent protection. The devices implement reset delay on
power up to indicate the output voltage is stable and in regulation. One can program the delay with an external
capacitor. A low-voltage tracking feature allows for a smaller input capacitor and can possibly eliminate the need
of using a boost converter during cold-crank conditions.
The devices operate in the –40°C to 125°C temperature range. These features suit the devices well for power
supplies in various automotive applications.
TYPICAL APPLICATION SCHEMATIC
TPS7A66xx-Q1
TPS7A69xx-Q1
Vbat
Vbat
Vreg
Vreg
Vout
PG
8
6
1
Vin
Vout
8
7
6
1
2
Vin
SO
EN
PG
2
4
SI
4
CT
GND
5
CT
GND
5
Figure 1. Hardware-Enable Option
Figure 2. Input-Voltage-Sensing Option
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2013, Texas Instruments Incorporated
TPS7A6601-Q1, TPS7A6633-Q1
TPS7A6650-Q1, TPS7A6933-Q1
TPS7A6950-Q1
SLVSBL0B –DECEMBER 2012–REVISED AUGUST 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
MAX
UNITS
Vin, EN
Vout
SI
Unregulated input(2) (3)(4)
Regulated output
45
V
V
7
Vin
(2) (3)
See
V
CT
25
V
FB, SO, PG
ESD
TJ
Vout
V
Electrostatic Discharge(5)
4
kV
°C
°C
Operating ambient temperature range
Storage temperature range
–40 to 150
–65 to 150
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to GND
(3) Absolute negative voltage on these pins not to go below –0.3 V
(4) Absolute maximum voltage, withstand 45 V for 200 ms
(5) The human-body model is a 107-pF capacitor discharged through a 1.5-kΩ resistor into each pin.
THERMAL INFORMATION
TPS7A66xx-Q1
TPS7A69xx-Q1
THERMAL METRIC(1)
UNITS
MSOP (8 PINS)
SOIC (8 PINS)
113.2
59.6
θJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance(2)
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
63.4
53.0
37.4
3.7
θJCtop
θJB
23.4
°C/W
ψJT
12.8
ψJB
37.1
13.5
52.9
θJCbot
NA
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
spacer
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
4
MAX UNITS
Vin
Unregulated input
40
40
V
V
EN, SI
CT
0
0
20
V
Vout
1.5
0
5.5
5.5
150
V
PG, SO, FB
TJ
Low voltage (I/O)
V
Operating junction temperature range
–40
°C
2
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TPS7A6650-Q1, TPS7A6933-Q1
TPS7A6950-Q1
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SLVSBL0B –DECEMBER 2012–REVISED AUGUST 2013
ELECTRICAL CHARACTERISTICS
Vin = 14 V, 1 mΩ < ESR < 2 Ω, TJ = –40°C to 150°C (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SUPPLY VOLTAGE AND CURRENT(Vin)
Vin
Input voltage
Fixed 5-V output, IOUT = 1 mA
5.5
4
40
40
20
4
V
V
Fixed 3.3-V output, IOUT = 1 mA
VIN = 5.5 V to 40 V, EN = ON, IOUT = 0.2 mA
No load current and EN = OFF
EN = 40 V
Iquiescent
ISleep
Quiescent current
Input sleep current
EN pin current
12
µA
µA
µA
V
IEN
1.0
2%
2.6
Vbg
Band gap
Reference voltage for FB
–2% 1.223
1
VinUVLO
UVLOHys
Undervoltage detection
Ramp Vin down until output turns OFF
V
V
ENABLE INPUT (EN)
VIL
VIH
Logic input low level
Logic input high level
0
0.4
V
V
1.7
REGULATED OUTPUT (Vout)
IOUT = 1 mA, TJ = 25°C
–1%
–2%
1%
2%
5
Vout
Regulated output
VIN = 6 V to 40 V, IOUT = 1 mA to 150 mA(1)
VIN = 5.5 V to 40 V, ∆VOUT, Iout = 50 mA
IOUT = 1 mA to 150 mA, ∆VOUT
VIN – VOUT, IOUT = 80 mA
Vline-reg
Vload-reg
Line regulation
Load regulation
mV
mV
20
180
300
240
450
58
VIN – VOUT, IOUT = 150 mA
VIN = 3 V, VIN – VOUT, IOUT = 5 mA
VIN = 3 V, VIN – VOUT, IOUT = 30 mA
VOUT in regulation
Vdropout
Dropout voltage
mV
12
44
0
27.5
80
145
150
800
Iout
Output current
mA
mA
Ilreg-CL
Output current limit
VOUT short to ground
500
VIN = 12 V, ILoad = 10 mA, COUT = 2.2 µF
Freq = 100 Hz
PSRR
Power supply ripple rejection(2)
60
40
dB
dB
Freq = 100 kHz
VOLTAGE SENSING PRE-WARNING
VSIth
Sense low threshold
VSI decreasing
1.089 1.123
1.157
150
0.4
1
V
mV
V
VSIth,hys
VSOL
Sense threshold hysteresis
Sense output low voltage
Sense output leakage
Sense input current
50
100
0.1
(VSI ≤ 1.06 V, Vin ≥ 4 V, RSO = 10 kΩ to VOUT
(VSO = 5 V, VSI ≥ 1.5 V)
)
ISOH
µA
µA
ISI
–1
1
RESET (PG)
VOL
Reset pulled low
IOL = 0.5 mA
0.4
1
V
IOH
Reset pulled Vout through 10-kΩ resistor
Power-on-reset threshold
Hysteresis
Leakage current
µA
VTH-(POR)
VThres
RESET DELAY (CT)
Vout power up set tolerance
Vout power down set tolerance
89.6
91.6
2
93.6 % of Vout
% of Vout
IChg
Vth
Delay-capacitor charging current
Threshold to release nRST high
Rdelay = 0 V
1.4
1
µA
V
TIMING FOR RESET (PG)
tPOR
Where C = Delay capacitor value Capacitance C = 100 nF(3)
No capacitor on pin
50
100
20
100
290
250
180
650
ms
µs
µs
Power-on-reset delay
tPOR-fixed
tDeglitch
OPERATING TEMPERATURE RANGE
Reset deglitch time
TJ
Junction temperature
–40
150
°C
°C
Tshutdown
Junction shutdown temperature
175
(1) Adjustable version with precision external feedback resistor with tolerance of less than ±1%.
(2) Design information – Not tested, specified by characterization.
(3) This information only will NOT be tested in production and equation will be based as; (C × 1) / 1 × 10–6 = tDelay (delay time).
Where C = Delay capacitor value. Capacitance C range = 100 pF to 100 nF.
Copyright © 2012–2013, Texas Instruments Incorporated
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TPS7A6650-Q1, TPS7A6933-Q1
TPS7A6950-Q1
SLVSBL0B –DECEMBER 2012–REVISED AUGUST 2013
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ELECTRICAL CHARACTERISTICS (continued)
Vin = 14 V, 1 mΩ < ESR < 2 Ω, TJ = –40°C to 150°C (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
THyst
Hysteresis of thermal shutdown
20
°C
4
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TPS7A6601-Q1, TPS7A6633-Q1
TPS7A6650-Q1, TPS7A6933-Q1
TPS7A6950-Q1
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SLVSBL0B –DECEMBER 2012–REVISED AUGUST 2013
DEVICE INFORMATION
SOIC 8 (TPS7A69xx-Q1)
MSOP 8 (TPS7A66xx-Q1)
DGN Package
(Top View)
D Package
(Top View)
Vin
SI
1
2
3
4
8
7
6
5
Vout
SO
Vin
1
2
3
4
8
7
6
5
Vout
FB/NC
PG
EN
NC
CT
NC
CT
PG
GND
GND
Pin Functions
PIN NO.
PIN
NAME
TYPE
DESCRIPTION
SOIC-D
MSOP - DGN
CT
EN
4
4
2
O
I
Reset-pulse delay adjustment. Connecting this pin via a capacitor to GND
Enable pin. Standby state when enable pin becomes lower than threshold
Feedback pin when using external resistor divider or NC pin when using internal resistor
divider
FB/NC
7
I
GND
NC
5
3
5
3
G
Ground reference
Not connected pins
Output ready. This open-drain pin must connect to Vout via an external resistor. The
output voltage going below threshold pulls it down.
PG
SI
6
2
7
6
O
I
Sense input pin to supervise input voltage. Connect via an external voltage divider
connected to Vs and GND
Sense output. This open-drain pin must connect to Vout via an external resistor. The SI
voltage becoming lower than the threshold pulls it down.
SO
O
Vin
1
8
1
8
P
P
Input power-supply voltage
Output voltage
Vout
—
Thermal pad for MSOP-DGN package
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TPS7A6650-Q1, TPS7A6933-Q1
TPS7A6950-Q1
SLVSBL0B –DECEMBER 2012–REVISED AUGUST 2013
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FUNCTIONAL BLOCK DIAGRAMS
TPS7A66xx-Q1
UVLO
Comp
Vref3
+
Vin
Band Gap
Vref1
1
Vbattery
22 μF
0.1 μF
Overcurrent
Detection
Logic
Control
Thermal
Shutdown
EN
2
Regulator
Control
Vout
8
Vreg
4.7 μF
Vref1
+
Vreg
GND
5
10 kΩ
PG
6
CT
Reset
Control
4
Figure 3. TPS7A66xx Functional Block Diagram
6
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TPS7A6650-Q1, TPS7A6933-Q1
TPS7A6950-Q1
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SLVSBL0B –DECEMBER 2012–REVISED AUGUST 2013
TPS7A69xx-Q1
UVLO
Comp
Vref3
+
Vin
Band Gap
1
Vbattery
22 μF
0.1 μF
Vref1
Overcurrent
Detection
Logic
Control
Thermal
Shutdown
Regulator
Control
Vout
8
Vreg
4.7 μF
Vref1
+
Vreg
GND
5
10 kΩ
PG
6
CT
Reset
Control
4
Vreg
10 kΩ
Vin
SO
7
SI
2
+
Vref1
Figure 4. TPS7A69xx Functional Block Diagram
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TPS7A6650-Q1, TPS7A6933-Q1
TPS7A6950-Q1
SLVSBL0B –DECEMBER 2012–REVISED AUGUST 2013
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TYPICAL CHARACTERISTICS
POWER-GOOD THRESHOLD VOLTAGE
vs
TEMPERATURE (Vin=14 V, NO LOAD)
LINE REGULATION (Vin = 14 V, Iload = 1 mA)
92.0
91.5
91.0
90.5
90.0
89.5
89.0
88.5
1.0
0.8
PG Rising
PG Falling
T = ±40C
T = 25C
T = 125C
0.6
0.4
0.2
0.0
±0.2
±0.4
±0.6
±0.8
±1.0
±40 ±25 ±10
5
20 35 50 65 80 95 110 125
0
0
0
5
10
15
20
25
30
35
40
45
C001
C002
Temperature (C)
Input Voltage (V)
Figure 5.
Figure 6.
GROUND CURRENT
vs
QUIESCENT CURRENT
vs
INPUT VOLTAGE (Iload = 0)
OUTPUT CURRENT (Vin = 14V)
120
100
80
60
40
20
0
25
20
15
10
5
T = ±40C
T = 25C
T = 125C
T = ±40C
T = 25C
T = 125C
0
0
20
40
60
80
100
5
10
15
20
25
30
35
40
45
C003
C004
Output Current (mA)
Input Voltage (V)
Figure 7.
Figure 8.
DROPOUT VOLTAGE
vs
LOAD REGULATION (Vin= 14 V) \
OUTPUT CURRENT (Vin = 4 V)
2.0
1.5
350
300
250
200
150
100
50
T = ±40C
T = 25C
T = 125C
T = ±40C
T = 25C
T = 125C
1.0
0.5
0.0
±0.5
±1.0
±1.5
±2.0
0
0
10
20
30
40
50
60
70
80
90 100
10
20
30
40
50
60
70
80
90 100
C005
C006
Output Current (mA)
Output Current (mA)
Figure 9.
Figure 10.
8
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TPS7A6650-Q1, TPS7A6933-Q1
TPS7A6950-Q1
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SLVSBL0B –DECEMBER 2012–REVISED AUGUST 2013
TYPICAL CHARACTERISTICS (continued)
OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE
(Fixed 5V Version, Iload = 0)
OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE
(Fixed 3.3V Version, Iload = 0
6
5
4
3
2
1
0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
C007
C008
Supply Voltage (V)
Supply Voltage (V)
Figure 11.
Figure 12.
LOAD CAPACITANCE
vs
ESR STABILITY
100.0
80.0
60.0
40.0
20.0
Stable Region
2.2
0.001
0.5
1.0
1.5
2.0
C009
ESR of Cout (ꢁ)
Figure 13.
All oscilloscope waveforms were taken at room temperature.
Figure 14. Power Up (5 V), 20 ms/div, Iload = 20 mA
Figure 15. Load Transient Response, 10 ms/div
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TPS7A6650-Q1, TPS7A6933-Q1
TPS7A6950-Q1
SLVSBL0B –DECEMBER 2012–REVISED AUGUST 2013
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TYPICAL CHARACTERISTICS (continued)
All oscilloscope waveforms were taken at room temperature.
Figure 16. Load Transient Response, 10 ms/div
Figure 17. Line Transient Response, Iload = 1 mA, 1 V/µs
Figure 18. Line Transient Response, Iload = 10 mA, 1 V/µs
DETAILED DESCRIPTION
This product is a combination of a low-dropout linear regulator with reset function. The power-on-reset initializes
once the output Vout exceeds 91.6% of the target value. The power-on-reset delay is a function of the value set
by an external capacitor on the Rdelay pin before releasing the RST terminal high.
Enable (EN):
This is a high-voltage-tolerant terminal; high input actives the device and turns the regulator ON. One can
connect this input to the Vin terminal for self-bias applications.
Regulated Output (Vout):
This is the regulated output based on the required voltage. The output has current limitation. During initial power
up, the regulator has a soft start incorporated to control initial current through the pass element and the output
capacitor.
In the event the regulator drops out of regulation, the output tracks the input minus a drop based on the load
current. When the input voltage drops below the UVLO threshold, the regulator shuts down until the input voltage
recovers above the minimum start-up level.
Power-On-Reset (PG):
This is an output with an external pullup resistor to the regulated supply. The output remains low until the
regulated Vout has exceeded approximately 90% of the set value and the power-on-reset delay has expired. The
on-chip oscillator presets the delay. The regulated output falling below the 90% level asserts this output low after
a short de-glitch time of approximately 50 µs (typical).
Reset Delay Timer (CT):
10
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TPS7A6650-Q1, TPS7A6933-Q1
TPS7A6950-Q1
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SLVSBL0B –DECEMBER 2012–REVISED AUGUST 2013
An external capacitor on this pin sets the timer delay before the reset pin is asserted high. The constant output
current charges an external capacitor until the voltage exceeds a threshold to trip an internal comparator. If this
pin is open, the default delay time is 150 µs (typ). After releasing the nRST pin high, the capacitor on this pin
discharges, thus allowing the capacitor to charge from approx 0.2 V for the next power-on-reset delay-timer
function.
An external capacitor CT defines the reset-pulse delay time, tCT, with the charge time of :
CCT ´1V
tCT
=
1mA
(1)
The power-on-reset initializes once the output Vout exceeds 90% of the programmed value. The power-on-reset
delay is a function of the value set by an external capacitor on the CT pin before the releasing of the PG terminal
high.
Vin
t < tRST_DEGLITCH
VTH(POR)
UVThres
Vout
CT
Internally Set
VTH(RST_DLY)
VTH(RST_DLY)
tRST_DELAY
tRST_DELAY
tRST_DEGLITCH
PG
tRST_DEGLITCH
Figure 19. Conditions for Activation of Reset
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TPS7A6650-Q1, TPS7A6933-Q1
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SLVSBL0B –DECEMBER 2012–REVISED AUGUST 2013
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Vin
0.9 × Vout
Vout
Vth
CT
tPOR
PG
Figure 20. External Programmable Reset Delay
Sense Comparator (SI and SO for TPS7A69xx)
The sense comparator compares an input signal with an internal voltage reference of 1.223 V for rising and
1.123 V for falling threshold. The use of an external voltage divider makes this comparator very flexible in the
application.
The device can supervise the input voltage either before or after the protection diode and give additional
information to the microprocessor, like low-voltage warnings.
The regulator operates in low-power mode when the output load is below 2 mA (typical, 1-mA to 10-mA range).
In this mode, the regulator output tolerance is approximately Vout ± 1%.
Adjustable Output Voltage (FB for TPS7A6601)
One can select an output voltage between 1.5 V and 5.5 V by using the external resistor dividers. Calculate the
output voltage using the following equation, where VFB= 1.223 V.
R1
æ
ç
è
ö
÷
ø
Vout = VFB ´ 1+
R2
(2)
12
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Product Folder Links: TPS7A6601-Q1 TPS7A6633-Q1 TPS7A6650-Q1 TPS7A6933-Q1 TPS7A6950-Q1
TPS7A6601-Q1, TPS7A6633-Q1
TPS7A6650-Q1, TPS7A6933-Q1
TPS7A6950-Q1
www.ti.com
SLVSBL0B –DECEMBER 2012–REVISED AUGUST 2013
TPS7A6601-Q1
Vbat
1
Vin
Vout
8
7
Vreg
C1
C2
R1
FB
R2
2
4
EN
CT
R3
PG
6
5
GND
C3
Figure 21. External Feedback Resistor Divider
Undervoltage Shutdown
There is an internally fixed undervoltage shutdown threshold. Undervoltage shutdown activates when the input
voltage on Vin drops below VinUVLO. This ensures the regulator is not latched into an unknown state during low
input supply voltage. If the input voltage has a negative transient which drops below the UVLO threshold and
recovers, the regulator shuts down and powers up like a normal power-up sequence once the input voltage is
above the required levels.
Low-Voltage Tracking
At low input voltages the regulator drops out of regulation, the output voltage tracks input minus a voltage based
on the load current (IOUT) and switch resistance (RSW). This allows for a smaller input capacitor and can possibly
eliminate the need of using a boost convertor during cold-crank conditions.
Thermal Shutdown
These devices incorporate a thermal shutdown (TSD) circuit as a protection from overheating. For continuous
normal operation, the junction temperature should not exceed the TSD trip point. If the junction temperature
exceeds the TSD trip point, the output turns off. When the junction temperature falls below the TSD trip point, the
output turns on again.
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TPS7A6601-Q1, TPS7A6633-Q1
TPS7A6650-Q1, TPS7A6933-Q1
TPS7A6950-Q1
SLVSBL0B –DECEMBER 2012–REVISED AUGUST 2013
www.ti.com
APPLICATION INFORMATION
Figure 22 and Figure 23 show typical application circuits for the TPS7A66xx and TPS7A69xx, respectively. One
may use different values of external components, depending on the end application. An application may require a
larger output capacitor may uring fast load steps in order to prevent reset from occurring. TI recommends a low-
ESR ceramic capacitor with dielectric of type X5R or X7R.
TPS7A66xx-Q1
TPS7A69xx-Q1
Vbat
Vbat
1
Vin
Vout
8
Vreg
1
Vin
Vout
8
7
Vreg
2.2 ꢀF
1 ꢀF
1 ꢀF
2.2 ꢀF
10 kꢁꢀ
SO
2
4
EN
CT
2
4
SI
10 kꢁꢀ
10 kꢁꢀ
2.2 ꢀF
PG
6
5
PG
6
5
GND
CT
GND
1 nF
1 nF
Figure 22. Typical Application Schematic for
TPS7A66xx
Figure 23. Typical Application Schematic for
TPS7A69xx
Power Dissipation and Thermal Considerations
Calculate power dissipated in the device using Equation 3.
space
PD = Iout × (Vin – Vout) + Iquiescent × Vin
(3)
Where:
PD = continuous power dissipation
Iout = output current
Vin = input voltage
Vout = output voltage
As Iquiescent << Iout, therefore ignore the term Iquiescent × Vin in Equation 3.
For a device under operation at a given ambient air temperature (TA), calculate the junction temperature (TJ)
using Equation 4.
space
TJ = TA + (θJA × PD)
(4)
where:
θJA = junction-to-ambient air thermal impedance
space
ΔT = TJ – TA = (θJA × PD)
(5)
14
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TPS7A6601-Q1, TPS7A6633-Q1
TPS7A6650-Q1, TPS7A6933-Q1
TPS7A6950-Q1
www.ti.com
SLVSBL0B –DECEMBER 2012–REVISED AUGUST 2013
LAYOUT INFORMATION
Package Mounting
Solder pad footprint recommendations for the TPS7A66xx-Q1 and TPS7A69xx-Q1 are available at the end of
this product data sheet and at www.ti.com.
Board Layout Recommendations to Improve PSRR and Noise Performance
To improve ac performance such as PSRR, output noise, and transient response, TI recommends a board
design with separate ground planes for Vin and Vout, with each ground plane connected only at the GND pin of
the device. In addition, the ground connection for the output capacitor should connect directly to the GND pin of
the device.
Minimize equivalent series inductance (ESL) and ESR in order to maximize performance and ensure stability.
Place every capacitor as close as possible to the device and on the same side of the PCB as the regulator itself.
Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. TI
strongly discourages the use of vias and long traces because they may impact system performance negatively
and even cause instability.
If possible, and to ensure the maximum performance specified in this product data sheet, use the same layout
pattern used for the TPS7A66xx-Q1 and TPS7A69xx-Q1 evaluation board, available at www.ti.com.
Additional Layout Considerations
The high impedance of the FB pin makes the regulator sensitive to parasitic capacitances that may couple
undesirable signals from nearby components (especially from logic and digital ICs, such as microcontrollers and
microprocessors); these capacitive-coupled signals may produce undesirable output voltage transients. In these
cases, TI recommends the use of a fixed-voltage version of the TPS7A66xx-Q1, or isolation of the FB node by
flooding the local PCB area with ground-plane copper to minimize any undesirable signal coupling.
Thermal Protection
Thermal protection disables the output when the junction temperature rises to approximately 170°C, allowing the
device to cool. Cooling of the junction temperature to approximately 150°C enables the output circuitry.
Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may
cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result of
overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heat-spreading area. For reliable operation, junction temperature should be limited to a maximum of 125°C at the
worst-case ambient temperature for a given application. To estimate the margin of safety in a complete design
(including the copper heat-spreading area), increase the ambient temperature until the thermal protection is
triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at
least 45°C above the maximum expected ambient condition of the particular application. This configuration
produces a worst-case junction temperature of 125°C at the highest expected ambient temperature and worst-
case load.
The purpose of the design of the internal protection circuitry of the TPS7A66/69xx-Q1 is for protection against
overload conditions, not as a replacement for proper heat-sinking. Continuously running the TPS7A66xx-Q1 or
TPS7A69xx-Q1 into thermal shutdown degrades device reliability.
spacer
REVISION HISTORY
Changes from Revision A (March 2013) to Revision B
Page
•
Added two conditions to Vdropout in the Electrical Characteristics table ............................................................................. 3
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Product Folder Links: TPS7A6601-Q1 TPS7A6633-Q1 TPS7A6650-Q1 TPS7A6933-Q1 TPS7A6950-Q1
TPS7A6601-Q1, TPS7A6633-Q1
TPS7A6650-Q1, TPS7A6933-Q1
TPS7A6950-Q1
SLVSBL0B –DECEMBER 2012–REVISED AUGUST 2013
www.ti.com
Changes from Original (December 2012) to Revision A
Page
•
•
Deleted the ORDERING INFORMATION table .................................................................................................................... 2
Changed From: TA Operating ambient temperature range –40 to 125°C To: TJ Operating junction temperature range
–40 to 150°C ......................................................................................................................................................................... 2
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PACKAGE OPTION ADDENDUM
www.ti.com
20-Oct-2013
PACKAGING INFORMATION
Orderable Device
TPS7A6601QDGNRQ1
TPS7A6633QDGNRQ1
TPS7A6650QDGNRQ1
TPS7A6933QDRQ1
TPS7A6950QDRQ1
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
MSOP-
PowerPAD
DGN
8
8
8
8
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
CU NIPDAUAG
CU NIPDAUAG
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-3-260C-168 HR
Level-3-260C-168 HR
PA4Q
PA2Q
PA1Q
6933
ACTIVE
ACTIVE
ACTIVE
ACTIVE
MSOP-
PowerPAD
DGN
DGN
D
2500
2500
2500
2500
Green (RoHS
& no Sb/Br)
MSOP-
PowerPAD
Green (RoHS
& no Sb/Br)
SOIC
Green (RoHS
& no Sb/Br)
SOIC
D
Green (RoHS
& no Sb/Br)
CU NIPDAU
6950
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
20-Oct-2013
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Oct-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
2500
2500
2500
2500
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS7A6601QDGNRQ1 MSOP-
DGN
DGN
DGN
D
8
8
8
8
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
5.3
5.3
5.3
6.4
3.4
3.4
3.4
5.2
1.4
1.4
1.4
2.1
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Power
PAD
TPS7A6633QDGNRQ1 MSOP-
Power
PAD
TPS7A6650QDGNRQ1 MSOP-
Power
PAD
TPS7A6950QDRQ1
SOIC
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Oct-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS7A6601QDGNRQ1 MSOP-PowerPAD
TPS7A6633QDGNRQ1 MSOP-PowerPAD
TPS7A6650QDGNRQ1 MSOP-PowerPAD
DGN
DGN
DGN
D
8
8
8
8
2500
2500
2500
2500
366.0
366.0
366.0
367.0
364.0
364.0
364.0
367.0
50.0
50.0
50.0
35.0
TPS7A6950QDRQ1
SOIC
Pack Materials-Page 2
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