TPS7A6650H-Q1 [TI]
具有电源正常指示功能的汽车类 50mA、电池供电运行 (40V)、低 IQ、低压降稳压器;
| 型号： | TPS7A6650H-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有电源正常指示功能的汽车类 50mA、电池供电运行 (40V)、低 IQ、低压降稳压器 电池 稳压器 |
| 文件： | 总20页 (文件大小：1921K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Sample &
Buy
Support &
Community
Product
Folder
Tools &
Software
Technical
Documents
TPS7A6650H-Q1
ZHCSER8 –DECEMBER 2015
TPS7A6650H-Q1 40V、超低 I(q)、环境温度最高为 150°C 的稳压器
1 特性
3 说明
1
•
适用于汽车电子 应用
TPS7A6650H-Q1 是一款低压降线性稳压器，其设计
适用于输入电压高达 40V 的操作。该器件在无负载时
的静态电流仅为 12µA，非常适合待机微处理器控制单
元系统，尤其是汽车 应用。
•
具有符合 AEC-Q100 标准的下列结果：
–
–
–
器件温度：-40°C 至 150°C 的环境工作温度范
围
器件人体模型 (HBM) 静电放电 (ESD) 分类等级
H2
该器件 具有 集成式短路和过流保护。此器件在上电时
执行复位延迟以指示输出电压稳定且处于稳压状态。用
户可使用一个外部电容器来设定此延迟。低压跟踪特性
允许使用更小的输入电容器并且有可能在冷启动条件下
无需使用升压转换器。
器件组件充电模式 (CDM) ESD 分类等级 C4
•
•
•
4V 至 40V 的宽输入电压范围，瞬态电压高达 45V
输出电流：50mA
低静态电流 (I(q))：
该器件可在 –40°C 至 150°C 的温度范围内工作，非常
适合各类汽车应用中的 电源。
–
–
当 EN = 低电平时（关断模式）时为 2µA
轻负载时典型值为 12µA
•
•
低等效串联电阻 (ESR) 陶瓷输出稳定电容器
(2.2µF-100µF)
器件信息(1)
封装
器件型号
封装尺寸（标称值）
50mA 时的压降电压为 130mV
（V(Vin)= 4V 时的典型值）
TPS7A6650H-Q1
HVSSOP (8)
3.00mm x 3.00mm
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
•
•
•
5V 固定输出电压
低输入电压跟踪
集成型加电复位
硬件使能选项
V(bat)
–
–
可编程复位脉冲延迟
漏极开路复位输出
V(reg)
Vout
8
1
2
Vin
EN
•
•
集成故障保护
PG
6
–
–
热关断
短路保护功能
8 引脚 MSOP-DGN 封装
4
CT
GND
5
2 应用
•
•
•
•
动力传动传感器模块
具有睡眠模式的信息娱乐系统
车身控制模块
常开电池 应用
–
–
–
网关 应用
遥控无钥匙进入系统
发动机防盗锁止系统
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSD64
TPS7A6650H-Q1
ZHCSER8 –DECEMBER 2015
www.ti.com.cn
目录
7.2 Functional Block Diagram ......................................... 9
7.3 Feature Description................................................... 9
7.4 Device Functional Modes........................................ 12
Application and Implementation ........................ 13
8.1 Application Information............................................ 13
8.2 Typical Application .................................................. 13
Power Supply Recommendations...................... 14
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 3
6.1 Absolute Maximum Ratings ...................................... 3
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 4
6.6 Switching Characteristics.......................................... 5
6.7 Qualification Summary.............................................. 5
6.8 Typical Characteristics.............................................. 6
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
8
9
10 Layout................................................................... 15
10.1 Layout Guidelines ................................................. 15
10.2 Layout Example .................................................... 15
10.3 Power Dissipation and Thermal Considerations... 15
11 器件和文档支持 ..................................................... 16
11.1 商标....................................................................... 16
11.2 静电放电警告......................................................... 16
11.3 Glossary................................................................ 16
12 机械、封装和可订购信息....................................... 16
7
4 修订历史记录
日期
修订版本
注释
2015 年 11 月
*
最初发布版本
2
Copyright © 2015, Texas Instruments Incorporated
TPS7A6650H-Q1
www.ti.com.cn
ZHCSER8 –DECEMBER 2015
5 Pin Configuration and Functions
8-Pin HVSSOP
DGN Package
Top View
Vin
EN
NC
CT
1
2
3
4
8
7
6
5
Vout
NU
Thermal
Pad
PG
GND
NC – No internal connection
NU – Make no external connection
Pin Functions
PIN NAME
PIN NO.
TYPE
DESCRIPTION
CT
4
O
Reset-pulse delay adjustment. Connect this pin via a capacitor to GND
Enable pin. The device enters the standby state when the enable pin becomes lower than the
threshold.
EN
2
I
NU
GND
NC
7
5
3
I
Not-used pin; make no external connection
Ground reference
G
—
Not-connected pin
Output ready. This open-drain pin must connect to Vout via an external resistor. The output
voltage going below threshold pulls it down.
PG
6
O
Vin
Vout
—
1
8
P
O
Input power-supply voltage
Output voltage
—
—
Thermal pad
6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted)
(1)
MIN
–0.3
–0.3
–0.3
–0.3
–40
MAX UNIT
Vin, EN
Vout
CT
Unregulated input(2) (3)
Regulated output
45
7
V
V
25
V
PG
Vout
160
160
V
TJ
Operating junction temperature range
Storage temperature range
°C
°C
Tstg
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to GND
(3) Absolute maximum voltage, withstand 45 V for 200 ms
Copyright © 2015, Texas Instruments Incorporated
3
TPS7A6650H-Q1
ZHCSER8 –DECEMBER 2015
www.ti.com.cn
6.2 ESD Ratings
VALUE
±4000
±1000
±1000
UNIT
Human body model (HBM), per AEC Q100-002(1)
All pins
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per AEC
Corner pins (1, 4, 5, and
8)
Q100-011
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
spacer
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
MAX UNIT
Vin
EN
CT
Vout
PG
TA
Unregulated input
4
0
40
40
V
V
0
20
V
1.5
0
5.5
5.5
150
V
Low voltage (I/O)
V
Operating ambient temperature
–40
°C
6.4 Thermal Information
TPS7A6650H-Q1
THERMAL METRIC(1)
DGN (HVSSOP)
UNIT
8 PINS
63.4
53
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance(2)
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
37.4
3.7
ψJT
ψJB
37.1
13.5
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
(2) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
6.5 Electrical Characteristics
V(Vin) = 14 V, 1 mΩ < ESR < 2 Ω, TJ = –40°C to 160°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE AND CURRENT (Vin)
V(Vin)
I(q)
I(Sleep)
I(EN)
Input voltage
IO = 1 mA
5.5
40
22
4
V
µA
µA
µA
V
Quiescent current
Input sleep current
EN pin current
V(Vin) = 5.5 V to 40 V, EN = ON, IO = 0.2 mA
No load current and EN = OFF
V(EN) = 40 V
12
1
V(VinUVLO
)
Undervoltage detection
Undervoltage hysteresis
Ramp V(Vin) down until output turns OFF
2.6
V(UVLOhys)
1
V
ENABLE INPUT (EN)
VIL
VIH
Logic input low level
Logic input high level
0
0.4
V
V
1.7
4
版权 © 2015, Texas Instruments Incorporated
TPS7A6650H-Q1
www.ti.com.cn
ZHCSER8 –DECEMBER 2015
Electrical Characteristics (接下页)
V(Vin) = 14 V, 1 mΩ < ESR < 2 Ω, TJ = –40°C to 160°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
REGULATED OUTPUT (Vout)
IO = 1 mA, TJ = 25°C
–1%
–2%
1%
2%
5
V(Vout)
Regulated output
V(Vin) = 6 V to 40 V, IO = 1 mA to 50 mA
V(Vin) = 5.5 V to 40 V, IO = 50 mA
IO = 1 mA to 50 mA
V(line-reg)
V(load-reg)
V(dropout)
IO
Line regulation
Load regulation
Dropout voltage
Output current
mV
mV
mV
mA
mA
20
V(dropout) = V(Vin) – V(Vout), IOUT = 50 mA
V(Vout) in regulation
130
500
240
50
0
I(lreg-CL)
Output current limit
V(Vout) short to ground
800
V(Vin) = 12 V, IL = 10 mA, output capacitance = 2.2 µF,
V(Vin) = 12 V, IL = 10 mA, output capacitance = 2.2 µF,
frequency = 100 Hz
60
40
dB
dB
PSRR
Power supply ripple rejection(1)
V(Vin) = 12 V, IL = 10 mA, output capacitance = 2.2 µF,
frequency = 100 kHz
RESET (PG)
VOL
Reset output, low voltage
Leakage current
IOL = 0.5 mA
0.4
1
V
Ilkg
Reset pulled Vout through 10-kΩ resistor
V(Vout) increasing
µA
V(TH-POR)
V(Thres)
Power-on-reset threshold
Hysteresis
89.6
91.6
2
93.6 % of Vout
% of Vout
RESET DELAY (CT)
I(Chg) Delay-capacitor charging current
V(th) Threshold to release PG high
OPERATING TEMPERATURE RANGE
V(CT) = 0 V
1.4
1
µA
V
TJ
Junction temperature
–40
160
°C
°C
°C
T(shutdown)
T(hyst)
Junction shutdown temperature
Hysteresis of thermal shutdown
175
20
(1) Design information – Not tested
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TIMING FOR RESET (PG)
TEST CONDITIONS
MIN
TYP
MAX UNIT
Where C = delay capacitor value; capacitance
C = 100 nF(1)
t(POR)
50
100
180
650
ms
Power-on-reset delay
t(POR-fixed)
t(Deglitch)
No capacitor on pin
100
20
290
250
µs
µs
Reset deglitch time
(1) This information only is not tested in production and equation basis is (C × 1) / 1 × 10–6 = td (delay time).
Where C = Delay capacitor value. Capacitance C range = 100 pF to 100 nF.
6.7 Qualification Summary
The TPS7A6650H-Q1 device has passed all the Grade 0 level qualification items required in AEC-Q100 with one
exception: High temperature storage lifetime (HTSL). For the HTSL item, the Grade 0 level requirement is
passing 175ºC for 1000 hours of stress. For this device, it passed at 160°C for 1000 hours stress.
版权 © 2015, Texas Instruments Incorporated
5
TPS7A6650H-Q1
ZHCSER8 –DECEMBER 2015
www.ti.com.cn
6.8 Typical Characteristics
95
94
93
92
91
90
89
88
87
86
85
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-40°C
25°C
125°C
150°C
PG Rising
PG Falling
-40
-10
20
50
80
110
140
0
5
10
15
20
25
30
35
40
Temperature (°C)
Input Voltage (V)
D001
D002
Vin = 14 V
No Load
Vin = 14 V
IL = 1 mA
图 1. Power-Good Threshold Voltage vs Temperature
图 2. Line Regulation
25
20
15
10
5
90
80
70
60
50
40
30
20
10
0
-40°C
-40°C
25°C
125°C
150°C
25°C
125°C
150°C
0
0
5
10
15
20
25
30
35
40
45
50
0
5
10
15
20
25
30
35
40
Output Current (mA)
Input Voltage (V)
D003
D004
Vin = 14 V
图 3. Ground Current vs Output Current
IL = 0
图 4. Quiescent Current vs Input Voltage
200
175
150
125
100
75
1
-40°C
25°C
125°C
150°C
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
50
25
-40°C
25°C
125°C
150°C
0
0
5
10
15
20
25
30
35
40
45
50
0
5
10
15
20
25
30
35
40
45
50
Output Current (mA)
Output Current (mA)
D005
D006
Vin = 14 V
Vin = 4 V
图 6. Dropout Voltage vs Output Current
图 5. Load Regulation
6
版权 © 2015, Texas Instruments Incorporated
TPS7A6650H-Q1
www.ti.com.cn
ZHCSER8 –DECEMBER 2015
Typical Characteristics (接下页)
6
100.0
80.0
60.0
40.0
20.0
5
4
3
2
1
0
Stable Region
2.2
0.001
0
5
10
15
20
25
30
35
40
0.5
1.0
1.5
2.0
C007
C009
Supply Voltage (V)
ESR of Cout (ꢁ)
图 7. Output Voltage vs Supply Voltage (Fixed 5-V Version,
图 8. Load Capacitance vs ESR Stability
IL = 0)
120
100
80
60
40
20
0
œ20
10
100
1k
10k
100k
1M
10M
100M
Frequency (Hz)
C010
图 9. Power-Supply Rejection Ratio vs Frequency
All oscilloscope waveforms were taken at room temperature.
图 10. Load Transient Response, 10 ms/div
图 11. Line Transient Response, IL = 1 mA, 1 V/µs
版权 © 2015, Texas Instruments Incorporated
7
TPS7A6650H-Q1
ZHCSER8 –DECEMBER 2015
www.ti.com.cn
Typical Characteristics (接下页)
All oscilloscope waveforms were taken at room temperature.
图 12. Line Transient Response, IL = 10 mA, 1 V/µs
8
版权 © 2015, Texas Instruments Incorporated
TPS7A6650H-Q1
www.ti.com.cn
ZHCSER8 –DECEMBER 2015
7 Detailed Description
7.1 Overview
This product is a combination of a low-dropout linear regulator with reset function. The power-on reset initializes
once the Vout output exceeds 91.6% of the target value. The power-on-reset delay is a function of the value set
by an external capacitor on the CT pin before releasing the PG pin high.
7.2 Functional Block Diagram
UVLO
Comp
Vref(3)
GND
5
+
Vin
Band Gap
1
V(bat)
22 μF
0.1 μF
Vref(1)
Overcurrent
Detection
Logic
Control
Thermal
Shutdown
EN
2
Regulator
Control
Vout
8
V(reg)
4.7 μF
Vref(1)
+
V(reg)
CT
4
10 kΩ
PG
6
Reset
Control
图 13. TPS7A6650H-Q1 Functional Block Diagram
7.3 Feature Description
7.3.1 Enable (EN)
This is a high-voltage-tolerant pin; high input activates the device and turns the regulator ON. One can connect
this input to the Vin pin for self-bias applications.
7.3.2 Regulated Output (Vout)
This is the regulated output based on the required voltage. The output has current limitation. During initial power
up, the regulator has a soft start incorporated to control initial current through the pass element and the output
capacitor.
版权 © 2015, Texas Instruments Incorporated
9
TPS7A6650H-Q1
ZHCSER8 –DECEMBER 2015
www.ti.com.cn
Feature Description (接下页)
In the event the regulator drops out of regulation, the output tracks the input minus a drop based on the load
current. When the input voltage drops below the UVLO threshold, the regulator shuts down until the input voltage
recovers above the minimum start-up level.
7.3.3 Power-On Reset (PG)
This is an output with an external pullup resistor to the regulated supply. The output remains low until the
regulated Vout has exceeded approximately 90% of the set value and the power-on-reset delay has expired. The
on-chip oscillator presets the delay. The regulated output falling below the 90% level asserts this output low after
a short de-glitch time of approximately 250 µs (typical).
7.3.4 Reset Delay Timer (CT)
An external capacitor on this pin sets the timer delay before the reset pin is asserted high. The constant output
current charges an external capacitor until the voltage exceeds a threshold to trip an internal comparator. If this
pin is open, the default delay time is 290 µs (typ). After releasing the PG pin high, the capacitor on this pin
discharges, thus allowing the capacitor to charge from approximately 0.2 V for the next power-on-reset delay-
timer function.
An external capacitor, CT, defines the reset-pulse delay time, t(POR), with the charge time of:
C
(CT) ´ 1 V
t(POR)
=
1mA
(1)
The power-on reset initializes once the output V(Vout) exceeds 91.6% of the programmed value. The power-on-
reset delay is a function of the value set by an external capacitor on the CT pin before the releasing of the PG
pin high.
Vin
t < t(Deglitch)
VTH(POR)
V(Thres)
Vout
V(th)
V(th)
CT
t(POR)
t(POR)
t(Deglitch)
PG
t(Deglitch)
图 14. Conditions for Activation of Reset
10
版权 © 2015, Texas Instruments Incorporated
TPS7A6650H-Q1
www.ti.com.cn
ZHCSER8 –DECEMBER 2015
Feature Description (接下页)
Vin
0.9 × V(th)
Vout
CT
V(th)
t(POR)
PG
图 15. External Programmable Reset Delay
7.3.5 Undervoltage Shutdown
There is an internally fixed undervoltage shutdown threshold. Undervoltage shutdown activates when the input
voltage on Vin drops below V(VinUVLO). This ensures the regulator is not latched into an unknown state during low
input supply voltage. If the input voltage has a negative transient which drops below the UVLO threshold and
recovers, the regulator shuts down and powers up with a normal power-up sequence once the input voltage is
above the required levels.
7.3.6 Low-Voltage Tracking
At low input voltages, the regulator drops out of regulation and the output voltage tracks input minus a voltage
based on the load current (IO) and switch resistance (R(SW)). This allows for a smaller input capacitor and can
possibly eliminate the need of using a boost convertor during cold-crank conditions.
7.3.7 Thermal Shutdown
These devices incorporate a thermal shutdown (TSD) circuit as a protection from overheating. For continuous
normal operation, the junction temperature should not exceed the TSD trip point. If the junction temperature
exceeds the TSD trip point, the output turns off. When the junction temperature falls below the TSD trip point, the
output turns on again.
Thermal protection disables the output when the junction temperature rises to approximately 175°C, allowing the
device to cool. Cooling of the junction temperature to approximately 155°C enables the output circuitry.
Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may
cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result of
overheating.
版权 © 2015, Texas Instruments Incorporated
11
TPS7A6650H-Q1
ZHCSER8 –DECEMBER 2015
www.ti.com.cn
Feature Description (接下页)
The purpose of the design of the internal protection circuitry of the TPS7A6650H-Q1 is for protection against
overload conditions, not as a replacement for proper heat-sinking. Continuously running the TPS7A6650H-Q1
device into thermal shutdown degrades device reliability.
7.4 Device Functional Modes
7.4.1 Operation With V(VIN) < 4 V
The devices operate with input voltages above 4 V. The maximum UVLO voltage is 2.6 V, and the devices
operate at an input voltage above 4 V. The devices can also operate at lower input voltages; no minimum UVLO
voltage is specified. At input voltages below the actual UVLO voltage, the devices do not operate.
7.4.2 Operation With EN Control
The enable rising edge threshold voltage is 1.7 V (maximum). With the EN pin held above that voltage and the
input voltage above 4 V, the device becomes active. The enable falling edge is 0.4 V (minimum). Holding the EN
pin below that voltage disables the device, thus reducing the IC quiescent current.
12
版权 © 2015, Texas Instruments Incorporated
TPS7A6650H-Q1
www.ti.com.cn
ZHCSER8 –DECEMBER 2015
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS7A6650H-Q1 device is a 150-mA low-dropout linear regulator designed for up to 40-V Vin operation with
only 12-µA quiescent current at no load.
8.2 Typical Application
图 16 shows a typical application circuits for the TPS7A6650H-Q1. One may use different values of external
components, depending on the end application. An application may require a larger output capacitor during fast
load steps in order to prevent reset from occurring. TI recommends a low-ESR ceramic capacitor with dielectric
of type X7R or X8R.
8.2.1 TPS7A6650H-Q1 Typical Application
V(bat)
1
Vin
Vout
8
V(reg)
2.2 μF
1 μF
10 kΩ
2
4
EN
CT
PG
6
5
GND
1 nF
图 16. Typical Application Schematic for TPS7A6650H-Q1
8.2.1.1 Design Requirements
For this design example, use the parameters listed in 表 1 as the design parameters.
表 1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range
Output voltage
4 V to 40 V
5 V
Output current rating
Output capacitor range
50 mA
2.2 µF to 100 µF
1 mΩ to 2 Ω
100 pF to 100 nF
Output capacitor ESR range
CT capacitor range
版权 © 2015, Texas Instruments Incorporated
13
TPS7A6650H-Q1
ZHCSER8 –DECEMBER 2015
www.ti.com.cn
8.2.1.2 Detailed Design Procedure
To begin the design process, determine the following:
•
•
•
•
•
•
Input voltage range
Output voltage
Output current rating
Input capacitor
Output capacitor
Power-up-reset delay time
8.2.1.2.1 Input Capacitor
The device requires an input decoupling capacitor, the value of which depends on the application. The typical
recommended value for the decoupling capacitor is 10 µF. The voltage rating must be greater than the maximum
input voltage.
8.2.1.2.2 Output Capacitor
The device requires an output capacitor to stablize the output voltage. The capacitor value should be between
2.2 µF and 100 µF. The ESR range should be between 1 mΩ and 2 Ω. TI recommends to selecting a ceramic
capacitor with low ESR to improve the load transient response.
8.2.1.3 Application Performance Plot
图 17. Power Up (5 V), 20 ms/div, IL = 20 mA
9 Power Supply Recommendations
Design of the device is for operation from an input voltage supply with a range between 4 V and 28 V. This input
supply must be well regulated. If the input supply is located more than a few inches from the TPS7A6650H-Q1
device, TI recommends adding an electrolytic capacitor with a value of 22 µF and a ceramic bypass capacitor at
the input.
14
版权 © 2015, Texas Instruments Incorporated
TPS7A6650H-Q1
www.ti.com.cn
ZHCSER8 –DECEMBER 2015
10 Layout
10.1 Layout Guidelines
10.1.1 Package Mounting
Solder pad footprint recommendations for the TPS7A6650H-Q1 are available at the end of this product data
sheet and at www.ti.com.
10.1.2 Board Layout Recommendations to Improve PSRR and Noise Performance
For the layout of TPS7A6650H-Q1, place the input and output capacitors close to the devices as shown in 图 18.
In order to enhance the thermal performance, TI recommends surrounding the device with some vias.
To improve ac performance such as PSRR, output noise, and transient response, TI recommends a board
design with separate ground planes for Vin and Vout, with each ground plane connected only at the GND pin of
the device. In addition, the ground connection for the output capacitor should connect directly to the GND pin of
the device.
Minimize equivalent series inductance (ESL) and ESR in order to maximize performance and ensure stability.
Place every capacitor as close as possible to the device and on the same side of the PCB as the regulator itself.
Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. TI
strongly discourages the use of vias and long traces because they may impact system performance negatively
and even cause instability.
If possible, and to ensure the maximum performance specified in this product data sheet, use the same layout
pattern used for the TPS7A6650H-Q1 evaluation board, available at www.ti.com.
10.2 Layout Example
Vin
EN
NC
CT
Vout
NU
PG
GND
Power Ground
图 18. TPS7A6650H-Q1 Board Layout Diagram
10.3 Power Dissipation and Thermal Considerations
Calculate power dissipated in the device using 公式 2.
space
PD = IO´ (V(Vin) - V(Vout) ) + I(q) ´ V(Vin)
(2)
where:
PD = continuous power dissipation
IO = output current
V(Vin) = input voltage
V(Vout) = output voltage
As I(q) << IO, therefore ignore the term I(q) × V(Vin) in 公式 2.
For a device under operation at a given ambient air temperature (TA), calculate the junction temperature (TJ)
using 公式 3.
版权 © 2015, Texas Instruments Incorporated
15
TPS7A6650H-Q1
ZHCSER8 –DECEMBER 2015
www.ti.com.cn
Power Dissipation and Thermal Considerations (接下页)
space
TJ = TA + (RqJA ´ PD)
)
(3)
where:
θJA = junction-to-ambient air thermal impedance
R
space
DT = TJ - TA = (RqJA ´ PD)
)
(4)
11 器件和文档支持
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.1 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.2 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。本数据随时可能发生变更并
且不对本文档进行修订，恕不另行通知。要获得这份数据表的浏览器版本，请查阅左侧的导航窗格。
16
版权 © 2015, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS7A6650HQDGNRQ1
ACTIVE
HVSSOP
DGN
8
2500 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 150
13LV
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Apr-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS7A6650HQDGNRQ1 HVSSOP DGN
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Apr-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HVSSOP DGN
SPQ
Length (mm) Width (mm) Height (mm)
366.0 364.0 50.0
TPS7A6650HQDGNRQ1
8
2500
Pack Materials-Page 2
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
相关型号：
©2020 ICPDF网 联系我们和版权申明