TPS7A74 [TI]
具有可编程软启动功能的 1.5A 低压降 (LDO) 线性稳压器;
| 型号： | TPS7A74 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有可编程软启动功能的 1.5A 低压降 (LDO) 线性稳压器 软启动 稳压器 |
| 文件： | 总42页 (文件大小：3004K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS7A74
ZHCSO39B –MAY 2022 –REVISED AUGUST 2022
TPS7A74 具有可编程软启动功能的1.5A 低压降线性稳压器
1 特性
3 说明
• VOUT 范围：0.65V 至3.6V
• 超低VIN 范围：0.65 V 至6 V
• VBIAS 范围：1.7 V 至6 V
• 低压降：1.5A、VBIAS = 5V 下的典型值为150 mV
• 噪声：7.1μVRMS
TPS7A74 低压降 (LDO) 线性稳压器可面向多种应用提
供易于使用的稳健型电源管理解决方案。用户可编程软
启动通过减少启动时的电容涌入电流，更大限度地减少
了输入电源上的应力。软启动具有单调性，非常适合为
各类处理器和专用集成电路 (ASIC) 供电。借助使能输
入，可通过外部稳压器轻松实现时序控制。凭借全方位
的灵活性，该器件可为现场可编程门阵列 (FPGA)、数
字信号处理器 (DSP) 等具有特殊启动要求的应用配置
可满足其时序要求的解决方案。
• PSRR：
– 1kHz 时为70dB
– 10 kHz 时为60dB
– 100 kHz 时为55dB
– 在1MHz 时为50dB
该器件还具有高精度的参考电压电路和误差放大器，可
在整个负载、线路、温度和过程范围内提供 1.5% 精
度。该器件在使用大于或等于 10μF 的任何类型的电
容器时都能保持稳定运行，并具有 TJ = –40°C 至
+125°C 的额定结温范围。TPS7A74 采用小型 3mm ×
3mm WSON-8 封装，可实现高度紧凑的总体解决方案
尺寸。
• 线路、负载和温度范围内的精度为1.5%
• 可编程软启动可提供线性电压启动
• VBIAS 支持低VIN 运行，具有良好的瞬态响应
• IN 和BIAS 上都有UVLO
• 与≥10μF 的任何输出电容器一起工作时可保持稳
定
• 封装：小型3mm × 3mm × 0.8mm WSON-8
封装信息(1)
2 应用
封装尺寸（标称值）
器件型号
TPS7A74
封装
WSON (8)
3.00mm × 3.00mm
• 高性能计算
• 微服务器
• 台式计算机和PC 主板
• 数据集中器
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 耐用型PC 笔记本电脑
TPS7A74
VIN
IN
OUT
OUT
VOUT
COUT
CIN
EN
R1
VBIAS
CBIAS
BIAS
SS
FB
R2
CSS
GND
典型应用电路（可调节）
带载启动
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBVS416
TPS7A74
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ZHCSO39B –MAY 2022 –REVISED AUGUST 2022
Table of Contents
7.5 Programming............................................................ 23
8 Application and Implementation..................................25
8.1 Application Information............................................. 25
8.2 Typical Application.................................................... 29
8.3 Power Supply Recommendations.............................30
8.4 Layout....................................................................... 31
9 Device and Documentation Support............................33
9.1 Device Support......................................................... 33
9.2 Documentation Support............................................ 33
9.3 接收文档更新通知..................................................... 33
9.4 支持资源....................................................................33
9.5 Trademarks...............................................................33
9.6 Electrostatic Discharge Caution................................33
9.7 术语表....................................................................... 33
10 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics................................................7
7 Detailed Description......................................................18
7.1 Overview...................................................................18
7.2 Functional Block Diagram.........................................18
7.3 Feature Description...................................................19
7.4 Device Functional Modes..........................................22
Information.................................................................... 34
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (July 2022) to Revision B (August 2022)
Page
• Changed Minimum startup time parameters limit values....................................................................................5
Changes from Revision * (May 2022) to Revision A (July 2022)
Page
• 将文档状态从预告信息更改为量产数据.............................................................................................................1
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5 Pin Configuration and Functions
BIAS
EN
SS
1
2
3
4
8
7
6
5
GND
FB
Thermal
Pad
OUT
OUT
IN
Not to scale
图5-1. DSD Package, 8-Pin WSON With Thermal Pad (Top View)
Pin Functions
PIN
NAME
TYPE
DESCRIPTION
NO.
Bias input voltage for error amplifier, reference, and internal control circuits. Use a 0.1 µF or larger input
capacitor for optimal performance. If IN is connected to BIAS, a 4.7 µF or larger capacitor must be used.
1
BIAS
I
2
3
4
EN
SS
IN
I
I
I
Enable pin.
Soft-start pin. This pin must be connected to a capacitor to GND.
Input to the device. Use a 1 µF or larger input capacitor for optimal performance.
Regulated output voltage. A small capacitor (total typical capacitance of ≥10 μF, ceramic) is required
from this pin to ground to assure stability.
5, 6
7
OUT
FB
O
I
Feedback pin. The feedback connection to the center tap of an external resistor divider network that
sets the output voltage. This pin must not be left floating.
8
GND
Ground.
Ground.
—
—
Thermal Pad
—
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6 Specifications
6.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
MAX
6.5
UNIT
V
Input voltage
Bias voltage
IN
BIAS
6.5
V
6.5
Enable voltage
EN
SS
FB
V
V
–0.3
6.5
2
Soft-start voltage
Feedback voltage
–0.3
–0.3
V
V
Output voltage
OUT
ILIMIT
ISC
VIN + 0.3
–0.3
Maximum output current
Output short-circuit duration
Continuous total power dissipation
Junction Temperature
Internally limited
Indefinite
PDISS
TJ
See Thermal Information
150
150
–40
–55
°C
Storage Temperature
Tstg
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
0.65
1.7
NOM
MAX
UNIT
V
VIN
Input supply voltage
BIAS supply voltage
Enable voltage
V
BIAS –0.1
(1)
VBIAS
VEN
VOUT
IOUT
COUT
CIN
6
6
V
V
Output voltage
0.65
0
3.6
1.5
V
Output current
A
Output capacitor
Input capacitor(2)
Bias capacitor
10
µF
µF
µF
1
CBIAS
TJ
0.1
–40
1
Operating junction temperature
125
℃
(1) BIAS supply is required when VIN is below VOUT + 1.62 V.
(2) If VIN and VBIAS are connected to the same supply, the recommended minimum capacitor for the supply is 4.7 μF.
6.4 Thermal Information
TPS7A74
THERMAL METRIC(1)
DSD (WSON) (2)
DSD (WSON) (3)
10 PINS
UNIT
10 PINS
49.3
55.3
21.3
1.9
RθJA
Junction-to-ambient thermal resistance
34.9
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
–
–
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.6
ψJT
21.3
5.8
18.8
ψJB
RθJC(bot)
–
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
(2) JEDEC standard. (2s2p, no vias to internal planes and bottom layer).
(3) TPS7A74 thermal characteristics on EVM.
6.5 Electrical Characteristics
at VEN = 1.1 V, VIN = VOUT + 0.3 V, CBIAS = 0.1 μF, CIN = COUT = 10 μF, CNR = 10 nF, IOUT = 10 mA, VBIAS = 5.0 V (3), and TJ
= –40°C to 125°C (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER
TEST CONDITIONS
MIN
0.641
–1.5
TYP
0.65
±0.5
0.2
MAX
0.659
1.5
UNIT
VREF
Internal reference (adj.)
Output accuracy (1) (4) (5)
V
%
2.97 V ≤VBIAS ≤6 V, 0 mA ≤IOUT ≤1.5 A
Max(2.7 V, VOUT + 1.6 V) ≤VBIAS ≤6 V
VOUT(nom) + 0.15 V ≤VIN ≤6 V
0 mA ≤IOUT ≤1.5 A
Line regulation (VBIAS
Line regulation (VIN)
Load regulation
)
0.32
0.05
%/V
%/V
%/A
mV
V
0.01
0.33
150
1.1
VDO(IN)
VDO(BIAS)
ICL
VIN dropout voltage(2)
180
1.3
IOUT = 1.5 A, VBIAS –VOUT(nom) ≥2.8 V
IOUT = 1.5 A, VIN = VBIAS
VBIAS dropout voltage(2)
Output current limit
VOUT = 80% × VOUT(nom)
2
2.7
3.3
A
IBIAS
BIAS pin current
IOUT = 10 mA
0.25
0.33
mA
Shutdown supply current
ISHDN
1
0.15
1.4
55
1
µA
µA
V
VEN ≤0.4 V, VIN = 6 V, VBIAS = 6 V
(IGND
)
IFB
Feedback pin current
–1
Bias rail UVLO rising
threshold
VBIAS(UVLO)
1.04
1.65
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6.5 Electrical Characteristics (continued)
at VEN = 1.1 V, VIN = VOUT + 0.3 V, CBIAS = 0.1 μF, CIN = COUT = 10 μF, CNR = 10 nF, IOUT = 10 mA, VBIAS = 5.0 V (3), and TJ
= –40°C to 125°C (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VBIAS(UVLO),
Bias rail UVLO hysteresis
0.02
0.06
0.07
V
HYST
In rail UVLO rising
threshold
VIN(UVLO), rising
0.39
0.455
0.26
0.5
V
In rail UVLO falling
threshold
VIN(UVLO), falling
0.21
35
8
0.3
335
31
V
tSTR
ISS
Minimum start-up time
RLOAD for IOUT = 1.0 A, CSS = open
VSS = 0 V
µs
µA
Soft-start charging
current
17
0
Soft-start pin disable
voltage
VSS
VEN = 0 V
50
mV
dB
1 kHz, Iout = 1.5 A, Vin = 1.8 V, Vout = 1.5 V
300 kHz, Iout = 1.5 A, Vin = 1.8 V, Vout = 1.5 V
57
27
Power-supply rejection
PSRR
(VBIAS to VOUT
)
Power-supply rejection
BW = 10 Hz to 1 MHz, IOUT = 1 A, VIN = 2.05 V, VOUT
= 1.8 V
PSRR
Vn
27
dB
(VIN to VOUT
)
BW = 10 Hz to 100 kHz, IOUT = 1 A, VIN = 0.95 V,
VOUT = 0.65 V
Output voltage noise
7.1
µVRMS
VEN(hi)
VEN(lo)
VEN(hys)
VEN(dg)
IEN
Enable input high level
Enable input low level
Enable pin hysteresis
Enable pin deglitch time
Enable pin current
1.1
0
5.5
0.4
V
V
55
20
mV
µs
µA
VEN = 5 V
0.1
0.2
1
RPULLDOWN(OU
VBIAS = 5 V, VEN = 0 V
0.6
kΩ
T)
RPULLDOWN(FB) VBIAS = 5 V, VEN = 0 V
120
165
140
Ω
Shutdown, temperature increasing
Reset, temperature decreasing
Thermal shutdown
TSD
℃
temperature
(1) Adjustable devices tested at 0.65 V; resistor tolerance is not taken into account.
(2) Dropout is defined as the voltage from VIN to VOUT when VOUT is 3% below nominal.
(3) VBIAS = VDO_MAX(BIAS) + VOUT for VOUT ≥3.4 V
(4) The device is not tested under conditions where VIN > VOUT + 1.65 V and IOUT = 1.5 A, because the power dissipation is higher than
the maximum rating of the package. Also, this accuracy specification does not apply on any application condition that exceeds the
power dissipation limit of the package under test.
(5) The device is not tested under conditions where VIN > VOUT + 1.65 V and IOUT = 1.5 A, because the power dissipation is higher than
the maximum rating of the package. Also, this accuracy specification does not apply on any application condition that exceeds the
power dissipation limit of the package under test.
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6.6 Typical Characteristics
at TJ = 25°C, VIN = VOUT(nom) + 0.3 V, VBIAS = 5 V, VEN = VIN, CIN = 10 μF, CBIAS = 1 μF, and COUT = 10 μF (unless
otherwise noted)
CIN = 0 μF, COUT = 10 μF, CBIAS = 1 μF
CIN = 0 μF, COUT = 10 μF, CBIAS = 1 μF
图6-1. PSRR vs Frequency and Overhead (OvHd) Voltage for
图6-2. PSRR vs Frequency and Overhead (OvHd) Voltage for
IOUT = 400 mA, VOUT = 1.8 V
IOUT = 750 mA, VOUT = 1.8 V
CIN = 0 μF, COUT = 10 μF, CBIAS = 1 μF
CIN = 0 μF, COUT = 10 μF, CBIAS = 1 μF
图6-3. PSRR vs Frequency and Overhead (OvHd) Voltage for
图6-4. PSRR vs Frequency and Overhead (OvHd) Voltage for
IOUT = 1.1 A, VOUT = 1.8 V
IOUT = 1.5 A, VOUT = 1.8 V
CIN = 0 μF, COUT = 10 μF, CBIAS = 1 μF, IOUT = 1.5 A
图6-5. PSRR vs Frequency and COUT for VOUT = 1.8 V
CIN = 0 μF, COUT = 10 μF, CBIAS = 1 μF
图6-6. PSRR vs Frequency and IOUT for VOvHd = 200 mV
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6.6 Typical Characteristics (continued)
at TJ = 25°C, VIN = VOUT(nom) + 0.3 V, VBIAS = 5 V, VEN = VIN, CIN = 10 μF, CBIAS = 1 μF, and COUT = 10 μF (unless
otherwise noted)
VIN = VOUT + 0.3 V, CBIAS = 0 μF, CIN = COUT = 10 μF,
CBIAS = 1 μF
CIN = COUT = 10 μF, CBIAS = 1 μF
图6-8. Noise vs Frequency and IOUT for VOUT = 0.65 V
图6-7. Bias Rail PSRR vs Frequency and IOUT
CIN = COUT = 10 μF, CBIAS = 1 μF
CIN = COUT = 10 μF, CBIAS = 1 μF, IOUT = 10 mA to 1.5 A to
10 mA at 1 A/μs
图6-9. Noise vs Frequency and IOUT for VOUT = 3.3 V
图6-10. Load Transient for VOUT = 0.65 V
CIN = COUT = 10 μF, CBIAS = 1 μF, IOUT = 1.5 A,
VIN = 0.95 V to 6 V to 0.95 V at 1 V/μs
CIN = COUT = 10 μF, CBIAS = 1 μF, IOUT = 10 mA to 1.5 A to
10 mA at 1 A/μs
图6-12. Line Transient for VOUT = 0.65 V
图6-11. Load Transient for VOUT = 3.3 V
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6.6 Typical Characteristics (continued)
at TJ = 25°C, VIN = VOUT(nom) + 0.3 V, VBIAS = 5 V, VEN = VIN, CIN = 10 μF, CBIAS = 1 μF, and COUT = 10 μF (unless
otherwise noted)
CIN = COUT = 10 μF, CBIAS = 1 μF, IOUT = 1.5 A,
VIN = 3.9 V to 5.8 V to 3.9 V at 1 V/μs
CIN = COUT = 10 μF, CBIAS = 1 μF, IOUT = 1.5 A, VBIAS = 5 V
图6-14. Input Ramp-Up and Ramp-Down
图6-13. Line Transient for VOUT = 3.3 V
CIN = COUT = 10 μF, CBIAS = 1 μF, IOUT = 1.5 A, VIN = 1.1 V,
CIN = COUT = 10 μF, CBIAS = 1 μF, CSS = 0 nF, VBIAS = 5 V,
VBIAS = 5 V
VEN = 1.1 V
图6-15. Input Ramp With Fast Soft-Start
图6-16. IN Line Regulation for VOUT = 0.65 V, IOUT = 0 A
CIN = COUT = 10 μF, CBIAS = 1 μF, CSS = 0 nF, VBIAS = 5 V,
CIN = COUT = 10 μF, CBIAS = 1 μF, CSS = 0 nF, VBIAS = 5 V,
VEN = 1.1 V
VEN = 1.1 V
图6-17. IN Line Regulation for VOUT = 0.65 V, IOUT = 10 mA
图6-18. IN Line Regulation for VOUT = 0.65 V, IOUT = 1.5 A
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6.6 Typical Characteristics (continued)
at TJ = 25°C, VIN = VOUT(nom) + 0.3 V, VBIAS = 5 V, VEN = VIN, CIN = 10 μF, CBIAS = 1 μF, and COUT = 10 μF (unless
otherwise noted)
CIN = COUT = 10 μF, CBIAS = 1 μF, CSS = 0 nF, VIN = 0.95 V,
CIN = COUT = 10 μF, CBIAS = 1 μF, CSS = 0 nF, VIN = 0.95 V,
VEN = 1.1 V
VEN = 1.1 V
图6-19. BIAS Line Regulation for VOUT = 0.65 V, IOUT = 0 A
图6-20. BIAS Line Regulation for VOUT = 0.65 V,
IOUT = 10 mA
CIN = COUT = 10 μF, CBIAS = 1 μF, CSS = 0 nF, VIN = 0.95 V,
CIN = COUT = 10 μF, CBIAS = 1 μF, CSS = 0 nF, VBIAS = 5 V,
VEN = 1.1 V
VEN = 1.1 V
图6-21. BIAS Line Regulation for VOUT = 0.65 V, IOUT = 1.5 A
图6-22. IN Line Regulation for VOUT = 3.3 V, IOUT = 0 A
CIN = COUT = 10 μF, CBIAS = 1 μF, CSS = 0 nF, VBIAS = 5 V,
CIN = COUT = 10 μF, CBIAS = 1 μF, CSS = 0 nF, VBIAS = 5 V,
VEN = 1.1 V
VEN = 1.1 V
图6-23. IN Line Regulation for VOUT = 3.3 V, IOUT = 10 mA
图6-24. IN Line Regulation for VOUT = 3.3 V, IOUT = 1.5 A
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6.6 Typical Characteristics (continued)
at TJ = 25°C, VIN = VOUT(nom) + 0.3 V, VBIAS = 5 V, VEN = VIN, CIN = 10 μF, CBIAS = 1 μF, and COUT = 10 μF (unless
otherwise noted)
CIN = COUT = 10 μF, CBIAS = 1 μF, CSS = 0 nF,
3.6 V ≤VIN ≤6 V, VEN = 1.1 V
CIN = COUT = 10 μF, CBIAS = 1 μF, CSS = 0 nF,
3.6 V ≤VIN ≤6 V, VEN = 1.1 V
图6-25. BIAS Line Regulation for VOUT = 3.3 V, IOUT = 0 A
图6-26. BIAS Line Regulation for VOUT = 3.3 V, IOUT = 10 mA
CIN = COUT = 10 μF, CBIAS = 1 μF, CSS = 0 nF,
3.6 V ≤VIN ≤6 V, VEN = 1.1 V
CIN = COUT = 10 μF, CBIAS = 1 μF, CSS = 0 nF, VIN = 0.95 V,
2.3 V ≤VBIAS ≤5 V, VEN = 1.1 V
图6-27. BIAS Line Regulation for VOUT = 3.3 V, IOUT = 1.5 A
图6-28. Load Regulation for IOUT = 0 A to Load,
VOUT = 0.65 V
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6.6 Typical Characteristics (continued)
at TJ = 25°C, VIN = VOUT(nom) + 0.3 V, VBIAS = 5 V, VEN = VIN, CIN = 10 μF, CBIAS = 1 μF, and COUT = 10 μF (unless
otherwise noted)
CIN = COUT = 10 μF, CBIAS = 1 μF, CSS = 0 nF, VIN = 0.95 V,
CIN = COUT = 10 μF, CBIAS = 1 μF, CSS = 0 nF, VIN = 0.95 V,
2.3 V ≤VBIAS ≤5 V, VEN = 1.1 V
VBIAS = 5 V, VEN = 1.1 V
图6-29. Load Regulation for IOUT = 0 A to Load, VOUT = 3.3 V
图6-30. Load Regulation for IOUT = 10 mA to Load,
VOUT = 0.65 V
CIN = COUT = 10 μF, CBIAS = 1 μF, CSS = 0 nF, VIN = 0.95 V,
CIN = COUT = 10 μF, CBIAS = 1 μF, CSS = 0 nF, VBIAS = 5 V,
VBIAS = 5 V, VEN = 1.1 V
VEN = 1.1 V
图6-31. Load Regulation for IOUT = 10 mA to Load,
图6-32. Dropout Voltage vs Input Voltage
VOUT = 3.3 V
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6.6 Typical Characteristics (continued)
at TJ = 25°C, VIN = VOUT(nom) + 0.3 V, VBIAS = 5 V, VEN = VIN, CIN = 10 μF, CBIAS = 1 μF, and COUT = 10 μF (unless
otherwise noted)
CIN = COUT = 10 μF, CBIAS = 1 μF, CSS = 0 nF, VBIAS = VIN,
CIN = COUT = 10 μF, CBIAS = 1 μF, CSS = 0 nF, VBIAS = VIN,
VEN = 1.1 V
VEN = 1.1 V
图6-33. Dropout Voltage vs Bias Voltage for IOUT = 0 A
图6-34. Dropout Voltage vs Bias Voltage for IOUT = 50 mA
CIN = COUT = 10 μF, CBIAS = 1 μF, CSS = 0 nF, VBIAS = VIN,
CIN = COUT = 10 μF, CBIAS = 1 μF, CSS = 0 nF, VBIAS = VIN,
VEN = 1.1 V
VEN = 1.1 V
图6-35. Dropout Voltage vs Bias Voltage for IOUT = 500 mA
图6-36. Dropout Voltage vs Bias Voltage for IOUT = 1.5 A
CIN = COUT = 10 μF, CBIAS = 1 μF, CSS = 0 nF, VBIAS = VIN
=
CIN = COUT = 10 μF, CBIAS = 1 μF, CSS = 0 nF, VIN = 0.95 V,
6 V, VOUT = 0.65 V, VEN = 1.5 V, IOUT = 0 A
VEN = 1.1 V
图6-37. Soft-Start Current vs Temperature
图6-38. Current Limit vs Bias Voltage for VOUT = 0.65 V
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6.6 Typical Characteristics (continued)
at TJ = 25°C, VIN = VOUT(nom) + 0.3 V, VBIAS = 5 V, VEN = VIN, CIN = 10 μF, CBIAS = 1 μF, and COUT = 10 μF (unless
otherwise noted)
CIN = COUT = 10 μF, CBIAS = 1 μF, CSS = 0 nF, VIN = 3.6 V,
CIN = COUT = 10 μF, CBIAS = 1 μF, CSS = 0 nF, VEN = 0.4 V
图6-40. Shutdown Current vs Bias Voltage for VIN = 0.95 V
VEN = 1.1 V
图6-39. Current Limit vs Bias Voltage for VOUT = 3.3 V
CIN = COUT = 10 μF, CBIAS = 1 μF, CSS = 0 nF, VEN = 0.4 V
图6-41. Shutdown Current vs Bias Voltage for VIN = 6 V
CIN = COUT = 10 μF, CBIAS = 1 μF, CSS = 0 nF, VBIAS = 6 V
图6-42. Enable Voltage Threshold vs Temperature
CIN = COUT = 10 μF, CBIAS = 1 μF, CSS = 0 nF, VBIAS = 6 V
图6-43. Enable Voltage Hysteresis vs Temperature
CIN = COUT = 10 μF, CBIAS = 1 μF, CSS = 0 nF, VBIAS = 5 V,
1.1 V ≤VEN ≤6 V
图6-44. UVLOIN Voltage Threshold vs Temperature
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6.6 Typical Characteristics (continued)
at TJ = 25°C, VIN = VOUT(nom) + 0.3 V, VBIAS = 5 V, VEN = VIN, CIN = 10 μF, CBIAS = 1 μF, and COUT = 10 μF (unless
otherwise noted)
CIN = COUT = 10 μF, CBIAS = 1 μF, CSS = 0 nF, VBIAS = 5 V,
1.1 V ≤VEN ≤6 V
CIN = COUT = 10 μF, CBIAS = 1 μF, CSS = 0 nF, VBIAS = 5 V,
1.1 V ≤VEN ≤6 V
图6-45. UVLOIN Voltage Hysteresis vs Temperature
图6-46. UVLOBIAS Voltage Threshold vs Temperature
CIN = COUT = 10 μF, CBIAS = 1 μF, CSS = 0 nF, VBIAS = 5 V,
1.1 V ≤VEN ≤6 V
CIN = COUT = 10 μF, CBIAS = 1 μF, CSS = 0 nF, VBIAS = 6 V,
VEN ≤0.4 V
图6-47. UVLOBIAS Voltage Hysteresis vs Temperature
图6-48. Pulldown Resistors vs Temperature
CIN = COUT = 10 μF, CBIAS = 1 μF, CSS = 0 nF, VIN = 6 V,
CIN = COUT = 10 μF, CBIAS = 1 μF, CSS = 0 nF, 0.95 V ≤VIN
VOUT(NOM) = 0.65 V, VBIAS = 6 V, IOUT = 2 mA, VEN = 6 V
≤6 V, VOUT(NOM) = 0.65 V, VBIAS = 6 V, IOUT = 2 mA, VEN = 6
V
图6-49. EN Pin Current vs Temperature
图6-50. FB Pin Current vs Temperature
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6.6 Typical Characteristics (continued)
at TJ = 25°C, VIN = VOUT(nom) + 0.3 V, VBIAS = 5 V, VEN = VIN, CIN = 10 μF, CBIAS = 1 μF, and COUT = 10 μF (unless
otherwise noted)
CIN = COUT = 10 μF, CBIAS = 1 μF, CSS = 0 nF, VIN = 3.6 V,
CIN = COUT = 10 μF, CBIAS = 1 μF, CSS = 0 nF, VIN = 3.6 V,
VOUT = 3.3 V, VEN = 1.1 V
VOUT = 3.3 V, VEN = 1.1 V
图6-51. BIAS Pin Quiescent Current vs Bias Voltage for IOUT
=
图6-52. IN Pin Quiescent Current vs Bias Voltage for
1.5 A
IOUT = 1.5 A
CIN = COUT = 10 μF, CBIAS = 1 μF, CSS = 0 nF, VIN = 3.6 V,
CIN = COUT = 10 μF, CBIAS = 1 μF, CSS = 0 nF, VIN = 3.6 V,
VOUT = 3.3 V, VEN = 1.1 V
VOUT = 3.3 V, VEN = 1.1 V
图6-53. BIAS Pin Quiescent Current vs Bias Voltage for IOUT
=
图6-54. IN Pin Quiescent Current vs Bias Voltage for
10 mA
IOUT = 10 mA
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6.6 Typical Characteristics (continued)
at TJ = 25°C, VIN = VOUT(nom) + 0.3 V, VBIAS = 5 V, VEN = VIN, CIN = 10 μF, CBIAS = 1 μF, and COUT = 10 μF (unless
otherwise noted)
CIN = COUT = 10 μF, CBIAS = 1 μF, CSS = 0 nF, VIN = 3.6 V,
CIN = COUT = 10 μF, CBIAS = 1 μF, CSS = 0 nF, VIN = 3.6 V,
VOUT = 3.3 V, VEN = 1.1 V
VOUT = 3.3 V, VEN = 1.1 V
图6-55. BIAS Pin Quiescent Current vs Bias Voltage for IOUT = 0
图6-56. IN Pin Quiescent Current vs Bias Voltage for
A
IOUT = 0 A
CIN = COUT = 10 μF, CBIAS = 1 μF, CSS = 0 nF, VIN = 3.6 V,
CIN = COUT = 10 μF, CBIAS = 1 μF, CSS = 0 nF, VIN = 3.6 V,
VOUT = 3.3 V, VBIAS = 5 V, VEN = 1.1 V
VOUT = 3.3 V, VBIAS = 5 V, VEN = 1.1 V
图6-57. BIAS Pin Quiescent Current vs Temperature
图6-58. IN Pin Quiescent Current vs Temperature
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7 Detailed Description
7.1 Overview
The TPS7A74 is a low-input, low-output, low-quiescent-current linear regulator optimized to support excellent
transient performance. This regulator uses a low-current bias rail to power all internal control circuitry, allowing
the n-type field effect transistor (NMOS) pass transistor to regulate very-low input and output voltages.
Using an NMOS-pass transistor offers several critical advantages for many applications. Unlike a p-channel
metal-oxide-semiconductor field effect transistor (PMOS) topology device, the output capacitor has little effect on
loop stability. This architecture allows the TPS7A74 to be stable with any ceramic capacitor 10 μF or greater.
Transient response is also superior to PMOS topologies, particularly for low VIN applications.
The TPS7A74 features a programmable voltage-controlled, soft-start circuit that provides a smooth, monotonic
start-up and limits start-up inrush currents that can be caused by large capacitive loads. An enable (EN) pin with
hysteresis and deglitch allows slow-ramping signals to be used for sequencing the device. The low VIN and VOUT
capability allows for inexpensive, easy-to-design, and efficient linear regulation between the multiple supply
voltages often required by processor-intensive systems.
7.2 Functional Block Diagram
OUT
IN
UVLO
VOUT
600 ꢀ
BIAS
UVLO
Thermal &
Current
Limit
20 µA
R1
SS
CSS
Soft-Start
Discharge
0.65-V
Reference
FB
120 ꢀ
Hysteresis
and Deglitch
R2
EN
GND
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7.3 Feature Description
7.3.1 Enable and Shutdown
The enable (EN) pin is active high and compatible with standard digital-signaling levels. Setting VEN below 0.4 V
turns the regulator off, and setting VEN above 1.1 V turns the regulator on. Unlike many regulators, the enable
circuitry has hysteresis and deglitching for use with relatively slowly ramping analog signals. This configuration
allows the device to be enabled by connecting the output of another supply to the EN pin. The enable circuitry
typically has 50 mV of hysteresis and a deglitch circuit to help avoid on-off cycling as a result of small glitches in
the VEN signal.
The enable threshold is typically 0.75 V and varies with temperature and process variations, see 图 6-42.
Temperature variation is approximately –1.2 mV/°C; process variation accounts for most of the rest of the
variation to the 0.4-V and 1.1-V limits. If precise turn-on timing is required, a fast rise-time signal must be used.
If not used, EN can be connected to BIAS. Place the connection as close as possible to the bias capacitor.
7.3.2 Active Discharge
The TPS7A74 has two internal active pulldown circuits: one on the FB pin and one on the OUT pin.
Each active discharge function uses an internal metal-oxide-semiconductor field-effect transistor (MOSFET) that
connects a resistor (RPULLDOWN) to ground when the low-dropout resistor (LDO) is disabled in order to actively
discharge the output voltage. The active discharge circuit is activated when the device is disabled by driving EN
to logic low, when the voltage at IN or BIAS is below the UVLO threshold, or when the regulator is in thermal
shutdown.
The discharge time after disabling the device depends on the output capacitance (COUT) and the load resistance
(RL) in parallel with the pulldown resistor.
The first active pulldown circuit connects the output to GND through a 600-Ω resistor when the device is
disabled.
The second circuit connects FB to GND through a 120-Ω resistor when the device is disabled. This resistor
discharges the FB pin. 方程式 1 calculates the output capacitor discharge time constant when OUT is shorted to
FB, or when the output voltage is set to 0.65 V.
τOUT = (600 || 120 × RL / (600 || 120 + RL) × COUT
(1)
If the LDO is set to an output voltage greater than 0.65 V, a resistor divider network is in place and minimizes the
FB pin pulldown. 方程式2 and 方程式3 calculate the time constants set by these discharge resistors.
RDISCHARGE = (120 || R2) + R1
(2)
(3)
τOUT = RDISCHARGE × RL / (RDISCHARGE + RL) × COUT
Do not rely on the active discharge circuit for discharging a large amount of output capacitance after the input
supply has collapsed because reverse current can flow from the output to the input and can cause damage to
the device. Limit reverse current to no more than 5% of the device-rated current.
See 图6-48 for additional information.
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7.3.3 Global Undervoltage Lockout (UVLO) Circuit
Two undervoltage lockout (UVLO) circuits are present to prevent the TPS7A74 from turning on with an
insufficient rail. One circuit is present on the BIAS pin and the other circuit is on the IN pin. The two UVLO
signals are connected internally through an AND gate, as shown in 图 7-1, that turns off the device when the
voltage on either input is below their respective UVLO thresholds.
In other words, the output is disabled until the IN pin voltage reaches a value greater than UVLOIN and the BIAS
pin voltage reaches a voltage greater than UVLOBIAS
.
UVLO(IN)
Global UVLO
UVLO(BIAS)
图7-1. Global UVLO Circuit
7.3.4 Internal Current Limit
The device has an internal current-limit circuit that protects the regulator during transient high-load current faults
or shorting events. The current limit is a hybrid brick-wall foldback scheme. The current limit transitions from a
brick-wall scheme to a foldback scheme at the foldback voltage (VFOLDBACK). In a high-load current fault with the
output voltage above VFOLDBACK, the brick-wall scheme limits the output current to the current limit (ICL). When
the voltage drops below VFOLDBACK, a foldback current limit activates that scales back the current when the
output voltage approaches GND. When the output is shorted, the device supplies a typical current called the
short-circuit current limit (ISC). ICL and ISC are listed in the Electrical Characteristics table.
For this device, VFOLDBACK is approximately 60% × VOUT(nom)
.
The output voltage is not regulated when the device is in current limit. When a current-limit event occurs, the
device begins to heat up because of the increase in power dissipation. When the device is in a brick-wall current
limit, the pass transistor dissipates power [(VIN –VOUT) × ICL]. When the device output is shorted and the output
is below VFOLDBACK, the pass transistor dissipates power [(VIN – VOUT) × ISC]. If thermal shutdown is triggered,
the device turns off. When the device sufficiently cools down, the internal thermal shutdown circuit turns the
device back on. If the output current fault condition continues, the device cycles between current limit and
thermal shutdown. For more information on current limits, see the Know Your Limits application note. 图 7-2
illustrates a diagram of the foldback current limit.
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VOUT
Brickwall
VOUT(NOM)
VFOLDBACK
Foldback
0 V
IOUT
IRATED
0 mA
ISC
ICL
图7-2. Foldback Current Limit
7.3.5 Thermal Shutdown Protection (TSD
)
The internal thermal shutdown protection circuit disables the output when the thermal junction temperature (TJ )
of the pass transistor rises to the thermal shutdown temperature threshold, TSD(shutdown) (typical). The thermal
shutdown circuit hysteresis ensures that the LDO resets (turns on) when the temperature falls to TSD(reset) (typical)
.
The thermal time constant of the semiconductor die is fairly short; thus, the device may cycle on and off when
thermal shutdown is reached until the power dissipation is reduced. Power dissipation during start up can be
high from large VIN – VOUT voltage drops across the device or from high inrush currents charging large output
capacitors. Under some conditions, the thermal shutdown protection disables the device before start up
completes.
For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating
Conditions table. Operation above this maximum temperature causes the device to exceed operational
specifications. Although the internal protection circuitry is designed to protect against thermal overload
conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the regulator into
thermal shutdown, or above the maximum recommended junction temperature, reduces long-term reliability.
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7.4 Device Functional Modes
表 7-1 shows the conditions that lead to the different modes of operation. See the Electrical Characteristics table
for parameter values.
表7-1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN
VBIAS
VEN
IOUT
TJ
VIN ≥VOUT (nom) + VDO
and VIN ≥VIN(min)
TJ < TSD for
shutdown
V
BIAS ≥VOUT +
VDO(BIAS)
Normal mode
Dropout mode
IOUT < ICL
VEN ≥VHI(EN)
VIN(min) < VIN < VOUT
(nom) + VDO(IN)
TJ < TSD for
shutdown
VBIAS < VOUT + VDO(BIAS)
VEN > VHI(EN)
IOUT < ICL
Disabled mode
(any true condition
disables the device)
TJ ≥TSD for
shutdown
VIN < VUVLO(IN)
VBIAS < VBIAS(UVLO)
VEN < VLO(EN)
—
7.4.1 Normal Operation
The device regulates to the nominal output voltage when the following conditions are met:
• The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO
)
• The bias voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO
• The output current is less than the current limit (IOUT < ICL)
)
• The device junction temperature is less than the thermal shutdown temperature ( TJ < TSD(shutdown)
)
• The enable voltage has previously exceeded the enable rising threshold voltage and has not yet decreased
to less than the enable falling threshold
7.4.2 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. Similarly, if the bias voltage is
lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for
normal operation, the device operates in dropout mode as well. In this mode, the output voltage tracks the input
voltage. During this mode, the transient performance of the device becomes significantly degraded because the
pass transistor is in the ohmic or triode region, and functions as a switch. Line or load transients in dropout can
result in large output voltage deviations.
When operating in dropout, the ground current may increase. For dropout operation and the effect on the IN and
BIAS current, see 图6-51 to 图6-56.
When the device is in a steady dropout state, defined as when the device is in dropout, (VIN < VOUT + VDO or
VBIAS < VOUT + VDO directly after being in normal regulation state, but not during start up), the pass transistor is
driven into the ohmic or triode region. When the input voltage returns to a value greater than or equal to the
nominal output voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short
time when the device pulls the pass transistor back into the linear region.
7.4.3 Disabled
The output of the device can be shutdown by forcing the voltage of the enable pin to less than VIL(EN) (see the
Electrical Characteristics table). When disabled, the pass transistor is turned off, internal circuits are shutdown,
and the output voltage is actively discharged to ground by an internal discharge circuit from the output to ground.
The device is disabled under the following conditions:
• The input or bias voltages are below the respective minimum specifications
• The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising
threshold
• The device junction temperature is greater than the thermal shutdown temperature
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7.5 Programming
7.5.1 Programmable Soft-Start
The TPS7A74 features a programmable, monotonic, voltage-controlled soft-start that is set with an external
capacitor (CSS). This feature is important for many applications because the soft-start eliminates power-up
initialization problems when powering FPGAs, DSPs, or other processors. The controlled voltage ramp of the
output also reduces peak inrush current during start-up, minimizing start-up transient events to the input power
bus.
To achieve a linear and monotonic soft-start, the error amplifier tracks the voltage ramp of the external soft-start
capacitor until the voltage exceeds the internal reference. The soft-start ramp time depends on the soft-start
charging current (ISS), soft-start capacitance (CSS), and the internal reference voltage (VREF). 方程式4 calculates
the soft-start ramp time.
(VREF ´ CSS
)
tSS
=
ISS
(4)
If large output capacitors are used, the device current limit (ICL) and the output capacitor may set the start-up
time. The start-up time is given by 方程式5 in this case.
(VOUT(NOM) ´ COUT
)
tSSCL
=
ICL(MIN)
(5)
where:
• VOUT(nom) is the nominal output voltage
• COUT is the output capacitance
• ICL(min) is the minimum current limit for the device
In applications where monotonic start up is required, the soft-start time given by 方程式 4 must be set greater
than 方程式5.
The maximum recommended soft-start capacitor is 15 nF. Larger soft-start capacitors can be used and do not
damage the device; however, the soft-start capacitor discharge circuit may not be able to fully discharge the soft-
start capacitor when enabled. Soft-start capacitors larger than 15 nF can be a problem in applications where the
enable pin must be rapidly pulsed and the device must soft-start from ground. CSS must be low-leakage; X7R,
X5R, or C0G dielectric materials are preferred. 表7-2 lists suggested soft-start capacitor values.
表7-2. Standard Capacitor Values for Programming the Soft-Start Time(1)
CSS
Open
1 nF
SOFT-START TIME
0.1 ms
0.032 ms
5.6 nF
10 nF
0.182 ms
0.325 ms
V
∂C
0.65V∂C (F)
REF SS
I
SS
t
(s)=
SS
=
20ꢀA
SS
(1)
, where tSS(s) = soft-start time in seconds.
Another option to set the start-up rate is to use a feedforward capacitor; see the Pros and Cons of Using a
Feedforward Capacitor with a Low-Dropout Regulator application note for more information.
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7.5.2 Sequencing Requirements
VIN, VBIAS, and VEN can be sequenced in any order without causing damage to the device. However, for the soft-
start function to work as intended, certain sequencing rules must be applied. Connecting EN to IN is acceptable
for most applications, as long as VIN is greater than 1.1 V and the ramp rate of VIN and VBIAS is faster than the
set soft-start ramp rate.
There are several different start-up responses that are possible, but not typical:
• If the ramp rate of the input sources is slower than the set soft-start time, the output tracks the slower supply
minus the dropout voltage until reaching the set output voltage
• If EN is connected to BIAS, the device soft-starts as programmed, provided that VIN is present before VBIAS
• If VBIAS and VEN are present before VIN is applied and the set soft-start time has expired, then VOUT tracks
VIN
• If the soft-start time has not expired, the output tracks VIN until VOUT reaches the value set by the charging
soft-start capacitor
图 7-3 shows the use of an RC-delay circuit to hold off VEN until VBIAS has ramped. This technique can also be
used to drive EN from VIN. An external control signal can also be used to enable the device after VIN and VBIAS
are present.
VIN
IN
VOUT
OUT
FB
R1
R2
CIN
COUT
BIAS
TPS7A74
R
C
VBIAS
EN
SS
GND
CBIAS
CSS
图7-3. Soft-Start Delay Using an RC Circuit to Enable the Device
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8 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The TPS7A74 is a low-input, low-output (LILO) low-dropout regulator (LDO) that feature soft-start capability. This
regulator uses a low-current bias input to power all internal control circuitry, allowing the NMOS pass transistor to
regulate very low input and output voltages.
The use of an NMOS pass transistor offers several critical advantages for many applications. Unlike a PMOS
topology device, the output capacitor has little effect on loop stability. This architecture allows stability with
ceramic capacitors of 10 μF or greater. Transient response is also superior to PMOS topologies, particularly for
low VIN applications.
A programmable voltage-controlled, soft-start circuit provides a smooth, monotonic start-up and limits start-up
inrush currents that can be caused by large capacitive loads. An enable (EN) pin with hysteresis and deglitch
allows slow-ramping signals to be used for sequencing the device. The low VIN and VOUT capability allows for
inexpensive, easy-to-design, and efficient linear regulation between the multiple supply voltages often required
by processor-intensive systems.
8.1.1 Adjusting the Output Voltage
图8-1 shows the typical application circuit for the adjustable output device.
VIN
IN
VOUT
OUT
FB
R1
R2
10 µF
10 µF
BIAS
TPS7A74
VBIAS
EN
SS
GND
1 µF
10 nF
图8-1. Typical Application Circuit for the TPS7A74 (Adjustable)
R1 and R2 can be calculated for any output voltage using the formula shown in 图 8-1. 表 8-1 lists sample
resistor values of common output voltages. In order to achieve the maximum accuracy specifications, R2 must
be ≤4.99 kΩ.
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表8-1. Standard 1% Resistor Values for Programming the Output Voltage(1)
Targeted VOUT (V)
R1 (kΩ)
Short
0.768
2.43
R2 (kΩ)
Open
4.99
4.53
4.42
4.99
4.99
3.83
2.80
1.74
1.21
0.65
0.75
1.00
1.05
1.10
1.20
1.50
1.80
2.51
3.33
2.72
3.48
4.22
4.99
4.99
4.99
4.99
(1) VOUT = 0.65 × (1 + R1 / R2).
备注
When VBIAS and VEN are present and VIN is not supplied, this device outputs approximately 50 μA of
current from OUT. Although this condition does not cause any damage to the device, the output
current can charge the OUT node if total resistance between OUT and GND (including external
feedback resistors) is greater than 10 kΩ.
Because this LDO has a relatively low quiescent current of 50 μA, some applications may benefit from using
larger R1 and R2 resistor values. In such cases where resistor values greater than 5 kΩ are considered, adding a
Cff capacitor across R1 may help improve stability.
8.1.2 Input, Output, and Bias Capacitor Requirements
The device is designed to be stable for ceramic capacitor of values ≥ 10 μF. The device is also stable with
multiple capacitors in parallel, which can be of any type or value.
The capacitance required on the IN and BIAS pins strongly depends on the input supply source impedance. To
counteract any inductance in the input, the minimum recommended capacitor for VIN is 1 μF and the minimum
recommended capacitor for VBIAS is 0.1 µF. If VIN and VBIAS are connected to the same supply, the
recommended minimum capacitor for VBIAS is 4.7 μF. Use good quality, low equivalent series resistance (ESR)
and equivalent series inductance (ESL) capacitors on the input; ceramic X5R and X7R capacitors are preferred.
Place these capacitors as close the pins as possible for optimum performance.
Low ESR and ESL capacitors improve high-frequency PSRR.
8.1.3 Transient Response
The TPS7A74 is designed to have excellent transient response for most applications with a small amount of
output capacitance. In some cases, the transient response can be limited by the transient response of the input
supply. This limitation is especially true in applications where the difference between the input and output is less
than 300 mV. In this case, adding additional input capacitance improves the transient response more than just
adding additional output capacitance. With a solid input supply, adding additional output capacitance reduces
undershoot and overshoot during a transient event; see 图 6-10 in the Typical Characteristics section. Because
the TPS7A74 is stable with output capacitors as low as 10 μF, many applications may then need very little
capacitance at the LDO output. For these applications, local bypass capacitance for the powered device may be
sufficient to meet the transient requirements of the application. This design reduces the total solution cost by
avoiding the need to use expensive, high-value capacitors at the LDO output.
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8.1.4 Dropout Voltage
The TPS7A74 offers very low dropout performance, making the device well-suited for high-current, low VIN and
low VOUT applications. The low dropout allows the device to be used in place of a dc/dc converter and still
achieve good efficiency. 方程式6 provides a quick estimate of the efficiency.
V
OUT ´ IOUT
VOUT
VIN
at IOUT >> IQ
»
Efficiency »
VIN ´ (IIN + IQ)
(6)
This efficiency provides designers with the power architecture for their applications to achieve the smallest,
simplest, and lowest cost solutions.
For this architecture, there are two different specifications for dropout voltage. The first specification (see 图 8-2)
is referred to as VIN dropout and is used when an external bias voltage is applied to achieve low dropout. This
specification assumes that VBIAS is at least 2.8 V above VOUT, which is the case for VBIAS when powered by a
5.0-V rail with 5% tolerance and with VOUT = 1.5 V. If VBIAS is higher than VOUT + 2.8 V, the VIN dropout is less
than specified.
备注
2.8 V is a test condition of this device and can be adjusted by referring to the Electrical Characteristics
table.
The second specification (illustrated in 图 8-2) is referred to as VBIAS dropout and applies to applications where
IN and BIAS are tied together. This option allows the device to be used in applications where an auxiliary bias
voltage is not available or low dropout is not required. Dropout is limited by BIAS in these applications because
VBIAS provides the gate drive to the pass transistor; therefore, VBIAS must be 1.3 V above VOUT. Because of this
usage, having IN and BIAS tied together become a highly inefficient solution that can consume large amounts of
power. Pay attention not to exceed the power rating of the device package.
8.1.5 Output Noise
The TPS7A74 provides low output noise when a soft-start capacitor is used. When the device reaches the end of
the soft-start cycle, the soft-start capacitor serves as a filter for the internal reference. By using a 1-nF, soft-start
capacitor, the output noise is reduced by half and is typically 7.1 μVRMS for a 0.65-V output (10 Hz to 100 kHz).
Further increasing CSS has little effect on noise. Because most of the output noise is generated by the internal
reference, the noise is a function of the set output voltage. 方程式 7 gives the RMS noise with a 1-nF, soft-start
capacitor:
ꢀV
≈
∆
∆
«
’
÷
÷
◊
RMS
V
V ( ꢀVRMS ) = 7.1∂
∂VOUT (V)
N
(7)
The low output noise makes this LDO a good choice for powering transceivers, phase-locked loops (PLLs), or
other noise-sensitive circuitry.
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8.1.6 Estimating Junction Temperature
By using the thermal metrics ΨJT and ΨJB, as shown in the Thermal Information table, the junction temperature
can be estimated with corresponding formulas (given in 方程式 8). For backwards compatibility, an older θJC(top)
parameter is listed as well.
YJT: TJ = TT + YJT · PD
YJB: TJ = TB + YJB · PD
(8)
Where PD is the power dissipation shown by 方程式 9, TT is the temperature at the center-top of the package,
and TB is the PCB temperature measured 1 mm away from the package on the PCB surface.
备注
Both TT and TB can be measured on actual application boards using a thermo-gun (an infrared
thermometer).
For more information about measuring TT and TB, see the Using New Thermal Metrics application note,
available for download at www.ti.com.
For a more detailed discussion of why TI does not recommend using θJC(top) to determine thermal
characteristics, see the Using New Thermal Metrics application note, available for download at www.ti.com. For
further information, see the Semiconductor and IC Package Thermal Metrics application note, also available on
the TI website.
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8.2 Typical Application
8.2.1 FPGA I/O Supply at 1.8 V With a Bias Rail
VBIAS
VIN
CBIAS
CIN
VBIAS = 5V ±5%
VIN = 2.1V
VOUT = 1.8V
IOUT = 1.5A
IN
BIAS
Efficiency = 83.3%
Reference
+
VOUT
OUT
COUT
EN
SS
R1
FB
Simplified Block Diagram
R2
CSS
图8-2. Typical Application Using an Auxiliary Bias Rail
8.2.1.1 Design Requirements
This application powers the I/O rails of an FPGA , at VOUT(nom) = 1.8 V and IOUT(dc) = 1.5 A. The available
external supply voltages are 2.1 V, 3.3 V, and 5 V.
表8-2 lists the parameters for this design example.
表8-2. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
VIN
2.1 V
2.4 V to 5.5 V
VBIAS
VOUT
IOUT
1.8 V
600 mA (typical), 900 mA (peak)
8.2.1.2 Detailed Design Procedure
First, determine what supplies to use for the input and bias rails. A 2.1-V input can be stepped down to 1.5 V at
1.5 A if an external bias is provided, because the maximum dropout voltage is 180 mV if VBIAS is at least 2.8 V
higher than VOUT. To achieve this voltage step, the bias rail is supplied by the 5-V supply. The approximation in
方程式6 estimates the efficiency at 83.3%.
The output voltage then must be set to 1.5 V. As 表 8-1 describes, set R1 = 4.99 kΩand R2 = 3.82 kΩto obtain
the required output voltage. The minimum capacitor sizing requires the total solution size footprint to be reduced;
see the Input, Output, and Bias Capacitor Requirements section for CIN = 1 µF, CBIAS = 1 µF, and COUT = 2.2 µF.
Use CSS = 1 nF for a typical 0.032-ms start-up time.
图8-2 shows a simplified version of the final circuit.
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8.2.1.3 Application Curves
CIN = COUT = 10 μF, CBIAS = 1 μF, VIN = 2.1 V, VBIAS = 6 V
CIN = COUT = 10 μF, CBIAS = 1 μF, VBIAS = 5 V, VIN = 2.1 V
to 3.5 V to 6 V, IOUT = 1.5 A
to 4.1 V to 2.1 V, IOUT = 1.5 A
图8-3. VBIAS Line Transient
图8-4. VIN Line Transient
CIN = COUT = 10 μF, CBIAS = 1 μF, VBIAS = 5 V, VIN = 2.1 V,
CIN = COUT = 10 μF, CBIAS = 1 μF, VBIAS = 5 V, VIN = 2.1 V,
IOUT = 0 mA
IOUT = 10 mA to 1.5 A to 10 mA
图8-6. Turn-On Response
图8-5. Output Load Transient Response
8.3 Power Supply Recommendations
The TPS7A74 is designed to operate from an input voltage up to 6.0 V, provided the bias rail is at least 1.3 V
higher than the input supply and dropout requirements are met. The bias rail and the input supply must both
provide adequate headroom and current for the device to operate normally. Connect a low output impedance
power supply directly to the IN pin. This supply must have at least 1 μF of capacitance near the IN pin for
optimal performance. A supply with similar requirements must also be connected directly to the bias rail with a
separate 1 μF or larger capacitor. If the IN pin is tied to the bias pin, a minimum 4.7-μF capacitor is required for
performance. To increase the overall PSRR of the solution at higher frequencies, use a pi-filter or ferrite bead
before the input capacitor.
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8.4 Layout
8.4.1 Layout Guidelines
An optimal layout can greatly improve transient performance, PSRR, and noise. To minimize the voltage drop on
the input of the device during load transients, the capacitance on IN and BIAS must be connected as close as
possible to the device. This capacitance also minimizes the effects of parasitic inductance and resistance of the
input source and can, therefore, improve stability. To achieve optimal transient performance and accuracy, the
top side of R1 in 图 8-1 must be connected as close as possible to the load. If BIAS is connected to IN, connect
BIAS as close to the sense point of the input supply as possible. This connection minimizes the voltage drop on
BIAS during transient conditions and can improve the turn-on response.
Knowing the device power dissipation and proper sizing of the thermal plane that is connected to the thermal
pad is critical to avoiding thermal shutdown and ensuring reliable operation. Power dissipation (PD) of the device
depends on input voltage and load conditions. 方程式9 calculates PD.
PD = (VIN - VOUT) ´ IOUT
(9)
Power dissipation can be minimized and greater efficiency can be achieved by using the lowest possible input
voltage necessary to achieve the required output voltage regulation.
On the WSON (DSD) package, the primary conduction path for heat is through the exposed pad to the printed
circuit board (PCB). The pad can be connected to ground or left floating; however, this pad must be attached to
an appropriate amount of copper PCB area to ensure the device does not overheat. The maximum junction-to-
ambient thermal resistance depends on the maximum ambient temperature, maximum device junction
temperature, and power dissipation of the device. 方程式 10 calculates the maximum junction-to-ambient
thermal resistance.
(+125°C - TA)
RqJA
=
PD
(10)
备注
When the device is mounted on an application PCB, TI strongly recommends using ΨJT and ΨJB, as
explained in the Estimating Junction Temperature section.
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8.4.1.1 Estimating Junction Temperature
By using the thermal metrics ΨJT and ΨJB, as shown in the Thermal Information table, the junction temperature
can be estimated with corresponding formulas (given in 方程式 11). For backwards compatibility, an older
θJC(top) parameter is listed as well.
YJT: TJ = TT + YJT · PD
YJB: TJ = TB + YJB · PD
(11)
Where PD is the power dissipation shown by 方程式 9, TT is the temperature at the center-top of the package,
and TB is the PCB temperature measured 1 mm away from the package on the PCB surface.
备注
Both TT and TB can be measured on actual application boards using a thermo-gun (an infrared
thermometer).
For more information about measuring TT and TB, see the Using New Thermal Metrics application note,
available for download at www.ti.com.
For a more detailed discussion of why TI does not recommend using θJC(top) to determine thermal
characteristics, see the Using New Thermal Metrics application note, available for download at www.ti.com. For
further information, see the Semiconductor and IC Package Thermal Metrics application note, also available on
the TI website.
8.4.2 Layout Example
TOP View
CBIAS
GND Plane
BIAS
GND
BIAS
EN
SS
R2
FB
CFF
R1
OUT
OUT
Thermal vias
GND Plane
CSS
IN
COUT
CIN
Represents a via
图8-7. Example Layout (DSD Package)
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9 Device and Documentation Support
9.1 Device Support
9.1.1 Development Support
9.1.1.1 Evaluation Modules
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the
TPS7A74. The evaluation module(and related user guide user's guide) can be requested at the Texas
Instruments website through the product folders or purchased directly from the TI eStore.
9.1.1.2 Spice Models
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of
analog circuits and systems. A SPICE model for the TPS7A74 is available through the product folders under
Tools & Software.
9.2 Documentation Support
9.2.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Using New Thermal Metrics application note
• Texas Instruments, Semiconductor and IC Package Thermal Metrics application note
• Texas Instruments, Ultimate Regulation with Fixed Output Versions of TPS742xx, TPS743xx, and TPS744xx
application note
• Texas Instruments, Pros and Cons of Using a Feed-Forward Capacitor with a Low Dropout Regulator
application note
• Texas Instruments, TPS74701EVM-177 and TPS74801EVM-177 user's guide
9.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
9.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
9.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
9.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
13-Sep-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS7A7401DSDR
ACTIVE
SON
DSD
8
5000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7A7401
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Sep-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS7A7401DSDR
SON
DSD
8
5000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Sep-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SON DSD
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
TPS7A7401DSDR
8
5000
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DSD 8
3 X 3, 0.8 mm pitch
WSON - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4227007/A
www.ti.com
PACKAGE OUTLINE
DSD0008B
WSON - 0.8 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
3.1
2.9
PIN 1 INDEX AREA
0.8 MAX
SEATING PLANE
0.05 C
0.05
0.00
1.75
1.55
(0.12) TYP
EXPOSED
THERMAL PAD
4
5
2X
2.5
2.3
1.95
8
1
6X 0.65
0.36
0.26
8X
0.45
0.35
PIN 1 ID
8X
0.1
C A B
C
(OPTIONAL)
0.05
4226923/A 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DSD0008B
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
SYMM
8X (0.6)
1
8
8X (0.31)
(2.4)
(0.95)
6X (0.65)
4
5
(R0.05) TYP
(0.575)
(2.8)
(
0.2) VIA
TYP
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4226923/A 06/2021
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
DSD0008B
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
METAL
TYP
8X (0.6)
1
8
8X (0.31)
(0.635)
SYMM
(1.07)
6X (0.65)
5
4
(R0.05) TYP
(1.47)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
82% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4226923/A 06/2021
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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