TPS7A8101-Q1 [TI]
具有使能功能的汽车类、1A、高 PSRR、可调节低压降稳压器;
| 型号： | TPS7A8101-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有使能功能的汽车类、1A、高 PSRR、可调节低压降稳压器 稳压器 |
| 文件： | 总28页 (文件大小：1331K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS7A8101-Q1
ZHCSBR4A –APRIL 2014–REVISED JUNE 2014
TPS7A8101-Q1 低噪声、宽带宽、高电源抑制比 (PSRR)，
低压降 1A 线性稳压器
1 特性
2 应用范围
1
•
•
符合汽车应用要求
具有符合 AEC-Q100 的下列结果：
•
•
汽车应用中的射频 (RF) 电源
汽车用高级驾驶员辅助系统 (ADAS) 电子控制单元
(ECU)
–
–
–
器件温度 1 级：-40°C 至 125°C 的环境运行温
度范围
•
•
•
远程信息处理控制单元
音频
器件人体模型 (HBM) 静电放电 (ESD) 分类等级
H2
高速接口 (I/F)（锁相环 (PLL) 和压控振荡器
(VCO)）
器件充电器件模型 (CDM) ESD 分类等级 C4B
•
•
•
具有使能功能的低压降 1A 稳压器
可调节输出电压：0.8V 至 6V
宽带宽高 PSRR：
3 说明
TPS7A8101-Q1 低压降线性稳压器 (LDO) 在输出噪声
情况下可提供极佳的性能和电源抑制比 (PSRR)。 这
款 LDO 使用一个先进的双极 CMOS (BiCMOS) 工艺
和一个功率金属氧化物半导体场效应晶体管
(PMOSFET) 无源器件来实现极低噪音、出色瞬态响应
和极佳的 PSRR 性能。
–
–
–
1kHz 时为 80dB
100kHz 时为 60dB
1MHz 时为 54dB
•
低噪音：23.5μVRMS典型值 (100Hz 至
100kHz)
•
•
•
•
•
•
在使用 4.7μF 输出电容时保持稳定
出色的负载和线路瞬态响应
TPS7A8101-Q1 器件与 4.7μF 陶瓷输出电容器一起工
作时保持稳定，并使用一个精确电压基准和反馈环路在
所有负载、线路、过程和温度变化范围内实现至少 3%
的精度。
总体精度 3%（在负载、线路、温度范围内）
过流和过温保护
极低压降：1A 时的典型值为 170mV
这款器件在 TA = -40°C 至 +125°C 的温度范围完全额
定运行，并采用装有散热焊盘的
封装方式：3mm x 3mm 小外形尺寸无引线 (SON)-
8
3mm x 3mm SON-8 封装。
器件信息(1)
产品型号
封装
SON (8)
封装尺寸（标称值）
TPS7A8101-Q1
3.00mm x 3.00mm
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
4 典型应用电路
VI
VO
典型电源纹波抑制
IN
OUT
C(IN)
C(BYPASS)
100
90
80
70
60
50
R1
R2
TPS7A8101-Q1
EN
FB/SNS
NR
C(OUT)
GND
C(NR)
V(EN)
40
IO = 10 mA
30
IO = 100 mA
IO = 750 mA
20
IO = 1 A
10
10
100
1k
10k
100k
1M
10M
G103
Frequency (Hz)
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SLVSCK0
TPS7A8101-Q1
ZHCSBR4A –APRIL 2014–REVISED JUNE 2014
www.ti.com.cn
目录
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 12
Application and Implementation ........................ 13
9.1 Application Information............................................ 13
9.2 Typical Application .................................................. 13
1
2
3
4
5
6
7
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
典型应用电路 ........................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 Handling Ratings....................................................... 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 4
7.5 Electrical Characteristics........................................... 5
7.6 Typical Characteristics.............................................. 6
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 11
9
10 Power Supply Recommendations ..................... 17
11 Layout................................................................... 17
11.1 Layout Guidelines ................................................. 17
11.2 Layout Example .................................................... 17
11.3 Thermal Information.............................................. 18
12 器件和文档支持 ..................................................... 21
12.1 文档支持................................................................ 21
12.2 Trademarks........................................................... 21
12.3 Electrostatic Discharge Caution............................ 21
12.4 术语表 ................................................................... 21
13 机械封装和可订购信息 .......................................... 21
8
5 修订历史记录
Changes from Original (April 2014) to Revision A
Page
•
已更改 器件状态从 产品预览 更改为 生产数据 ....................................................................................................................... 1
2
Copyright © 2014, Texas Instruments Incorporated
TPS7A8101-Q1
www.ti.com.cn
ZHCSBR4A –APRIL 2014–REVISED JUNE 2014
6 Pin Configuration and Functions
8-Pin SON
DRB Package
(Top View)
OUT
OUT
1
2
3
4
8
7
6
5
IN
IN
FB/SNS
GND
FNBR/SNS
EN
Pin Functions
PIN
DESCRIPTION
NAME
NO.
Driving this pin high turns on the regulator. Driving this pin low puts the regulator into shutdown mode. See
to the Shutdown section for more details. The EN pin must not be left floating and can be connected to the
IN pin if not used.
EN
5
FB/SNS
GND
3
4
7
8
This pin is the input to the error amplifier and is used to set the output voltage of the device.
Ground
IN
Unregulated input supply
Connect an external capacitor between this pin and ground to reduce output noise to very low levels. The
capacitor also slows down the VO ramp (RC soft start).
NR
6
1
2
OUT
Regulator output. A 4.7-μF or larger ceramic capacitor is required for stability.
Thermal Pad
—
The Thermal Pad should be connected to GND.
Copyright © 2014, Texas Instruments Incorporated
3
TPS7A8101-Q1
ZHCSBR4A –APRIL 2014–REVISED JUNE 2014
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted).(1)
MIN
–0.3
–0.3
–0.3
–0.3
MAX
UNIT
V
IN
7
FB/SNS, NR
3.6
VI + 0.3(2)
7
V
Voltage
EN
V
OUT
V
Current
OUT
Internally Limited
A
Operating junction temperature, TJ
–55
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-
maximum-rated conditions for extended periods my affect device reliability.
(2) V(EN) absolute maximum rating is VI + 0.3 V or + 7 V, whichever is smaller.
7.2 Handling Ratings
MIN
–55
–2
MAX
150
2
UNIT
°C
Tstg
Storage temperature range
Human body model (HBM), per AEC Q100-002, classification level H2(1)
kV
Electrostatic
discharge
Corner pins
(1, 4, 5, and 8)
V(ESD)
–750
–500
750
500
Charged device model (CDM), per JEDEC
specification JESD22-C101, classification level C4B
V
Other pins
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 Specification.
7.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VI
IO
TA
Input voltage
2.2
0
6.5
1
V
A
Output current
Operating free air temperature
–40
125
°C
7.4 Thermal Information
DRB
(8 PINS)
45.7
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
53.1
21.2
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.9
ψJB
21.4
RθJC(bot)
5.2
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A.
4
Copyright © 2014, Texas Instruments Incorporated
TPS7A8101-Q1
www.ti.com.cn
ZHCSBR4A –APRIL 2014–REVISED JUNE 2014
7.5 Electrical Characteristics
Over the temperature range of –40°C ≤ TA, TJ ≤ 125°C, VI = VOnom + 0.5 V or 2.2 V (whichever is greater), IO = 1 mA, V(EN)
=
2.2 V, C(OUT) = 4.7 μF, C(NR) = 0.01 μF, and C(BYPASS) = 0 μF, unless otherwise noted. The device is tested at VO = 0.8 V and
VO = 6 V. Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
2.2
TYP
MAX
6.5
UNIT
VI
Input voltage range(1)
Internal reference
Output voltage range
V
V
V
V(NR)
0.79
0.8
0.8
0.81
6
VO + 0.5 V ≤ VI ≤ 6 V, VI ≥ 2.5 V,
100 mA ≤ IO ≤ 500 mA, 0°C ≤ TJ ≤ 85°C
–2%
–3%
2%
3%
VO
Output accuracy(2)
VO + 0.5 V ≤ VI ≤ 6.5 V, VI ≥ 2.2 V,
100 mA ≤ IO ≤ 1 A
±0.3%
VOnom + 0.5 V ≤ VI ≤ 6.5 V, VI ≥ 2.2 V,
IO = 100 mA
ΔVO(ΔVI)
ΔVO(ΔIL)
Line regulation
Load regulation
150
2
μV/V
μV/mA
mV
100 mA ≤ IO ≤ 1 A
VO + 0.5 V ≤ VI ≤ 6.5 V, VI ≥ 2.2 V,
IO = 500 mA, V(FB/SNS) = GND
250
350
500
VO + 0.5 V ≤ VI ≤ 6.5 V, VI ≥ 2.5 V,
IO = 750 mA, V(FB/SNS) = GND
VDO
Dropout voltage(3)
mV
mV
VO + 0.5 V ≤ VI ≤ 6.5 V, VI ≥ 2.5 V,
IO = 1 A, V(FB/SNS) = GND
IL
Output current-limit
Ground pin current
VO = 0.85 × VOnom, VI ≥ 3.3 V
IO = 1 mA
1100
1400
60
2000
100
mA
μA
μA
I(GND)
IO = 1 A
350
V
(EN) ≤ 0.4 V, VI ≥ 2.2 V, RL = 1 kΩ,
IL(sd)
Shutdown current (I(GND)
)
0.2
2.5
1
μA
0°C ≤ TJ ≤ 125°C
I(FB/SNS)
Feedback pin current
VI = 6.5 V, V(FB/SNS) = 0.8 V
0.02
80
μA
dB
dB
dB
dB
dB
ƒ = 100 Hz
ƒ = 1 kHz
82
VI = 4.3 V, VO = 3.3 V,
IO = 750 mA
PSRR
Power-supply rejection ratio
ƒ = 10 kHz
ƒ = 100 kHz
ƒ = 1 MHz
78
60
54
BW = 100 Hz to 100 kHz,
VI = 3.8 V, VO = 3.3 V,
Vn
Output noise voltage
Enable high (enabled)
23.5
μVRMS
IO = 100 mA, C(NR) = C(BYPASS) = 470 nF
2.2 V ≤ VI ≤ 3.6 V, RL = 1 kΩ
3.6 V < VI ≤ 6.5 V, RL = 1 kΩ
RL = 1 kΩ
1.2
1.35
0
V
V
V(EN)H
V(EN)L
I(EN)
Enable low (shutdown)
0.4
1
V
Enable pin current, enabled
VI = V(EN) = 6.5 V
0.02
80
μA
VOnom = 3.3 V, VO = 0% to 90% VOnom
R1 = 3.3 kΩ, C(OUT) = 10 μF, C(NR) = 470 nF
,
tst
Startup time
ms
Undervoltage lockout
Hysteresis
VI rising, RL = 1 kΩ
1.86
2
75
2.1
V
UVLO
VI falling, RL = 1 kΩ
mV
°C
°C
Shutdown, temperature increasing
Reset, temperature decreasing
160
140
Tsd
Thermal shutdown temperature
(1) Minimum VI = VO + VDO or 2.2 V, whichever is greater.
(2) The TPS7A8101-Q1 does not include external resistor tolerances and it is not tested at this condition: VO = 0.8 V, 4.5 V ≤ VI ≤ 6.5 V,
and 750 mA ≤ IO ≤ 1 A because the power dissipation is greater than the maximum rating of the package.
(3) VDO is not measured for fixed output voltage devices with VO < 1.7 V because minimum VI = 2.2 V.
Copyright © 2014, Texas Instruments Incorporated
5
TPS7A8101-Q1
ZHCSBR4A –APRIL 2014–REVISED JUNE 2014
www.ti.com.cn
7.6 Typical Characteristics
At VOnom = 3.3 V, VI = VOnom + 0.5 V or 2.2 V (whichever is greater), IO = 100 mA, V(EN) = VI, C(IN) = 1 μF, C(OUT) = 4.7 μF, and C(NR) = 0.01
μF; all temperature values refer to TJ, unless otherwise noted.
3.399
3.366
3.333
3.3
3.399
3.366
3.333
3.3
125°C
85°C
25°C
0°C
125°C
85°C
25°C
0°C
–40°C
–40°C
3.267
3.234
3.201
3.267
3.234
3.201
0
100 200 300 400 500 600 700 800 900 1000
Output Current (mA)
0
5
10
15
20
25
Output Current (mA)
NOTE: The Y-axis shows 1% VO per division
NOTE: The Y-axis shows 1% VO per division
Figure 1. Load Regulation
Figure 2. Load Regulation Under Light Loads
0.824
0.816
0.818
0.8
0.824
0.816
0.808
0.8
125°C
85°C
25°C
0°C
125°C
85°C
25°C
0°C
–40°C
–40°C
0.792
0.784
0.776
0.792
0.784
0.776
2.2 2.6
3
3.4 3.8 4.2 4.6
5
5.4 5.8 6.2 6.6
2.2 2.6
3
3.4 3.8 4.2 4.6
5
5.4 5.8 6.2 6.6
Input Voltage (V)
Input Voltage (V)
VO = 0.8 V
IO = 750 mA
VO = 0.8 V
IO = 5 mA
NOTE: The Y-axis shows 1% VO per division
NOTE: The Y-axis shows 1% VO per division
Figure 3. Line Regulation
Figure 4. Line Regulation Under Light Loads
500
450
400
350
300
250
200
150
100
50
500
450
400
350
300
250
200
150
100
50
125°C
125°C
85°C
25°C
0°C
85°C
25°C
0°C
–40°C
–40°C
0
0
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
Input Voltage (V)
Input Voltage (V)
IO = 1 A
IO = 750 mA
Figure 5. Dropout Voltage vs Input Voltage
Figure 6. Dropout Voltage vs Input Voltage
6
Copyright © 2014, Texas Instruments Incorporated
TPS7A8101-Q1
www.ti.com.cn
ZHCSBR4A –APRIL 2014–REVISED JUNE 2014
Typical Characteristics (continued)
At VOnom = 3.3 V, VI = VOnom + 0.5 V or 2.2 V (whichever is greater), IO = 100 mA, V(EN) = VI, C(IN) = 1 μF, C(OUT) = 4.7 μF, and
C(NR) = 0.01 μF; all temperature values refer to TJ, unless otherwise noted.
500
450
400
350
300
250
200
150
100
50
500
450
400
350
300
250
200
150
100
50
125°C
85°C
25°C
0°C
125°C
85°C
25°C
0°C
–40°C
–40°C
0
0
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
0
100 200 300 400 500 600 700 800 900 1000
Output Current (mA)
Input Voltage (V)
IO = 500 mA
VI = 3.6 V
Figure 7. Dropout Voltage vs Input Voltage
Figure 8. Dropout Voltage vs Load Current
500
450
400
350
300
250
200
150
100
50
300
250
200
150
100
50
IO = 1000 mA
IO = 750 mA
IO = 5 mA
125°C
85°C
25°C
0°C
–40°C
0
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
2.2 2.6
3
3.4 3.8 4.2 4.6
5
5.4 5.8 6.2 6.6
Input Voltage (V)
VI = 3.6 V
VO = 0.8 V
IO = 750 mA
Figure 9. Dropout Voltage vs Temperature
Figure 10. Ground Pin Current vs Input Voltage
2
1.8
1.6
1.4
1.2
1
300
250
200
150
100
50
VI = 5 V
VI = 2.2 V
VI = 2.5 V
VI = 3 V
VI = 5.5 V
VI = 6 V
VI = 6.6 V
VI = 3.3 V
0.8
0.6
0.4
0.2
0
125°C
85°C
25°C
0°C
–40°C
0
0
100 200 300 400 500 600 700 800 900 1000
Output Current (mA)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
V(EN) = 0.4 V
Figure 11. Ground Pin Current vs Load Current
Figure 12. Shutdown Current vs Temperature
Copyright © 2014, Texas Instruments Incorporated
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TPS7A8101-Q1
ZHCSBR4A –APRIL 2014–REVISED JUNE 2014
www.ti.com.cn
Typical Characteristics (continued)
At VOnom = 3.3 V, VI = VOnom + 0.5 V or 2.2 V (whichever is greater), IO = 100 mA, V(EN) = VI, C(IN) = 1 μF, C(OUT) = 4.7 μF, and
C(NR) = 0.01 μF; all temperature values refer to TJ, unless otherwise noted.
100
90
80
70
60
50
40
30
20
10
1800
1600
1400
1200
1000
800
600
400
200
0
VI = 2.2 V
VI = 3.8 V
VI = 5.5 V
VI = 6.5 V
VI ꢀ VO = 1 V
VI ꢀ VO = 0.5 V
VI ꢀ VO = 0.3 V
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
10
100
1000
10000 100000 1000000 1E+7
Frequency (Hz)
D001
VO = VI – 0.5 V
C(NR) = C(BYPASS) = 470 nF
C(OUT) = 10 µF
C(IN) = 0 F
Figure 13. Current-Limit vs Temperature
Figure 14. PSRR vs Frequency
100
90
80
70
60
50
40
30
20
10
100
90
80
70
60
50
40
30
20
10
IO = 10 mA
IO = 100 mA
IO = 750 mA
IO = 1 A
IO = 10 mA
IO = 100 mA
IO = 750 mA
IO = 1 A
10
100
1000
10000 100000 1000000 1E+7
10
100
1000
10000 100000 1000000 1E+7
Frequency (Hz)
Frequency (Hz)
D002
D003
VI – VO = 1 V
C(IN) = 0 F
C(OUT) = 10 µF
VI – VO = 0.5 V
C(IN) = 0 F
C(OUT) = 10 µF
C(NR) = C(BYPASS) = 470 nF
C(NR) = C(BYPASS) = 470 nF
Figure 15. PSRR vs Frequency
Figure 16. PSRR vs Frequency
100
100
90
80
70
60
50
40
90
80
70
60
50
40
30
20
10
IO = 10 mA
IO = 10 mA
IO = 100 mA
IO = 750 mA
IO = 1 A
30
20
10
IO = 100 mA
IO = 750 mA
IO = 1 A
10
100
1000
10000 100000 1000000 1E+7
10
100
1000
10000 100000 1000000 1E+7
Frequency (Hz)
Frequency (Hz)
D004
D005
VI – VO = 1 V
C(IN) = 0 F
C(OUT) = 10 µF
VI – VO = 0.5 V
C(IN) = 0 F
C(OUT) = 10 µF
C(NR) = C(BYPASS) = 470 nF
C(NR) = C(BYPASS) = 470 nF
Figure 17. PSRR vs Frequency
Figure 18. PSRR vs Frequency
8
Copyright © 2014, Texas Instruments Incorporated
TPS7A8101-Q1
www.ti.com.cn
ZHCSBR4A –APRIL 2014–REVISED JUNE 2014
Typical Characteristics (continued)
At VOnom = 3.3 V, VI = VOnom + 0.5 V or 2.2 V (whichever is greater), IO = 100 mA, V(EN) = VI, C(IN) = 1 μF, C(OUT) = 4.7 μF, and
C(NR) = 0.01 μF; all temperature values refer to TJ, unless otherwise noted.
90
80
70
60
50
40
30
20
10
90
80
70
60
50
40
30
20
10
ƒ = 1 kHz
ƒ = 1 kHz
ƒ = 10 kHz
ƒ = 100 kHz
ƒ = 1 MHz
ƒ = 10 kHz
ƒ = 100 kHz
ƒ = 1 MHz
0
0.5
1
1.5
2
2.5
3
3.5
0
0.5
1
1.5
2
2.5
3
3.5
Dropout Voltage (V)
Dropout Voltage (V)
IO = 100 mA
C(IN) = 0 F
IO = 750 mA
C(IN) = 0 F
Figure 19. PSRR vs Dropout Voltage
Figure 20. PSRR vs Dropout Voltage
100
10
100
50
20
10
5
2
1
1
0.5
0.2
0.1
0.1
VO = 1.8 V
VO = 2.5 V
VO = 3.3 V
0.05
C(NR) = C(BYPASS) = 100 nF
C(NR) = C(BYPASS) = 470 nF
0.02
0.01
0.01
10 2030 50 100 200 5001000
Frequency (Hz)
10000
100000
D006
10
100
1000
Frequency (Hz)
10000
100000
D007
VI – VO = 0.5 V
C(OUT) = 10 µF
C(IN) = 10 µF
25.89 µVRMS (VO = 1.8 V)
23.54 µVRMS (VO = 2.5 V)
23.54 µVRMS (VO = 3.3 V)
C(IN) = 10 µF
C(NR) = 470 nF
VI – VO = 0.5 V
24.09 µVRMS (C(NR) = C(BYPASS) = 100 nF)
23.54 µVRMS (C(NR) = C(BYPASS) = 470 nF)
C(OUT) = 10 µF
C(BYPASS) = 470 nF
Figure 21. Output Spectral Noise Density vs Frequency
(RMS noise (100 Hz to 100 kHz))
Figure 22. Output Spectral Noise Density vs Frequency
(RMS noise (100 Hz to 100 kHz))
100
10
1
100
10
1
0.1
0.1
IO = 100 mA
IO = 750 mA
IO = 1 A
CO = 10 µF
CO = 22 µF
CO = 100 µF
0.01
0.01
10
100
1000
Frequency (Hz)
10000
100000
D008
10
100
1000
Frequency (Hz)
10000
100000
D009
23.54 µVRMS (IO = 100 mA)
23.71 µVRMS (IO = 750 mA)
22.78 µVRMS (IO = 1 A)
C(IN) = 10 µF
C(NR) = 470 nF
VI – VO = 0.5 V
23.54 µVRMS (CO = 10 µF)
23.91 µVRMS (CO = 22 µF)
22.78 µVRMS (CO = 100 µF)
C(IN) = 10 µF
C(NR) = 470 nF
VI – VO = 0.5 V
C(OUT) = 10 µF
C(OUT) = 10 µF
C(BYPASS) = 470 nF
C(BYPASS) = 470 nF
Figure 23. Output Spectral Noise Density vs Frequency
(RMS noise (100 Hz to 100 kHz))
Figure 24. Output Spectral Noise Density vs Frequency
(RMS noise (100 Hz to 100 kHz))
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Typical Characteristics (continued)
At VOnom = 3.3 V, VI = VOnom + 0.5 V or 2.2 V (whichever is greater), IO = 100 mA, V(EN) = VI, C(IN) = 1 μF, C(OUT) = 4.7 μF, and
C(NR) = 0.01 μF; all temperature values refer to TJ, unless otherwise noted.
1000
7
6.5
6
3.333
500
3.32475
3.3165
3.30825
3.3
VO
300
200
100
50
5.5
5
VI (1V/div)
30
20
4.5
4
3.29175
3.2835
3.27525
3.267
10
5
3
2
3.5
3
VI
ꢀ VO = 1 V
1
50 ms/div
10
20 30 40 50 70 100
200 300 500 7001000
C(NR) = C(BYPASS) (nF)
VI = 3.8 V → 4.8 V → 3.8 V
D010
Using the same value of C(NR) and C(BYPASS) in the X-Axis
IO = 500 mA
Figure 25. Startup Time vs Noise Reduction Capacitance
Figure 26. Line Transient Response
4.5
4
3.85
3.8
3.75
3.7
VI (for reference)
3.5
3
EN
OUT
2.5
2
VO
3.35
3.3
2.5
2
1.5
1
IO
3.25
3.2
1.5
1
0.5
0
3.15
3.15
0.5
0
-0.5
-0.002
0
0.002
0.004
0.006
0.008
Time (50 ms/div)
C(NR) = 470 nF
C(IN) = 10 µF
50 µs/div
D011
IO = 100 mA → 1 A → 100 mA
RL = 33 Ω
C(OUT) = 10 µF
C(BYPASS) = 470 nF
Figure 27. Load Transient Response
Figure 28. Enable Pulse Response, see (1) in Figure 29
6.5
6
5.5
5
VI = VEN
4.5
4
3.5
3
VO
2.5
2
1.5
1
0.5
0
-0.5
-0.05
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45
Time (50 ms/div)
D012
RL = 33 Ω
C(NR) = 470 nF
C(IN) = 10 µF
C(BYPASS) = 470 nF
C(OUT) = 10 µF
(1) The internal reference requires approximately 80 ms of rampup
time (see Startup) from the enable event; therefore, VO fully reaches
the target output voltage of 3.3 V in 80 ms from startup.
Figure 29. Power-Up and Power-Down Response
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8 Detailed Description
8.1 Overview
The TPS7A8101-Q1 device belongs to a family of new-generation LDO regulators that use innovative circuitry to
achieve wide bandwidth and high loop gain, resulting in extremely high PSRR (over a 1-MHz range) even with
very low headroom (VI – VO). A noise-reduction capacitor (C(NR)) at the NR pin and a bypass capacitor (C(BYPASS)
)
decrease noise generated by the bandgap reference in order to improve PSRR, while a quick-start circuit fast-
charges the noise-reduction capacitor. This family of regulators offers sub-bandgap output voltages, current-limit,
and thermal protection, and is fully specified from –40°C to 125°C.
8.2 Functional Block Diagram
IN
OUT
Current-Limit
EN
Thermal
Shutdown
UVLO
FB/SNS
33 kΩ
Quick-Start
225 kΩ
1.2-V
Band Gap
NR
33 kΩ
15 pF
0.8 V
Adjustable
58.7 kΩ
TPS7A8101-Q1
GND
Figure 30. Functional Block Diagram
8.3 Feature Description
8.3.1 Internal Current-Limit
The TPS7A8101-Q1 internal current-limit helps protect the regulator during fault conditions. During the current-
limit, the output sources a fixed amount of current that is largely independent of the output voltage. For reliable
operation, the device should not be operated in a current-limit state for extended periods of time.
The PMOS pass element in the TPS7A8101-Q1 device has a built-in body diode that conducts current when the
voltage at the OUT pin (V(OUT)) exceeds the voltage at the IN pin (V(IN)). This current is not limited, so if extended
reverse-voltage operation is anticipated, external limiting may be appropriate.
8.3.2 Shutdown
The enable pin (EN) is active high and is compatible with standard-voltage and low-voltage TTL-CMOS levels.
When shutdown capability is not required, the EN pin can connect to the IN pin.
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Feature Description (continued)
8.3.3 Startup
Through a lower resistance, the bandgap reference can quickly charge the noise-reduction capacitor (C(NR)). The
TPS7A8101-Q1 device has a quick-start circuit to quickly charge C(NR), if present; see Figure 30. At startup, this
quick-start switch is closed, with only 33 kΩ of resistance between the bandgap reference and the NR pin. The
quick-start switch opens approximately 100 ms after any device-enabling event, and the resistance between the
bandgap reference and the NR pin becomes higher in value (approximately 250 kΩ) to form a very-good low-
pass (RC) filter. This low-pass filter reduces the noise present on the reference voltage; therefore, reducing the
noise on the output.
Inrush current can cause problems in many applications. The 33-kΩ resistance during the startup period is
intentionally placed between the bandgap reference and the NR pin in order to slow down the reference voltage
rampup, thus reducing the inrush current.
Use Equation 1 to calculate the startup time with other C(NR) values. For example, the capacitance of connecting
the recommended C(NR) value of 0.47 μF along with the 33-kΩ resistance causes an 80-ms RC delay
(approximately).
tst (s) = 170000 × C(NR) (F)
(1)
Although the noise-reduction effect is nearly saturated at 0.47 μF, connecting a C(NR) value greater than 0.47 μF
can additionally help reduce noise. However, when connecting a C(NR) value greater than 0.47 µF, the startup
time is extremely long because the quick-start switch opens after approximately 100 ms. That is, if C(NR) is not
fully charged during this 100-ms period, C(NR) finishes charging through a higher resistance of 250 kΩ, and takes
much longer to fully charge.
NOTE
A low-leakage capacitor should be used for C(NR). Most ceramic capacitors are suitable
8.3.4 Undervoltage Lockout (UVLO)
The TPS7A8101-Q1 device uses an undervoltage-lockout (UVLO) circuit to ensure that the output is shut off until
the internal circuitry has enough voltage to operate properly. The UVLO circuit has a deglitch feature so that the
circuit typically ignores undershoot transients on the input if the duration is less than 50-μs.
8.4 Device Functional Modes
Driving the EN pin over 1.2 V for VI between 2.2 V to 3.6 V or 1.35 V for VI between 3.6 V and 6.5 V turns on the
regulator. Driving the EN pin below 0.4 V causes the regulator to enter shutdown mode.
In shutdown, the current consumption of the device is reduced to 0.02 µA typically.
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9 Application and Implementation
9.1 Application Information
The TPS7A8101-Q1 device belongs to a family of new-generation LDO regulators that use innovative circuitry to
achieve wide bandwidth and high loop gain, resulting in extremely high PSRR (over a 1-MHz range) even with
very low headroom (VI – VO). A noise-reduction capacitor (C(NR)) at the NR pin and a bypass capacitor (C(BYPASS)
)
decrease noise generated by the bandgap reference in order to improve PSRR, while a quick-start circuit fast-
charges the noise-reduction capacitor. This family of regulators offers sub-bandgap output voltages, current-limit,
and thermal protection, and is fully specified from –40°C to 125°C.
9.2 Typical Application
Figure 31 shows the connections for the device.
VI
VO
IN
OUT
R1
R2
C(BYPASS)
C(IN)
TPS7A8101-Q1
EN
FB/SNS
NR
GND
C(OUT)
C(NR)
V(EN)
Figure 31. Typical Application Circuit
The voltage on the FB pin sets the output voltage and is determined by the values of the resistors R1 and R2.
Use Equation 2 to calculate the values of R1 and R2 any voltage.
R1+ R2
(
)
VO
=
´ 0.8
R2
(2)
Table 1 lists sample resistor values for common output voltages. In Table 1, E96 series resistors are used, and
all values meet 1% of the target VO, assuming resistors with zero error. For the actual design, pay attention to
any resistor error-factors. Using lower values for R1 and R2 reduces the noise injected into the FB pin.
9.2.1 Design Requirements
9.2.1.1 Dropout Voltage
The TPS7A8101-Q1 device uses a PMOS pass transistor to achieve low dropout. When (VI – VOnom) is less than
the dropout voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output
resistance is the rDS(on) of the PMOS pass element. VDO is proportional to the output current because the PMOS
device in dropout functions in the same way as a resistor.
As with any linear regulator, PSRR and transient responses are degraded as (VI – VO) approaches dropout.
Figure 19 and Figure 20 in the Typical Characteristics section shown this effect.
9.2.1.2 Minimum Load
The TPS7A8101-Q1 device is stable and functions well with no output load. Traditional PMOS-LDO regulators
suffer from lower loop gain at very light output loads. The TPS7A8101-Q1 device employs an innovative low-
current mode circuit to increase loop gain under very light or no-load conditions, resulting in improved output
voltage regulation performance down to zero output current.
9.2.1.3 Input And Output Capacitor Requirements
Although an input capacitor is not required for stability, connecting a 0.1-µF to 1-µF low-equivalent series-
resistance (ESR) capacitor from the input supply near the regulator to ground is good analog-design practice.
This capacitor counteracts reactive input sources and improves transient response and ripple rejection. A higher-
value capacitor may be necessary if large, fast load transients are anticipated or if the device is located several
inches from the power source. If source impedance is not sufficiently low, a 0.1-μF input capacitor may be
necessary to ensure stability.
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Typical Application (continued)
The TPS7A8101-Q1 device is designed to be stable with standard ceramic capacitors of capacitance values 4.7
μF or larger. This device was evaluated using a 10-μF ceramic capacitor of 10-V rating, 10% tolerance, X5R
type, and 0805 size (2 mm × 1,25 mm).
X5R-type and X7R-type capacitors are highly recommended because they have minimal variation in capacitance
and ESR over temperature. The maximum ESR should be less than 1 Ω.
Table 1. Recommended Feedback Resistor Values for Common Output Voltages
VO
R1
R2
0.8 V
1 V
0 Ω (Short)
2.49 kΩ
4.99 kΩ
8.87 kΩ
12.5 kΩ
21 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
5 V
30.9 kΩ
52.3 kΩ
Table 2. Recommended Capacitor Values
NAME
DESCRIPTION
VALUE
C(NR)
Noise-reduction capacitor between the NR and
GND pins
470 nF
C(BYPASS)
C(OUTPUT)
C(IN)
Noise-reduction capacitor across R1
Output capacitor
470 nF
10 µF
10 µF
Input capacitor
9.2.1.4 Transient Response
As with any regulator, increasing the size of the output capacitor reduces overshoot and undershoot magnitude
but increases the duration of the transient response. Using a larger noise-reduction capacitor (C(NR)), bypass
capacitor (C(BYPASS)), or both types of capacitors can improve line-transient performance.
9.2.2 Detailed Design Procedure
9.2.2.1 Output Noise
In most LDOs, the bandgap is the dominant noise source. If a noise reduction capacitor (C(NR)) is used with the
TPS7A8101-Q1 device, the bandgap does not contribute significantly to noise. Instead, noise is dominated by
the output resistor-divider and the error-amplifier input. If a bypass capacitor (C(BYPASS)) across the high-side
feedback resistor (R1) is used with the TPS7A8101-Q1 device, noise from these other sources can also be
significantly reduced.
To maximize noise performance in a given application, use a 0.47-μF noise-reduction capacitor plus a 0.47-μF
bypass capacitor.
14
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9.2.3 Application Curves
100
90
80
70
60
50
40
100
90
80
70
60
50
40
30
20
10
IO = 10 mA
30
VI ꢀ VO = 1 V
VI ꢀ VO = 0.5 V
VI ꢀ VO = 0.3 V
IO = 100 mA
IO = 750 mA
IO = 1 A
20
10
10
100
1000
10000 100000 1000000 1E+7
10
100
1000
10000 100000 1000000 1E+7
Frequency (Hz)
Frequency (Hz)
D001
D002
C(NR) = C(BYPASS) = 470 nF
C(OUT) = 10 µF
C(IN) = 0 F
VI – VO = 1 V
C(IN) = 0 F
C(OUT) = 10 µF
C(NR) = C(BYPASS) = 470 nF
Figure 32. PSRR vs Frequency
Figure 33. PSRR vs Frequency
100
90
80
70
60
50
40
30
20
10
100
50
20
10
5
2
1
0.5
0.2
0.1
IO = 10 mA
0.05
IO = 100 mA
IO = 750 mA
IO = 1 A
C(NR) = C(BYPASS) = 100 nF
C(NR) = C(BYPASS) = 470 nF
0.02
0.01
10 2030 50 100 200 5001000
Frequency (Hz)
10000
100000
D006
10
100
1000
10000 100000 1000000 1E+7
Frequency (Hz)
D003
VI – VO = 0.5 V
C(OUT) = 10 µF
C(IN) = 10 µF
VI – VO = 0.5 V
C(IN) = 0 F
C(OUT) = 10 µF
24.09 µVRMS (C(NR) = C(BYPASS) = 100 nF)
23.54 µVRMS (C(NR) = C(BYPASS) = 470 nF)
C(NR) = C(BYPASS) = 470 nF
Figure 35. Output Spectral Noise Density vs Frequency
(RMS noise (100 Hz to 100 kHz))
Figure 34. PSRR vs Frequency
100
10
100
10
1
1
0.1
0.1
IO = 100 mA
IO = 750 mA
IO = 1 A
VO = 1.8 V
VO = 2.5 V
VO = 3.3 V
0.01
0.01
10
100
1000
Frequency (Hz)
10000
100000
D008
10
100
1000
Frequency (Hz)
10000
100000
D007
23.54 µVRMS (IO = 100 mA)
23.71 µVRMS (IO = 750 mA)
22.78 µVRMS (IO = 1 A)
C(IN) = 10 µF
C(NR) = 470 nF
VI – VO = 0.5 V
25.89 µVRMS (VO = 1.8 V)
23.54 µVRMS (VO = 2.5 V)
23.54 µVRMS (VO = 3.3 V)
C(IN) = 10 µF
C(NR) = 470 nF
VI – VO = 0.5 V
C(OUT) = 10 µF
C(OUT) = 10 µF
C(BYPASS) = 470 nF
C(BYPASS) = 470 nF
Figure 36. Output Spectral Noise Density vs Frequency
(RMS noise (100 Hz to 100 kHz))
Figure 37. Output Spectral Noise Density vs Frequency
(RMS noise (100 Hz to 100 kHz))
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100
10
1
1000
500
300
200
100
50
30
20
10
0.1
5
CO = 10 µF
CO = 22 µF
CO = 100 µF
0.01
3
2
VI ꢀ VO = 1 V
1
10
100
1000
Frequency (Hz)
10000
100000
10
20 30 40 50 70 100
200 300 500 7001000
C(NR) = C(BYPASS) (nF)
D009
D010
23.54 µVRMS (CO = 10 µF)
23.91 µVRMS (CO = 22 µF)
22.78 µVRMS (CO = 100 µF)
C(IN) = 10 µF VI – VO = 0.5 V
Using the same value of C(NR) and C(BYPASS) in the X-Axis
C(NR) = 470 nF
C(OUT) = 10 µF
C(BYPASS) = 470 nF
Figure 38. Output Spectral Noise Density vs Frequency
(RMS noise (100 Hz to 100 kHz))
Figure 39. Startup Time vs Noise Reduction Capacitance
3.85
7
6.5
6
3.333
3.8
3.75
3.7
3.32475
3.3165
3.30825
3.3
VO
VI (for reference)
5.5
5
VI (1V/div)
VO
3.35
3.3
2.5
2
4.5
4
3.29175
3.2835
3.27525
3.267
IO
3.25
3.2
1.5
1
3.5
3
3.15
3.15
0.5
0
50 ms/div
50 µs/div
VI = 3.8 V → 4.8 V → 3.8 V
IO = 100 mA → 1 A → 100 mA
IO = 500 mA
Figure 40. Line Transient Response
Figure 41. Load Transient Response
4.5
6.5
6
4
3.5
3
5.5
5
EN
VI = VEN
4.5
4
OUT
2.5
2
3.5
3
VO
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
-0.5
-0.05
-0.5
-0.002
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45
Time (50 ms/div)
0
0.002
0.004
0.006
0.008
Time (50 ms/div)
C(NR) = 470 nF
C(IN) = 10 µF
D012
D011
RL = 33 Ω
C(NR) = 470 nF
C(IN) = 10 µF
C(BYPASS) = 470 nF
RL = 33 Ω
C(OUT) = 10 µF
C(BYPASS) = 470 nF
C(OUT) = 10 µF
(1) The internal reference requires approximately 80 ms of
rampup time (see Startup) from the enable event; therefore, VO
fully reaches the target output voltage of 3.3 V in 80 ms from
startup.
Figure 42. Enable Pulse Response, See (1) in Figure 43
Figure 43. Power-Up and Power-Down Response
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10 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 2.2 V and 6.5 V. The input
voltage range should provide adequate headroom in order for the device to have a regulated output. This input
supply should be well regulated. If the input supply is noisy, additional input capacitors with low ESR can help
improve the output noise performance.
11 Layout
11.1 Layout Guidelines
11.1.1 Board Layout Recommendations To Improve PSRR And Noise Performance
To improve AC performance such as PSRR, output noise, and transient response, designing with separate
ground planes for VI and VO, with each ground plane connected only at the GND pin of the device, is
recommended. In addition, the ground connection for the noise-reduction capacitor should connect directly to the
GND pin of the device.
High ESR capacitors may degrade PSRR.
11.2 Layout Example
GND
R2
C(NR)
R1
C(IN)
C(OUT)
C(BYPASS)
VI
GND
VO
Figure 44. TPS7A8101-Q1 Layout Example
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11.3 Thermal Information
11.3.1 Thermal Protection
Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the
device to cool. When the junction temperature cools to approximately 140°C the output circuitry is again enabled.
Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may
cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage because of
overheating.
Any activation of the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink.
For reliable operation, junction temperature should be limited to 125°C (maximum). To estimate the margin of
safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection is
triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at
least 35°C above the maximum expected ambient condition of your particular application. This configuration
produces a worst-case junction temperature of 125°C at the highest expected ambient temperature and worst-
case load.
The internal protection circuitry of the TPS7A8101-Q1 device has been designed to protect against overload
conditions. The internal thermal protection circuitry was not intended to replace proper heatsinking. Continuously
running the TPS7A8101-Q1 device into thermal shutdown degrades device reliability.
11.3.2 Package Mounting
See the 机械封装和可订购信息 section for solder pad footprint recommendations and recommended land
patterns.
11.3.3 Power Dissipation
Knowing the device power dissipation and proper sizing of the thermal plane that is connected to the tab or pad
is critical to avoiding thermal shutdown and ensuring reliable operation.
The power dissipation of the device depends on input voltage and load conditions. To calculate the device power
dissipation, use Equation 3.
PD = (VI – VO) × IO
(3)
Using the lowest possible input voltage necessary to achieve the required output voltage regulation minimizes
power dissipation and achieves greater efficiency.
On the SON (DRB) package, the primary conduction path for heat is through the exposed pad to the printed
circuit board (PCB). The pad can be connected to ground or can be left floating; however, the pad should be
attached to an appropriate amount of copper PCB area to ensure the device does not overheat. The maximum
junction-to-ambient thermal resistance depends on the maximum ambient temperature, maximum device junction
temperature, and power dissipation of the device. Calculate the maximum junction-to-ambient thermal resistance
using Equation 4.
125°C - T
(
)
A
RqJA
=
PD
(4)
Once the maximum RθJA value is calculated, use Figure 45 to estimate the minimum amount of PCB copper area
needed for appropriate heatsinking.
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Thermal Information (continued)
160
140
120
100
80
60
40
20
0
0
1
2
3
4
5
6
7
8
9
10
Board Copper Area (in2)
Note: The RθJA value at board size of 9 in2 (that is, 3 in × 3 in) is a JEDEC standard.
Figure 45. RθJA vs Board Size
Figure 45 shows the variation of RθJA as a function of ground plane copper area in the board. Figure 45 is
intended as a guideline only to demonstrate the effects of heat spreading in the ground plane and should not be
used to estimate actual thermal performance in real application environments.
NOTE
When the device is mounted on an application PCB, using ΨJT and ΨJB, as explained in
the section is strongly recommended.
11.3.4 Estimating Junction Temperature
Using the thermal metrics ΨJT and ΨJB, as shown in the Thermal Information table, the junction temperature can
be estimated with the corresponding equations, Equation 5 and Equation 6. For backwards compatibility, an
older θJC,Top parameter is listed as well.
φJT: TJ = TT + φJT × PD
where
•
•
PD is the power dissipation (see Equation 4)
TT is the temperature at the center-top of the IC package
(5)
(6)
φJB: TJ = TB + φJB × PD
where
•
TB is the PCB temperature measured 1-mm away from the IC package on the PCB surface as shown in
Figure 46
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Thermal Information (continued)
TT on top
of IC surface
TB
TB on PCB
TT
1 mm
1 mm
Figure 46. Measuring Points for TT and TB
NOTE
Both TT and TB can be measured on actual application boards using an infrared
thermometer.
For more information about measuring TT and TB, see TI's application report SBVA025, Using New Thermal
Metrics.
As shown in Figure 47, the new thermal metrics (ΨJT and ΨJB) have very little dependency on board size. That
is, using ΨJT or ΨJB with Equation 5 is a good way to estimate TJ by simply measuring TT or TB, regardless of the
application board size.
20
18
ΨJB
16
14
12
10
8
6
ΨJT
4
2
0
0
1
2
3
4
5
6
7
8
9
10
Board Copper Area (in2)
Figure 47. ΨJT and ΨJB vs Board Size
For a more detailed discussion of why TI does not recommend using RθJC(top) to determine thermal
characteristics, refer to TI's application report SBVA025, Using New Thermal Metrics. For further information,
refer to TI's application report SPRA953, IC Package Thermal Metrics.
20
Copyright © 2014, Texas Instruments Incorporated
TPS7A8101-Q1
www.ti.com.cn
ZHCSBR4A –APRIL 2014–REVISED JUNE 2014
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档ꢀ
相关文档如下：
•
•
•
•
《LDO 噪声详细检查》，SLYT489
《LDO 在接近压降电压时的性能》, SBVA029
TPS7A8101EVM 评估模块，SLVU600
LDO 的宽带宽 PSRR 作者 Nogawa 和 Van Renterghem Bodo's Power Systems®：运动和转换中的电子元器
件，2011 年 3 月
12.2 Trademarks
Bodo's Power Systems is a registered trademark of Arlt Bodo.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.4 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
13 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
Copyright © 2014, Texas Instruments Incorporated
21
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Copyright © 2014, 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS7A8101QDRBRQ1
ACTIVE
SON
DRB
8
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
SLY
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
DRB0008A
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
DIM A
OPT 1
(0.1)
OPT 2
(0.2)
1.5 0.1
4X (0.23)
EXPOSED
THERMAL PAD
(DIM A) TYP
4
5
2X
1.95
1.75 0.1
8
1
6X 0.65
0.37
0.25
8X
PIN 1 ID
0.1
C A B
C
(OPTIONAL)
(0.65)
0.05
0.5
0.3
8X
4218875/A 01/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRB0008A
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.5)
(0.65)
SYMM
8X (0.6)
(0.825)
8
8X (0.31)
1
SYMM
(1.75)
(0.625)
6X (0.65)
4
5
(R0.05) TYP
(
0.2) VIA
(0.23)
TYP
(0.5)
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218875/A 01/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRB0008A
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.65)
4X (0.23)
SYMM
METAL
TYP
8X (0.6)
4X
(0.725)
8
1
8X (0.31)
(2.674)
(1.55)
SYMM
6X (0.65)
4
5
(R0.05) TYP
(1.34)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
84% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218875/A 01/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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