TPS7A88-Q1 [TI]
汽车类 1A、低噪声、高精度、双通道可调节低压降稳压器;
| 型号： | TPS7A88-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类 1A、低噪声、高精度、双通道可调节低压降稳压器 稳压器 |
| 文件： | 总41页 (文件大小：1394K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS7A88-Q1
ZHCSGO4A –AUGUST 2017–REVISED SEPTEMBER 2017
TPS7A88-Q1 汽车双路 1A 低噪声 (4 µVRMS) LDO 稳压器
1 特性
3 说明
1
•
符合 AEC-Q100 标准，其中包括以下内容：
TPS7A88-Q1 是一款双路低噪声 (4µVRMS) 低压降
(LDO) 稳压器，每通道具有 1A 的拉电流能力，且最高
压降为 250mV。
–
–
–
温度等级 1：–40°C ≤ TA ≤ +125°C
HBM ESD 分类等级 2
CDM ESD 分类等级 C5
TPS7A88-Q1 提供两个独立的 LDO，极具灵活性，解
决方案尺寸要比两个单通道 LDO 小 50% 左右。每个
输出可通过外部电阻在 0.8V 至 5.15V 范围内进行调
节。TPS7A88-Q1 的宽输入电压范围支持其在低至
1.4V 和高达 6.5V 的电压下工作。
•
•
•
•
•
•
两个独立的 LDO 通道
低输出噪声：4µVRMS（10Hz 至 100kHz）
低压降：1A 电流时为 230mV（最大值）
宽输入电压范围：1.4V 至 6.5V
宽输出电压范围：0.8V 至 5.15V
高电源纹波抑制：
凭借 1% 的输出电压精度（整个线路、负载和温度范
围内）和用于降低浪涌电流的软启动功能，TPS7A88-
Q1 非常适合为敏感类模拟低压器件（例如压控振荡器
[VCO]、模数转换器 [ADC]、数模转换器 [DAC]、高端
处理器和现场可编程门阵列 [FPGA]）供电。
–
–
–
100Hz 时为 70dB
100kHz 时为 40dB
1MHz 时为 40dB
•
•
•
•
•
•
线路、负载和温度范围内的精度为 1%
出色的负载瞬态响应
TPS7A88-Q1 旨在为射频、雷达通信和远程信息处理
等 应用中的噪声敏感类组件供电。此器件具有较低的
4µVRMS 输出噪声和宽带 PSRR（1MHz 时为
40dB），可最大限度地减少相位噪声和时钟抖动。这
些 特性 最大限度提升了计时器件、ADC 和 DAC 的性
能。TPS7A88-Q1 采用了 可湿性侧面，可轻松进行光
学检查。
可调启动浪涌控制
可选软启动充电电流
独立开漏电源正常 (PG) 输出
与 10µF 或更大的陶瓷输出电容器一起工作时保持
稳定
•
•
低热阻：RθJA = 39.8°C/W
4mm × 4mm 可湿性侧面 WQFN 封装
器件信息(1)
器件型号
封装
WQFN (20)
封装尺寸（标称值）
2 应用
TPS7A88-Q1
4.00mm x 4.00mm
•
•
汽车应用中的射频和雷达 电源
(1) 如需了解所有可用封装，请参阅产品说明书末尾的封装选项附
录。
汽车用高级驾驶员辅助系统 (ADAS) 电子控制单元
(ECU)
•
•
•
远程信息处理控制单元
信息娱乐系统和仪表组
高速接口 (I/F)（锁相环 (PLL) 和压控振荡器
(VCO)）
典型应用图
频谱噪声密度与输出电压间的关系
10
PG1
IN1
VOUTx = 0.8 V, 3.94 mVRMS
VOUTx = 1.2 V, 4.31 mVRMS
VOUTx = 1.8 V, 5.1 mVRMS
VOUTx = 2.5 V, 6.03 mVRMS
VOUTx = 3.3 V, 7.43 mVRMS
VOUTx = 5.0 V, 10.3 mVRMS
VIN1
EN1
OUT1
OUT2
VIN_RF1
EN1
Radar
Sensor System
1
0.1
TPS7A88-Q1
VIN2
EN2
IN2
VIN_RF2
EN2
PG2
0.01
Copyright © 2017, Texas Instruments Incorporated
0.001
1E+1
1E+2
1E+3
1E+4
1E+5
1E+6
1E+7
Frequency (Hz)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBVS289
TPS7A88-Q1
ZHCSGO4A –AUGUST 2017–REVISED SEPTEMBER 2017
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 18
Application and Implementation ........................ 19
8.1 Application Information............................................ 19
8.2 Typical Application .................................................. 30
Power Supply Recommendations...................... 32
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 7
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
7.3 Feature Description................................................. 15
8
9
10 Layout................................................................... 32
10.1 Layout Guidelines ................................................. 32
10.2 Layout Example .................................................... 33
11 器件和文档支持 ..................................................... 34
11.1 器件支持 ............................................................... 34
11.2 文档支持 ............................................................... 34
11.3 社区资源................................................................ 34
11.4 商标....................................................................... 35
11.5 静电放电警告......................................................... 35
11.6 Glossary................................................................ 35
12 机械、封装和可订购信息....................................... 36
7
4 修订历史记录
Changes from Original (August 2017) to Revision A
Page
•
•
已更改 将“低热阻：RθJA”从 40°C/W 更改为 39.8°C/W 以便与热性能信息 表内容匹配........................................................... 1
Deleted output voltage range from Recommended Operating Conditions table; this parameter is already listed in the
Electrical Characteristics table ............................................................................................................................................... 4
•
Changed ENx pin current parameter min and max values from ±0.2 µA to ±0.5 µA in Electrical Characteristics table........ 5
2
Copyright © 2017, Texas Instruments Incorporated
TPS7A88-Q1
www.ti.com.cn
ZHCSGO4A –AUGUST 2017–REVISED SEPTEMBER 2017
5 Pin Configuration and Functions
RTJ Package
20-Pin WQFN With Exposed Thermal Pad
Top View
IN1
IN1
1
2
3
4
5
15
14
13
12
11
OUT1
OUT1
GND
Thermal
Pad
GND
IN2
OUT2
OUT2
IN2
Not to scale
Pin Functions
PIN
NO.
DESCRIPTION
NAME
EN1
I/O
Enable pin for each channel. These pins turn the regulator on and off. If VENx(1) ≥ VIH(ENx), then the regulator is enabled. If
ENx ≤ VIL(ENx), then the regulator is disabled. The ENx pin must be connected to INx if the enable function is not used.
20
6
I
V
EN2
FB1
16
Feedback pins connected to the error amplifier. Although not required, a TI recommends a 10-nF feedforward capacitor from
FBx to OUTx (as close as possible to the device) to maximize AC performance. The use of a feedforward capacitor can
disrupt PGx (power good) functionality. See Feedforward Capacitor (CFFx) and Setting the Output Voltage (Adjustable
Operation) for more details.
I
FB2
10
GND
IN1
3, 13
1, 2
—
I
Ground pins. These pins must be connected to ground, the thermal pad, and each other with a low-impedance connection.
Input supply pins for LDO 1. An input capacitor with a value of 10 µF or larger (5 µF or greater of effective capacitance) is
required. Place the input capacitor as close as possible to the input.
Input supply pins for LDO 2. An input capacitor with a value of 10 µF or larger (5 µF or greater of effective capacitance) is
required. Place the input capacitor as close as possible to the input.
IN2
4, 5
19
I
NR/SS1
Noise-reduction and soft-start pin for each channel. Connecting an external capacitor between this pin and ground reduces
reference voltage noise and enables the soft-start function. Although not required, TI recommends connecting a capacitor
with a value of 10 nF or larger from NR/SSx to GND (as close as possible to the pin) to maximize AC performance. See
Noise-Reduction and Soft-Start Capacitor (CNR/SSx) for more details.
—
NR/SS2
OUT1
7
Regulated outputs for LDO 1. A ceramic capacitor with a value of 5 µF or larger (10 μF or greater of effective capacitance)
from OUTx to ground is required for stability and must be placed as close as possible to the output. Minimize the impedance
from the OUT1 pin to the load. See Input and Output Capacitor (CINx and COUTx) for more details.
14, 15
O
O
O
Regulated outputs for LDO 2. A ceramic capacitor with a value of 10 µF or larger (5 μF or greater of effective capacitance)
from OUTx to ground is required for stability and must be placed as close as possible to the output. Minimize the impedance
from the OUT2 pin to the load. See Input and Output Capacitor (CINx and COUTx) for more details.
OUT2
11, 12
PG1
PG2
17
9
Open-drain power-good indicator pins for the LDO 1 and LDO 2 output voltages. A 10-kΩ to 100-kΩ external pullup resistor is
required. These pins can be left floating or connected to GND if not used. The use of a feedforward capacitor can disrupt
power-good functionality. See Feedforward Capacitor (CFFx) for more details.
SS_CTRL1
SS_CTRL2
Thermal pad
18
8
Soft-start control pins for each channel. Connect these pins to GND or INx to allow normal or fast charging of the NR/SSx
capacitor. If a CNR/SSx capacitor is not used, SS_CTRLx must be connected to GND to avoid output overshoot.
I
—
Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND.
(1) Lowercase x indicates that the specification under consideration applies to both channel 1 and channel 2, one channel at a time.
Copyright © 2017, Texas Instruments Incorporated
3
TPS7A88-Q1
ZHCSGO4A –AUGUST 2017–REVISED SEPTEMBER 2017
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating junction temperature range and all voltages with respect to GND (unless otherwise noted)(1)
(2)
MIN
–0.3
–0.3
–0.3
MAX
UNIT
INx, PGx, ENx
OUTx , SS_CTRLx
NR/SSx, FBx
7
Voltage
Current
VINx + 0.3(3)
V
3.6
Internally
limited
Internally
limited
OUTx
A
PGx (sink current into device)
5
mA
°C
Operating junction temperature, TJ
Storage temperature, Tstg
–55
–55
150
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Lowercase x indicates that the specification under consideration applies to both channel 1 and channel 2, one channel at a time.
(3) The absolute maximum rating is VINx + 0.3 V or 7 V, whichever is smaller.
6.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
1.4
0
MAX
6.5
1
UNIT
VINx
Input supply voltage range
Output current
V
IOUTx
CINx
A
Input capacitor, each input
Output capacitor, each output
Noise-reduction capacitor
Power-good pullup resistance
Junction temperature range
10
10
µF
µF
µF
kΩ
°C
COUTx
CNR/SSx
RPG
1
100
140
10
TJ
–40
6.4 Thermal Information
TPS7A88-Q1
RTJ (WQFN)
20 PINS
39.8
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
27.7
16.9
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ψJB
16.6
RθJC(bot)
1.5
(1) For more information about traditional and new thermal metrics, see theSemiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2017, Texas Instruments Incorporated
TPS7A88-Q1
www.ti.com.cn
ZHCSGO4A –AUGUST 2017–REVISED SEPTEMBER 2017
6.5 Electrical Characteristics
over operating temperature range (TJ = –40°C to +140°C), VINx = 1.4 V, VOUTx(TARGET) = 0.8 V, IOUTx = 5 mA, VENx = 1.4 V,
COUTx = 10 μF, CNR/SSx = 0 nF, CFFx = 0 nF, SS_CTRLx = GND, PGx pin pulled up to VINx with 100 kΩ, and for each channel;
typical values are at TJ = 25°C (1) (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VINx
Input supply voltage range
Reference voltage
Input supply UVLO
VUVLO Hysteresis
1.4
6.5
V
VREF
VUVLO
VHYS
0.8
1.31
290
V
VINx rising
1.39
V
mV
V
TJ = –40°C to +125°C
0.8 – 1%
5.15 + 1%
5.15 + 1%
Output voltage range
0.8 – 1.5%
0.8 V ≤ VOUTx ≤ 5.15 V
5 mA ≤ IOUTx ≤ 1 A
TJ = –40°C to +125°C
VOUTx
–1%
1%
1%
Output voltage accuracy(2)(3)
0.8 V ≤ VOUTx ≤ 5.15 V
5 mA ≤ IOUTx ≤ 1 A
–1.5%
IOUTx= 5 mA
1.4 V ≤ VINx ≤ 6.5 V
ΔVOUTx(ΔVINx)
ΔVOUTx(ΔIOUTx)
Line regulation
Load regulation
0.003
0.03
%/V
%/A
5 mA ≤ IOUTx ≤ 1 A
VINx ≥ 1.4 V
0.8 V ≤ VOUTx ≤ 5.15 V
IOUTx = 1 A
225
mV
VDO
Dropout voltage
VFBx = 0.8 V – 3%, TJ = –40°C to +125°C
VINx ≥ 1.4 V, 0.8 V ≤ VOUTx ≤ 5.15 V,
IOUTx = 1 A, VFBx = 0.8 V – 3%
250
1.9
3.5
4
mV
A
VOUTx forced at 0.9 × VOUTx(TARGET)
,
ILIM
Output current limit
GND pin current
1.5
1.7
2.1
VINx = VOUTx(TARGET) + 300 mV
Both channels enabled, per channel
VINx = 6.5 V, IOUTx = 5 mA
IGND
mA
Both channels enabled, per channel
VINx = 1.4 V, IOUTx = 1 A
Both channels shutdown, per channel, PGx = (open)
ISDN
Shutdown GND pin current
ENx pin current
0.1
15
μA
VINx = 6.5 V
VENx = 0.4 V
VINx = 6.5 V
0 V ≤ VENx ≤ 6.5 V
IENx
–0.5
0
0.5
0.4
μA
V
ENx pin low-level input voltage
(device disabled)
VIL(ENx)
VIH(ENx)
ISS_CTRLx
VIT(PGx)
ENx pin high-level input voltage
(device enabled)
1.1
6.5
V
VINx = 6.5 V
0 V ≤ VSS_CTRLx ≤ 6.5 V
SS_CTRLx pin current
PGx pin threshold
–0.2
82%
0.2
μA
For PGx transitioning low with falling VOUTx
expressed as a percentage of VOUTx(TARGET)
;
88.9%
1%
93%
For PGx transitioning high with rising VOUTx
expressed as a percentage of VOUTx(TARGET)
;
Vhys(PGx)
VOL(PGx)
Ilkg(PGx)
PGx pin hysteresis
PGx pin low-level output voltage VOUTx < VIT(PGx), IPGx = –1 mA (current into device)
0.4
1
V
VOUTx > VIT(PGx)
PGx pin leakage current
µA
VPGx = 6.5 V
VNR/SSx = GND
1.4 V ≤ VINx ≤ 6.5 V
4
6.2
10
VSS_CTRLx = GND
INR/SSx
NR/SSx pin charging current
µA
nA
VNR/SSx = GND
1.4 V ≤ VINx ≤ 6.5 V
VSS_CTRLx = VINx
65
100
150
100
VINx = 6.5 V
FBx pin leakage current
IFBx
–100
VFBx = 0.8 V
(1) Lowercase x indicates that the specification under consideration applies to both channel 1 and channel 2, one channel at a time.
(2) When the device is connected to external feedback resistors at the FBx pin, external resistor tolerances are not included.
(3) The device is not tested under conditions where VINx > VOUTx + 2.5 V and IOUTx = 1 A; the power dissipation is higher than the maximum
rating of the package. This accuracy specification does not apply on any application condition that exceeds the power dissipation limit of
the package under test.
Copyright © 2017, Texas Instruments Incorporated
5
TPS7A88-Q1
ZHCSGO4A –AUGUST 2017–REVISED SEPTEMBER 2017
www.ti.com.cn
Electrical Characteristics (continued)
over operating temperature range (TJ = –40°C to +140°C), VINx = 1.4 V, VOUTx(TARGET) = 0.8 V, IOUTx = 5 mA, VENx = 1.4 V,
COUTx = 10 μF, CNR/SSx = 0 nF, CFFx = 0 nF, SS_CTRLx = GND, PGx pin pulled up to VINx with 100 kΩ, and for each channel;
typical values are at TJ = 25°C (1) (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
f = 500 kHz
VINx = 3.8 V
VOUTx = 3.3 V
IOUTx = 750 mA
CNR/SSx = 10 nF
CFFx = 10 nF
PSRR
Power-supply ripple rejection
40
dB
BW = 10 Hz to 100 kHz
VINx = 1.8 V
VOUTx = 0.8 V
IOUTx = 1 A
CNR/SSx = 1 µF
CFFx = 100 nF
Vn
Output noise voltage
Noise spectral density
3.8
μVRMS
f = 10 kHz
VINx = 1.8 V
VOUTx = 0.8 V
11
nV/√Hz
IOUTx = 1 A
CNR/SSx = 10 nF
CFFx = 10 nF
Output active discharge
resistance
Rdiss
VENx = GND
250
Ω
Shutdown, temperature increasing
Reset, temperature decreasing
160
140
Tsd
Thermal shutdown temperature
°C
6
版权 © 2017, Texas Instruments Incorporated
TPS7A88-Q1
www.ti.com.cn
ZHCSGO4A –AUGUST 2017–REVISED SEPTEMBER 2017
6.6 Typical Characteristics
at TJ = 25°C, 1.4 V ≤ VINx < 6.5 V, VINx ≥ VOUTx(TARGET) + 0.3 V, VOUTx = 0.8 V, SS_CTRLx = GND, IOUTx = 5 mA, VENx = 1.1 V,
COUTx = 10 μF, CNR/SSx = 0 nF, CFFx = 0 nF, PGx pin pulled up to VOUTx with 100 kΩ, and SS_CTRLx = GND (unless otherwise
noted)
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
IOUTx = 1 A
CNR/SSx = Open
CNR/SSx = 0.01 mF
CNR/SSx = 0.1 mF
CNR/SSx = 1 mF
CNR/SSx = 10 mF
IOUTx = 0.75 A
IOUTx = 0.5 A
IOUTx = 0.25 A
IOUTx = 0.1 A
1E+1
1E+2
1E+3
1E+4
1E+5
1E+6
1E+7
1E+1
1E+2
1E+3
1E+4
1E+5
1E+6
1E+7
Frequency (Hz)
Frequency (Hz)
VOUTx = 1.2 V, VINx = VENx = 1.7 V
COUTx = 10 µF CNR/SSx = CFFx = 10 nF
VOUTx = 1.2 V, VINx = VENx = 1.7 V, IOUTx = 1 A, COUTx = 10 µF,
CFFx = 10 nF
图 2. Power-Supply Rejection vs CNR/SSx
图 1. Power-Supply Rejection vs Output Current
90
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
VINx = 1.5 V
VINx = 1.7 V
VINx = 1.8 V
VINx = 2.5 V
VINx = 3.3 V
VINx = 5.0 V
IOUTx = 1 A
20
10
0
IOUTx = 0.75 A
IOUTx = 0.5 A
IOUTx = 0.25 A
IOUTx = 0.1 A
1E+1
1E+2
1E+3
1E+4
1E+5
1E+6
1E+7
1E+1
1E+2
1E+3
1E+4
1E+5
1E+6
1E+7
Frequency (Hz)
Frequency (Hz)
VOUTx = 1.2 V, IOUTx = 1.0 A, COUTx = 10 µF,
CNR/SSx = CFFx = 10 nF
VOUTx = 3.3 V, VINx = VENx = 3.8 V, COUTx = 10 µF, CNR/SSx = CFFx
= 10 nF
图 4. Power-Supply Rejection vs Output Current
图 3. Power-Supply Rejection vs Input Voltage
80
70
60
50
40
30
20
10
90
80
70
60
50
40
30
20
COUTx = 10 mF
COUTx = 22 mF
COUTx = 100 mF
VINx = 6.0 V
VINx = 5.0 V
VINx = 3.8 V
10
0
1E+1
1E+2
1E+3
1E+4
1E+5
1E+6
1E+7
1E+1
1E+2
1E+3
1E+4
1E+5
1E+6
1E+7
Frequency (Hz)
Frequency (Hz)
VOUTx = 1.2 V, VINx = VENx = 1.7 V, IOUTx = 1 A, CFFx = 10 nF
VOUTx = 3.3 V, IOUTx = 1 A, COUTx = 10 µF, CNR/SSx = CFFx = 10 nF
图 5. Power-Supply Rejection vs Output Capacitance
图 6. Power-Supply Rejection vs Input Voltage
版权 © 2017, Texas Instruments Incorporated
7
TPS7A88-Q1
ZHCSGO4A –AUGUST 2017–REVISED SEPTEMBER 2017
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Typical Characteristics (接下页)
at TJ = 25°C, 1.4 V ≤ VINx < 6.5 V, VINx ≥ VOUTx(TARGET) + 0.3 V, VOUTx = 0.8 V, SS_CTRLx = GND, IOUTx = 5 mA, VENx = 1.1 V,
COUTx = 10 μF, CNR/SSx = 0 nF, CFFx = 0 nF, PGx pin pulled up to VOUTx with 100 kΩ, and SS_CTRLx = GND (unless otherwise
noted)
110
100
90
80
70
60
50
40
30
20
10
0
10
1
VOUTx = 0.8 V, 3.94 mVRMS
VOUTx = 1.2 V, 4.31 mVRMS
VOUTx = 1.8 V, 5.1 mVRMS
VOUTx = 2.5 V, 6.03 mVRMS
VOUTx = 3.3 V, 7.43 mVRMS
VOUTx = 5.0 V, 10.3 mVRMS
0.1
0.01
VOUT1 to VOUT2
VOUT2 to VOUT1
0.001
1E+1
1E+2
1E+3
1E+4
1E+5
1E+6
1E+7
1E+1
1E+2
1E+3
1E+4
1E+5
1E+6
1E+7
Frequency (Hz)
Frequency (Hz)
VOUTx = 1.8 V, IOUTx = 100 mA, COUTx = 10 µF,
CNR/SSx = CFFx = 10 nF
VINx = VOUTx + 1 V, IOUTx = 1 A, VRMS BW = 10 Hz to 100 kHz,
COUTx = 10 µF, CNR/SSx = CFFx = 10 nF
图 8. Spectral Noise Density vs Output Voltage
图 7. Channel-to-Channel Output Voltage Isolation vs
Frequency
10
10
CNR/SSx = None, 11.43 mVRMS
CNR/SSx = 0.01 mF, 4.94 mVRMS
CNR/SSx = 0.1 mF, 4.24 mVRMS
CFFx = 0 mF
CFFx = 0.01 mF
CFFx = 0.1 mF
CNR/SSx = 1.0 mF, 4.22 mVRMS
1
0.1
1
0.1
0.01
0.01
0.001
0.001
1E+1
1E+2
1E+3
1E+4
1E+5
1E+6
1E+7
1E+1
1E+2
1E+3
1E+4
1E+5
1E+6
1E+7
Frequency (Hz)
Frequency (Hz)
VINx = 1.7 V, VOUTx = 1.2 V, IOUTx = 1A, VRMS BW = 10 Hz to 100
kHz, COUTx = 10 µF, CFFx = 10 nF
VINx = 3.8 V, VOUTx = 3.3 V, IOUTx = 1 A, VRMS BW = 10 Hz to 100
kHz, COUTx = 10 µF, CNR/SSx = 10 nF
图 9. Spectral Noise Density vs CNR/SSx
图 10. Spectral Noise Density vs CFFx
10
10
VINx = 1.5 V
VINx = 1.8 V
VINx = 2.5 V
COUTx = 10 mF, 4.94 mVRMS
COUTx = 22 mF, 5.05 mVRMS
COUTx = 100 mF, 5.66 mVRMS
VINx = 3.3 V
1
0.1
1
0.1
0.01
0.01
0.001
0.001
1E+1
1E+2
1E+3
1E+4
1E+5
1E+6
1E+7
1E+1
1E+2
1E+3
1E+4
1E+5
1E+6
1E+7
Frequency (Hz)
Frequency (Hz)
VOUTx = 1.2 V, IOUTx = 1 A, COUTx = 10 µF, CNR/SSx = 10 nF
VOUTx = 1.8 V, IOUTx = 1 A, VRMS BW = 10 Hz to 100 kHz,
CFFx = 0.01 µF
图 12. Spectral Noise Density vs COUTx
图 11. Spectral Noise Density vs VINx
8
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Typical Characteristics (接下页)
at TJ = 25°C, 1.4 V ≤ VINx < 6.5 V, VINx ≥ VOUTx(TARGET) + 0.3 V, VOUTx = 0.8 V, SS_CTRLx = GND, IOUTx = 5 mA, VENx = 1.1 V,
COUTx = 10 μF, CNR/SSx = 0 nF, CFFx = 0 nF, PGx pin pulled up to VOUTx with 100 kΩ, and SS_CTRLx = GND (unless otherwise
noted)
12
10
8
12
10
8
6
6
4
4
2
2
0
0
1E-6
1E-5 0.0001 0.001
0.01
0.1
1
10
1E-6
1E-5
0.0001
0.001
0.01
0.1
Noise Reduction Capacitor [CNR/SSx] (mF)
Feed-Forward Capacitor [CFFx] (mF)
VOUTx = 1.8 V, IOUTx = 1 A, CFFx = 0.01 µF,
BW = 10 Hz to 100 kHz
VOUTx = 1.8 V, IOUTx = 1 A, CNR/SSx = 1 µF,
BW = 10 Hz to 100 kHz
图 13. RMS Output Noise vs CNR/SSx
图 14. RMS Output Noise vs CFFx
VOUT2
VOUT2
50 mV/div
20 mV/div
VOUT1
20 mV/div
VOUT1
50 mV/div
IOUT1
500 mA/div
IOUT1
500 mA/div
Time (10 ms/div)
Time (10 ms/div)
VINx = 5.5 V, VOUTx = 5.0 V, IOUTx = 100 mA to 1 A to 100 mA at 1
A/µs, COUTx = 10 µF
VINx = 1.5 V, VOUTx = 1.2 V, IOUTx = 100 mA to 1 A to 100 mA at 1
A/µs, COUTx = 10 µF
图 16. Load Transient Response ()
图 15. Load Transient Response
VENx
1 V/div
VOUTx
200 mV/div
VINx
2 V/div
VPGx
200mV/div
VOUTx
20 mV/div
VPGx
1 V/div
Time (50 ms/div)
VINx = 1.4 V, SS_CTRLx = GND, CNR/SSx = 0 nF
Time (200 ms/div)
VINx = 1.4 V to 6.5 V to 1.4 V at 2 V/µs, VOUTx = 0.8 V,
IOUTx = 1 A, CNR/SSx = CFFx = 10 nF
图 17. Line Transient
图 18. Start-Up
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Typical Characteristics (接下页)
at TJ = 25°C, 1.4 V ≤ VINx < 6.5 V, VINx ≥ VOUTx(TARGET) + 0.3 V, VOUTx = 0.8 V, SS_CTRLx = GND, IOUTx = 5 mA, VENx = 1.1 V,
COUTx = 10 μF, CNR/SSx = 0 nF, CFFx = 0 nF, PGx pin pulled up to VOUTx with 100 kΩ, and SS_CTRLx = GND (unless otherwise
noted)
VEN1
1 V/div
VEN1
1 V/div
VOUT1
200 mV/div
VOUT1
200 mV/div
VPG1
200 mV/div
VPG1
200 mV/div
Time (50 ms/div)
Time (500 ms/div)
VINx = 1.4 V, SS_CTRLx = VINx, CNR/SSx = 10 nF
VINx = 1.4 V, SS_CTRLx = GND, CNR/SSx = 10 nF
图 20. Start-Up
图 19. Start-Up
200
150
100
50
Junction Temperature (TJ)
-40 èC
25 èC
85 èC
125 èC
140 èC
VEN1
1 V/div
-10 èC
VOUT1
200 mV/div
VPG1
200 mV/div
0
0
0.2
0.4
0.6
0.8
1
Time (2 ms/div)
Output Current (A)
VINx = 1.4 V, SS_CTRLx = VINx, CNR/SSx = 1 µF
VINx = 5.5 V. VFB = 95% × VFB(nom)
图 21. Start-Up
图 22. Dropout Voltage vs Output Current
320
240
160
80
0.18
0.12
0.06
0
Junction Temperature (TJ)
-40 èC
25 èC
85 èC
125 èC
140 èC
-10 èC
Junction Temperature (TJ)
-40 èC
-10 èC
25 èC
85 èC
125 èC
140 èC
0
-0.06
0
1.5
3
4.5
6
0
1.5
3
4.5
6
7.5
Input Voltage (V)
Input Voltage (V)
IOUTx = 1 A. VFB = 95% × VFB(nom)
Both channels
图 23. Dropout Voltage vs Input Voltage
图 24. Shutdown Current vs Input Voltage
10
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Typical Characteristics (接下页)
at TJ = 25°C, 1.4 V ≤ VINx < 6.5 V, VINx ≥ VOUTx(TARGET) + 0.3 V, VOUTx = 0.8 V, SS_CTRLx = GND, IOUTx = 5 mA, VENx = 1.1 V,
COUTx = 10 μF, CNR/SSx = 0 nF, CFFx = 0 nF, PGx pin pulled up to VOUTx with 100 kΩ, and SS_CTRLx = GND (unless otherwise
noted)
0.807
0.804
0.801
0.798
0.795
0.792
0.6
0.3
0
Junction Temperature (TJ)
Junction Temperature (TJ)
-40 èC
25 èC
85 èC
125 èC
140 èC
-40 èC
25 èC
85 èC
125 èC
140 èC
-10 èC
-10 èC
-0.3
-0.6
0
0.25
0.5
Output Current (A)
0.75
1
0
1.5
3
4.5
6
7.5
7.2
7.2
Input Voltage (V)
VINx = 1.4 V, VOUTx = 0.8 V
VOUTx = 0.8 V, IOUTx = 50 mA
图 25. Load Regulation
图 26. Line Regulation
3.31
3.3
0
Junction Temperature (TJ)
-40 èC
-10 èC
25 èC
85 èC
125 èC
140 èC
-0.25
-0.5
-0.75
-1
3.29
3.28
3.27
Junction Temperature (TJ)
-40 èC
-10 èC
25 èC
85 èC
125 èC
140 èC
0
0.25
0.5
Output Current (A)
0.75
1
3.2
4
4.8
5.6
6.4
Input Voltage (V)
VINx = 3.6 V, VOUTx = 3.3 V
VOUTx = 3.3 V, IOUTx = 10 mA
图 27. Load Regulation
图 28. Line Regulation
5.025
5.01
0.4
0
Junction Temperature (TJ)
-40 èC
-10 èC
25 èC
85 èC
125 èC
140 èC
4.995
4.98
-0.4
-0.8
-1.2
Junction Temperature (TJ)
-40 èC
-10 èC
25 èC
85 èC
125 èC
140 èC
4.965
0
0.2
0.4
0.6
0.8
1
5.2
5.6
6
6.4
6.8
Output Current (A)
Input Voltage
VINx = 5.3 V, VOUTx = 5 V
VOUTx = 5 V, IOUTx = 5 mA
图 29. Load Regulation
图 30. Line Regulation
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Typical Characteristics (接下页)
at TJ = 25°C, 1.4 V ≤ VINx < 6.5 V, VINx ≥ VOUTx(TARGET) + 0.3 V, VOUTx = 0.8 V, SS_CTRLx = GND, IOUTx = 5 mA, VENx = 1.1 V,
COUTx = 10 μF, CNR/SSx = 0 nF, CFFx = 0 nF, PGx pin pulled up to VOUTx with 100 kΩ, and SS_CTRLx = GND (unless otherwise
noted)
6
7
6
5
4
3
Junction Temperature (TJ)
-40 èC
-10 èC
25 èC
85 èC
125 èC
140 èC
4
2
0
Junction Temperature (TJ)
-40 èC
25 èC
85 èC
125 èC
140 èC
-10 èC
-2
0
1.5
3
4.5
6
7.5
0
0.2
0.4
0.6
0.8
1
Input Voltage (V)
Output Current (A)
Both channels enabled
Both channels enabled
图 31. Ground Current vs Input Voltage
图 32. Ground Current vs Output Current
0.8
0.6
0.4
0.2
0
90
89.5
89
VIN = 1.4 V, IPG = 1 mA
VIN = 1.4 V, IPG = 2 mA
VIN = 1.4 V, IPG = 3 mA
VIN = 6.5 V, IPG = 1 mA
VIN = 6.5 V, IPG = 2 mA
VIN = 6.5 V, IPG = 3 mA
88.5
Falling Threshold
Rising Threshold
88
-40
0
40
80
120
160
-40
0
40
80
120
160
Junction Temperature (èC)
Junction Temperature (èC)
VINx = 1.4 V, 6.5 V
VINx = 1.4 V, 6.5 V
图 33. PG Low Level vs Temperature
图 34. PG Threshold vs Temperature
0.2
0.15
0.1
9
8
7
6
5
VIN = 1.4 V
VIN = 6.5 V
0.05
0
-40
0
40
80
120
160
-50
0
50
100
150
200
Junction Temperature (èC)
Junction Temperature (èC)
VINx = VPGx = 6.5 V
SS_CTRLx = GND
图 35. PG Leakage Current vs Temperature
图 36. Soft-Start Current vs Temperature
12
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Typical Characteristics (接下页)
at TJ = 25°C, 1.4 V ≤ VINx < 6.5 V, VINx ≥ VOUTx(TARGET) + 0.3 V, VOUTx = 0.8 V, SS_CTRLx = GND, IOUTx = 5 mA, VENx = 1.1 V,
COUTx = 10 μF, CNR/SSx = 0 nF, CFFx = 0 nF, PGx pin pulled up to VOUTx with 100 kΩ, and SS_CTRLx = GND (unless otherwise
noted)
120
112
104
96
0.8
0.72
0.64
0.56
0.48
VIN = 1.4 V
VIN = 6.5 V
Falling Threshold
Rising Threshold
88
-50
0
50
100
150
200
-40
0
40
80
120
160
Junction Temperature (èC)
Junction Temperature (èC)
SS_CTRLx = VINx
VINx = 1.4 V
图 37. Soft-Start Current vs Temperature
图 38. Enable Threshold vs Temperature
1.5
1.35
1.2
90
89.5
89
Falling Threshold
Rising Threshold
1.05
88.5
Falling Threshold
Rising Threshold
0.9
88
-50
0
50
100
150
200
-40
0
40
80
120
160
Junction Temperature (èC)
Junction Temperature (èC)
VINx = 1.4 V
图 39. Input UVLO Threshold vs Temperature
图 40. PG Threshold vs Temperature
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7 Detailed Description
7.1 Overview
The TPS7A88-Q1 is a monolithic, dual-channel, low-dropout (LDO) regulator. Each channel is low-noise, high-
PSRR, and capable of sourcing a 1-A load with 250 mV of maximum dropout. These features make the device a
robust solution to solve challenging problems in generating a clean, accurate power supply.
The various features for each of the TPS7A88-Q1 fully independent LDOs simplify using the device in a variety
of applications. These features are organized into three categories as listed in 表 1.
表 1. Features
VOLTAGE REGULATION
High accuracy
SYSTEM START-UP
Programmable soft start
Sequencing controls
Power-good output
INTERNAL PROTECTION
Foldback current limit
Low-noise, high-PSRR output
Fast transient response
Thermal shutdown
7.2 Functional Block Diagram
Current
Limit
IN1
OUT1
Charge
Pump
Active
Discharge
0.8-V
VREF
+
Error
Amp
œ
Softstart
INR/SSx
SS_CTRL1
Control
NR/SS1
FB1
PG1
œ
0.89 x VREF
+
UVLO
Internal
Enable
Control
Thermal
Shutdown
EN1
IN2
Current
Limit
OUT2
Charge
Pump
Active
Discharge
0.8-V
VREF
+
Error
Amp
œ
Softstart
INR/SSx
SS_CTRL2
Control
NR/SS2
FB2
PG2
œ
0.89 x VREF
+
UVLO
Internal
Enable
Control
Thermal
Shutdown
EN2
GND
14
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7.3 Feature Description
7.3.1 Voltage Regulation Features
7.3.1.1 DC Regulation
An LDO functions as a buffed op-amp in which the input signal is the internal reference voltage (VREF), as shown
in 图 41. VREF is designed to have a very low-bandwidth at the input to the error amplifier through the use of a
low-pass filter (VNR/SSx.)
The reference can be considered as a pure DC input signal. The low output impedance of an LDO comes from
the combination of the output capacitor and pass element. The pass element also presents a high input
impedance to the source voltage when operating as a current source. A positive LDO can only source current
because of the class-B architecture.
This device achieves a maximum of 1% output voltage accuracy primarily because of the high-precision band-
gap voltage (VBG) that creates VREF. The low dropout voltage (VDO) reduces the thermal power dissipation
required by the device to regulate the output voltage at a given current level, which improves system efficiency.
Combined, these features help make this device a good approximation of an ideal voltage source.
This device replaces two stand-alone power-supplies and provides load-to-load isolation. The LDOs can be put
in series (cascaded) to achieve even higher PSRR by connecting the output of one channel to the input of the
other channel.
VINx
To Load
R1
VREF
R2
GND
NOTE: VOUTx = VREF × (1 + R1x / R2x).
图 41. Simplified Regulation Circuit
7.3.1.2 AC and Transient Response
Each LDO responds quickly to a transient (large-signal response) on the input supply (line transient) or the
output current (load transient) resulting from the LDO high-input impedance and low output-impedance across
frequency. This same capability also means that each LDO has a high power-supply rejection-ratio (PSRR) and,
when coupled with a low internal noise-floor (Vn), the LDO approximates an ideal power supply in AC (small-
signal) and large-signal conditions.
The performance and internal layout of the device minimizes the coupling of noise from one channel to the other
channel (crosstalk). Good printed circuit board (PCB) layout minimizes the crosstalk.
The choice of external component values optimizes the small- and large-signal response. The NR/SSx capacitor
(CNR/SSx) and feedforward capacitor (CFFx) easily reduce the device noise floor and improve PSRR. See
Optimizing Noise and PSRR for more information on optimizing the noise and PSRR performance.
7.3.2 System Start-Up Features
In many different applications, the power-supply output must turn on within a specific window of time to either
ensure proper operation of the load or to minimize the loading on the input supply or other sequencing
requirements. Each LDO start-up is well-controlled and user-adjustable, solving the demanding requirements
faced by many power-supply design engineers in a simple fashion.
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Feature Description (接下页)
7.3.2.1 Programmable Soft-Start (NR/SSx)
Soft start directly controls the output start-up time and indirectly controls the output current during start-up (in-
rush current).
The external capacitor at the NR/SSx pin (CNR/SSx) sets the output start-up time by setting the rise time of the
internal reference (VNR/SSx), as shown in 图 42. SS_CTRLx provides additional control over the rise time of the
internal reference by enabling control over the charging current (INR/SSx) for CNR/SSx. The voltage at the
SS_CTRLx pin (VSS_CTRLx) must be connected to ground (GND) or VINx
.
Note that if CNR/SSx = 0 nF and the SS_CTRLx pin is connected to VINx, then the output voltage overshoots during
start-up.
SW
INR/SSx
RNRx
NR/SSx Control
VREF
+
CNR/SSx
œ
VFBx
GND
图 42. Simplified Soft-Start Circuit
7.3.2.2 Sequencing
Controlling when a single power supply turns on can be difficult in a power distribution network (PDN) because of
the high power levels inherent in a PDN and the variations between the supplies. The specific channel enable
circuit (ENx) and undervoltage lockout circuit (UVLOx) set the turnon and turnoff time shown in 图 43 and 表 2.
ENx
Internal Enable
Control
UVLOx
图 43. Simplified Turn-On Control
表 2. Sequencing Functionality Table
LDO
STATUS
ACTIVE
DISCHARGE
INPUT VOLTAGE
ENABLE STATUS
POWER-GOOD
ENx = 1
ENx = 0
On
Off
Off
Off
PGx = 1 when VOUTx ≥ VIT(PGx)
VINx ≥ VUVLOx
On
On(1)
PGx = 0
PGx = 0
VINx < VUVLOx – VHYS
ENx = don't care
(1) The active discharge remains on as long as VINx provides enough headroom for the discharge circuit to function.
7.3.2.2.1 Enable (ENx)
The enable signal (VENx) is an active-high digital control that enables the LDO when the enable voltage is past
the rising threshold (VENx ≥ VIH(ENx)) and disables the LDO when the enable voltage is below the falling threshold
(VENx ≤ VIL(ENx)). The exact enable threshold is between VIH(ENx) and VIL(ENx) because ENx is a digital control. In
applications that do not use the enable control, connect ENx to VINx
.
16
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7.3.2.2.2 Undervoltage Lockout (UVLOx) Control
The UVLOx circuit responds quickly to glitches on VINx and attempts to disable the output of the device if these
rails collapse.
As a result of the fast response time of the input supply UVLOx circuit, fast and short line transients well below
the input supply UVLOx falling threshold (brownouts) can cause momentary glitches during the edges of the
transient. These glitches are typical in most LDOs. The local input capacitance prevents severe brownouts in
most applications; see Undervoltage Lockout (UVLOx) Control for more details.
7.3.2.2.3 Active Discharge
When ENx or UVLOx is low, the device connects a resistor of several hundred ohms from VOUTx to GND,
discharging the output capacitance.
Do not rely on the active discharge circuit for discharging large output capacitors when the input voltage drops
below the targeted output voltage. Current flows from the output to the input (reverse current) when VOUTx > VINx
,
which can cause damage to the device (when VOUTx > VINx + 0.3 V); see Reverse Current Protection for more
details.
7.3.2.3 Power-Good Output (PGx)
The PGx signal provides an easy solution to meet demanding sequencing requirements because PGx signals
when the output nears the nominal value. PGx can be used to signal other devices in a system when the output
voltage is near, at, or above the set output voltage (VOUTx(Target)). 图 44 shows a simplified schematic.
The PGx signal is an open-drain digital output that requires a pullup resistor to a voltage source and is active
high. The power-good circuit sets the PGx pin into a high-impedance state to indicate that the power is good.
Using a large feedforward capacitor (CFFx) delays the output voltage and, because the power-good circuit
monitors the FBx pin, the PGx signal can indicate a false positive. A simple solution to this scenario is to use an
external voltage detector device, such as the TPS3780; see Feedforward Capacitor (CFFx) for more information.
VPGx
VBG
VINx
VFBx
œ
+
GND
ENx
GND
UVLOx
GND
图 44. Simplified PGx Circuit
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7.3.3 Internal Protection Features
In many applications, fault events can damage devices in the system. Short-circuits and excessive heat are the
most common fault events for power supplies. The TPS7A88-Q1 implements circuitry for each LDO to protect the
device and the load during these events. Continuously operating in these fault conditions or above a junction
temperature outside of the specified operating range is not recommended because it reduces the long-term
reliability of the device.
7.3.3.1 Foldback Current Limit (ICLx
)
The internal current limit circuit protects the LDO against short-circuit and excessive load current conditions. The
output current decreases (folds back) when the output voltage falls to better protect the device. Each channel
features an independent current limit circuit.
7.3.3.2 Thermal Protection (Tsdx
)
The thermal shutdown circuit protects the LDO against excessive heat in the system, either resulting from current
limit or high ambient temperature. Each channel features an independent thermal shutdown circuit.
The output of the LDO turns off when the LDO temperature (junction temperature, TJ) exceeds the rising thermal
shutdown temperature (Tsdx). The output turns on again after TJ decreases below the falling thermal shutdown
temperature (Tsdx).
A high power dissipation across the device, combined with a high ambient temperature (TA), can cause TJ to be
greater than or equal to Tsdx, triggering the thermal shutdown and causing the output to fall to 0 V. The LDO can
cycle on and off when thermal shutdown is reached under these conditions.
7.4 Device Functional Modes
表 3 provides a comparison between the regulation and disabled operation.
表 3. Device Functional Modes Comparison
PARAMETER
OPERATING MODE
VINx
ENx
IOUTx
IOUTx < ICLx
—
TJ
Regulation(1)
Disabled(2)
VINx > VOUTx(nom) + VDO
VINx < VUVLOx
VENx > VIH(ENx)
VENx < VIL(ENx)
TJ < Tsd
TJ > Tsd
(1) All table conditions must be met.
(2) The device is disabled when any condition is met.
7.4.1 Regulation
The device regulates the output to the targeted output voltage when all the conditions in 表 3 are met.
7.4.2 Disabled
When disabled, the pass device is turned off, the internal circuits are shut down, and the output voltage is
actively discharged to ground by an internal resistor from the output to ground.
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
Successfully implementing an LDO in an application depends on the application requirements. This section
discusses key device features and how to best implement them to achieve a reliable design.
8.1.1 External Component Selection
8.1.1.1 Setting the Output Voltage (Adjustable Operation)
Each LDO resistor feedback network sets the output voltage as (图 45 shows) with an output voltage range of
0.8 V to 5.15 V.
VIN1
IN1
VOUT1
COUT1
OUT1
FB1
TPS7A88-Q1
R1
CIN1
EN1
SS_CTRL1
NR/SS1
R2
CNR/SS1
PG1
VIN2
VOUT2
COUT2
OUT2
IN2
R3
CIN2
EN2
FB2
SS_CTRL2
NR/SS2
R4
CNR/SS2
PG2
GND
Copyright © 2017, Texas Instruments Incorporated
图 45. Adjustable Operation
公式 1 relates the values R1x and R2x to VOUTx(Target) and VFBx. 公式 1 is a rearranged version of 公式 2 which
simplifies the feedback resistor calculation. The current through the feedback network must be equal to or
greater than 5 μA for optimum noise performance and accuracy, as shown in 公式 3.
VOUTx = VFBx × (1 + R1x / R2x)
R1x = (VOUTx / VFBx – 1) × R2x
R2x < VREF / 5 µA
(1)
(2)
(3)
The input bias current into the error amplifier (feedback pin current, IFBx) and tighter tolerance resistors must be
taken into account for optimizing the output voltage accuracy.
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Application Information (接下页)
表 4 lists the resistor combinations for several common output voltages using commercially-available, 1%
tolerance resistors.
表 4. Recommended Feedback Resistor Values
FEEDBACK RESISTOR VALUES(1)
TARGETED OUTPUT
VOLTAGE (V)
CALCULATED OUTPUT
VOLTAGE (V)
R1x (kΩ)
Short
1.37
1.91
2.55
3.32
3.57
4.64
5.49
6.98
9.31
13.7
14.7
22.6
27.4
29.4
33.2
35.7
44.2
56.2
R2x (kΩ)
Open
11
0.8
0.9
0.95
1
0.8
0.9
10.2
10.2
10.7
9.53
10.7
11
0.95
1
1.05
1.1
1.15
1.2
1.35
1.5
1.8
1.9
2.5
2.85
3
1.048
1.1
1.147
1.199
1.347
1.496
1.796
1.899
2.49
2.849
2.998
3.282
3.6
10.2
10.7
11
10.7
10.7
10.7
10.7
10.7
10.2
9.53
10.7
3.3
3.6
4.5
5
4.51
5.002
(1) R1x is connected from OUTx to FBx; R2x is connected from FBx to GND; see 图 45.
8.1.1.2 Capacitor Recommendations
The device is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input
and output pins. Multilayer ceramic capacitors have become the industry standard for these types of applications
and are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and
COG-rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of
Y5V-rated capacitors is not recommended because of large variations in capacitance.
Regardless of the selected ceramic capacitor type, ceramic capacitance varies with operating voltage and
temperature. As a rule of thumb, derate ceramic capacitors by at least 50%. The input and output capacitors
recommended herein account for an effective capacitance derating of approximately 50%, but at higher VINx and
VOUTx conditions (that is, VINx = 5.5 V to VOUTx = 5 V) the derating can be greater than 50% and must be taken
into consideration.
8.1.1.3 Input and Output Capacitor (CINx and COUTx
)
The device is designed and characterized for operation with ceramic capacitors of 10 µF or greater (5 µF or
greater of effective capacitance) at each input and output. Locate the input and output capacitors as near as
practical to the respective input and output pins to minimize the trace inductance from the capacitor to the
device.
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8.1.1.4 Feedforward Capacitor (CFFx
)
Although a feedforward capacitor (CFFx) from the FBx pin to the OUTx pin is not required to achieve stability, a
10-nF external CFFx optimizes the transient, noise, and PSRR performance. A higher capacitance CFFx can be
used; however, the start-up time is longer and the power-good signal can incorrectly indicate that the output
voltage is settled. The maximum recommended value is 100 nF.
To ensure proper PGx functionality, the time constant defined by CNR/SSx must be greater than or equal to the
time constant from CFFx. For a detailed description, see Pros and Cons of Using a Feedforward Capacitor with a
Low Dropout Regulator.
8.1.1.5 Noise-Reduction and Soft-Start Capacitor (CNR/SSx
)
Although a noise-reduction and soft-start capacitor (CNR/SSx) from the NR/SSx pin to GND is not required, CNR/SSx
is highly recommended to control the start-up time and reduce the noise floor of the device. The typical value
used is 10 nF, and the maximum recommended value is 10 µF.
8.1.2 Start-Up
8.1.2.1 Circuit Soft-Start Control (NR/SSx)
Each output of the device features a user-adjustable, monotonic, voltage-controlled soft start that is set with an
external capacitor (CNR/SSx). This soft start eliminates power-up initialization problems when powering field-
programmable gate arrays (FPGAs), digital signal processors (DSPs), or other processors. The controlled
voltage ramp of the output also reduces peak in-rush current during start-up, which minimizes start-up transients
to the input power bus.
The output voltage (VOUTx) rises proportionally to VNR/SSx during start-up as the LDO regulates so that the
feedback voltage equals the NR/SSx voltage (VFBx = VNR/SSx). As such, the time required for VNR/SSx to reach the
nominal value determines the rise time of VOUTx (start-up time).
The soft-start ramp time depends on the soft-start charging current (INR/SSx), the soft-start capacitance (CNR/SSx),
and the internal reference (VREF). The approximate soft-start ramp time (tSSx) can be calculated with 公式 4:
tSSx = (VREF × CNR/SSx) / INR/SSx
(4)
The SS_CTRLx pin for each output sets the value of the internal current source, maintaining a fast start-up time
even with a large CNR/SSx capacitor. When the SS_CTRLx pin is connected to GND, the typical value for the
INR/SSx current is 6.2 µA. Connecting the SS_CTRLx pin to INx increases the typical soft-start charging current to
100 µA. The larger charging current for INR/SSx is useful when smaller start-up ramp times are required or when
using larger noise-reduction capacitors.
Not using a noise-reduction capacitor on the NR/SSx pin and tying the SS_CTRLx pin to VINx results in output
voltage overshoot of approximately 10%. Connecting the SS_CTRLx pin to GND or using a capacitor on the
NR/SSx pin minimizes the overshoot.
Values for the soft-start charging currents are provided in Electrical Characteristics.
8.1.2.1.1 In-Rush Current
In-rush current is defined as the current into the LDO at the INx pin during start-up. In-rush current then consists
primarily of the sum of load current and the current used to charge the output capacitor. This current is difficult to
measure because the input capacitor must be removed, which is not recommended. However, this soft-start
current can be estimated by 公式 5:
C
OUTx ´ dVOUTx(t)
VOUTx(t)
RLOAD
IOUTx(t) =
+
dt
where:
•
•
•
VOUTx(t) is the instantaneous output voltage of the turn-on ramp
dVOUTx(t) / dt is the slope of the VOUTx ramp
RLOAD is the resistive load impedance
(5)
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8.1.2.2 Undervoltage Lockout (UVLOx) Control
The UVLOx circuit ensures that the device stays disabled before the input or bias supplies reach the minimum
operational voltage range and ensures that the device properly shuts down when the input supply collapses.
图 46 and 表 5 explain the UVLOx circuit response to various input voltage events, assuming VENx ≥ VIH(ENx)
.
UVLOx Rising Threshold
UVLOx Hysteresis
VINx
C
VOUTx
tAt
tBt
tDt
tEt
tFt
tGt
图 46. Typical UVLOx Operation
表 5. Typical UVLOx Operation Description
REGION
EVENT
VOUTx STATUS
COMMENT
A
B
C
D
Turn-on, VINx ≥ VUVLOx
Regulation
0
1
1
1
Start-up
Regulates to target VOUTx
Brownout, VINx ≥ VUVLOx – VHYS
Regulation
The output can fall out of regulation but the device is still enabled.
Regulates to target VOUTx
The device is disabled and the output falls because of the load and
active discharge circuit. The device is reenabled when the UVLOx
rising threshold is reached by the input voltage and a normal start-
up then follows.
E
Brownout, VINx < VUVLOx – VHYS
0
F
Regulation
1
0
Regulates to target VOUTx
G
Turn-off, VINx < VUVLOx – VHYS
The output falls because of the load and active discharge circuit.
Similar to many other LDOs with this feature, the UVLOx circuit takes a few microseconds to fully assert. During
this time, a downward line transient below approximately 0.8 V causes the UVLOx to assert for a short time;
however, the UVLOx circuit does not have enough stored energy to fully discharge the internal circuits inside of
the device. When the UVLOx circuit is not given enough time to fully discharge the internal nodes, the outputs
are not fully disabled.
The effect of the downward line transient can be mitigated by using a larger input capacitor to increase the fall
time of the input supply when operating near the minimum VINx
.
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8.1.2.3 Power-Good (PGx) Function
The power-good circuit monitors the voltage at the feedback pin to indicate the status of the output voltage. The
power-good circuit asserts whenever FBx, VINx, or ENx are below the thresholds. The PGx operation versus the
output voltage is shown in 图 47, which 表 6 describes.
PGx Rising Threshold
PGx Falling Threshold
VOUTx
E
C
PGx
tAt
tBt
tDt
tFt
tGt
图 47. Typical PGx Operation
表 6. Typical PGx Operation Description
REGION
EVENT
Turn-on
PGx STATUS
FBx VOLTAGE
A
B
C
D
E
F
0
VFBx < VIT(PGx) + VHYS(PGx)
Regulation
Output voltage dip
Regulation
Hi-Z
Hi-Z
Hi-Z
0
VFBx ≥ VIT(PGx)
Output voltage dip
Regulation
VFBx < VIT(PGx)
FBx ≥ VIT(PGx)
VFBx < VIT(PGx)
Hi-Z
0
V
G
Turn-off
The PGx pin is open-drain and connecting a pullup resistor to an external supply enables other devices to
receive power-good as a logic signal that can be used for sequencing. Make sure that the external pullup supply
voltage results in a valid logic signal for the receiving device or devices.
To ensure proper operation of the power-good circuit, the pullup resistor value must be between 10 kΩ and 100
kΩ. The lower limit of 10 kΩ results from the maximum pulldown strength of the power-good transistor, and the
upper limit of 100 kΩ results from the maximum leakage current at the power-good node. If the pullup resistor is
outside of this range, then the power-good signal may not read a valid digital logic level.
Using a large CFFx with a small CNR/SSx causes the power-good signal to incorrectly indicate that the output
voltage has settled during turn-on. The CFFx time constant must be greater than the soft-start time constant to
ensure proper operation of the PGx during start-up. For a detailed description, see Pros and Cons of Using a
Feedforward Capacitor with a Low Dropout Regulator.
The state of PGx is only valid when the device operates above the minimum supply voltage. During short
brownout events and at light loads, power-good does not assert because the output voltage (therefore VFBx) is
sustained by the output capacitance.
8.1.3 AC and Transient Performance
LDO AC performance for a dual-channel device includes power-supply rejection ratio, channel-to-channel output
isolation, output current transient response, and output noise. These metrics are primarily a function of open-loop
gain, bandwidth, and phase margin that control the closed-loop input and output impedance of the LDO. The
output noise is primarily a result of the reference and error amplifier noise.
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8.1.3.1 Power-Supply Rejection Ratio (PSRR)
PSRR is a measure of how well the LDO control-loop rejects signals from VINx to VOUTx across the frequency
spectrum (usually 10 Hz to 10 MHz). 公式 6 shows the PSRR calculation as a function of frequency for the input
signal (VINx[f]) and output signal (VOUTx[f]).
≈
∆
«
’
÷
◊
V
INx(f)
PSRR (dB) = 20 Log10
VOUTx(f)
(6)
Even though PSRR is a loss in signal amplitude, PSRR is shown as positive values in decibels (dB) for
convenience.
A simplified diagram of PSRR versus frequency is shown in 图 48.
PSRR Boost Circuit Improves PSRR in This Region
Band-Gap
RC Filter
Error Amplifier,
Flat-Gain Region
Error Amplifier,
Gain Roll-Off
Output Capacitor
|ZCOUTx| Decreasing
Output Capacitor
|ZCOUTx| Increasing
Band Gap
Sub 10 Hz
10 Hzœ1 MHz
100 kHz +
Frequency (Hz)
图 48. Power-Supply Rejection Ratio Diagram
An LDO is often employed not only as a DC-DC regulator, but also to provide exceptionally clean power-supply
voltages that exhibit ultra-low noise and ripple to sensitive system components. This usage is especially true for
the TPS7A88-Q1.
The TPS7A88-Q1 features an innovative circuit to boost the PSRR between 200 kHz and 1 MHz; see 图 4. To
achieve the maximum benefit of this PSRR boost circuit, using a capacitor with a minimum impedance in the
100-kHz to 1-MHz band is recommended.
8.1.3.2 Channel-to-Channel Output Isolation and Crosstalk
Output isolation is a measure of how well the device prevents voltage disturbances on one output from affecting
the other output. This attenuation appears in load transient tests on the other output; however, to numerically
quantify the rejection, the output channel isolation is expressed in decibels (dB).
Output isolation performance is a strong function of the PCB layout. See Layout on how to optimize the isolation
performance.
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8.1.3.3 Output Voltage Noise
The TPS7A88-Q1 is designed for system applications where minimizing noise on the power-supply rail is critical
to system performance. For example, the TPS7A88-Q1 can be used in a phase-locked loop (PLL)-based
clocking circuit can be used for minimum phase noise, or in test and measurement systems where small power-
supply noise fluctuations reduce system dynamic range.
LDO noise is defined as the internally-generated intrinsic noise created by the semiconductor circuits alone. This
noise is the sum of various types of noise (such as shot noise associated with current-through-pin junctions,
thermal noise caused by thermal agitation of charge carriers, flicker noise, or 1/f noise and dominates at lower
frequencies as a function of 1/f). 图 49 shows a simplified output voltage noise density plot versus frequency.
Charge Pump Spurs
Wide-Band Noise
Integrated Noise
From Band-Gap and Error Amplifier
Measurement Noise Floor
Frequency (Hz)
图 49. Output Voltage Noise Diagram
For further details, see How to Measure LDO Noise.
8.1.3.4 Optimizing Noise and PSRR
The ultra-low noise floor and PSRR of the device can be improved in several ways, as 表 7 describes.
表 7. Effect of Various Parameters on AC Performance(1)(2)
NOISE
PSRR
PARAMETER
LOW-
MID-
HIGH-
LOW-
MID-
HIGH-
FREQUENCY
FREQUENCY
FREQUENCY
FREQUENCY
FREQUENCY
FREQUENCY
CNR/SSx
CFFx
+++
No effect
No effect
+++
++
+
No effect
+
++
No effect
+
+++
+
+
+++
+
+++
+
COUTx
No effect
+++
+++
++
VINx – VOUTx
PCB layout
+
+++
+++
++
++
+
+
+++
(1) The number of plus signs indicate the improvement in noise or PSRR performance by increasing the parameter value.
(2) Shaded cells indicate the easiest improvement to noise or PSRR performance.
The noise-reduction capacitor (in conjunction with the noise-reduction resistor) forms a low-pass filter (LPF) that
filters out the noise from the reference before gaining up with the error amplifier, which minimizes the output
voltage noise floor. The LPF is a single-pole filter and the cutoff frequency can be calculated with 公式 7. The
typical value of RNR is 250 kΩ. The effect of the CNR/SSx capacitor increases when VOUTx(Target) increases because
the noise from the reference is gained up when the output voltage increases. For low-noise applications, a 10-nF
to 10-µF CNR/SSx is recommended.
fcutoff = 1 / (2 × π × RNR × CNR/SSx
)
(7)
The feedforward capacitor reduces output voltage noise by filtering out the mid-band frequency noise. The
feedforward capacitor can be optimized by placing a pole-zero pair near the edge of the loop bandwidth and
pushing out the loop bandwidth, thus improving mid-band PSRR.
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A larger COUTx or multiple output capacitors reduces high-frequency output voltage noise and PSRR by reducing
the high-frequency output impedance of the power supply.
Additionally, a higher input voltage improves the noise and PSRR because greater headroom is provided for the
internal circuits. However, a high power dissipation across the die increases the output noise because of the
increase in junction temperature.
Good PCB layout improves the PSRR and noise performance by providing heat sinking at low frequencies and
isolating VOUTx at high frequencies.
8.1.3.4.1 Charge Pump Noise
The device internal charge pump generates a minimal amount of noise.
The high-frequency components of the output voltage noise density curve are filtered out in most applications by
using 10-nF to 100-nF bypass capacitors close to the load. Using a ferrite bead between the LDO output and the
load input capacitors forms a pi-filter with reduces the high-frequency noise contribution.
8.1.3.5 Load Transient Response
The load-step transient response is the output voltage response by the LDO to a step in load current, whereby
output voltage regulation is maintained. There are two key transitions during a load transient response: the
transition from a light to a heavy load and the transition from a heavy to a light load. The regions shown in 图 50
are broken down in this section and are described in 表 8. Regions A, E, and H are where the output voltage is in
steady-state.
VOUTx
B
F
A
C
D
E
G
H
IOUTx
图 50. Load Transient Waveform
表 8. Load Transient Waveform Description
REGION
DESCRIPTION
COMMENT
A
B
Regulation
Regulation
Output current ramping
Initial voltage dip is a result of the depletion of the output capacitor charge.
Recovery from the dip results from the LDO increasing the sourcing current, and leads
to output voltage regulation.
C
LDO responding to transient
At high load currents the LDO takes some time to heat up. During this time the output
voltage changes slightly.
D
E
F
Reaching thermal equilibrium
Regulation
Regulation
Initial voltage rise results from the LDO sourcing a large current, and leads to the
output capacitor charge to increase.
Output current ramping
Recovery from the rise results from the LDO decreasing the sourcing current in
combination with the load discharging the output capacitor.
G
H
LDO responding to transient
Regulation
Regulation
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The transient response peaks (VOUTx(max) and VOUTx(min)) are improved by using more output capacitance;
however, doing so slows down the recovery time (Wrise and Wfall). 图 51 shows these parameters during a load
transient with a given pulse duration (PW) and current levels (IOUTx(LO) and IOUTx(HI)).
VOUTx(max)
Wrise
VOUTx
Wfall
VOUTx(min)
IOUTx(HI)
PW
IOUTx
IOUTx(LO)
IOUTx(LO)
trise
tfall
图 51. Simplified Load Transient Waveform
8.1.4 DC Performance
8.1.4.1 Output Voltage Accuracy (VOUTx
)
The device features an output voltage accuracy of 1% maximum that includes the errors introduced by the
internal reference, load regulation, line regulation, and operating temperature as specified by Electrical
Characteristics. Output voltage accuracy specifies minimum and maximum output voltage error relative to the
expected nominal output voltage stated as a percent.
8.1.4.2 Dropout Voltage (VDO
)
Generally speaking, the dropout voltage often refers to the minimum voltage difference between the input and
output voltage (VDO = VINx – VOUTx) that is required for regulation. When VINx drops below the required VDO for
the given load current, the device functions as a resistive switch and does not regulate output voltage. Dropout
voltage is proportional to the output current because the device is operating as a resistive switch, as shown in 图
52.
VDO
IOUTx
图 52. Dropout Voltage versus Output Current
Dropout voltage is affected by the drive strength for the gate of the pass element, which is nonlinear with respect
to VINx on this device because of the internal charge pump. Dropout voltage increases exponentially when the
input voltage nears the maximum operating voltage because the charge pump multiplies the input voltage by a
factor of 4 and then is internally clamped.
8.1.4.2.1 Behavior When Transitioning From Dropout Into Regulation
Some applications can have transients that place the LDO into dropout, such as slower ramps on VINX for start-
up or load transients. As with other LDOs, the output can overshoot on recovery from these conditions.
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A ramping input supply can cause an LDO to overshoot on start-up when the slew rate and voltage levels are in
the right range, as shown in 图 53. This condition is easily avoided by using an enable signal or increasing the
soft-start time with CSS/NRx
.
Input Voltage
Response time for
LDO to get back into
regulation.
Load current discharges
output voltage.
VINx = VOUTx(nom) + VDO
Output Voltage
Dropout
VOUTx = VINx - VDO
Output Voltage in
normal regulation.
Time
图 53. Start-Up Into Dropout
8.1.5 Reverse Current Protection
As with most LDOs, this device can be damaged by excessive reverse current.
Reverse current is current that flows through the body diode on the pass element instead of the normal
conducting channel. At high enough magnitudes, this current flow degrades long-term reliability of the device
resulting from risks of electromigration and excess heat that is dissipated across the device. If the current flow is
high enough, a latch-up condition can be entered.
Conditions where excessive reverse current can occur are outlined in this section, all of which can exceed the
absolute maximum rating of VOUTx > VINx + 0.3 V:
•
•
•
If the device has a large COUTx and the input supply collapses quickly with little or no load current
The output is biased when the input supply is not established
The output is biased above the input supply
If excessive reverse current flow is expected in the application, then external protection must be used to protect
the device. 图 54 shows one approach of protecting the device.
Schottky Diode
Internal Body Diode
INx
OUTx
TI Device
COUTx
CINx
GND
Copyright © 2016, Texas Instruments Incorporated
图 54. Example Circuit for Reverse Current Protection Using a Schottky Diode
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8.1.6 Power Dissipation (PD)
Circuit reliability demands that proper consideration is given to device power dissipation, location of the circuit on
the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must
be as free as possible of other heat-generating devices that cause added thermal stresses.
As a first-order approximation, power dissipation in the regulator depends on the input-to-output voltage
difference and load conditions. PD can be approximated using 公式 8:
PD = (VOUTx – VINx) × IOUTx
(8)
An important note is that power dissipation can be minimized, and thus greater efficiency achieved, by proper
selection of the system voltage rails. Proper selection allows the minimum input-to-output voltage differential to
be obtained. The low dropout of the device allows for maximum efficiency across a wide range of output
voltages.
The main heat conduction path for the device is through the thermal pad on the package. As such, the thermal
pad must be soldered to a copper pad area under the device. This pad area contains an array of plated vias that
conduct heat to any inner plane areas or to a bottom-side copper plane.
The maximum power dissipation determines the maximum allowable junction temperature (TJ) for the device.
Power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance
(θJA) of the combined PCB, device package, and the temperature of the ambient air (TA), according to 公式 9.
The equation is rearranged for output current in 公式 10.
TJ = TA + θJA × PD
(9)
IOUTx = (TJ – TA) / [θJA × (VINx – VOUTx)]
(10)
Unfortunately, this thermal resistance (θJA) is highly dependent on the heat-spreading capability built into the
particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the
planes. The θJA recorded in the table is determined by the JEDEC standard, PCB, and copper-spreading area,
and is only used as a relative measure of package thermal performance. Note that for a well-designed thermal
layout, θJA is actually the sum of the VQFN package junction-to-case (bottom) thermal resistance (θJCbot) plus the
thermal resistance contribution by the PCB copper.
8.1.6.1 Estimating Junction Temperature
The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures
of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal
resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics
are determined to be significantly independent of the copper-spreading area. The key thermal metrics (ΨJT and
ΨJB) are given in the table and are used in accordance with 公式 11.
YJT: TJ = TT + YJT ´ PD
YJB: TJ = TB + YJB ´ PD
where:
•
•
•
PD is the power dissipated as explained in 公式 8
TT is the temperature at the center-top of the device package, and
TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge
(11)
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29
TPS7A88-Q1
ZHCSGO4A –AUGUST 2017–REVISED SEPTEMBER 2017
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8.2 Typical Application
This section discusses the implementation of the TPS7A88-Q1 to regulate from a common input voltage to two
output voltages of the same value. This is a common application where two noise-sensitive loads must have the
same supply voltage but have high channel-to-channel isolation. The schematic for this application circuit is
shown in 图 55.
VIN1
IN1
VOUT1
COUT1
OUT1
FB1
TPS7A88-Q1
R1
CIN1
EN1
SS_CTRL1
NR/SS1
R2
CNR/SS1
PG1
VIN2
VOUT2
COUT2
OUT2
IN2
R3
CIN2
EN2
FB2
SS_CTRL2
NR/SS2
R4
CNR/SS2
PG2
GND
Copyright © 2017, Texas Instruments Incorporated
图 55. Application Example
8.2.1 Design Requirements
For the design example shown in 图 55, use the parameters listed in 表 9 as the input parameters.
表 9. Design Parameters
PARAMETER
DESIGN REQUIREMENT
1.8 V, ±3%, provided by the DC-DC converter switching at 750 kHz
55°C
Input voltages (VIN1 and VIN2
)
Maximum ambient operating temperature
Output voltages (VOUT1 and VOUT2
)
1.2 V, ±1%, output voltages are isolated
1 A (maximum), 10 mA (minimum)
Isolation greater than 50 dB at 100 kHz
< 5 µVRMS, bandwidth = 10 Hz to 100 kHz
> 40 dB
Output currents (IOUT2 and IOUT2
Channel-to-channel isolation
RMS noise
)
PSRR at 750 kHz
Start-up time
< 5 ms
8.2.2 Detailed Design Procedure
The output voltages can be set to 1.2 V by selecting the correct values for R1, R3 and R2, R4; see 公式 1.
Input and output capacitors are selected in accordance with External Component Selection . Ceramic
capacitances of 10 µF for inputs and outputs are selected.
To satisfy the required startup time (tSSx) and still maintain low-noise performance, a 0.1-µF CNR/SSx is selected
for channels with SS_CTRL1 and SS_CTRL2 connected to VIN1 and VIN2, respectively. This value is calculated
with 公式 12.
tSSx = (VREF ´ CNR/SSx ) /1NR/SSx
(12)
With a 1-A maximum load, the internal power dissipation is 600 mW per channel (or 1.2-W total), which
corresponds to a 40°C junction temperature increase. With an 55°C maximum ambient temperature, the junction
temperature is at 95°C. To minimize noise, a feedforward capacitance (CFF) of 10 nF is selected.
30
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TPS7A88-Q1
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Channel-to-channel isolation depends significantly on the layout of the design. To minimize crosstalk between
the outputs, keep the output capacitor grounds on separate sides of the design. See Layout for an example of
how to layout the TPS7A88-Q1 to achieve best PSRR, channel-to-channel isolation, and noise.
8.2.3 Application Curves
90
80
70
60
50
40
30
20
10
0
110
100
90
80
70
60
50
40
30
20
10
VINx = 1.8 V
1E+1
1E+2
1E+3
1E+4
1E+5
1E+6
1E+7
1E+1
1E+2
1E+3
1E+4
1E+5
1E+6
Frequency (Hz)
Frequency (Hz)
图 56. Power-Supply Rejection
图 57. Channel-to-Channel Isolation
0.5
VINx = 1.8 V, VRMS = 4.26 mV
0.3
0.2
0.1
0.05
0.03
0.02
0.01
0.005
0.003
0.002
0.001
1E+1
1E+2
1E+3
1E+4
1E+5
1E+6
1E+7
Frequency (Hz)
BW range
图 58. Output Noise
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TPS7A88-Q1
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9 Power Supply Recommendations
Both inputs of the TPS7A88-Q1 are designed to operate from an input voltage range between 1.4 V and 6.5 V.
The input voltage range must provide adequate headroom for the device to have a regulated output. This input
supply must be well-regulated. If the input supply is noisy, additional input capacitors with low ESR can help
improve the output noise performance.
10 Layout
10.1 Layout Guidelines
General guidelines for linear regulator designs are to place all circuit components on the same side of the circuit
board and as near as practical to the respective LDO pin connections. Place ground return connections to the
input and output capacitor, and to the LDO ground pin as close to each other as possible, connected by a wide,
component-side, copper surface. The use of vias and long traces to create LDO circuit connections is strongly
discouraged and negatively affects system performance.
10.1.1 Board Layout
To maximize the AC performance of the TPS7A88-Q1, TI recommends following the layout example shown in 图
59.This layout isolates the analog ground (AGND) from the noisy power ground. Components that must be
connected to the quiet analog ground are the noise reduction capacitors (CNR/SSx) and the lower feedback
resistors (R2 and R4). These components must have a separate connection back to the power pad of the device.
To minimize crosstalk between the two outputs, the output capacitor grounds are positioned on opposite sides of
the layout and only connect back to the device at opposite sides of the thermal pad. TI recommends connecting
the GND pins directly to the thermal pad and not to any external plane.
To maximize the output voltage accuracy, the connection from each output voltage back to top output divider
resistors (R1 and R3) must be made as close as possible to the load. This method of connecting the feedback
trace eliminates the voltage drop from the device output to the load.
To improve thermal performance, a thermal via array must connect the thermal pad to internal ground planes. A
larger area for the internal ground planes improves the thermal performance and lowers the operating
temperature of the device.
32
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TPS7A88-Q1
www.ti.com.cn
ZHCSGO4A –AUGUST 2017–REVISED SEPTEMBER 2017
10.2 Layout Example
Power Ground
RPG1
AGND
R2
PGOOD1
R1
CNR/SS1
CFF1
VOUT1 SENSE
on Bottom
Layer
20
19
18
17
16
CIN1
COUT1
1
2
3
4
5
15
14
13
12
11
IN1
IN1
OUT1
VIN1
VOUT1
OUT1
GND
GND
IN2
IN2
OUT2
OUT2
VOUT2
VIN2
CIN2
COUT2
6
7
8
9
10
VOUT2 SENSE
on Bottom
Layer
CFF2
CNR/SS2
R3
PGOOD2
R4
AGND
RPG2
Circles denote PCB via connections.
Power Ground
图 59. TPS7A88-Q1 Example Layout
版权 © 2017, Texas Instruments Incorporated
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TPS7A88-Q1
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11 器件和文档支持
11.1 器件支持
11.1.1 开发支持
11.1.1.1 评估模块
我们提供了一款评估模块 (EVM)，可与 TPS7A88-Q1 配套使用，帮助评估初始电路性能。表 10 列出了此装置的摘
要信息。
表 10. 设计套件与评估模块(1)
名称
部件号
TPS7A88 低压降稳压器评估模块
TPS7A88EVM-776
(1) 欲获得最新的封装和订货信息，请参阅本文档末尾的封装选项附录，或者访问 www.ti.com 查看器件产品文件夹。
可在德州仪器 (TI) 网站 (www.ti.com) 上的 TPS7A88-Q1 产品文件夹下申请获取该 EVM。
11.1.1.2 Spice 模型
分析模拟电路和系统的性能时，使用 spice 模型对电路性能进行计算机仿真非常有用。可从 TPS7A88-Q1 产品文
件夹中的仿真模型下申请获取 TPS7A88-Q1 的 Spice 模型。
11.1.2 器件命名规则
表 11. 订购信息(1)
产品
说明
YYY 为封装标识符。
TPS7A88xxQYYYZ -Q1
XX 表示输出电压。01 为可调输出版本。
Z 为封装数量。
(1) 欲获得最新的封装和订货信息，请参阅本文档末尾的封装选项附录，或者访问 www.ti.com 查看器件产品文件夹。
11.2 文档支持
11.2.1 相关文档
《TPS3780 产品说明书》(SBVS250)
《TPS7A88 评估模块》(SBVU027)
《使用前馈电容器和低压降稳压器的优缺点》(SBVA042)
《如何测量 LDO 噪声》（文献编号：SLYY076）
11.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
34
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TPS7A88-Q1
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ZHCSGO4A –AUGUST 2017–REVISED SEPTEMBER 2017
11.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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TPS7A88-Q1
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12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据如有变更，恕不另行通知
和修订此文档。如欲获取此产品说明书的浏览器版本，请参阅左侧的导航。
36
版权 © 2017, Texas Instruments Incorporated
TPS7A88-Q1
www.ti.com.cn
ZHCSGO4A –AUGUST 2017–REVISED SEPTEMBER 2017
PACKAGE OUTLINE
RTJ0020J
WQFN - 0.8 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
B
0.5
0.3
A
0.3
0.2
PIN 1 INDEX AREA
DETAIL
OPTIONAL TERMINAL
TYPICAL
4.1
3.9
0.1 MIN
(0.05)
SECTION A-A
SCALE 25.000
SECTION A-A
TYPICAL
C
0.8 MAX
SEATING PLANE
0.08 C
0.05
0.00
2.5 0.1
2X 2
A3
EXPOSED
THERMAL PAD
(0.2) TYP
4X ( 0.35)
6
10
A2
SEE TERMINAL
DETAIL
5
11
(1.695)
TYP
2X
A
A
SYMM
21
2
1
15
16X 0.5
0.3
0.2
20X
A4
A1
0.1
C A B
20
16
SYMM
20X
0.05
PIN 1 ID
(OPTIONAL)
0.5
0.3
(1.695) TYP
4223320/A 11/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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版权 © 2017, Texas Instruments Incorporated
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TPS7A88-Q1
ZHCSGO4A –AUGUST 2017–REVISED SEPTEMBER 2017
www.ti.com.cn
EXAMPLE BOARD LAYOUT
RTJ0020J
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
2.5)
(1.695)
TYP
20
16
20X (0.6)
A1
20X (0.25)
1
A4
15
(1.695)
TYP
21
SYMM
(3.8)
(1)
TYP
16X (0.5)
5
11
(R0.05)
TYP
A2
A3
4X ( 0.35)
6
10
(1) TYP
(
0.2) TYP
VIA
SYMM
(3.8)
LAND PATTERN EXAMPLE
SCALE:15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4223320/A 11/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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TPS7A88-Q1
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ZHCSGO4A –AUGUST 2017–REVISED SEPTEMBER 2017
EXAMPLE STENCIL DESIGN
RTJ0020J
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
(1.695)
(0.655) TYP
20
16
4X ( 0.35)
20X (0.6)
A1
A4
21
1
15
(1.695)
20X (0.25)
(0.655)
TYP
SYMM
(3.8)
16X (0.5)
11
5
(R0.05)
TYP
METAL
TYP
A2
A3
6
10
4X ( 1.11)
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 21:
79% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4223320/A 11/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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版权 © 2017, Texas Instruments Incorporated
39
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS7A8801QRTJRQ1
ACTIVE
QFN
RTJ
20
3000 RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 140
----->
7A88Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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