TPS7B63-Q1 [TI]
汽车类 300mA、电池供电运行 (40V)、高 PSRR、低 IQ、低压降稳压器;
| 型号： | TPS7B63-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类 300mA、电池供电运行 (40V)、高 PSRR、低 IQ、低压降稳压器 电池 稳压器 |
| 文件： | 总34页 (文件大小：1995K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS7B6333-Q1, TPS7B6350-Q1
ZHCSG47C –FEBRUARY 2017 –REVISED DECEMBER 2022
TPS7B63xx-Q1
300mA、40V 高压超低静态电流看门狗LDO
1 特性
3 说明
• 符合面向汽车应用的AEC-Q100 标准：
– 温度等级1: –40 ° C 至125 ° C 、T A
• 最大输出电流：300mA
在汽车微控制器或微处理器电源应用中，看门狗用于监
测微控制器的工作状态，以防止软件失控。在可靠的系
统中，看门狗必须独立于微控制器。
• 4V 至40V 宽VIN 输入电压范围，瞬态电压高达
45V
TPS7B63xx-Q1 是300mA 看门狗低压降稳压器 (LDO)
系列器件，额定工作电压高达 40V，轻负载条件下的
典型静态电流仅为 19µA。该系列器件集成了一项可编
程功能，用于选择窗口看门狗或标准看门狗，并使用外
部电阻设置看门狗时间，精度在10% 以内。
• 3.3V 和5V 两种固定输出电压
• 最大压降电压：400mV/300mA
• 在宽电容（4.7µF 至500µF）和ESR（0.001Ω至
20Ω）范围内，与输出电容器搭配使用时可保持稳
定
TPS7B63xx-Q1 器件上的 PG 引脚指示输出电压何时
达到稳定且处于稳压范围内。可以通过选择外部组件来
调整电源正常延迟周期和电源正常阈值。该系列器件还
具有集成的短路保护和过流保护功能。上述特性组合使
得该系列器件极具灵活性，适用于为汽车应用中的微控
制器供电。
• 低静态电流(I(Q))：
– EN 为低电平（关断模式）时< 4µA
– 轻负载（WD_EN 为高电平）时具有19µA 的典
型值（看门狗禁用）
• 可针对窗口看门狗和标准看门狗进行配置
• 开关窗口比例可配置为1:1 或8:1
• 完全可调的看门狗周期（10ms 至500ms）
• 看门狗周期精度为10%
• 专用WD_EN 引脚，用于控制看门狗开关
• 完全可调的电源正常阈值和电源正常延迟周期
• 针对UVLO 的低输入电压跟踪功能
• 集成故障保护
器件信息
器件型号(1)
输出电压
固定3.3V
固定5V
封装
TPS7B6333-Q1
TPS7B6350-Q1
HTSSOP (16)
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
– 过载电流限制保护
– 热关断
• 功能安全型
– 可提供用于功能安全系统设计的文档
• 16 引脚HTSSOP 封装
2 应用
• 汽车MCU 电源
• 车身控制模块(BCM)
• 座椅舒适模块
• EV 和HEV 电池管理系统(BMS)
• 电子换挡器
• 变速箱
• 电动助力转向(EPS)
典型应用原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSDU9
TPS7B6333-Q1, TPS7B6350-Q1
ZHCSG47C –FEBRUARY 2017 –REVISED DECEMBER 2022
www.ti.com.cn
Table of Contents
7.3 Feature Description...................................................13
7.4 Device Functional Modes..........................................20
8 Application and Implementation..................................21
8.1 Application Information............................................. 21
8.2 Typical Application.................................................... 21
8.3 Power Supply Recommendations.............................23
8.4 Layout....................................................................... 24
9 Device and Documentation Support............................25
9.1 Documentation Support............................................ 25
9.2 接收文档更新通知..................................................... 25
9.3 支持资源....................................................................25
9.4 Trademarks...............................................................25
9.5 Electrostatic Discharge Caution................................25
9.6 术语表....................................................................... 25
10 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Switching Characteristics............................................8
6.7 Typical Characteristics................................................9
7 Detailed Description......................................................13
7.1 Overview...................................................................13
7.2 Functional Block Diagram.........................................13
Information.................................................................... 25
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision B (September 2020) to Revision C (December 2022)
Page
• Changed PADJ and WTS pins to inputs instead of outputs................................................................................3
• Changed Load Regulation graph and changed VIN condition for IOUT = 200 mA Line Transient graphs...........9
• Changed resistor values in TPS7B63xx-Q1 Typical Application Schematic figure...........................................21
Changes from Revision A (March 2017) to Revision B (September 2020)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• 更改了特性部分中的汽车特定应用要点..............................................................................................................1
• 将特性部分的看门狗周期精度从9% 更改为10%.............................................................................................. 1
• 向特性部分添加了“功能安全型”要点..............................................................................................................1
• 将说明部分的精度从9% 更改为10%................................................................................................................ 1
• Added ESD classification levels to ESD Ratings table.......................................................................................4
• Changed VOUT parameter: added temperature range to test conditions of first parameter row and added
second row to parameter....................................................................................................................................5
• Changed V(dropout) maximum specification in second row of parameter from 260 mV to 325 mV......................5
• Changed t(DEGLITCH) minimum specification from 100 μs to 50 μs, changed t(DLY_FIX) maximum specification
from 550 μs to 900 μs, and deleted t(DLY_FIX) minimum specification..............................................................8
• Changed fault 1 maximum open-window duration from t(WD) / 2 to t(WD) .........................................................19
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5 Pin Configuration and Functions
IN
EN
1
16
OUT
2
3
4
5
6
7
8
15
14
13
12
11
10
9
PGADJ
PG
FSEL
WTS
GND
NC
GND
WRS
WD_EN
WDO
WD
Thermal
pad
ROSC
DELAY
Not to scale
NC - No internal connection
图5-1. PWP PowerPAD™ Package, 16-Pin HTSSOP With Exposed Thermal Pad (Top View)
表5-1. Pin Functions
PIN
TYPE
DESCRIPTION
NAME
DELAY
NO.
Power-good delay period adjustment pin. Connect this pin with a capacitor to ground to adjust the
power-good delay time.
8
O
I
Device enable pin. Pull this pin down to low-level voltage to disable the device. Pull this pin up to
high-level voltage to enable the device.
EN
2
3
Internal oscillator frequency selection pin. Pull this pin down to low-level voltage to select the
high-frequency oscillator. Pull this pin up to high-level voltage to select the low-frequency
oscillator.
FSEL
I
GND
IN
5, 13
1
Ground reference
—
I
Device input power-supply pin
Not connected
NC
6
—
OUT
16
O
Device 3.3-V or 5-V regulated output voltage pin
Power-good pin. Open-drain output pin. Pull this pin up to VOUT or to a reference through a
resistor. When the output voltage is not ready, this pin is pulled down to ground.
PG
14
15
O
I
Power-good threshold adjustment pin. Connect a resistor divider between the PGADJ and OUT
pins to set the power-good threshold. Connect this pin to ground to set the threshold to 91.6% of
PGADJ
output voltage VOUT
.
Watchdog timer adjustment pin. Connect a resistor between the ROSC pin and the GND pin to
set the duration of the watchdog monitor. Leaving this pin open or connecting this pin to ground
results in the watchdog reporting a fault at the watchdog output (WDO).
ROSC
7
O
WD
9
I
Watchdog service-signal input pin.
Watchdog status pin. Open-drain output pin. Pull this pin up to OUT or a reference voltage
through a resistor. When watchdog fault occurs, this pin is pulled down to a low-level voltage.
WDO
10
O
Watchdog enable pin. Pull this pin down to a low level to enable the watchdog. Pull this pin up to
a high level to disable the watchdog.
WD_EN
WRS
11
12
I
I
Window ratio selection pin (only applicable for the window watchdog). Pull this pin down to a low
level to set the open:closed window ratio to 1:1. Pull this pin up to high level to set the
open:closed window ratio to 8:1.
Watchdog type-selection pin. To set the window watchdog, connect this pin to the GND pin. To
set the standard watchdog, pull this pin high.
WTS
4
I
Thermal pad
Solder to board to improve the thermal performance.
—
—
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6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted)(1) (2)
MIN
MAX
45
7
UNIT
V
Unregulated input
IN, EN
ROSC
DELAY
OUT
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–40
Internal oscillator reference voltage
Power-good delay-timer output
Regulated output
V
7
V
7
V
Power-good output voltage
PG
7
V
Watchdog status output voltage
Watchdog frequency selection, watchdog-type selection
Watchdog enable
WDO
7
V
FSEL, WTS
WD_EN
WD
45
7
V
V
Watchdog service signal voltage
Window ratio selection
7
V
WRS
7
V
Power-good threshold-adjustment voltage
Operating junction temperature, TJ
Storage temperature, Tstg
PGADJ
7
V
150
150
°C
°C
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values are with respect to ground.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per AEC Q100-002(1), device HBM ESD classification
level 2
±2000
Electrostatic
discharge
V(ESD)
V
All pins
±500
±750
Charged-device model (CDM), per AEC Q100-011,
device CDM ESD classification level C4B
Corner pins (1, 14, 15, and 28)
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
Over operating ambient temperature range (unless otherwise noted)
MIN
4
MAX
40
UNIT
Unregulated input
40-V pins
IN
V
V
V
EN, FSEL, WTS
OUT
0
VIN
5.5
Regulated output
0
Power good, watchdog status,
reference oscillator
PG, WDO, ROSC
0
5.5
V
Low voltage pins
WD, WD_EN, PGADJ, DELAY, WRS
0
0
5.5
300
125
V
Output current
mA
°C
Ambient temperature, TA
–40
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6.4 Thermal Information
TPS7B63xx-Q1
THERMAL METRIC(1)
PWP (HTSSOP)
UNIT
16 PINS
39.7
28.9
23.8
1.3
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJT
23.7
3.1
ψJB
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
VIN = 14 V, COUT ≥4.7 µF, 1 mΩ< ESR < 20 Ω, and TJ = –40°C to 150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE AND CURRENT (IN)
VIN
Input voltage
4
40
4
V
I(SLEEP)
Input sleep current
EN = OFF
µA
VIN = 5.6 V to 40 V for fixed 5-V VOUT
VIN = 4 V to 40 V for fixed 3.3-V VOUT
;
;
19
28
78
29.6
42
EN = ON; watchdog disabled; IOUT < 1 mA;
TJ < 80°C
VIN = 5.6 V to 40 V for fixed 5-V VOUT
VIN = 4 V to 40 V for fixed 3.3-V VOUT
;
;
I(Q)
Input quiescent current
µA
EN = ON; watchdog enabled; IOUT < 1 mA
VIN = 5.6 V to 40 V for fixed 5-V VOUT
VIN = 4 V to 40 V for fixed 3.3-V VOUT
EN = ON; watchdog enabled;
IOUT < 100 mA
;
;
98
V(UVLO)
Undervoltage lockout, falling
Ramp VIN down until output is turned off
2.6
V
V
V(UVLO_HYST) UVLO hysteresis
ENABLE INPUT, WATCHDOG TYPE SELECTION AND FSEL (EN, WTS, AND FSEL)
0.5
VIL
Low-level input voltage
High-level input voltage
Hysteresis
0.7
0.7
V
V
VIH
Vhys
2
2
150
mV
WATCHDOG ENABLE (WD_EN PIN)
Low-level input threshold voltage
for watchdog enable pin
VIL
Watchdog enabled
Watchdog disabled
VWD_EN = 5 V
V
V
High-level input threshold voltage
for watchdog enable pin
VIH
Pulldown current for watchdog
enable pin
IWD_EN
3
µA
REGULATED OUTPUT (OUT)
VIN = 5.6 V to 40 V for fixed 5-V VOUT
VIN = 4 V to 40 V for fixed 3.3-V VOUT
,
,
2%
–2%
IOUT = 0 to 300 mA, –40°C ≤TJ ≤125°C
VOUT
Regulated output
Line regulation
VIN = 5.6 V to 40 V for fixed 5-V VOUT
VIN = 4 V to 40 V for fixed 3.3-V VOUT
IOUT = 0 to 300 mA
;
;
2.5%
10
–2.5%
VIN = 5.6 V to 40 V
mV
ΔVOUT(ΔVIN)
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6.5 Electrical Characteristics (continued)
VIN = 14 V, COUT ≥4.7 µF, 1 mΩ< ESR < 20 Ω, and TJ = –40°C to 150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ΔVOUT(Δ
Load regulation
IOUT = 1 mA to 300 mA
20
mV
IOUT)
IOUT = 300 mA(2)
IOUT = 200 mA(2)
VOUT in regulation
300
170
400
325
300
V(dropout)
mV
Dropout voltage (VIN –VOUT
)
IOUT
I(LIM)
Output current
0
mA
mA
VOUT shorted to ground, VIN = 5.6 V to
40 V
Output current limit
301
680
60
1000
IOUT = 100 mA; COUT = 10 µF;
frequency (f) = 100 Hz
PSRR
Power-supply ripple rejection(1)
dB
IOUT = 100 mA; COUT = 10 µF;
frequency (f) = 100 kHz
40
POWER-GOOD (PG, PGADJ)
VOL(PG) PG output, low voltage
IOL = 5 mA, PG pulled low
0.4
1
V
PG pulled to VOUT through a 10-kΩ
resistor
Ilkg(PG)
PG pin leakage current
Default power-good threshold
Power-good hysteresis
µA
VOUT powered above the internally set
tolerance, PGADJ pin shorted to ground
% of
VOUT
V(PG_TH)
89.6
91.6
2
93.6
VOUT falling below the internally set
tolerance hysteresis
% of
VOUT
V(PG_HYST)
PGADJ
Switching voltage for the power-
good adjust pin
V(PGADJ_TH)
VOUT is falling
1.067
1.1
1.133
V
POWER-GOOD DELAY
I(DLY_CHG) DELAY capacitor charging current
3
5
1
10
µA
V
DELAY pin threshold to release
PG high
V(DLY_TH)
Voltage at DELAY pin is ramped up
VDELAY = 1 V
0.95
1.05
DELAY capacitor discharging
current
I(DLY_DIS)
0.5
mA
V
CURRENT VOLTAGE REFERENCE (ROSC)
VROSC Voltage reference
WATCHDOG (WD, WDO, WRS)
Low-level threshold voltage for
the watchdog input and window- For WD and WRS pins
0.95
1
1.05
30
% of
VOUT
VIL
ratio select
High-level threshold voltage for
the watchdog input and window- For WD and WRS pins
ratio select
% of
VOUT
VIH
70
% of
VOUT
V(HYST)
Hysteresis
10
2
IWD
VOL
Pulldown current for the WD pin
Low-levlel watchdog output
VWDO = 5 V
IWDO = 5 mA
4
µA
V
0.4
WDO pin pulled to VOUT through 10-kΩ
resistor
Ilkg
WDO pin leakage current
1
µA
OPERATING TEMPERATURE RANGE
TJ
Junction temperature
150
°C
°C
°C
–40
T(SD)
T(HYST)
Junction shutdown temperature
Hysteresis of thermal shutdown
175
25
(1) Design information –not tested, determined by characterization.
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(2) This test is done with VOUT in regulation, measuring the VIN –VOUT when VOUT drops by 100 mV from the rated output voltage at the
specified load.
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6.6 Switching Characteristics
VI = 14 V, CO ≥4.7 µF, 1 mΩ< ESR < 20 Ω, and TJ = –40°C to 150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER-GOOD DELAY (DELAY)
t(DEGLITCH)
t(DLY_FIX)
t(DLY)
Power-good deglitch time
50
180
248
20
250
900
µs
µs
Fixed power-good delay
Power-on-reset delay
No capacitor connect at DELAY pin
Delay capacitor value: C(DELAY) = 100 nF
ms
WATCHDOG (WD, WDO, WRS)
9
10
50
11
55
R(ROSC) = 20 kΩ±1%, FSEL = LOW
R(ROSC) = 20 kΩ±1%, FSEL = HIGH
t(WD)
Watchdog window duration
ms
45
Tolerance of watchdog window
duration using external resistor
Excludes tolerance of R(ROSC) = 20 kΩto
100 kΩ
t(WD_TOL)
tp(WD)
t(WD_HOLD)
10%
–10%
Watchdog service-signal duration
100
µs
Watchdog output resetting time
(percentage of settled watchdog
window duration)
20
% of t(WD)
1.8
9
2
2.2
11
R(ROSC) = 20 kΩ± 1%, FSEL = LOW
R(ROSC) = 20 kΩ± 1%, FSEL = HIGH
t(WD_RESET)
Watchdog output resetting time
ms
10
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6.7 Typical Characteristics
at VIN = 14 V, VEN ≥2 V, and TJ = –40°C to +150°C (unless otherwise noted)
80
70
60
50
40
30
20
10
0
400
350
300
250
200
150
100
50
-40 °C
25 °C
125 °C
IOUT = 1 mA
IOUT = 100 mA
IOUT = 200 mA
0
0
50
100
150
Output Current (mA)
200
250
300
0
5
10
15
Input Voltage (V)
20
25
30
35
40
D001
D002
图6-1. Quiescent Current vs Output Current
图6-2. Quiescent Current vs Input Voltage
4
3
2
1
0
35
30
25
20
15
10
5
IOUT = 1 mA
IOUT = 100 mA
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Ambient Temperature (èC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Ambient Temperature (°C)
D003
D004
图6-3. Shutdown Current vs Ambient Temperature
图6-4. Quiescent Current vs Ambient Temperature
350
300
-40 °C
25 °C
125 °C
300
250
200
150
100
50
250
200
150
100
50
0
0
0
50
100
150 200
Output Current (mA)
250
300
350
-40 -25 -10
5
20 35 50 65 80 95 110 125
Ambient Temperature (°C)
D005
D006
IOUT = 200 mA
图6-5. Dropout Voltage vs Output Current
图6-6. Dropout Voltage vs Ambient Temperature
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6.7 Typical Characteristics (continued)
at VIN = 14 V, VEN ≥2 V, and TJ = –40°C to +150°C (unless otherwise noted)
5.06
5.03
5
6
5
4
3
2
1
0
4.97
-40èC
25èC
125èC
4.94
-40 -25 -10
5
20 35 50 65 80 95 110 125
Ambient Temperature (°C)
0
5
10
15
20
25
Input Voltage (V)
30
35
40
D007
D008
VOUT = 5 V
图6-7. Output Voltage vs Ambient Temperature
VOUT = 5 V
图6-8. Output Voltage vs Input Voltage
900
800
700
600
500
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
−40 °C
25 °C
125 °C
-40 -25 -10
5
20 35 50 65 80 95 110 125
Ambient Temperature (°C)
0
50
100
150
200
250
300
350
Output Current (mA)
D009
VIN = 5.6 V
图6-10. Load Regulation
图6-9. Output Current Limit (ILIM) vs Ambient Temperature
1
120
100
80
60
40
20
0
-40èC
0.8
25èC
125èC
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0
5
10
15
Input Voltage (V)
20
25
30
35
40
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
D011
D012
COUT = 10 μF, IOUT = 1 mA, TA = 25°C
图6-12. PSRR vs Frequency
图6-11. Line Regulation
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6.7 Typical Characteristics (continued)
at VIN = 14 V, VEN ≥2 V, and TJ = –40°C to +150°C (unless otherwise noted)
120
100
80
60
40
20
0
1k
Unstable Region
Stable Region
500
100
10
4.7
Unstable Region
1
0.001
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
0.01
0.1
ESR (W)
1
10 20
D013
D014
COUT = 10 μF, IOUT = 100 mA, TA = 25°C
图6-13. PSRR vs Frequency
图6-14. ESR Stability vs Output Capacitance
VIN (10 V/div)
VOUT (1 V/div)
VOUT (1 V/div)
VIN (10 V/div)
VOUT(AC) (100 mV/div)
VOUT(AC) (100 mV/div)
IOUT (10 mA/div)
IOUT (10 mA/div)
VIN = 6 V to 40 V, VOUT = 5 V, COUT = 10 µF, IOUT = 1 mA
VIN = 40 V to 6 V, VOUT = 5 V, COUT = 10 µF, IOUT = 1 mA
图6-15. Line Transient
图6-16. Line Transient
VIN (5 V/div)
VIN (5 V/div)
VOUT (1 V/div)
VOUT (1 V/div)
VOUT(AC) (50 mV/div)
IOUT (200 mA/div)
VOUT(AC) (50 mV/div)
IOUT (200 mA/div)
VIN = 9 V to 16 V, VOUT = 5 V, COUT = 10 µF, IOUT = 200 mA
VIN = 16 V to 9 V, VOUT = 5 V, COUT = 10 µF, IOUT = 200 mA
图6-17. Line Transient
图6-18. Line Transient
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6.7 Typical Characteristics (continued)
at VIN = 14 V, VEN ≥2 V, and TJ = –40°C to +150°C (unless otherwise noted)
VIN (5 V/div)
VIN (5 V/div)
VOUT (1 V/div)
VOUT (1 V/div)
VOUT(AC) (500 mV/div)
VOUT(AC) (500 mV/div)
IOUT (200 mA/div)
IOUT (200 mA/div)
VOUT = 5 V, COUT = 10 µF, IOUT = 1 mA to 200 mA
图6-19. Load Transient
VOUT = 5 V, COUT = 10 µF, IOUT = 200 mA to 1 mA
图6-20. Load Transient
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7 Detailed Description
7.1 Overview
The TPS7B63xx-Q1 device is a family of 300-mA, 40-V monolithic low-dropout linear voltage regulators with
integrated watchdog and adjustable power-good threshold functionality. These voltage regulators consume only
19-µA quiescent current in light-load applications. Because of the adjustable power-good delay (also called
power-on-reset delay) and the adjustable power-good threshold, these devices are well-suited as power supplies
for microprocessors and microcontrollers in automotive applications.
7.2 Functional Block Diagram
IN
OUT
VBAT
VREG
Overcurrent
Protection
Regulator
Control
Thermal
Shutdown
Undervoltage
Lockout
Band Gap
Error
Amp
Vref
EN
PG
DELAY
ROSC
Power-Good
Control With
Delay
V(PG_REF )
Current
Regulator
Watchdog
Oscillator
Amp
PGADJ
WDO
WD
MCU I/O
Timer
WD_EN
Digital I/O
Watchdog
Fault Control
GND
FSEL
WTS
WRS
7.3 Feature Description
7.3.1 Device Enable (EN)
The EN pin is a high-voltage-tolerant pin. A high input activates the device and turns the regulator ON. Connect
this input pin to an external microcontroller or a digital control circuit to enable and disable the device, or connect
to the IN pin for self-bias applications.
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7.3.2 Adjustable Power-Good Threshold (PG, PGADJ)
The PG pin is an open-drain output with an external pullup resistor to the regulated supply, and the PGADJ pin is
a power-good threshold adjustment pin. Connecting the PGADJ pin to GND sets the power-good threshold value
to the default, V(PG_TH). When VOUT exceeds the default power-good threshold, the PG output turns high after
the power-good delay period has expired. When VOUT falls below V(PG_TH) – V(PG_HYST), the PG output turns
low after a short deglitch time.
The power-good threshold is also adjustable from 1.1 V to 5 V by using an external resistor divider between
PGADJ and OUT. The threshold can be calculated using 方程式1:
R1+ R2
R2
V PG_ ADJ falling = V PGADJ_ TH falling
ì
(
)
(
)
R1+ R2
R2
»
ÿ
⁄
V PG_ ADJ risng = V PGADJ_ TH falling + 26 mV typ
ì
(
)
(
)
(
)
(1)
where
• V(PG_ADJ) is the adjustable power-good threshold
• V(PG_REF) is the internal comparator reference voltage of the PGADJ pin, 1.1 V typical, 2% accuracy specified
under all conditions
By setting the power-good threshold V(PG_ADJ), when VOUT exceeds this threshold, the PG output turns high after
the power-good delay period has expired. When VOUT falls below V(PG_ADJ) – V(PG_HYST), the PG output turns
low after a short deglitch time. 图7-1 shows typical hardware connections for the PGADJ pin and DELAY pin.
OUT
VREG
Adjustable Power-
Good Threshold
PG
R1
DELAY
Power-Good
Control
R2
V(PG_REF)
Amp
PGADJ
图7-1. Adjustable Power-Good Threshold
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7.3.3 Adjustable Power-Good Delay Timer (DELAY)
The power-good delay period is a function of the value set by an external capacitor on the DELAY pin before
turning the PG pin high. 图 7-2 illustrates typical power-good and delay behavior. Connecting an external
capacitor from this pin to GND sets the power-good delay period. The constant current charges an external
capacitor until the voltage exceeds a threshold to trip an internal comparator, and 方程式 2 determines the
power-good delay period:
%
T 18
&'.#;
P:
= P
+
;
&.;
@HU _BET
5 ä#
(2)
where
• t(DLY) is the adjustable power-good delay period
• CDELAY is the value of the power-good delay capacitor
VIN
V
(UVLO)
t < t(DEGLITCH)
V(PG_HYST)
V(PG_TH) rising
V(PG_TH) falling
V(PG_ADJ) falling
V(PG_ADJ) rising
VOUT
V
(DLY_TH)
DELAY
t(DEGLITCH)
t(DEGLITCH)
t
t
(DLY)
(DLY)
PG
Power Up
Input Voltage Drop
Undervoltage
Power Down
图7-2. Power Up and Conditions for Activating Power-Good
If the DELAY pin is open, the default delay time is t(DLY_FIX)
.
7.3.4 Undervoltage Shutdown
These devices have an integrated undervoltage lockout (UVLO) circuit to shut down the output if the input
voltage falls below an internal UVLO threshold, V(UVLO). This ensures that the regulator does not latch into an
unknown state during low-input-voltage conditions. If the input voltage has a negative transient which drops
below the UVLO threshold and recovers, the regulator shuts down and powers up with a normal power-up
sequence once the input voltage is above the required level.
7.3.5 Current Limit
These devices feature current-limit protection to keep the device in a safe operating area when an overload or
output short-to-ground condition occurs. This protects devices from excessive power dissipation. For example,
during a short-circuit condition on the output, fault protection limits the current through the pass element to I(LIM)
to protect the device from excessive power dissipation.
7.3.6 Thermal Shutdown
These devices incorporate a thermal shutdown (TSD) circuit as a protection from overheating. For continuous
normal operation, the junction temperature should not exceed the TSD trip point. The junction temperature
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exceeding the TSD trip point causes the output to turn off. When the junction temperature falls below the T(SD)
T(HYST), the output turns on again.
–
7.3.7 Integrated Watchdog
These devices have an integrated watchdog with fault (WDO) output option. Both window watchdog and
standard watchdog are available in one device. The watchdog operation, service fault conditions, and
differences between window watchdog and standard watchdog are described as follows.
7.3.7.1 Window Watchdog (WTS, ROSC, FSEL and WRS)
These devices work in the window watchdog mode when the watchdog type selection (WTS) pin is connected to
a to low voltage level. The user can set the duration of the watchdog window by connecting an external resistor
(RROSC) to ground at the ROSC pin and setting the voltage level at the FSEL pin. The current through the RROSC
resistor sets the clock frequency of the internal oscillator. The user can adjust the duration of the watchdog
window (the watchdog timer period) by changing the resistor value. A high voltage level at the FSEL pin sets the
watchdog window duration to 5 times as long as that of a low voltage level with same external component
configuration.
The duration of the watchdog window and the duration of the fault output are multiples of the internal oscillator
frequency, as shown by the following equations:
FSEL low
t(WD) = RROSC × 0.5 × 10-6
t(WD) = RROSC × 2.5 × 10-6
t(WD_INI) = 8 × t(WD)
(3)
(4)
(5)
(6)
(7)
(8)
FSEL high
Watchdog initialization
Open and closed windows
WRS low
t(WD) = t(OW) + t(CW)
t(OW) = t(CW) = 50% × t(WD)
t(OW) = 8 × t(CW) = (8 / 9) × t(WD)
WRS high
where:
• t(WD) is the duration of the watchdog window
• RROSC is the resistor connected at the ROSC pin
• t(WD_INI) is the duration of the watchdog initialization
• t(OW) is the duration of the open watchdog window
• t(CW) is the duration of the closed watchdog window
For all the foregoing items, the unit of resistance is Ωand the unit of time is s.
表7-1 illustrates several periods of watchdog window with typical conditions.
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表7-1. Several Typical Periods of Watchdog Window
FSEL
I(ROSC) (µA)
t(WD) (ms)
WATCHDOG PERIOD
TOLERANCE
R(ROSC) (kΩ)
200
100
50
5
500
250
125
100
62.5
50
15%
10
20
25
40
50
10
20
25
40
50
High
40
10%
25
20
100
50
50
25
Low
40
20
10%
25
12.5
10
20
As illustrated in 图 7-3, each watchdog window consists of an open window and a closed window. While the
window ratio selection (WRS) pin is low, each open window (t(OW)) and closed window (t (CW)) has a width
approximately 50% of the watchdog window (t (WD)). While the WRS pin is high, the ratio between open window
and closed window is about 8:1. However, there is an exception to this; the first open window after watchdog
initialization (t(WD_INI)) is eight times the duration of the watchdog window. The watchdog must receive the
service signal (by software, external microcontroller, and so forth) during this initialization open window.
A watchdog fault occurs when servicing the watchdog during a closed window, or not servicing during an open
window.
t(WD_INI)
t(WD)
Closed Window
(Must Not Be Serviced
to Prevent Fault)
Open Window
(Must Be Serviced
to Prevent Fault)
Open Window
After Watchdog Initialization
(Must Be Serviced to Prevent Fault)
WRS = Low
t(CW) = ½ ´ t(WD)
t(OW) = ½ ´ t(WD)
8 ´ t(WD)
Open Window
After Watchdog Initialization
(Must Be Serviced to Prevent Fault)
Open Window
(Must Be Serviced
to Prevent Fault)
CW
WRS = High
t(OW) = 8 / 9 ´ t(WD)
8 ´ t(WD)
Closed Window
(Must Not Be Serviced
to Prevent Fault)
Event Causing
Watchdog Initialization
t(CW) = 1 / 9 ´ t(WD)
图7-3. Watchdog Initialization, Open Window and Closed Window
7.3.7.2 Standard Watchdog (WTS, ROSC and FSEL)
These devices work in the standard watchdog mode when the watchdog type selection (WTS) pin is connected
to a high voltage level. The same as in window watchdog mode, the user can set the duration of the watchdog
window by adjusting the external resistor (RROSC) value at the ROSC pin and setting the voltage level at the
FSEL pin. The current through the RROSC resistor sets the clock frequency of the internal oscillator. The user can
adjust the duration of the watchdog window (the watchdog timer period) by changing the resistor value. A high
voltage level at the FSEL pin sets the watchdog window duration to 5 times as long as that of a low voltage level
with same external component configuration.
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The duration of the watchdog window and the duration of the fault output are multiples of the internal oscillator
frequency, as shown by the following equations:
FSEL low
t(WD) = RROSC × 0.5 × 10-6
t(WD) = RROSC × 2.5 × 10-6
t(WD_INI) = 8 × t(WD)
(9)
(10)
(11)
FSEL high
Watchdog initialization
where:
• t(WD) is the duration of the watchdog window
• RROSC is the resistor connected at the ROSC pin
• t(WD_INI) is the duration of the watchdog initialization
For all the foregoing items, the unit of resistance is Ωand the unit of time is s
Compared with window watchdog, there is no closed window in standard watchdog mode. The standard
watchdog receives a service signal at any time within the watchdog window. The watchdog fault occurs when not
servicing watchdog during the watchdog window.
7.3.7.3 Watchdog Service Signal and Watchdog Fault Outputs (WD and WDO)
The watchdog service signal (WD) must stay high for at least 100 µs. The WDO pin is the fault output terminal
and is tied high through a pullup resistor to a regulated output supply. When a watchdog fault occurs, the devices
momentarily pull WDO low for a duration of t(WD_HOLD)
(WD _HOLD) = 20%´ t(WD)
7.3.7.4 ROSC Status Detection (ROSC)
.
t
(12)
When a watchdog function is enabled, if the ROSC pin is shorted to GND or open, the watchdog output (WDO)
pin remains low, indicating a fault status. If the watchdog function is disabled, ROSC pin status detection does
not work.
7.3.7.5 Watchdog Enable (PG and WD_EN)
When PG (power good) is high, an external microcontroller or a digital circuit can apply a high or low logic signal
to the WD_EN pin to disable or enable the watchdog. A low input to this pin turns the watchdog on, and a high
input turns the watchdog off. If PG is low, the watchdog is disabled and the watchdog-fault output (WDO) pin
stays in the high-impedance state.
7.3.7.6 Watchdog Initialization
On power up and during normal operation, the watchdog initializes under the conditions shown in 表7-2.
表7-2. Conditions for Watchdog Initialization
EDGE
WHAT CAUSES THE WATCHDOG TO INITIALIZE
Rising edge of PG (power good) while the watchdog is in the enabled state, for example,
during soft power up
↑
Falling edge of WD_EN while PG is already high, for example, when the microprocessor
enables the watchdog after the device is powered up
↓
↑
Rising edge of WDO while PG is already high and the watchdog is in the enabled state, for
example, right after a closed window is serviced
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7.3.7.7 Window Watchdog Operation (WTS = Low)
The window watchdog is able to monitor whether the frequency of the watchdog service signal (WD) is within
certain ranges. A watchdog low-voltage fault is reported when the frequency of the watchdog service signal is
out of the setting range. 图 7-4 shows the window watchdog initialization and operation for the TPS7B63xx-Q1
(WRS is low). After the output voltage is in regulation and PG is high, the window watchdog becomes enabled
when an external signal pulls WD_EN (the watchdog enable pin) low. This causes the watchdog to initialize and
wait for a service signal during the first initialization window for 8 times the duration of t(WD). A service signal
applied to the WD pin during the initialization open window resets the watchdog counter and a closed window
starts. To prevent a fault condition from occurring, watchdog service must not occur during the closed window.
Watchdog service must occur during the following open window to prevent a fault condition from occurring. The
fault output (WDO), externally pulled up to VOUT (typical), stays high as long as the watchdog receives a proper
service signal and there is no other fault condition.
VIN
V(PG_TH) rising
V(PG_ADJ) rising
)
VOUT
DELAY
PG
V(PG_TH) falling
V(PG_ADJ) falling
t(DLY)
V(DLY_TH)
t(DLY)
t(DEGLITCH)
WD_EN
WD
WDO
OW
WD
OW
WD
OW
WD Ini- NA
tialization
F
L
T
OW
WD Initial-
ization
F
L
T
F
L
T
OW
WD Initialization
OW
WD Initialization
N
A
Watchdog
Window Status
CW
OW CW
CW
OW
NA
Initial...
Initialization
<8 t(WD)
t(WD) / 2
<8 t(WD)
t(WD) / 2
t(WD) / 2
<8 t(WD)
8 t(WD)
<8 t(WD)
Normal Operation
20% ´ t(WD)
20% ´ t(WD)
20% ´ t(WD)
Fault 1
Fault 2
Fault 3
图7-4. Window Watchdog Operation
Three different fault conditions occur in 图7-4:
• Fault 1: The watchdog service signal is received during the closed window. The WDO is triggered once,
receiving a WD rising edge during the closed window.
• Fault 2: The watchdog service signal is not received during the open window. WDO is triggered after the
maximum open-window duration t(WD) / 2.
• Fault 3: The watchdog service signal is not received during the WD initialization. WDO is triggered after the
maximum initialization window duration 8 × t(WD)
.
7.3.7.8 Standard Watchdog Operation (WTS = High)
The standard watchdog is able to monitor whether the frequency of the watchdog service signal (WD) is lower
than a certain value. A watchdog low-voltage fault is reported when the frequency of the watchdog service signal
is lower than the set value.
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图 7-5 shows the standard watchdog initialization and operation for the TPS7B63xx-Q1. Similar to the window
watchdog, after output the voltage is in regulation and PG asserts high, the standard watchdog becomes
enabled when an external signal pulls WD_EN low. This causes the standard watchdog to initialize and wait for a
service signal during the first initialization window for 8 times the duration of t(WD). A service signal applied to the
WD pin during the first open window resets the watchdog counter and another open window starts. To prevent a
fault condition from occurring, watchdog service must occur during the every open window to prevent a fault
condition from occurring. The fault output (WDO), externally pulled up to VOUT (typical), stays high as long as the
watchdog receives proper service and there is not fault condition.
VIN
V(PG_TH) rising
V(PG_ADJ) rising
VOUT
V(PG_TH) falling
V(PG_ADJ) falling
t(DLY)
V(DLY_TH)
DELAY
t(DLY)
PG
t(DEGLITCH)
WD_EN
WD
WDO
OW
WD
OW
WD
OW
WD Ini- NA
tialization
F
L
T
F
L
T
OW
WD Initialization
OW
WD Initialization
N
A
Watchdog
Window Status
NA
OW
OW
OW OW
OW
OW
OW
Initialization Initial...
<8 t(WD)
<t(WD)
<t(WD)
<t(WD) <t(WD)
<t(WD)
<t(WD)
<8 t(WD)
8 t(WD)
<8 t(WD)
20% ´ t(WD)
20% ´ t(WD)
Normal Operation
Fault 1
Fault 2
图7-5. Standard Watchdog Operation
Two different fault conditions occur in 图7-5:
• Fault 1: The watchdog service signal is not received during the open window. WDO is triggered after the
maximum open-window duration t(WD)
• Fault 2: The watchdog service signal is not received during the WD initialization. WDO is triggered after the
.
maximum initialization window duration 8 × t(WD)
.
7.4 Device Functional Modes
7.4.1 Operation With Input Voltage Lower Than 4 V
The devices normally operate with input voltages above 4 V. The devices can also operate at lower input
voltages; the maximum UVLO voltage is 2.6 V. At input voltages below the actual UVLO voltage, the devices do
not operate.
7.4.2 Operation With Input Voltage Higher Than 4 V
When the input voltage is greater than 4 V, if the input voltage is higher than the output set value plus the device
dropout voltage, then the output voltage is equal to the set value. Otherwise, the output voltage is equal to the
input voltage minus the dropout voltage.
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The TPS7B63xx-Q1 is a 300-mA low-dropout watchdog linear regulator with ultralow quiescent current. The
PSpice transient model is available for download on the product folder and can be used to evaluate the basic
function of the device.
8.2 Typical Application
图 8-1 shows a typical application circuit for the TPS7B63xx-Q1 device. Different values of external components
can be used, depending on the end application. An application may require a larger output capacitor during fast
load steps to prevent a large drop on the output voltage. TI recommends using a low-ESR ceramic capacitor with
a dielectric of type X7R.
IN
OUT
MCU Supply
Battery
10 µF
4.7 µF
to
500 µF
1 kW
to
200 kW
1 kW
to
20 kW
to
22 µF
EN
WD_EN
WD
RADJ
1 kW
1 kW
to
200 kW
Digital Output
MCU O
to
20 kW
WDO
PG
TPS7B63xx-Q1
MCU I
WTS
MCU RESET
ROSC
FSEL
WRS
20 kW
to
100 kW
DELAY
100 pF
to
100 nF
图8-1. TPS7B63xx-Q1 Typical Application Schematic
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8.2.1 Design Requirements
For this design example, use the parameters listed in 表8-1.
表8-1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUES
Input voltage range
4 V to 40 V for TPS7B6333-Q1
5.6 V to 40 V for TPS7B6350-Q1
10 μF to 22 μF
Input capacitor range
Output voltage
3.3 V, 5 V
Output current rating
Output capacitor range
Power-good threshold
300 mA maximum
4.7 μF to 500 μF
Adjustable or fixed
Power-good delay capacitor
Watchdog type
100 pF to 100 nF
Standard watchdog or window watchdog
10 ms to 500 ms
Watchdog window periods
8.2.2 Detailed Design Procedure
To begin the design process, determine the following:
• Input voltage range
• Output voltage
• Output current
• Power-good threshold
• Power-good delay capacitor
• Watchdog type
• Watchdog window period
8.2.2.1 Input Capacitor
When using a TPS7B63xx-Q1 device, TI recommends adding a 10-μF to 22-μF capacitor with a 0.1 μF
ceramic bypass capacitor in parallel at the input to keep the input voltage stable. The voltage rating must be
greater than the maximum input voltage.
8.2.2.2 Output Capacitor
Ensuring the stability of the TPS7B63xx-Q1 device requires an output capacitor with a value in the range from
4.7 μF to 500 μF and with an ESR range from 0.001 Ωto 20 Ω. TI recommends selecting a ceramic capacitor
with low ESR to improve the load transient response.
8.2.2.3 Power-Good Threshold
The power-good threshold is set by connecting PGADJ to GND or to a resistor divider from OUT to GND. The
Adjustable Power-Good Threshold (PG, PGADJ) section provides the method for setup of the power-good
threshold.
8.2.2.4 Power-Good Delay Period
The power-good delay period is set by an external capacitor (CDELAY) to ground, with a typical capacitor value
from 100 pF to 100 nF. Calculate the correct capacitance for the application using 方程式2.
8.2.2.5 Watchdog Setup
The Integrated Watchdog section discusses the watchdog type selection and watchdog window-period setup
method.
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8.2.3 Application Curves
VOUT (5 V/div)
WD Signal (5 V/div)
VIN (5 V/div)
VOUT (2 V/div)
VPG (2 V/div)
WDO Signal (5 V/div)
IOUT (10 mA/div)
IOUT (10 mA/div)
图8-3. TPS7B6350-Q1 Watchdog Fault (High-
图8-2. TPS7B6350-Q1 Power-Up Waveform
Frequency Watchdog Service Signal)
8.3 Power Supply Recommendations
The device is designed to operate from an input-voltage supply range from 4 V to 40 V. This input supply must
be well regulated. If the input supply is located more than a few inches from the TPS7B63xx-Q1 device, TI
recommends adding a capacitor with a value of ≥10 μF with a 0.1 μF ceramic bypass capacitor in parallel at
the input.
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www.ti.com.cn
8.4 Layout
8.4.1 Layout Guidelines
For LDO power supplies, especially high-voltage and high-current ones, layout is an important step. If layout is
not carefully designed, the regulator could not deliver enough output current because of thermal limitation. To
improve the thermal performance of the device and maximize the current output at high ambient temperature, TI
recommends spreading the thermal pad as much as possible and putting enough thermal vias on the thermal
pad. 图8-4 shows an example layout.
8.4.2 Layout Example
IN
EN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
OUT
PGADJ
PG
FSEL
WTS
GND
NC
Thermal
Pad
GND
WRS
WDEN
WDO
WD
ROSC
DELAY
图8-4. Layout Recommendation
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9 Device and Documentation Support
9.1 Documentation Support
9.1.1 Related Documentation
For related documentation see the following:
Texas Instruments, TPS7B63xx-Q1 Evaluation Module user's guide
9.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
9.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
9.4 Trademarks
PowerPAD™ and TI E2E™ are trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
9.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most-
current data available for the designated devices. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.
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PACKAGE OPTION ADDENDUM
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5-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS7B6333QPWPRQ1
TPS7B6350QPWPRQ1
ACTIVE
ACTIVE
HTSSOP
HTSSOP
PWP
PWP
16
16
2000 RoHS & Green
2000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
7B6333Q
7B6350Q
Samples
Samples
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
5-Oct-2022
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Oct-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS7B6333QPWPRQ1 HTSSOP PWP
TPS7B6350QPWPRQ1 HTSSOP PWP
16
16
2000
2000
330.0
330.0
12.4
12.4
6.9
6.9
5.6
5.6
1.6
1.6
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Oct-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS7B6333QPWPRQ1
TPS7B6350QPWPRQ1
HTSSOP
HTSSOP
PWP
PWP
16
16
2000
2000
350.0
350.0
350.0
350.0
43.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
PWP0016A
PowerPAD TM HTSSOP - 1.2 mm max height
S
C
A
L
E
2
.
4
0
0
PLASTIC SMALL OUTLINE
C
6.6
6.2
TYP
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
0.19
4.5
4.3
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
4X 0.166 MAX
NOTE 5
2X 1.34 MAX
NOTE 5
THERMAL
PAD
0.25
GAGE PLANE
3.3
2.7
17
1.2 MAX
0.15
0.05
0 - 8
0.75
0.50
DETAIL A
TYPICAL
(1)
3.3
2.7
4214868/A 02/2017
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
PWP0016A
PowerPAD TM HTSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(3.4)
NOTE 9
SOLDER MASK
DEFINED PAD
(3.3)
16X (1.5)
SYMM
SEE DETAILS
1
16
16X (0.45)
(1.1)
TYP
17
SYMM
(3.3)
(5)
NOTE 9
14X (0.65)
8
9
(
0.2) TYP
VIA
(1.1) TYP
METAL COVERED
BY SOLDER MASK
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
PADS 1-16
4214868/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
PWP0016A
PowerPAD TM HTSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(3.3)
BASED ON
0.125 THICK
STENCIL
16X (1.5)
(R0.05) TYP
1
16
16X (0.45)
(3.3)
17
SYMM
BASED ON
0.125 THICK
STENCIL
14X (0.65)
9
8
SYMM
(5.8)
METAL COVERED
BY SOLDER MASK
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
3.69 X 3.69
3.3 X 3.3 (SHOWN)
3.01 X 3.01
0.125
0.15
0.175
2.79 X 2.79
4214868/A 02/2017
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
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