TPS7B68-Q1 [TI]

具有看门狗计时器的汽车类 500mA、电池供电运行 (40V)、高 PSRR、低 IQ、低压降稳压器;


型号：	TPS7B68-Q1
厂家：	TEXAS INSTRUMENTS
描述：	具有看门狗计时器的汽车类 500mA、电池供电运行 (40V)、高 PSRR、低 IQ、低压降稳压器电池稳压器
文件：	总36页 (文件大小：2249K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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TPS7B68-Q1

ZHCSFR0C –MAY 2015–REVISED FEBRUARY 2019

TPS7B68-Q1 500mA 40V 高电压超低静态电流看门狗 LDO

1 特性

3 说明

•

适用于汽车电子应用

具有符合 AEC-Q100 标准的下列结果：

在汽车微控制器或微处理器电源应用中，看门狗用于

监测微控制器的工作状态，防止软件失控。在可靠的系

统中，看门狗必须独立于微控制器。

•

–

器件温度 1 级：–40°C 至 +125°C 的环境工作

温度范围

TPS7B68-Q1 是一款专为实现高达 40V 的工作电压而

设计的 500mA 看门狗 LDO，其轻载条件下的典型静

态电流仅为 19µA。该器件集成了一项可编程功能，用

于选择窗口或标准看门狗，并使用外部电阻器来设置看

门狗时间（精度在 10% 以内）。

–

器件 HBM ESD 分类等级 2

器件 CDM ESD 分类等级 C4B

•

最大输出电流：500mA

4V 至 40V 宽 V_IN输入电压范围，瞬态电压高达

45V

TPS7B68-Q1 上的 PG 引脚指示输出电压何时达到稳

定且处于稳压范围内。电源正常延迟周期和电源正常阈

值可通过外部组件来调整。此外，该器件还具备短路

和过流保护。这些特性组合使得该器件极具灵活性，

适用于为汽车应用中的微控制器供电。

•

3.3V 和 5V 两种固定输出电压

最大压降电压：600mV（电流为 500mA）

在宽电容（4.7µF 至 500µF）和 ESR（0.001Ω 至

20Ω）范围内，与输出电容器一起工作时保持稳定

•

低静态电流 (I_(Q))：

–

EN 为低电平（关断模式）时 < 4µA

器件信息⁽¹⁾

轻负载（WD_EN 为高电平）时具有 19µA 的典

型值（看门狗禁用）

器件型号

封装

封装尺寸（标称值）

TPS7B68-Q1

HTSSOP (28)

9.70mm × 4.40mm

•

可针对窗口看门狗和标准看门狗进行配置

开关窗口比例可配置为 1:1 或 8:1

完全可调的看门狗周期（10ms 至 500ms）

10% 精度看门狗周期

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

典型应用原理图

TPS7B6850-Q1

Battery

专用 WD_EN 引脚，用于控制看门狗开关

完全可调的电源正常阈值和电源正常延迟周期

针对 UVLO 的低输入电压跟踪功能

集成故障保护：

OUT

MCU

Supply

PGADJ

–

过载电流限制保护

热关断

WD_EN

Digital I/O

MCU I/O

MCU

I/O

WDO

•

28 引脚 HTSSOP 封装

WTS

2 应用

ROSC

FSEL

WRS

MCU

Reset

•

汽车 MCU 电源

DELAY

车身控制模块 (BCM)

车身舒适模块

GND

EV 和 HEV 电池管理系统(BMS)

电子换挡器

变速器控制单元 (TCU)

电动助力转向 (EPS)

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLVSD43

TPS7B68-Q1

ZHCSFR0C –MAY 2015–REVISED FEBRUARY 2019

www.ti.com.cn

7.4 Device Functional Modes........................................ 21

Application and Implementation ........................ 22

8.1 Application Information............................................ 22

8.2 Typical Application ................................................. 22

Power Supply Recommendations...................... 25

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 4

Specifications......................................................... 5

6.1 Absolute Maximum Ratings ...................................... 5

6.2 ESD Ratings.............................................................. 6

6.3 Recommended Operating Conditions....................... 6

6.4 Thermal Information.................................................. 6

6.5 Electrical Characteristics........................................... 7

6.6 Switching Characteristics.......................................... 9

6.7 Typical Characteristics............................................ 10

Detailed Description ............................................ 14

7.1 Overview ................................................................. 14

7.2 Functional Block Diagram ....................................... 14

7.3 Feature Description................................................. 14

10 Layout................................................................... 25

10.1 Layout Guidelines ................................................. 25

10.2 Layout Example .................................................... 25

11 器件和文档支持 ..................................................... 26

11.1 文档支持................................................................ 26

11.2 接收文档更新通知 ................................................. 26

11.3 社区资源................................................................ 26

11.4 商标....................................................................... 26

11.5 静电放电警告......................................................... 26

11.6 术语表 ................................................................... 26

12 机械、封装和可订购信息....................................... 26

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision B (September 2017) to Revision C

Page

•

已更改通篇将看门狗精度从 9% 更改成了 10%...................................................................................................................... 1

已更改更改了器件信息表表................................................................................................................................................... 1

Changed test conditions of V_OUTparameter........................................................................................................................... 7

Added second row to V_OUTparameter ................................................................................................................................... 7

Changed V_(dropout)parameter maximum specifications from 600 mV to 800 mV at 500 mA and changed 260 mV to

325 mV at 200 mA.................................................................................................................................................................. 7

•

Added footnote indicating dropout is not tested for the 3.3-V option at 200 mA.................................................................... 7

Changed first row test conditions of I_(LIM)parameter: changed V_IN= 5.6 V to 40 V to V_IN= 5.6 V and added voltage

option...................................................................................................................................................................................... 7

•

Added second row to I_(LIM)parameter for the 3.3-V option..................................................................................................... 7

Changed t_(DEGLITCH)parameter minimum specification from 100 µs to 55 µs ........................................................................ 9

Changed t_{(DLY_FIX)}parameter specifications: deleted minimum specification and changed maximum specification

from 550 µs to 900 µs ........................................................................................................................................................... 9

•

Changed t_{(WD_TOL)}parameter: changes test conditions, changed minim specification from –9% to –10%, and

changed maximum specification from 9% to 10%.................................................................................................................. 9

已更改 Several Typical Periods of Watchdog Window table to reflect change in watchdog duration accuracy from

9% to 10% ............................................................................................................................................................................ 17

Changes from Revision A (December 2016) to Revision B

Page

•

Changed V_{(PG_TH)}symbol to V_{(PG_TH) rising}and V_{(PGADJ_TH)}symbol to V_{(PGADJ_TH) falling}in Electrical Characteristics table......... 8

Added V_{(PGADJ_HYST)}parameter to Electrical Characteristics table ......................................................................................... 8

已更改 Adjustable Power-Good Threshold section: updated symbols and changed Equation 1 ........................................ 15

已更改 parameter symbols in Power Up and Conditions for Activation of Power Good figure and added footnote............ 16

已更改 parameter symbols in Window Watchdog Operation figure and added footnote ..................................................... 20

已更改 parameter symbols in Standard Watchdog Operation figure and added footnote ................................................... 21

TPS7B68-Q1

www.ti.com.cn

ZHCSFR0C –MAY 2015–REVISED FEBRUARY 2019

Changes from Original (June 2016) to Revision A

Page

•

已将 TPS7B6850-Q1 的状态从产品预览改为量产数据........................................................................................................... 1

TPS7B68-Q1

ZHCSFR0C –MAY 2015–REVISED FEBRUARY 2019

www.ti.com.cn

5 Pin Configuration and Functions

PWP PowerPAD™ Package

28-Pin HTSSOP With Exposed Thermal Pad

Top View

OUT

PGADJ

FSEL

WTS

Thermal

Pad

GND

ROSC

DELAY

WRS

WD_EN

WDO

Not to scale

NC - No internal connection

Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NAME

DELAY

NO.

Power-good delay-period adjustment pin. Connect this pin via a capacitor to ground to adjust

the power-good delay time.

Device enable pin. Pull this pin down to low-level voltage to disable the device. Pull this pin

up to high-level voltage to enable the device.

Internal oscillator-frequency selection pin. Pull this pin down to low-level voltage to select the

high-frequency oscillator. Pull this pin up to high-level voltage to select the low-frequency

oscillator.

FSEL

GND

8, 21

Ground reference

Device input power-supply pin

2, 3, 7, 9, 10,

14, 17, 19,

20, 22, 23,

26, 27

—

Not connected

OUT

Device 3.3-V or 5-V regulated output voltage pin

Power-good pin. Open-drain output pin. Pull this pin up to V_OUTor to a reference through a

resistor. When the output voltage is not ready, this pin is pulled down to ground.

Power-good threshold-adjustment pin. Connect a resistor divider between the PGADJ and

OUT pins to set the power-good threshold. Connect this pin to ground to set the threshold to

PGADJ

91.6% of output voltage V_OUT

(1) I = input, O = output, G = ground.

TPS7B68-Q1

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ZHCSFR0C –MAY 2015–REVISED FEBRUARY 2019

Pin Functions (continued)

TYPE⁽¹⁾

DESCRIPTION

NAME

ROSC

NO.

Watchdog timer adjustment pin. Connect a resistor between the ROSC pin and the GND pin

to set the duration of the watchdog monitor. Leaving this pin open or connecting this pin to

ground results in the watchdog reporting a fault at the watchdog output (WDO).

Watchdog service-signal input pin.

Watchdog status pin. Open-drain output pin. Pull this pin up to OUT or a reference voltage

through a resistor. When watchdog fault occurs, this pin is pulled down to a low-level voltage.

WDO

Watchdog enable pin. Pull this pin down to a low level to enable the watchdog. Pull this pin

up to a high level to disable the watchdog.

WD_EN

WRS

Window ratio selection pin (only applicable for the window watchdog). Pull this pin down to a

low level to set the open:closed window ratio to 1:1. Pull this pin up to high level to set the

open:closed window ratio to 8:1.

Watchdog type-selection pin. To set the window watchdog, connect this pin to the GND pin.

To set the standard watchdog, pull this pin high.

WTS

6 Specifications

6.1 Absolute Maximum Ratings

over operating ambient temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

MIN

–0.3

–40

MAX

UNIT

Unregulated input

IN, EN

ROSC

DELAY

OUT

Internal oscillator reference voltage

Power-good delay-timer output

Regulated output

Power-good output voltage

Watchdog status output voltage

Watchdog frequency selection, watchdog-type selection

Watchdog enable

WDO

FSEL, WTS

WD_EN

Watchdog service signal voltage

Window ratio selection

WRS

Power good threshold adjustment voltage

Operating junction temperature, T_J

Storage temperature, T_stg

PGADJ

150

°C

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to ground.

TPS7B68-Q1

ZHCSFR0C –MAY 2015–REVISED FEBRUARY 2019

www.ti.com.cn

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

Charged-device model (CDM), per AEC Q100-011

±2000

±500

±750

Electrostatic

discharge

V_(ESD)

All pins

Corner pins (1, 14, 15, and 28)

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)

MIN

MAX

UNIT

Unregulated input

40-V pins

V_IN

5.5

EN, FSEL, WTS

OUT

Regulated output

Power good, watchdog status,

reference oscillator

PG, WDO, ROSC

5.5

Low voltage pins

WD, WD_EN, PGADJ, DELAY, WRS

5.5

500

150

125

Output current

°C

Operating junction temperature, T_J

Ambient temperature, T_A

–40

6.4 Thermal Information

TPS7B68-Q1

THERMAL METRIC⁽¹⁾

PWP (HTSSOP)

UNIT

28 PINS

37.8

18.4

18.7

0.8

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-board thermal resistance

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

ψ_JB

18.5

2.4

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

TPS7B68-Q1

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ZHCSFR0C –MAY 2015–REVISED FEBRUARY 2019

6.5 Electrical Characteristics

V_IN= 14 V, C_OUT≥ 4.7 µF, 1 mΩ < ESR < 20 Ω, and T_J= –40°C to 150°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY VOLTAGE AND CURRENT (IN)

V_IN

Input voltage

I_(SLEEP)

Input sleep current

EN = OFF

µA

V_IN= 5.6 V to 40 V for fixed 5-V

V_OUT; V_IN= 4 V to 40 V for fixed

3.3-V V_OUT; EN = ON; watchdog

disabled; I_OUT< 1 mA;

29.6

T_J< 80°C

V_IN= 5.6 V to 40 V for fixed 5-V

V_OUT; V_IN= 4 V to 40 V for fixed

3.3-V V_OUT; EN = ON; watchdog

enabled; I_OUT< 1 mA

I_(Q)

Input quiescent current

µA

V_IN= 5.6 V to 40 V for fixed 5-V

V_OUT; V_IN= 4 V to 40 V for fixed

3.3-V V_OUT; EN = ON; watchdog

enabled; I_OUT< 100 mA

Ramp V_INdown until output is

turned off

V_(UVLO)

Undervoltage lockout, falling

UVLO hysteresis

2.6

V_{(UVLO_}

HYST)

0.5

ENABLE INPUT, WATCHDOG TYPE SELECTION AND FSEL (EN, WTS, AND FSEL)

V_IL

Low-level input voltage

High-level input voltage

Hysteresis

0.7

V_IH

V_hys

150

WATCHDOG ENABLE (WD_EN PIN)

Low-level input threshold voltage for

watchdog enable pin

V_IL

Watchdog enabled

Watchdog disabled

V_{WD_EN}= 5 V

0.7

High-level input threshold voltage for

watchdog enable pin

V_IH

Pulldown current for watchdog

enable pin

I_{WD_EN}

µA

REGULATED OUTPUT (OUT)

V_IN= V_OUT+ 1 V to 40 V,

I_OUT= 0 to 500 mA

–2%

V_OUT

Regulated output

V_IN= 5.4 V, I_OUT= 250 mA

T_J= –40°C to 85°C

ΔV_OUT

(ΔVIN)

Line regulation

Load regulation

V_IN= 5.6 V to 40 V

ΔV_OUT

(ΔIOUT)

I_OUT= 1 mA to 500 mA

I_OUT= 500 mA

I_OUT= 200 mA⁽²⁾

350

170

800

325

500

(1)

V_(dropout)

I_OUT

Dropout voltage (V_IN– V_OUT

)

Output current

V_OUTin regulation

V_OUTshorted to ground, V_IN= 5.6 V,

TPS7B6850QPWPRQ1

550

690

1000

I_(LIM)

Output short-circuit current limit

Power supply ripple rejection⁽³⁾

V_OUTshorted to ground, V_IN= 5.6V,

TPS7B6833QPWPRQ1

490

I_OUT= 100 mA; C_OUT= 10 µF;

frequency (f) = 100 Hz

PSRR

I_OUT= 100 mA; C_OUT= 10 µF;

frequency (f) = 100 kHz

(1) This test is done with V_OUTin regulation, measuring the V_IN– V_OUTwhen V_OUTdrops by 100 mV from the rated output voltage at the

specified load.

(2) Dropout is not measured for V_OUT= 3.3 V in this test because V_INmust be 4 V or greater for proper operation.

(3) Design Information – Not tested, determined by characterization.

TPS7B68-Q1

ZHCSFR0C –MAY 2015–REVISED FEBRUARY 2019

www.ti.com.cn

Electrical Characteristics (continued)

V_IN= 14 V, C_OUT≥ 4.7 µF, 1 mΩ < ESR < 20 Ω, and T_J= –40°C to 150°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER GOOD (PG, PGADJ)

V_OL(PG)

PG output, low voltage

I_OL= 5 mA, PG pulled low

0.4

PG pulled to V_OUTthrough a 10-kΩ

resistor

I_lkg(PG)

PG pin leakage current

µA

V_OUTpowered above the internally

set tolerance, PGADJ pin shorted to

ground

V_{(PG_TH)}

rising

Default power-good threshold

89.6

91.6

93.6 % of V_OUT

% of V_OUT

V_OUTfalling below the internally set

tolerance hysteresis

V_{(PG_HYST)}Power-good hysteresis

PGADJ

V_{(PGADJ_}

TH) falling

V_{(PGADJ_}

HYST)

Switching voltage for the power-

good adjust pin

V_OUTis falling

1.067

1.1

1.133

PGADJ hysteresis

POWER-GOOD DELAY

I_{(DLY_CHG)}DELAY capacitor charging current

µA

DELAY pin threshold to release PG

V_{(DLY_TH)}

high

Voltage at DELAY pin is ramped up

V_DELAY= 1 V

0.95

1.05

DELAY capacitor discharging

I_{(DLY_DIS)}

current

0.5

CURRENT VOLTAGE REFERENCE (ROSC)

V_ROSC

WATCHDOG (WD, WDO, WRS)

Low-level threshold voltage for the

Voltage reference

0.95

1.05

V_IL

watchdog input and window-ratio

select

For WD and WRS pins

30 % of V_OUT

High-level threshold voltage for the

watchdog input and window-ratio

select

V_IH

% of V_OUT

V_(HYST)

I_WD

Hysteresis

Pulldown current for the WD pin

Watchdog output pulled low

V_WDO= 5 V

I_WDO= 5 mA

µA

V_OL

0.4

WDO pin pulled to V_OUTthrough

10-kΩ resistor

I_lkg

WDO pin leakage current

µA

OPERATING TEMPERATURE RANGE

T_J

Junction temperature

–40

150

°C

T_(SD)

T_(HYST)

Junction shutdown temperature

Hysteresis of thermal shutdown

175

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ZHCSFR0C –MAY 2015–REVISED FEBRUARY 2019

6.6 Switching Characteristics

V_I= 14 V, C_O≥ 4.7 µF, 1 mΩ < ESR < 20 Ω, and T_J= –40°C to 150°C (unless otherwise noted)

PARAMETER

POWER-GOOD DELAY (DELAY)

t_(DEGLITCH)Power-good deglitch time

TEST CONDITIONS

MIN

TYP

MAX

UNIT

180

248

250

900

µs

t_{(DLY_FIX)}

Fixed power-good delay

No capacitor connect at DELAY pin

Delay capacitor value:

C_(DELAY)= 100 nF

t_(DLY)

Power-on-reset delay

WATCHDOG (WD, WDO, WRS)

R_(ROSC)= 20 kΩ ±1%, FSEL = LOW

R_(ROSC)= 20 kΩ ±1%, FSEL = HIGH

t_(WD)

Watchdog window duration

Tolerance of watchdog window

duration using external resistor

R_(ROSC)=

20 kΩ ±1% to 50 kΩ ±1%

t_{(WD_TOL)}

t_p(WD)

–10%

100

10%

Watchdog service-signal duration

µs

Watchdog output resetting time

t_{(WD_HOLD)}(percentage of settled watchdog

window duration)

% of

t_(WD)

R_(ROSC)= 20 kΩ ± 1%, FSEL = LOW

1.8

2.2

t_{(WD_RESET)}Watchdog output resetting time

R_(ROSC)= 20 kΩ ± 1%,

FSEL = HIGH

TPS7B68-Q1

ZHCSFR0C –MAY 2015–REVISED FEBRUARY 2019

www.ti.com.cn

6.7 Typical Characteristics

V_IN= 14 V, V_EN≥ 2 V, T_J= –40°C to +150°C (unless otherwise noted)

120

110

100

400

350

300

250

200

150

100

I_OUT= 1 mA

I_OUT= 100 mA

I_OUT= 200 mA

-40èC

25èC

125èC

50 100 150 200 250 300 350 400 450 500

Output Current (mA)

Input Voltage (V)

D001

D002

图 1. Quiescent Current vs Output Current

图 2. Quiescent Current vs Input Voltage

I_OUT= 1 mA

I_OUT= 100 mA

-40 -25 -10

20 35 50 65 80 95 110 125

-40 -25 -10

20 35 50 65 80 95 110 125

Ambient Temperature (°C)

Ambient Temperature (èC)

D003

D004

图 3. Shutdown Current vs Ambient Temperature

图 4. Quiescent Current vs Ambient Temperature

600

500

400

300

200

100

300

250

200

150

100

-40èC

25èC

125èC

50 100 150 200 250 300 350 400 450 500

Output Current (mA)

-40 -25 -10

20 35 50 65 80 95 110 125

Ambient Temperature (°C)

D005

D006

I_OUT= 200 mA

图 6. Dropout Voltage vs Ambient Temperature

图 5. Dropout Voltage vs Output Current

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ZHCSFR0C –MAY 2015–REVISED FEBRUARY 2019

Typical Characteristics (接下页)

V_IN= 14 V, V_EN≥ 2 V, T_J= –40°C to +150°C (unless otherwise noted)

5.06

5.03

4.97

-40èC

25èC

125èC

4.94

-40 -25 -10

20 35 50 65 80 95 110 125

Ambient Temperature (°C)

Input Voltage (V)

D007

D008

V_OUT= 5 V

图 7. Output Voltage vs Ambient Temperature

图 8. Output Voltage vs Input Voltage

900

800

700

600

500

-40èC

0.8

0.6

0.4

0.2

25èC

125èC

-0.2

-0.4

-0.6

-0.8

-1

-40 -25 -10

20 35 50 65 80 95 110 125

Ambient Temperature (°C)

100

200

300

400

500

Output Current (mA)

D009

D010

V_IN= 5.6 V

图 9. Output Current Limit (I_LIM) vs Ambient Temperature

图 10. Load Regulation

120

100

-40èC

0.8

25èC

125èC

0.6

0.4

0.2

-0.2

-0.4

-0.6

-0.8

-1

100

10k

100k

10M

Input Voltage (V)

Frequency (Hz)

D011

D012

C_OUT= 10 μF

I_OUT= 1 mA

图 12. PSRR vs Frequency

T_A= 25°C

图 11. Line Regulation

TPS7B68-Q1

ZHCSFR0C –MAY 2015–REVISED FEBRUARY 2019

www.ti.com.cn

Typical Characteristics (接下页)

V_IN= 14 V, V_EN≥ 2 V, T_J= –40°C to +150°C (unless otherwise noted)

120

Unstable Region

Stable Region

500

100

4.7

Unstable Region

0.001

100

10k

100k

10M

0.01

0.1

ESR (W)

10 20

Frequency (Hz)

D013

D014

C_OUT= 10 μF

I_OUT= 100 mA

图 13. PSRR vs Frequency

T_A= 25°C

图 14. ESR Stability vs Output Capacitance

V_IN(10 V/div)

V_OUT(1 V/div)

V_IN(10 V/div)

V_OUT(AC)(100 mV/div)

I_OUT(10 mA/div)

V_OUT(AC)(100 mV/div)

I_OUT(10 mA/div)

V_IN= 6 V to 40 V

I_OUT= 1 mA

V_OUT= 5 V

C_OUT= 10 µF

V_IN= 40 V to 6 V

I_OUT= 1 mA

V_OUT= 5 V

C_OUT= 10 µF

图 15. Line Transient

图 16. Line Transient

V_IN(5 V/div)

V_OUT(1 V/div)

V_OUT(AC)(50 mV/div)

I_OUT(200 mA/div)

V_OUT(AC)(50 mV/div)

I_OUT(200 mA/div)

V_IN= 6 V to 40 V

I_OUT= 200 mA

V_OUT= 5 V

C_OUT= 10 µF

V_IN= 40 V to 6 V

I_OUT= 200 mA

V_OUT= 5 V

C_OUT= 10 µF

图 17. Line Transient

图 18. Line Transient

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Typical Characteristics (接下页)

V_IN= 14 V, V_EN≥ 2 V, T_J= –40°C to +150°C (unless otherwise noted)

V_IN(5 V/div)

V_OUT(1 V/div)

V_OUT(AC)(500 mV/div)

I_OUT(200 mA/div)

V_OUT= 5 V

C_OUT= 10 µF

I_OUT= 1 mA to 200 mA

V_OUT= 5 V

C_OUT= 10 µF

I_OUT= 200 mA to 1 mA

图 19. Load Transient

图 20. Load Transient

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7 Detailed Description

7.1 Overview

The TPS7B68-Q1 is a 500-mA, 40-V monolithic low-dropout linear voltage regulator with integrated watchdog

and adjustable power-good threshold functionality. This voltage regulator consumes only 19-µA quiescent current

in light-load applications. Because of the adjustable power-good delay (also called power-on-reset delay) and the

adjustable power-good threshold, this device is well-suited as power supplies for microprocessors and

microcontrollers in automotive applications.

7.2 Functional Block Diagram

OUT

V_BAT

V_REG

Overcurrent

Protection

Regulator

Control

Thermal

Shutdown

Undervoltage

Lockout

Band Gap

Error

Amp

V_ref

DELAY

ROSC

Power-Good

Control With

Delay

V_{(PG_REF )}

Current

Regulator

Watchdog

Oscillator

Amp

PGADJ

WDO

MCU I/O

Timer

WD_EN

Digital I/O

Watchdog

Fault Control

GND

FSEL

WTS

WRS

7.3 Feature Description

7.3.1 Device Enable (EN)

The EN pin is a high-voltage-tolerant pin. High input activates the devices and turns the regulators ON. Connect

this input pin to an external microcontroller or a digital control circuit to enable and disable the devices, or

connect to the IN pin for self-bias applications.

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Feature Description (接下页)

7.3.2 Adjustable Power-Good Threshold (PG, PGADJ)

The PG pin is an open-drain output with an external pullup resistor to the regulated supply, and the PGADJ pin is

a power-good threshold adjustment pin. Connecting the PGADJ pin to GND sets the power-good threshold value

to the default, V_{(PG_TH) rising}. When V_OUTexceeds the default power-good threshold, the PG output turns high after

the power-good delay period has expired. When V_OUTfalls below V_{(PG_TH) rising}– V_{(PG_HYST)}, the PG output turns

low after a short deglitch time.

The power-good threshold is also adjustable from 1.1 V to 5 V with external resistor divider between PGADJ and

OUT. The threshold can be calculated using 公式 1:

R1+ R2

V _{PG_ ADJ falling}= V _{PGADJ_ TH falling}

(

)

(

)

R1+ R2

⁄

V _{PG_ ADJ risng}= V _{PGADJ_ TH falling}+ 26 mV typ

(

)

(

)

(

)

where

•

V_{(PG_ADJ) rising}, V_{(PG_ADJ) falling}is the adjustable power-good threshold

V_{(PGADJ_TH) falling}is the internal comparator reference voltage of the PGADJ pin, 1.1 V typical, 3% accuracy

specified under all conditions

(1)

By setting the power-good threshold V_{(PG_ADJ) rising}, when V_OUTexceeds this threshold, the PG output turns high

after the power-good delay period has expired. When V_OUTfalls below V_{(PG_ADJ) falling}, the PG output turns low

after a short deglitch time.

OUT

V_REG

Adjustable Power-

Good Threshold

DELAY

Power-Good

Control

V_{(PG_REF)}

Amp

PGADJ

图 21. Adjustable Power Good Threshold

7.3.3 Adjustable Power-Good Delay Timer (DELAY)

The power-good delay period is a function of the value set by an external capacitor on the DELAY pin before

turning the PG pin high. Connecting an external capacitor from this pin to GND sets the power-good delay

period. The constant current charges an external capacitor until the voltage exceeds a threshold to trip an

internal comparator, and 公式 2 determines the power-good delay period:

_DELAY´ 1 V

t_(DLY)

5 mA

where

•

t_(DLY)is the adjustable power-good delay period

C_DELAYis the value of the power-good delay capacitor

(2)

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Feature Description (接下页)

V_IN

(UVLO)

t < t_(DEGLITCH)

V(PG_HYST)

V_{(PG_TH}) rising

V_{(PG_TH) falling}

V_{(PG_ADJ) falling}

V_{(PG_ADJ}) rising

V_OUT

(DLY_TH)

DELAY

t_(DEGLITCH)

(DLY)

Power Up

Input Voltage Drop

Undervoltage

Power Down

NOTE: V_{(PG_TH) falling}= V_{(PG_TH) rising}– V_{(PG_HYST)}

图 22. Power Up and Conditions for Activation of Power Good

If the DELAY pin is open, the default delay time is t_{(DLY_FIX)}

7.3.4 Undervoltage Shutdown

This device has an integrated undervoltage lockout (UVLO) circuit to shut down the output if the input voltage

falls below an internal UVLO threshold, V_(UVLO). This ensures that the regulator does not latch into an unknown

state during low input-voltage conditions. If the input voltage has a negative transient which drops below the

UVLO threshold and recovers, the regulator shuts down and powers up with a normal power-up sequence when

the input voltage is above the required levels.

7.3.5 Current Limit

This device features current-limit protection to keep the device in a safe operating area when an overload or

output short-to-ground condition occurs. This protects the device from excessive power dissipation. For example,

during a short-circuit condition on the output, fault protection limits the current through the pass element to I_(LIM)

to protect the device from excessive power dissipation.

7.3.6 Thermal Shutdown

This device incorporates a thermal shutdown (TSD) circuit as a protection from overheating. For continuous

normal operation, the junction temperature should not exceed the thermal shutdown trip point. The junction

temperature exceeding the TSD trip point causes the output to turn off. When the junction temperature falls

below the T_(SD)– T_(HYST), the output turns on again.

7.3.7 Integrated Watchdog

This device has an integrated watchdog with fault (WDO) output option. Both window watchdog and standard

watchdog are available in one device. The watchdog operation, service fault conditions, and differences between

window watchdog and standard watchdog are described as follows.

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Feature Description (接下页)

7.3.7.1 Window Watchdog (WTS, ROSC, FSEL and WRS)

This device works in the window watchdog mode when the watchdog type selection (WTS) pin is connected to a

to low voltage level. The user can set the duration of the watchdog window by connecting an external resistor

(R_ROSC) to ground at the ROSC pin and setting the voltage level at the FSEL pin. The current through the R_ROSC

resistor sets the clock frequency of the internal oscillator. The user can adjust the duration of the watchdog

window (the watchdog timer period) by changing the resistor value. A high voltage level at the FSEL pin sets the

watchdog window duration to 5 times as long as that of a low voltage level with same external component

configuration.

The duration of the watchdog window and the duration of the fault output are multiples of the internal oscillator

frequency, as shown by the following equations:

t_(WD)= R_ROSC× 0.5 × 10^-6

t_(WD)= R_ROSC× 2.5 × 10^-6

t_{(WD_INI)}= 8 × t_(WD)

(3)

(4)

(5)

(6)

(7)

(8)

FSEL low

FSEL high

Watchdog initialization

Open and closed windows

WRS low

t_(WD)= t_(OW)+ t_(CW)

t_(OW)= t_(CW)= 50% × t_(WD)

t_(OW)= 8 × t_(CW)= (8 / 9) × t_(WD)

WRS high

where:

•

t_(WD)is the duration of the watchdog window

R_ROSCis the resistor connected at the ROSC pin

t_{(WD_INI)}is the duration of the watchdog initialization

t_(OW)is the duration of the open watchdog window

t_(CW)is the duration of the closed watchdog window

For all the foregoing items, the unit of resistance is Ω and the unit of time is s.

表 1 illustrates several periods of watchdog window with typical conditions.

表 1. Several Typical Periods of Watchdog Window

FSEL

R_(ROSC)(kΩ)

I_(ROSC)(µA)

t_(WD)(ms)

WATCHDOG PERIOD

TOLERANCE

200

100

500

250

125

100

62.5

15%

High

10%

100

Low

12.5

As shown in 图 23, each watchdog window consists of an open window and a closed window. While the window

ratio selection (WRS) pin is low, each open window (t_(OW)) and closed window (t_(CW)) having a width

approximately 50% of the watchdog window (t_(WD)). While the WRS pin is high, the ratio between open window

and closed window is about 8:1. However, there is an exception to this; the first open window after watchdog

initialization (t_{(WD_INI)}) is eight times the duration of the watchdog window. The watchdog must receive the service

signal (by software, external microcontroller, and so forth) during this initialization open window.

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A watchdog fault occurs when servicing the watchdog during a closed window, or not servicing during an open

window.

t_{(WD_INI)}

t_(WD)

Closed Window

(Must Not Be Serviced

to Prevent Fault)

Open Window

(Must Be Serviced

to Prevent Fault)

Open Window

After Watchdog Initialization

(Must Be Serviced to Prevent Fault)

WRS = Low

t_(CW)= ½ ´ t_(WD)

t_(OW)= ½ ´ t_(WD)

8 ´ t_(WD)

Open Window

After Watchdog Initialization

(Must Be Serviced to Prevent Fault)

Open Window

(Must Be Serviced

to Prevent Fault)

WRS = High

t_(OW)= 8 / 9 ´ t_(WD)

8 ´ t_(WD)

Closed Window

(Must Not Be Serviced

to Prevent Fault)

Event Causing

Watchdog Initialization

t_(CW)= 1 / 9 ´ t_(WD)

图 23. Watchdog Initialization, Open Window and Closed Window

7.3.7.2 Standard Watchdog (WTS, ROSC and FSEL)

This device works in the standard watchdog mode when the watchdog type selection (WTS) pin is connected to

a high voltage level. The same as in window watchdog mode, the user can set the duration of the watchdog

window by adjusting the external resistor (R_ROSC) value at the ROSC pin and setting the voltage level at the

FSEL pin. The current through the R_ROSCresistor sets the clock frequency of the internal oscillator. The user can

adjust the duration of the watchdog window (the watchdog timer period) by changing the resistor value. A high

voltage level at the FSEL pin sets the watchdog window duration to 5 times as long as that of a low voltage level

with same external component configuration.

The duration of the watchdog window and the duration of the fault output are multiples of the internal oscillator

frequency as shown by the following equations:

t_(WD)= R_ROSC× 0.5 × 10^-6

t_(WD)= R_ROSC× 2.5 × 10^-6

t_{(WD_INI)}= 8 × t_(WD)

(9)

(10)

(11)

FSEL low

FSEL high

Watchdog initialization

where:

•

t_(WD)is the duration of the watchdog window

R_ROSCis the resistor connected at the ROSC pin

t_{(WD_INI)}is the duration of the watchdog initialization

For all the foregoing items, the unit of resistance is Ω and the unit of time is s

Compared with window watchdog, there is no closed window in standard watchdog mode. The standard

watchdog receives a service signal at any time within the watchdog window. The watchdog fault occurs when not

servicing watchdog during the watchdog window.

7.3.7.3 Watchdog Service Signal and Watchdog Fault Outputs (WD and WDO)

The correct watchdog service signal (WD) must stay high for at least 100 µs. The WDO pin is the fault output

terminal and is tied high through a pullup resistor to a regulated output supply. When a watchdog fault occurs,

the device momentarily pulls WDO low for a duration of t_{(WD_HOLD)}

_{(WD _HOLD)}= 20%´ t_(WD)

(12)

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7.3.7.4 ROSC Status Detection (ROSC)

When a watchdog function is enabled, if the ROSC pin is shorted to GND or open, the watchdog output (WDO)

pin remains low, indicating a fault status. If watchdog function is disabled, ROSC pin status detection does not

work.

7.3.7.5 Watchdog Enable (PG and WD_EN)

When PG (power good) is high, an external microcontroller or a digital circuit can apply a high or low logic signal

to the WD_EN pin to disable or enable the watchdog. A low input to this pin turns the watchdog on, and a high

input turns the watchdog off. If PG is low, the watchdog is disabled and the watchdog-fault output (WDO) pin

stays in the high-impedance state.

7.3.7.6 Watchdog Initialization

On power up and during normal operation, the watchdog initializes under the conditions shown in 表 2.

表 2. Conditions for Watchdog Initialization

EDGE

WHAT CAUSES THE WATCHDOG TO INITIALIZE

Rising edge of PG (power good) while the watchdog is in the enabled state, for example,

during soft power up

↑

Falling edge of WD_EN while PG is already high, for example, when the microprocessor

enables the watchdog after the device is powered up

↓

↑

Rising edge of WDO while PG is already high and the watchdog is in the enabled state, for

example, right after a closed window is serviced

7.3.7.7 Window Watchdog Operation (WTS = Low)

The window watchdog is able to monitor whether the frequency of the watchdog service signal (WD) is within

certain ranges. A watchdog low-voltage fault is reported when the frequency of the watchdog service signal is out

of the setting range. 图 24 shows the window watchdog initialization and operation for the TPS7B68-Q1 (WRS is

low). After the output voltage is in regulation and PG is high, the window watchdog becomes enabled when an

external signal pulls WD_EN (the watchdog enable pin) low. This causes the watchdog to initialize and wait for a

service signal during the first initialization window for 8 times the duration of t_(WD). A service signal applied to the

WD pin during the initialization open window resets the watchdog counter and a closed window starts. To prevent

a fault condition from occurring, watchdog service must not occur during the closed window. Watchdog service

must occur during the following open window to prevent a fault condition from occurring. The fault output (WDO),

externally pulled up to V_OUT(typical), stays high as long as the watchdog receives a proper service signal and

there is no other fault condition.

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V_IN

V_{(PG_TH) rising}

V_{(PG_ADJ) rising}

)

V_OUT

V_{(PG_TH) falling}

V_{(PG_ADJ) falling}

t_(DLY)

V_{(DLY_TH)}

DELAY

t_(DLY)

t_(DEGLITCH)

WD_EN

WDO

WD Ini- NA

tialization

WD Initial-

ization

WD Initialization

Watchdog

Window Status

OW CW

Initial...

Initialization

<8 t_(WD)

t_(WD)/ 2

<8 t_(WD)

t_(WD)/ 2

<8 t_(WD)

8 t_(WD)

<8 t_(WD)

Normal Operation

20% ´ t_(WD)

Fault 1

Fault 2

Fault 3

NOTE: V_{(PG_TH) rising}= V_{(PG_TH) falling}+ V_{(PG_HYST)}

图 24. Window Watchdog Operation

Three different fault conditions occur in 图 24:

•

Fault 1: The watchdog service signal is received during the closed window. The WDO is triggered one time,

receiving a WD rising edge during the closed window.

Fault 2: The watchdog service signal is not received during the open window. WDO is triggered after the

maximum open-window duration t_(WD)/ 2.

Fault 3: The watchdog service signal is not received during the WD initialization. WDO is triggered after the

maximum initialization window duration 8 × t_(WD)

7.3.7.8 Standard Watchdog Operation (WTS = High)

The standard watchdog is able to monitor whether the frequency of the watchdog service signal (WD) is lower

than a certain value. A watchdog low-voltage fault is reported when the frequency of the watchdog service signal

is lower than the set value.

图 25 shows the standard watchdog initialization and operation for the TPS7B68-Q1. Similar to the window

watchdog, after output the voltage is in regulation and PG asserts high, the standard watchdog becomes enabled

when an external signal pulls WD_EN low. This causes the standard watchdog to initialize and wait for a service

signal during the first initialization window for 8 times the duration of t_(WD). A service signal applied to the WD pin

during the first open window resets the watchdog counter and another open window starts. To prevent a fault

condition from occurring, watchdog service must occur during the every open window to prevent a fault condition

from occurring. The fault output (WDO), externally pulled up to V_OUT(typical), stays high as long as the watchdog

receives proper service and there is not fault condition.

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V_IN

V_{(PG_TH) rising}

V_{(PG_ADJ) rising}

V_OUT

V_{(PG_TH) falling}

V_{(PG_ADJ) falling}

t_(DLY)

V_{(DLY_TH)}

DELAY

t_(DLY)

t_(DEGLITCH)

WD_EN

WDO

WD Ini- NA

tialization

WD Initialization

Watchdog

Window Status

OW OW

Initialization Initial...

<8 t_(WD)

<t_(WD)

<t_(WD)<t_(WD)

<t_(WD)

<8 t_(WD)

8 t_(WD)

<8 t_(WD)

20% ´ t_(WD)

Normal Operation

Fault 1

Fault 2

NOTE: V_{(PG_TH) rising}= V_{(PG_TH) falling}+ V_{(PG_HYST)}

图 25. Standard Watchdog Operation

Two different fault conditions occur in 图 25:

•

Fault 1: The watchdog service signal is not received during the open window. WDO is triggered after the

maximum open-window duration t_(WD)/ 2.

Fault 2: The watchdog service signal is not received during the WD initialization. WDO is triggered after the

maximum initialization window duration 8 × t_(WD)

7.4 Device Functional Modes

7.4.1 Operation With Input Voltage Lower Than 4 V

The device normally operates with input voltages above 4 V. The device can also operate at lower input

voltages; the maximum UVLO voltage is 2.6 V. At input voltages below the actual UVLO voltage, the device does

not operate.

7.4.2 Operation With Input Voltage Higher Than 4 V

When the input voltage is greater than 4 V, if the input voltage is higher than the output set value plus the device

dropout voltage, then the output voltage is equal to the set value. Otherwise, the output voltage is equal to the

input voltage minus the dropout voltage.

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8 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS7B68-Q1 device is a 500-mA low-dropout watchdog linear regulator with ultralow quiescent current. The

PSpice transient model is available for download on the product folder and can be used to evaluate the basic

function of the device.

8.2 Typical Application

图 26 shows a typical application circuit for the TPS7B68-Q1. Different values of external components can be

used, depending on the end application. An application may require a larger output capacitor during fast load

steps to prevent a large drop on the output voltage. TI recommends using a low-ESR ceramic capacitor with a

dielectric of type X7R.

TPS7B6833-Q1

TPS7B6850-Q1

OUT

MCU

Supply

Battery

PGADJ

WD_EN

Digital

I/O

WTS

MCU

I/O

WDO

MCU

I/O

MCU

Reset

ROSC

FSEL

WRS

DELAY

GND

图 26. TPS7B68-Q1 Typical Application Schematic

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Typical Application (接下页)

8.2.1 Design Requirements

For this design example, use the parameters listed in 表 3.

表 3. Design Parameters

DESIGN PARAMETER

EXAMPLE VALUES

Input voltage range

4 V to 40 V for TPS7B6833-Q1

5.6 V to 40 V for TPS7B6850-Q1

Input capacitor range

Output voltage

10 μF to 22 μF

3.3 V, 5 V

Output current rating

Output capacitor range

Power-good threshold

500 mA maximum

4.7 μF to 500 μF

Adjustable or fixed

Power-good delay capacitor

Watchdog type

100 pF to 100 nF

Standard watchdog or window watchdog

10 ms to 500 ms

Watchdog window periods

8.2.2 Detailed Design Procedure

To begin the design process, determine the following:

•

Input voltage range

Output voltage

Output current

Power-good threshold

Power-good delay capacitor

Watchdog type

Watchdog window period

8.2.2.1 Input Capacitor

When using a TPS7B68-Q1 device, TI recommends adding a 10-μF to 22-μF capacitor with a 0.1 μF ceramic

bypass capacitor in parallel at the input to keep the input voltage stable. The voltage rating must be greater than

the maximum input voltage.

8.2.2.2 Output Capacitor

Ensuring the stability of the TPS7B68-Q1 requires an output capacitor with a value in the range from 4.7 μF to

500 μF and with an ESR range from 0.001 Ω to 20 Ω. TI recommends selecting a ceramic capacitor with low

ESR to improve the load transient response.

8.2.2.3 Power-Good Threshold

The power-good threshold is set by connecting PGADJ to GND or to a resistor divider from OUT to GND. The

Adjustable Power-Good Threshold (PG, PGADJ) section provides the method for setup the power-good

threshold.

8.2.2.4 Power-Good Delay Period

The power-good delay period is set by an external capacitor (C_DELAY) to ground, with a typical capacitor value

from 100 pF to 100 nF. Calculate the correct capacitance for the application using 公式 2.

8.2.2.5 Watchdog Setup

The Integrated Watchdog section discusses the watchdog type selection and watchdog window-period setup

method.

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8.2.3 Application Curves

V_OUT(5 V/div)

WD Signal (5 V/div)

V_IN(5 V/div)

WDO Signal (5 V/div)

I_OUT(10 mA/div)

V_OUT(2 V/div)

V_PG(2 V/div)

I_OUT(10 mA/div)

图 28. TPS7B6850-Q1 Watchdog Fault (High Frequency

图 27. TPS7B6850-Q1 Power-Up Waveform

Watchdog Service Signal)

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9 Power Supply Recommendations

The device is designed to operate from an input-voltage supply range from 4 V to 40 V. This input supply must

be well regulated. If the input supply is located more than a few inches from the TPS7B68-Q1 device, TI

recommends adding a capacitor with a value of ≥10 μF with a 0.1 μF ceramic bypass capacitor in parallel at the

input.

10 Layout

10.1 Layout Guidelines

For LDO power supplies, especially high-voltage and high-current ones, layout is an important step. If layout is

not carefully designed, the regulator could not deliver enough output current because of thermal limitation. To

improve the thermal performance of the device and maximize the current output at high ambient temperature, TI

recommends spreading the thermal pad as much as possible and put enough thermal vias on the thermal pad.

图 29 shows an example layout.

10.2 Layout Example

OUT

PGADJ

FSEL

WTS

Thermal

Pad

GND

ROSC

DELAY

WRS

WD_EN

WDO

图 29. Layout Recommendation

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11 器件和文档支持

11.1 文档支持

11.1.1 相关文档

请参阅如下相关文档：

德州仪器 (TI)，《TPS7B68-Q1 评估模块用户指南》

11.2 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.3 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.4 商标

PowerPAD, E2E are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

11.5 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

11.6 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、缩写和定义。

12 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查看左侧的导航面板。

重要声明和免责声明

TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资

源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示

担保。

所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、

验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用

所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权

许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。

TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约

束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS7B6833QPWPRQ1

TPS7B6850QPWPRQ1

ACTIVE

HTSSOP

PWP

2000 RoHS & Green

NIPDAU

Level-3-260C-168 HR

-40 to 125

7B6833Q

7B6850Q

NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

20-Feb-2019

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS7B6833QPWPRQ1 HTSSOP PWP

TPS7B6850QPWPRQ1 HTSSOP PWP

2000

330.0

16.4

6.9

10.2

1.8

12.0

16.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

20-Feb-2019

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS7B6833QPWPRQ1

TPS7B6850QPWPRQ1

HTSSOP

PWP

2000

350.0

43.0

Pack Materials-Page 2

GENERIC PACKAGE VIEW

PWP 28

4.4 x 9.7, 0.65 mm pitch

PowerPAD^TMTSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224765/B

www.ti.com

PACKAGE OUTLINE

PWP0028C

PowerPAD^TMTSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

6.6

6.2

TYP

0.1 C

PIN 1 INDEX

AREA

SEATING

PLANE

26X 0.65

9.8

9.6

8.45

NOTE 3

0.30

0.19

28X

4.5

4.3

0.1

C A B

SEE DETAIL A

(0.15) TYP

2X 0.95 MAX

NOTE 5

2X 0.2 MAX

NOTE 5

0.25

GAGE PLANE

1.2 MAX

5.18

4.48

THERMAL

PAD

0.15

0.05

0.75

0.50

0 -8

DETAIL A

TYPICAL

3.1

2.4

4223582/A 03/2017

PowerPAD is a trademark of Texas Instruments.

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. Reference JEDEC registration MO-153.

5. Features may differ or may not be present.

www.ti.com

EXAMPLE BOARD LAYOUT

PWP0028C

PowerPAD^TMTSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

(3.4)

NOTE 9

(3.1)

METAL COVERED

BY SOLDER MASK

SYMM

28X (1.5)

28X (0.45)

SEE DETAILS

(R0.05) TYP

(5.18)

(0.6)

26X (0.65)

SYMM

(9.7)

NOTE 9

SOLDER MASK

DEFINED PAD

(1.2) TYP

(

0.2) TYP

VIA

(1.2) TYP

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 8X

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

OPENING

METAL

EXPOSED METAL

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

15.000

(PREFERRED)

SOLDER MASK DETAILS

4223582/A 03/2017

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).

9. Size of metal pad may vary due to creepage requirement.

10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged

or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

PWP0028C

PowerPAD^TMTSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

(3.1)

BASED ON

0.125 THICK

STENCIL

28X (1.5)

METAL COVERED

BY SOLDER MASK

28X (0.45)

(R0.05) TYP

26X (0.65)

SYMM

(5.18)

BASED ON

0.125 THICK

STENCIL

SYMM

(5.8)

SEE TABLE FOR

DIFFERENT OPENINGS

FOR OTHER STENCIL

THICKNESSES

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 8X

STENCIL

THICKNESS

SOLDER STENCIL

OPENING

0.1

3.47 X 5.79

3.10 X 5.18 (SHOWN)

2.83 X 4.73

0.125

0.15

0.175

2.62 X 4.38

4223582/A 03/2017

NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

12. Board assembly site may have different recommendations for stencil design.

www.ti.com

重要声明和免责声明

TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资

源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示

担保。

所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、

验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用

所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权

许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。

TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约

束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122

TPS7B68-Q1 [TI]

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TPS7B6933DBVR

TPS7B6933QDBVRQ1

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