TPS7B84-Q1 [TI]

TPS7B84-Q1 150-mA, 40-V, Adjustable, Low-Dropout Regulator;


型号：	TPS7B84-Q1
厂家：	TEXAS INSTRUMENTS
描述：	TPS7B84-Q1 150-mA, 40-V, Adjustable, Low-Dropout Regulator
文件：	总33页 (文件大小：1097K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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TPS7B84-Q1

SBVS361 –APRIL 2020

TPS7B84-Q1 150-mA, 40-V, Adjustable, Low-Dropout Regulator

1 Features

3 Description

The TPS7B84-Q1 is a low-dropout linear regulator

designed to connect to the battery in automotive

applications. The device has an input voltage range

extending to 40 V, which allows the device to

withstand transients (such as load dump) that are

anticipated in automotive systems. With only a 20-µA

quiescent current at light loads, the device is an

optimal solution for powering always-on components

such as microcontrollers (MCUs) and controller area

network (CAN) transceivers in standby systems.

•

AEC-Q100 qualified for automotive applications:

–

Temperature grade 1: –40°C to +125°C, T_A

Junction temperature: –40°C to +150°C, T_J

•

Input voltage range: 3 V to 40 V (42 V max)

Output voltage range:

–

Adjustable output: 1.2 V to 18 V

Fixed output: 3.3 V and 5 V

•

Output current: up to 150 mA

Output voltage accuracy: ±1.5% (max)

Low dropout voltage:

The TPS7B84-Q1 has both fixed and adjustable

output types. The wide output voltage range allows

the device to generate the bias voltage for silicon

carbide (SiC) gate drivers and microphones as well

as power MCUs and processors.

–

255 mV (max) at 150 mA (V_OUT≥ 3.3 V)

•

Low quiescent current:

–

20 µA (typ) at light loads

5 µA (max) when disabled

The device has state-of-the-art transient response

that allows the output to quickly react to changes in

load or line (for example, during cold-crank

conditions). Additionally, the device has a novel

architecture that minimizes output overshoot when

recovering from dropout. During normal operation, the

device has a tight DC accuracy of ±1.5% over line,

load, and temperature.

Excellent line transient response:

–

±2% V_OUTdeviation during cold-crank

±2% V_OUTdeviation (1-V/µs V_INslew rate)

•

Stable with a 2.2-µF or larger capacitor

Package options:

The device is available in both a SOT223 package

and a small VSON package with wettable flanks that

facilitates a compact printed circuit board (PCB)

design. The low thermal resistance enables sustained

operation despite significant dissipation across the

device.

–

DRB (8-pin VSON), R_θJA: 50.8ºC/W

DCY (4-pin SOT-223), R_θJA: 85.5ºC/W

2 Applications

•

Reconfigurable instrument clusters

Body control modules (BCM)

Device Information⁽¹⁾

Always-on battery-connected applications:

PART NUMBER

PACKAGE

VSON (8)

SOT-223 (4)

BODY SIZE (NOM)

3.00 mm × 3.00 mm

6.50 mm × 3.50 mm

–

Automotive gateways

TPS7B84-Q1

Remote keyless entries (RKE)

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Line Transient Response (3-V/µs V_INSlew Rate)

0.25

V_IN

V_OUT

Typical Application Schematic

0.2

0.15

0.1

OUT

TPS7B84-Q1

0.05

GND

-0.05

-0.1

-0.15

-0.2

500

1000

1500

Time (ms)

2000

2500

3000

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to

change without notice.

TPS7B84-Q1

SBVS361 –APRIL 2020

www.ti.com

Table of Contents

7.4 Device Functional Modes........................................ 14

Application and Implementation ........................ 15

8.1 Application Information............................................ 15

8.2 Typical Application .................................................. 19

Power Supply Recommendations...................... 20

Features.................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics........................................... 5

6.6 Typical Characteristics.............................................. 6

Detailed Description ............................................ 10

7.1 Overview ................................................................. 10

7.2 Functional Block Diagrams ..................................... 10

7.3 Feature Description................................................. 12

10 Layout................................................................... 20

10.1 Layout Guidelines ................................................. 20

10.2 Layout Examples................................................... 21

11 Device and Documentation Support ................. 22

11.1 Receiving Notification of Documentation Updates 22

11.2 Support Resources ............................................... 22

11.3 Trademarks........................................................... 22

11.4 Electrostatic Discharge Caution............................ 22

11.5 Glossary................................................................ 22

12 Mechanical, Packaging, and Orderable

Information ........................................................... 22

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

DATE

REVISION

NOTES

April 2020

Initial release.

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SBVS361 –APRIL 2020

5 Pin Configuration and Functions

DCY Package

4-Pin SOT-223

Top View

DRB Package

8-Pin VSON

Top View

OUT

FB/NC

GND

Thermal pad

OUT

Not to scale

Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NAME

DCY

DRB

Enable pin. The device is disabled when the enable pin becomes lower than

the enable logic input low level (V_IL).

Ground pin. Connect this pin to the thermal pad with a low-impedance

connection.

GND

FB/NC

Feedback pin when using an external resistor divider or an NC pin when using

the device with a fixed output voltage.

—

No internal connection. Connect these pins to GND for the best thermal

performance.

3, 4, 6

Input power-supply voltage pin. For best transient response and to minimize

input impedance, use the recommended value or larger ceramic capacitor from

IN to ground as listed in the Recommended Operating Conditions table and the

Input Capacitor section. Place the input capacitor as close to the output of the

device as possible.

Regulated output voltage pin. A capacitor is required from OUT to ground for

stability. For best transient response, use the nominal recommended value or

larger ceramic capacitor from OUT to ground; see the Recommended

Operating Conditions table and the Output Capacitor section. Place the output

capacitor as close to output of the device as possible.

OUT

Thermal

pad

Thermal pad. Connect the pad to GND for the best possible thermal

performance. See the Layout section for more information.

—

Pad

—

(1) I = input; O = output; P = power; G = ground.

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

–40

MAX UNIT

Unregulated input

Enable input

OUT

T_J

V_IN+ 0.3⁽²⁾

Regulated output

Feedback

Operating junction temperature

Storage temperature

150

°C

T_stg

–65

150

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions isnot implied. Exposure to absolute-maximum-rated conditions for extended periods may affect devicereliability.

(2) The absolute maximum rating is V_IN+ 0.3 V or 20 V, whichever is smaller.

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per AEC Q100-002

V_(ESD)

Electrostatic discharge

All pins

Charged-device model (CDM), per AEC Q100-

011

Corner pins

±750

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

TYP

MAX

UNIT

V_IN

Input voltage

1.2

V_OUT

I_OUT

F_EN

V_EN

C_OUT

ESR

C_IN

Output voltage

Output current

Enable pin frequency⁽¹⁾

150

kHz

High voltage (I/O)

Output capacitor⁽²⁾

2.2

220

µF

Output capacitor ESR requirements

Input capacitor⁽³⁾

0.001

µF

°C

T_J

Operating junction temperature

–40

150

(1) Minimum pulse time on the EN pin is 100 µs.

(2) Effective output capacitance of 1 µF minimum required for stability.

(3) For robust EMI performance the minimum input capacitance is 500 nF.

6.4 Thermal Information

TPS7B84-Q1

THERMAL METRIC⁽¹⁾⁽²⁾

DRB (VSON)

DCY

4 PINS

85.5

46.6

11.3

4.9

Unit

8 PINS

50.8

55.6

22.9

1.2

θ_JA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

θ_JCtop

θ_JB

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

ψ_JB

22.9

7.5

θ_JCbot

(1) The thermal data is based on the JEDEC standard high K profile,JESD 51-7. Two-signal, two-plane, four-layer board with 2-oz. copper.

The copper pad is soldered tothe thermal land pattern. Also, correct attachment procedure must be incorporated.

(2) For more information about traditional and new thermal metrics,see the Semiconductor and IC PackageThermal Metrics application

report.

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SBVS361 –APRIL 2020

6.5 Electrical Characteristics

specified at T_J= –40°C to +150°C, V_IN= 13.5 V, I_OUT= 0 mA, C_OUT= 2.2 µF, 1 mΩ < C_OUTESR < 2 Ω, C_IN= 1 µF, and V_EN

2 V (unless otherwise noted); typical values are at T_J= 25°C

PARAMETER

TEST CONDITIONS

MIN

–0.75

-1

TYP

MAX

0.75

UNIT

T_J= 25ºC

V_IN= V_OUT+ 500 mV to 40 V,

I_OUT= 100 µA to 150 mA⁽¹⁾⁽²⁾

V_OUT

Regulated output

Line regulation

T_J= –40°C to +150ºC

Change in percent of output

voltage

V_IN= V_OUT+ 500 mV to

40 V, I_OUT= 100 µA

ΔV_OUT(ΔVIN)

0.2

V_IN= V_OUT+ 500 mV,

I_OUT= 100 µA to 150 mA,

Change in percent of output

voltage

ΔV_OUT(ΔIOUT)

Load regulation

V_OUT≥ 3.3 V

V_IN= V_OUT+ 500 mV,

I_OUT= 100 µA to 150 mA,

V_OUT< 3.3 V

Change in percent of output

voltage

ΔV_OUT(ΔIOUT)

0.3

T_J= 25ºC

V_IN= V_OUT+ 500 mV to 40 V,

I_OUT= 0 mA⁽¹⁾

I_Q

Quiescent current

µA

T_J= –40°C to +150ºC

T_J= 25ºC

I_OUT= 500 µA⁽¹⁾

V_EN= 0 V

2.5

I_SHUTDOWN

Shutdown supply current (I_GND

)

µA

T_J= –40°C to +150ºC

I_OUT≤ 1 mA, V_OUT≥ 3.3 V, V_IN= V_OUT(NOM)x 0.95

V_DO

Dropout voltage fixed output

I_OUT= 105 mA, V_OUT≥ 3.3 V, V_IN= V_OUT(NOM)

130

160

200

255

I_OUT= 150 mA, V_OUT≥ 3.3 V, V_IN= V_OUT(NOM)

_OUT≤ 1 mA, V_IN= 3 V, V_FB= 0.61 V⁽³⁾

I_OUT= 105 mA, V_IN= 3 V, V_FB= 0.61 V⁽³⁾

I_OUT= 150 mA, V_IN= 3 V, V_FB= 0.61 V⁽³⁾

Reference voltage for FB

Dropout voltage adjustable output

Dropout voltage Adjustable Output

Feedback voltage

V_DO

225

280

0.657

V_FB

0.643

0.65

I_FB

Feedback Current

V_UVLO(RISING)

V_{UVLO(FALLING)}

V_UVLO(HYST)

V_IL

Rising input supply UVLO

Falling input supply UVLO

V_UVLOhysteresis

V_INrising

V_INfalling

2.6

2.7

2.5

2.82

2.6

2.38

215

Enable logic input low level

Enable logic input high level

EN pin current

0.7

V_IH

I_EN

V_EN= V_IN= 13.5 V

µV_RMS

°C

I_CL

Output current limit

V_IN= V_OUT+ 1 V, V_OUTshort to 90% x V_OUT(NOM)

V_IN- V_OUT= 500 mV, frequency = 1 kHz, I_OUT= 150 mA

V_OUT= 3.3 V, BW = 10 Hz to 100 kHz

180

220

260

PSRR

Power-supply ripple rejection

Output noise voltage

V_n

280

175

T_SD(SHUTDOWN)

T_SD(HYST)

Junction shutdown temperature

Hysteresis of thermal shutdown

°C

(1) For adjustable devices this parameter is tested in unity gain, so resistor divider tolerances and current is not included.

(2) Power dissipation is limited to 2W for IC production testing purposes. The power dissipation can be higher during normal operation.

Please see the thermal dissipation section for more information on how much power the device can dissipate while maintaining a

junction temperature below 150℃.

(3) Dropout is not measured for V_IN≤ 3 V

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6.6 Typical Characteristics

specified at T_J= –40°C to +150°C, V_IN= 13.5 V, I_OUT= 100 µA, C_OUT= 2.2 µF, 1 mΩ < C_OUTESR < 2 Ω, C_IN= 1 µF, and V_EN

= 2 V (unless otherwise noted)

5.015

5.01

5.005

0.1

0.05

-55èC

-40èC

0èC

25èC

85èC

125èC

150èC

150 mA

100 mA

-0.05

-0.1

-0.15

-0.2

-0.25

-0.3

4.995

4.99

4.985

4.98

4.975

-60 -40 -20

20 40 60 80 100 120 140 160

Temperature èC

20 25

Input Voltage (V)

V_OUT= 5 V, I_OUT= 150 mA

Figure 2. Line Regulation vs V_IN

Figure 1. Accuracy vs Temperature

5.015

5.01

5.005

5.015

5.01

5.005

-55èC

-40èC

0èC

25èC

85èC

125èC

150èC

-55èC

-40èC

0èC

25èC

85èC

125èC

150èC

4.995

4.99

4.985

4.98

4.975

4.995

4.99

4.985

4.98

4.975

20 25

Input Voltage (V)

20 25

Input Voltage (V)

V_OUT= 5 V, I_OUT= 5 mA

Figure 3. Line Regulation vs V_IN

V_OUT= 5 V, I_OUT= 1 mA

Figure 4. Line Regulation vs V_IN

5.015

5.01

5.005

275

250

225

200

175

150

125

100

-55èC

-40èC

0èC

25èC

85èC

125èC

150èC

-55èC

-40èC

0èC

25èC

85èC

125èC

150èC

4.995

4.99

4.985

4.98

4.975

Output Current (mA)

100

125

150

60 90

Output Current (mA)

120

150

V_OUT= 5 V

V_IN= 3 V

Figure 5. Load Regulation vs I_OUT

Figure 6. Dropout Voltage (V_DO) vs I_OUT

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Typical Characteristics (continued)

specified at T_J= –40°C to +150°C, V_IN= 13.5 V, I_OUT= 100 µA, C_OUT= 2.2 µF, 1 mΩ < C_OUTESR < 2 Ω, C_IN= 1 µF, and V_EN

= 2 V (unless otherwise noted)

100

I_OUT= 150 mA

I_OUT= 100 mA

I_OUT= 50 mA

I_OUT= 10 mA

I_OUT= 1mA

V_IN= 5.5 V

V_IN= 6 V

V_IN= 7 V

V_IN= 10 V

V_IN= 13.5 V

100

10k 100k

Frequency (Hz)

10M

100

10k 100k

Frequency (Hz)

10M

C_OUT= 10 µF (X7R 50 V), V_OUT= 5 V

C_OUT= 10 µF (X7R 50 V), I_OUT= 150 mA, V_OUT= 5 V

Figure 7. PSRR vs Frequency and I_OUT

Figure 8. PSRR vs Frequency and V_IN

0.25

0.2

200

150

100

640

560

480

400

320

240

160

V_IN

V_OUT

I_OUT

0.15

0.1

0.05

-50

-0.05

-0.1

-0.15

-0.2

-100

-150

-200

500

1000

1500

Time (ms)

2000

2500

3000

0.25

0.5

0.75

Time (ms)

1.25

1.5

1.75

V_OUT= 5V, I_OUT= 1 mA, V_IN= 13.5 V to 45 V,

slew rate = 2.7 V/µs, V_EN= 3.3 V

V_OUT= 5 V, I_OUT= 0 mA to 100 mA, slew rate = 1 A/µs,

V_EN= 3.3 V

Figure 9. Line Transients

Figure 10. Load Transient, No Load to 100 mA

650

600

550

500

450

400

350

300

250

200

150

100

480

V_OUT

I_OUT

V_OUT

I_OUT

440

400

360

320

280

240

200

160

120

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-10

-20

-30

-40

-50

100

150

Time (ms)

200

250

300

350

50 100 150 200 250 300 350 400 450 500

Time (ms)

V_OUT= 5 V, I_OUT= 0 mA to 100 mA, slew rate = 1 A/µs,

V_EN= 3.3 V

V_OUT= 5 V, I_OUT= 100 mA to 0 mA, slew rate = 1 A/µs,

V_EN= 3.3 V

Figure 11. Load Transient, No Load to 100-mA Rising Edge

Figure 12. Load Transient, No Load to 100-mA Falling Edge

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Typical Characteristics (continued)

specified at T_J= –40°C to +150°C, V_IN= 13.5 V, I_OUT= 100 µA, C_OUT= 2.2 µF, 1 mΩ < C_OUTESR < 2 Ω, C_IN= 1 µF, and V_EN

= 2 V (unless otherwise noted)

400

360

320

280

240

200

160

120

400

360

320

280

240

200

160

120

V_OUT

I_OUT

V_OUT

I_OUT

-5

-10

-15

-20

-25

-10

-15

-20

-25

0.25 0.5 0.75

1.25 1.5 1.75

Time (ms)

2.25 2.5

100

150

Time (ms)

200

250

300

350

V_OUT= 5 V, I_OUT= 50 mA to 100 mA, slew rate = 0.1 A/µs,

V_EN= 3.3 V

V_OUT= 5 V, I_OUT= 50 mA to 100 mA, slew rate = 0.1 A/µs,

V_EN= 3.3 V

Figure 13. Load Transient, 50 mA to 100 mA

Figure 14. Load Transient, 50-mA to 100-mA Rising Edge

400

360

320

280

240

200

160

120

800

750

700

650

600

550

500

450

400

350

300

250

200

150

100

V_OUT

I_OUT

V_OUT

I_OUT

-10

-20

-30

-40

-50

-60

-70

-80

-5

-10

-15

-20

-25

350

200 400 600 800 1000 1200 1400 1600 1800 2000

100

150

200

250

300

Time (ms)

V_OUT= 5 V, I_OUT= 100 mA to 50 mA, slew rate = 0.1 A/µs,

V_EN= 3.3 V

V_OUT= 5 V, I_OUT= 0 mA to 150 mA, slew rate = 1 A/µs,

V_EN= 3.3 V

Figure 15. Load Transient, 50-mA to 100-mA Falling Edge

Figure 16. Load Transient, 0 mA to 150 mA

230

600

550

500

450

400

350

300

250

200

150

100

V_OUT

I_OUT

227.5

225

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

222.5

220

217.5

215

212.5

210

25 50 75 100 125 150 175 200 225 250 275 300

Time (ms)

-60 -40 -20

20 40 60 80 100 120 140 160

Temperature èC

V_OUT= 5 V, I_OUT= 0 mA to 150 mA, slew rate = 1 A/µs,

V_EN= 3.3 V

V_IN= V_OUT+ 1 V, V_OUT= 90% × V_OUT(NOM)

Figure 17. Load Transient, 0-mA to 150-mA Rising Edge

Figure 18. Current Limit vs Temperature

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Typical Characteristics (continued)

specified at T_J= –40°C to +150°C, V_IN= 13.5 V, I_OUT= 100 µA, C_OUT= 2.2 µF, 1 mΩ < C_OUTESR < 2 Ω, C_IN= 1 µF, and V_EN

= 2 V (unless otherwise noted)

175

150

125

100

-55èC

-40èC

0èC

25èC

85èC

125èC

150èC

-55èC

-40èC

0èC

25èC

85èC

125èC

150èC

20 25

Input Voltage (V)

Figure 19. Quiescent Current (I_Q) vs V_IN

Figure 20. Quiescent Current (I_Q) vs V_IN

1.38

1.36

1.34

1.32

1.3

2.8

2.75

2.7

Falling Threshold

Rising Threshold

Falling Threshold

Rising Threshold

2.65

2.6

1.28

1.26

1.24

1.22

1.2

2.55

2.5

2.45

2.4

-60 -40 -20

20 40 60 80 100 120 140 160

Temperature (èC)

-60 -40 -20

20 40 60 80 100 120 140 160

Temperature (èC)

V_PGADJ= 0 V

Figure 21. EN Threshold vs Temperature

Figure 22. Undervoltage Lockout (UVLO) Threshold vs

Temperature

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7 Detailed Description

7.1 Overview

The TPS7B84-Q1 is a low-dropout linear regulator (LDO) designed to connect to the battery in automotive

applications. The device has an input voltage range extending to 40 V, which allows the device to withstand

transients (such as load dumps) that are anticipated in automotive systems. With only a 20-µA quiescent current

at light loads, the device is an optimal solution for powering always-on components.

The device has a state-of-the-art transient response that allows the output to quickly react to changes in the load

or line (for example, during cold-crank conditions). Additionally, the device has a novel architecture that

minimizes output overshoot when recovering from dropout. During normal operation, the device has a tight DC

accuracy of ±1.5% over line, load, and temperature.

7.2 Functional Block Diagrams

OUT

Current

Limit

Thermal

Shutdown

UVLO

Bandgap

GND

Figure 23. Adjustable Output Block Diagram

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Functional Block Diagrams (continued)

OUT

Current

Limit

R₁

Thermal

Shutdown

UVLO

R₂

Bandgap

GND

Figure 24. Fixed Output Block Diagram

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7.3 Feature Description

7.3.1 Enable (EN)

The enable pin for the device is an active-high pin. The output voltage is enabled when the voltage of the enable

pin is greater than the high-level input voltage of the EN pin and disabled with the enable pin voltage is less than

the low-level input voltage of the EN pin. If independent control of the output voltage is not needed, connect the

enable pin to the input of the device.

7.3.2 Undervoltage Lockout

The device has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a

controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input

drops during turn on, the UVLO has hysteresis as specified in the Electrical Characteristics table.

7.3.3 Thermal Shutdown

The device contains a thermal shutdown protection circuit to disable the device when the junction temperature

(T_J) of the pass transistor rises to T_SD(shutdown)(typical). Thermal shutdown hysteresis assures that the device

resets (turns on) when the temperature falls to T_SD(reset)(typical).

The thermal time-constant of the semiconductor die is fairly short, thus the device may cycle on and off when

thermal shutdown is reached until power dissipation is reduced. Power dissipation during startup can be high

from large V_IN– V_OUTvoltage drops across the device or from high inrush currents charging large output

capacitors. Under some conditions, the thermal shutdown protection disables the device before startup

completes.

For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating

Conditions table. Operation above this maximum temperature causes the device to exceed its operational

specifications. Although the internal protection circuitry of the device is designed to protect against thermal

overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device

into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability.

7.3.4 Current Limit

The device has an internal current limit circuit that protects the regulator during transient high-load current faults

or shorting events. The current limit is a brickwall scheme. In a high-load current fault, the brickwall scheme limits

the output current to the current limit (I_CL). I_CLis listed in the Electrical Characteristics table.

The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the

device begins to heat up because of the increase in power dissipation. When the device is in brickwall current

limit, the pass transistor dissipates power [(V_IN– V_OUT) × I_CL]. If thermal shutdown is triggered, the device turns

off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If the output

current fault condition continues, the device cycles between current limit and thermal shutdown. For more

information on current limits, see the Know Your Limits application report.

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Feature Description (continued)

Figure 25 shows a diagram of the current limit.

V_OUT

Brickwall

V_OUT(NOM)

0 V

I_OUT

I_RATED

0 mA

I_CL

Figure 25. Current Limit

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7.4 Device Functional Modes

7.4.1 Device Functional Mode Comparison

The Device Functional Mode Comparison table shows the conditions that lead to the different modes of

operation. See the Electrical Characteristics table for parameter values.

Table 1. Device Functional Mode Comparison

PARAMETER

OPERATING MODE

V_IN

V_EN

I_OUT

T_J

Normal operation

Dropout operation

V_IN> V_OUT(nom)+ V_DOand V_IN> V_IN(min)

V_IN(min)< V_IN< V_OUT(nom)+ V_DO

V_EN> V_EN(HI)

I_OUT< I_OUT(max)

T_J< T_SD(shutdown)

Disabled

(any true condition

disables the device)

V_IN< V_UVLO

V_EN< V_EN(LOW)

Not applicable

T_J> T_SD(shutdown)

7.4.2 Normal Operation

The device regulates to the nominal output voltage when the following conditions are met:

•

The input voltage is greater than the nominal output voltage plus the dropout voltage (V_OUT(nom)+ V_DO

The output current is less than the current limit (I_OUT< I_CL

The device junction temperature is less than the thermal shutdown temperature (T_J< T_SD

The enable voltage has previously exceeded the enable rising threshold voltage and has not yet decreased to

less than the enable falling threshold

)

7.4.3 Dropout Operation

If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other

conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage

tracks the input voltage. During this mode, the transient performance of the device becomes significantly

degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load

transients in dropout can result in large output-voltage deviations.

When the device is in a steady dropout state (defined as when the device is in dropout, V_IN< V_OUT(NOM)+ V_DO

directly after being in a normal regulation state, but not during startup), the pass transistor is driven into the

ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output

voltage plus the dropout voltage (V_OUT(NOM)+ V_DO), the output voltage can overshoot for a short period of time

while the device pulls the pass transistor back into the linear region.

7.4.4 Disabled

The output of the device can be shutdown by forcing the voltage of the enable pin to less than the maximum EN

pin low-level input voltage (see the Electrical Characteristics table). When disabled, the pass transistor is turned

off, internal circuits are shutdown, and the output voltage is actively discharged to ground by an internal

discharge circuit from the output to ground.

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 Input and Output Capacitor Selection

The TPS7B84-Q1 requires an output capacitor of 2.2 µF or larger (1 µF or larger capacitance) for stability and an

equivalent series resistance (ESR) between 0.001 Ω and 2 Ω. For the best transient performance, use X5R- and

X7R-type ceramic capacitors because these capacitors have minimal variation in value and ESR over

temperature. When choosing a capacitor for a specific application, be mindful of the DC bias characteristics for

the capacitor. Higher output voltages cause a significant derating of the capacitor. For best performance, the

maximum recommended output capacitance is 220 µF.

Although an input capacitor is not required for stability, good analog design practice is to connect a capacitor

from IN to GND. Some input supplies have a high impedance, thus placing the input capacitor on the input

supply helps reduce the input impedance. This capacitor counteracts reactive input sources and improves

transient response, input ripple, and PSRR. If the input supply has a high impedance over a large range of

frequencies, several input capacitors can be used in parallel to lower the impedance over frequency. Use a

higher-value capacitor if large, fast, rise-time load transients are anticipated, or if the device is located several

inches from the input power source.

8.1.2 Adjustable Device Feedback Resistor Selection

The adjustable-version device requires external feedback divider resistors to set the output voltage. V_OUTis set

using the feedback divider resistors, R₁and R₂, according to the following equation:

V_OUT= V_FB× (1 + R₁/ R₂)

(1)

To ignore the FB pin current error term in the V_OUTequation, set the feedback divider current to 100x the FB pin

current listed in the Electrical Characteristics table. This setting provides the maximum feedback divider series

resistance, as shown in the following equation:

R₁+ R₂≤ V_OUT/ (I_FB× 100)

(2)

8.1.3 Feed-Forward Capacitor (C_FF)

For the adjustable-voltage version device, a feed-forward capacitor (C_FF) can be connected from the OUT pin to

the FB pin. C_FFimproves transient, noise, and PSRR performance, but is not required for regulator stability.

Recommended C_FFvalues are listed in the Recommended Operating Conditions table. A higher capacitance C_FF

can be used; however, the startup time increases. For a detailed description of C_FFtradeoffs, see the Pros and

Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator application report.

C_FFand R₁form a zero in the loop gain at frequency f_Z, while C_FF, R₁, and R₂form a pole in the loop gain at

frequency f_P. C_FFzero and pole frequencies can be calculated from the following equations:

f_Z= 1 / (2 × π × C_FF× R₁)

(3)

(4)

f_P= 1 / (2 × π × C_FF× (R₁|| R₂))

8.1.4 Dropout Voltage

Dropout voltage (V_DO) is defined as the input voltage minus the output voltage (V_IN– V_OUT) at the rated output

current (I_RATED), where the pass transistor is fully on. I_RATEDis the maximum I_OUTlisted in the Recommended

Operating Conditions table. The pass transistor is in the ohmic or triode region of operation, and acts as a switch.

The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed output

voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than the

nominal output regulation, then the output voltage falls as well.

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Application Information (continued)

For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (R_DS(ON)) of the

pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for

that current scales accordingly. Use Equation 5 to calculate the R_DS(ON)of the device.

V_DO

R_DS(ON)

I_RATED

(5)

8.1.5 Reverse Current

Excessive reverse current can damage this device. Reverse current flows through the intrinsic body diode of the

pass transistor instead of the normal conducting channel. At high magnitudes, this current flow degrades the

long-term reliability of the device.

Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute

maximum rating of V_OUT≤ V_IN+ 0.3 V.

•

If the device has a large C_OUTand the input supply collapses with little or no load current

The output is biased when the input supply is not established

The output is biased above the input supply

If reverse current flow is expected in the application, external protection is recommended to protect the device.

Reverse current is not limited in the device, so external limiting is required if extended reverse voltage operation

is anticipated.

8.1.6 Power Dissipation (P_D)

Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed circuit

board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few or no

other heat-generating devices that cause added thermal stress.

To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference

and load conditions. Equation 6 calculates power dissipation (P_D).

P_D= (V_IN– V_OUT) × I_OUT

(6)

NOTE

Power dissipation can be minimized, and therefore greater efficiency can be achieved, by

correct selection of the system voltage rails. For the lowest power dissipation use the

minimum input voltage required for correct output regulation.

For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal

pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an

array of plated vias that conduct heat to additional copper planes for increased heat dissipation.

The maximum power dissipation determines the maximum allowable ambient temperature (T_A) for the device.

According to Equation 7, power dissipation and junction temperature are most often related by the junction-to-

ambient thermal resistance (R_θJA) of the combined PCB and device package and the temperature of the ambient

air (T_A).

T_J= T_A+ (R_θJA× P_D)

(7)

Thermal resistance (R_θJA) is highly dependent on the heat-spreading capability built into the particular PCB

design, and therefore varies according to the total copper area, copper weight, and location of the planes. The

junction-to-ambient thermal resistance listed in the Thermal Information table is determined by the JEDEC

standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance.

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Application Information (continued)

8.1.6.1 Thermal Performance vs Copper Area

The most used thermal resistance parameter R_θJAis highly dependent on the heat-spreading capability built into

the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of

the planes. The R_θJArecorded in the TBD table is determined by the JEDEC standard as shown in Figure 26,

PCB, and copper-spreading area, and is only used as a relative measure of package thermal performance. Note

that for a well-designed thermal layout, R_θJAis actually the sum of the package junction-to-case (bottom) thermal

resistance (R_θJCbot) plus the thermal resistance contribution by the PCB copper.

Mold

Compound

Die

Wire

Die

Attach

2oz

Signal

Trace

Lead

Frame

Internal Signal

or power plane

1oz copper

Thermal

Pad or Tab

of the LDO

Internal

GND plane

1oz copper

Bottom

Relief

2oz copper

Thermal

Vias

Figure 26. JEDEC Standard 2s2p PCB

Figure 27 and Figure 28 show the functions of R_θJAand ψ_JBversus copper area and thickness. These plots are

generated with a 101.6-mm x 101.6-mm x 1.6-mm PCB of two and four layers. For the four-layer board, the inner

planes use a 1-oz copper thickness. Outer layers are simulated with both a 1-oz and 2-oz copper thickness. A

TBD array of thermal vias of 300-µm drill diameter and 25-µm Cu plating is located beneath the thermal pad of

the device. The thermal vias connect the top layer, the bottom layer and, in the case of the 4-layer board, the first

inner GND plane. Each of the layers has a copper plane of equal area.

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Application Information (continued)

115

105

4 Layer PCB, 1 oz copper

4 Layer PCB, 2 oz copper

2 Layer PCB, 1 oz copper

2 Layer PCB, 2 oz copper

90 100

Cu Area Per Layer (cm²)

Figure 27. R_θJAvs Copper Area 2s2p DRB Package

4 Layer PCB, 1 oz copper

4 Layer PCB, 2 oz copper

2 Layer PCB, 1 oz copper

2 Layer PCB, 2 oz copper

90 100

Cu Area Per Layer (cm²)

Figure 28. R ψ_JBvs Copper Area 2s2p DRB Package

8.1.7 Estimating Junction Temperature

The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures

of the linear regulator when in-circuit on a typical PCB board application. These metrics are not thermal

resistance parameters and instead offer a practical and relative way to estimate junction temperature. These psi

metrics are determined to be significantly independent of the copper area available for heat-spreading. The

Thermal Information table lists the primary thermal metrics, which are the junction-to-top characterization

parameter (ψ_JT) and junction-to-board characterization parameter (ψ_JB). These parameters provide two methods

for calculating the junction temperature (T_J). As described in , use the junction-to-top characterization parameter

(ψ_JT) with the temperature at the center-top of device package (T_T) to calculate the junction temperature. As

described in , use the junction-to-board characterization parameter (ψ_JB) with the PCB surface temperature 1 mm

from the device package (T_B) to calculate the junction temperature.

T_J= T_T+ ψ_JT× P_D

where:

•

P_Dis the dissipated power

T_Tis the temperature at the center-top of the device package

(8)

T_J= T_B+ ψ_JB× P_D

where

•

T_Bis the PCB surface temperature measured 1 mm from the device package and centered on the package

edge

(9)

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Application Information (continued)

For detailed information on the thermal metrics and how to use them, see the Semiconductor and IC Package

Thermal Metrics application report.

8.2 Typical Application

Figure 29 shows a typical application circuit for the TPS7B84-Q1. Use different values of external components,

depending on the end application. An application may require a larger output capacitor during fast load steps in

order to prevent a reset from occurring. TI recommends a low-ESR ceramic capacitor with a dielectric of type

X5R or X7R.

TPS7B84xx-Q1

V_I

V_o

bat

reg

10 …F

0.1 …F

GND

Figure 29. Typical Application Schematic for the TPS7B84-Q1

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Typical Application (continued)

8.2.1 Design Requirements

For this design example, use the parameters listed in Table 2 as the input parameters.

Table 2. Design Parameters

DESIGN PARAMETER

Input voltage range

Output voltage

EXAMPLE VALUE

6 V to 40 V

5 V

Output current

100 mA

10 µF

Output capacitor

8.2.2 Detailed Design Procedure

8.2.2.1 Input Capacitor

The device requires an input decoupling capacitor, the value of which depends on the application. The typical

recommended value for the decoupling capacitor is 1 µF. The voltage rating must be greater than the maximum

input voltage.

8.2.2.2 Output Capacitor

The device requires an output capacitor to stabilize the output voltage. The capacitor value must be between 2.2

µF and 200 µF and the ESR range must be between 1 mΩ and 2 Ω. For this design a low ESR, 10-µF ceramic

capacitor was used to improve transient performance.

9 Power Supply Recommendations

This device is designed for operation from an input voltage supply with a range between 3 V and 40 V. This input

supply must be well regulated. If the input supply is located more than a few inches from the TPS7B84-Q1, add

an electrolytic capacitor with a value of 22 µF and a ceramic bypass capacitor at the input.

10 Layout

10.1 Layout Guidelines

For best overall performance, place all circuit components on the same side of the circuit board and as near as

practical to the respective LDO pin connections. Place ground return connections to the input and output

capacitor, and to the LDO ground pin as close as possible to each other, connected by a wide, component-side,

copper surface. The use of vias and long traces to the input and output capacitors is strongly discouraged and

negatively affects system performance. TI also recommends a ground reference plane either embedded in the

PCB itself or located on the bottom side of the PCB opposite the components. This reference plane serves to

assure accuracy of the output voltage, shield noise, and behaves similarly to a thermal plane to spread (or sink)

heat from the LDO device when connected to the thermal pad. In most applications, this ground plane is

necessary to meet thermal requirements.

10.1.1 Package Mounting

Solder pad footprint recommendations for the TPS7B84-Q1 are available at the end of this document and at

www.ti.com.

10.1.2 Board Layout Recommendations to Improve PSRR and Noise Performance

As depicted in Figure 30 and Figure 31, place the input and output capacitors close to the device for the layout of

the TPS7B84-Q1. In order to enhance the thermal performance, place as many vias as possible around the

device. These vias improve the heat transfer between the different GND planes in the PCB.

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Layout Guidelines (continued)

To improve ac performance such as PSRR, output noise, and transient response, TI recommends a board

design with separate ground planes for VIN and VOUT, with each ground plane connected only at the GND pin

of the device. In addition, the ground connection for the output capacitor must connect directly to the GND pin of

the device.

Minimize equivalent series inductance (ESL) and ESR in order to maximize performance and ensure stability.

Place each capacitor as close as possible to the device and on the same side of the PCB as the regulator itself.

Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. TI

strongly discourages the use of vias and long traces to connect the capacitors because they may impact system

performance negatively and even cause instability.

If possible, and to ensure the maximum performance specified in this document, use the same layout pattern

used for the TPS7B84-Q1 evaluation board, available at www.ti.com.

10.2 Layout Examples

GND

V_IN

V_OUT

Denotes a via

Figure 30. SOT-223 (DCY) Layout

OUT

FB/NC

GND

Denotes a via

Figure 31. VSON (DRB) Layout

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11 Device and Documentation Support

11.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

11.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

11.3 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

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6-May-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(6)

(3)

(4/5)

PTPS7B8401QWDRBRQ1

PTPS7B8433QWDRBRQ1

PTPS7B8450QWDRBRQ1

ACTIVE

SON

DRB

3000

TBD

Call TI

-40 to 150

ACTIVE

DRB

3000

TPS7B8401QWDRBRQ1

TPS7B8433QWDRBRQ1

TPS7B8450QWDRBRQ1

PREVIEW

SON

DRB

3000

TBD

Call TI

-40 to 150

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

⁽⁶⁾Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

6-May-2020

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

TPS7B84-Q1

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PACKAGE OUTLINE

DRC0010U

VSON - 1 mm max height

SCALE 4.000

PLASTIC SMALL OUTLINE - NO LEAD

3.1

2.9

PIN 1 INDEX AREA

3.1

2.9

0.1 MIN

(0.13)

30.

SECTION A-A

TYPICAL

1.0

0.8

SEATING PLANE

0.08 C

0.05

0.00

1.65 0.1

2X (0.5)

4X (0.25)

(0.2) TYP

EXPOSED

THERMAL PAD

(0.16) TYP

SYMM

2.4 0.1

8X 0.5

0.3

0.2

10X

SYMM

10X

PIN 1 ID

(OPTIONAL)

0.1

C A B

0.05

0.5

0.3

4225163/A 07/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

DRC0010U

VSON - 1 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

(1.65)

(0.5)

10X (0.6)

10X (0.25)

(2.4)

SYMM

(3.4)

(0.95)

8X (0.5)

(R0.05) TYP

( 0.2) VIA

TYP

(0.25)

(0.575)

SYMM

(2.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

EXPOSED METAL

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4225163/A 07/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be ﬁlled, plugged or tented.

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EXAMPLE STENCIL DESIGN

DRC0010U

VSON - 1 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

2X (1.5)

(0.5)

SYMM

EXPOSED METAL

TYP

10X (0.6)

(1.53)

10X (0.25)

(1.06)

SYMM

(0.63)

8X (0.5)

(R0.05) TYP

4X (0.34)

4X (0.25)

(2.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 11:

80% PRINTED SOLDER COVERAGE BY AREA

SCALE:25X

4225163/A 07/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may oﬀer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

Submit Documentation Feedback

Product Folder Links: TPS7B84-Q1

PACKAGE OUTLINE

VSON - 1 mm max height

DRB0008J

PLASTIC QUAD FLAT PACK- NO LEAD

3.1

2.9

PIN 1 INDEX AREA

3.1

2.9

0.1 MIN

(0.13)

SECTION A-A

TYPICAL

1 MAX

SEATING PLANE

0.08 C

0.05

0.00

1.75

1.55

(0.2) TYP

6X 0.65

(0.19)

SYMM

2.5

2.3

1.95

0.36

0.26

PIN 1 ID

(OPTIONAL)

0.1

0.05

C A B

SYMM

0.5

0.3

4225036/A 06/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

VSON - 1 mm max height

DRB0008J

PLASTIC QUAD FLAT PACK- NO LEAD

(2.8)

(1.65)

8X (0.6)

8X (0.31)

SYMM

6X (0.65)

SYMM

(1.95) (2.4)

(0.95)

(R0.05) TYP

(Ø 0.2) VIA

TYP

(0.575)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 20X

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

METAL

SOLDER MASK

OPENING

EXPOSED METAL

SOLDER MASK

OPENING

METAL

NON- SOLDER MASK

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4225036/A 06/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

VSON - 1 mm max height

DRB0008J

PLASTIC QUAD FLAT PACK- NO LEAD

(2.8)

(1.51)

8X (0.6)

8X (0.31)

SYMM

(1.06)

6X (0.65)

SYMM

(1.95)

(0.63)

(R0.05) TYP

METAL

TYP

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

81% PRINTED COVERAGE BY AREA

SCALE: 20X

4225036/A 06/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

PACKAGE OPTION ADDENDUM

www.ti.com

6-Nov-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

PTPS7B8401QWDRBRQ1

PTPS7B8433QWDRBRQ1

PTPS7B8450QWDRBRQ1

TPS7B8401QWDRBRQ1

ACTIVE

SON

DRB

3000

TBD

Call TI

-40 to 150

Call TI

ACTIVE

Call TI

PREVIEW

Green (RoHS

& no Sb/Br)

NIPDAU

Level-2-260C-1 YEAR

7B8401

TPS7B8433QDCYRQ1

TPS7B8433QWDRBRQ1

TPS7B8450QDCYRQ1

TPS7B8450QWDRBRQ1

PREVIEW

SOT-223

SON

DCY

DRB

DCY

DRB

2500

3000

2500

3000

Green (RoHS

& no Sb/Br)

NIPDAU

Level-2-260C-1 YEAR

-40 to 150

7B8433

7B8450

Green (RoHS

& no Sb/Br)

SOT-223

SON

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

6-Nov-2020

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

permission to use these resources only for development of an application that uses the TI products described in the resource. Other

reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third

party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,

damages, costs, losses, and liabilities arising out of your use of these resources.

TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on

ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable

warranties or warranty disclaimers for TI products.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TPS7B84-Q1 [TI]

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