TPS7B8733QKVURQ1R2 [TI]
TPS7B87-Q1 500-mA, 40-V, Low-Dropout Regulator With Power-Good;
| 型号： | TPS7B8733QKVURQ1R2 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TPS7B87-Q1 500-mA, 40-V, Low-Dropout Regulator With Power-Good |
| 文件： | 总38页 (文件大小：3896K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS7B87-Q1
SBVS363A – DECEMBER 2020 – REVISED APRIL 2021
TPS7B87-Q1 500-mA, 40-V, Low-Dropout Regulator
With Power-Good
1 Features
3 Description
•
AEC-Q100 qualified for automotive applications:
The TPS7B87-Q1 is a low-dropout linear regulator
designed to connect to the battery in automotive
applications. The device has an input voltage range
extending to 40 V, which allows the device to
withstand transients (such as load dumps) that are
anticipated in automotive systems. With only a 17-
µA quiescent current at light loads, the device is an
optimal solution for powering always-on components
such as microcontrollers (MCUs) and controller area
network (CAN) transceivers in standby systems.
– Temperature grade 1: –40°C to +125°C, TA
– Junction temperature: –40°C to +150°C, TJ
Input voltage range: 3 V to 40 V (42 V max)
Output voltage range: 3.3 V and 5 V (fixed)
Maximum output current: 500 mA
Output voltage accuracy: ±0.85% (max)
Low dropout voltage:
– 475 mV (max) at 450 mA
Low quiescent current:
– 17 µA (typ) at light loads
Excellent line transient response:
– ±2% VOUT deviation during cold-crank
– ±2% VOUT deviation (1-V/µs VIN slew rate)
Power-good with programmable delay period
Stable with a 2.2-µF or larger capacitor
Functional Safety-Capable
– Documentation available to aid functional safety
system design
Package options:
•
•
•
•
•
•
•
The device has state-of-the-art transient response
that allows the output to quickly react to changes
in load or line (for example, during cold-crank
conditions). Additionally, the device has a novel
architecture that minimizes output overshoot when
recovering from dropout. During normal operation, the
device has a tight DC accuracy of ±0.85% over line,
load, and temperature.
•
•
•
The power-good delay can be adjusted by external
components, allowing the delay time to be configured
to fit application-specific systems.
•
– 5-pin TO-252 package: 29.7°C/W RθJA
– 8-pin HSOIC-8 package with thermal pad:
41.8°C/W RθJA
The device is available in thermally conductive
packaging to allow the device to efficiently transfer
heat to the circuit board.
2 Applications
Device Information (1)
•
•
•
Reconfigurable instrument clusters
Body control modules (BCM)
Always-on battery-connected applications:
– Automotive gateways
– Remote keyless entries (RKE)
PART NUMBER
PACKAGE
HSOIC (8)
TO-252 (5)
BODY SIZE (NOM)
4.89 mm × 3.90 mm
6.60 mm × 6.10 mm
TPS7B87-Q1
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
45
0.25
0.2
VIN
VOUT
40
35
30
25
20
15
10
5
0.15
0.1
IN
OUT
0.05
0
TPS7B87-Q1
-0.05
-0.1
-0.15
-0.2
DELAY
PG
I/O
GND
0
0
500
1000
1500
Time (ms)
2000
2500
3000
Output Equal to Reference Voltage
Line Transient Response (3-V/µs VIN Slew Rate)
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS7B87-Q1
SBVS363A – DECEMBER 2020 – REVISED APRIL 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information ...................................................5
6.5 Electrical Characteristics ............................................6
6.6 Switching Characteristics ...........................................7
6.7 Typical Characteristics................................................8
7 Detailed Description......................................................14
7.1 Overview...................................................................14
7.2 Functional Block Diagram.........................................14
7.3 Feature Description...................................................15
7.4 Device Functional Modes..........................................17
8 Application and Implementation..................................18
8.1 Application Information............................................. 18
8.2 Typical Application.................................................... 23
9 Power Supply Recommendations................................24
10 Layout...........................................................................25
10.1 Layout Guidelines................................................... 25
10.2 Layout Examples ................................................... 26
11 Device and Documentation Support..........................27
11.1 Device Support........................................................27
11.2 Documentation Support.......................................... 27
11.3 Receiving Notification of Documentation Updates..27
11.4 Support Resources................................................. 27
11.5 Trademarks............................................................. 27
11.6 Electrostatic Discharge Caution..............................27
11.7 Glossary..................................................................27
12 Mechanical, Packaging, and Orderable
Information.................................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (December 2020) to Revision A (April 2021)
Page
•
•
Added Functional Safety-Capable bullet to Features list....................................................................................1
Updated pin functions table to reflect pin 4 of the HSOIC (DDA) package as an NC pin...................................3
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5 Pin Configuration and Functions
IN
OUT
NC
1
2
3
4
8
7
6
5
NC
PG
GND
Thermal
Pad
Thermal
Pad
DELAY
NC
Figure 5-2. DDA Package, 8-Pin HSOIC, Top View
Not to scale
Figure 5-1. KVU Package, 5-Pin TO-252, Top View
Table 5-1. Pin Functions
PIN
KVU
TYPE(1)
DESCRIPTION
NAME
DDA
Power-good delay adjustment pin. Connect a capacitor from this pin to GND
to set the PG reset delay. Leave this pin floating for a default (t(DLY_FIX)) delay.
See the Power-Good (PG) section for more information. If this functionality is
not desired, leave this pin floating because connecting this pin to GND causes
a permanent increase in the GND current.
DELAY
4
3
I
GND
NC
3
5
G
Ground reference
No internal connection. This pin can be left floating or tied to GND for best
thermal performance.
—
2, 4, 7
—
Power-good pin. This pin has an internal pullup resistor. Do not connect this pin
to VOUT or any other biased voltage rail. VPG is logic level high when VOUT is
above the power-good threshold. See the Power-Good (PG) section for more
information.
PG
IN
2
1
6
8
I
Input power-supply voltage pin. For best transient response and to minimize
input impedance, use the recommended value or larger ceramic capacitor from
IN to GND as listed in the Recommended Operating Conditions table and the
Input Capacitor section. Place the input capacitor as close to the input of the
device as possible.
P
Regulated output voltage pin. A capacitor is required from OUT to GND for
stability. For best transient response, use the nominal recommended value or
larger ceramic capacitor from OUT to GND; see the Recommended Operating
Conditions table and the Output Capacitor section. Place the output capacitor
as close to output of the device as possible. If using a high equivalent
series resistance (ESR) capacitor, decouple the output with a 100-nF ceramic
capacitor.
OUT
5
1
O
Thermal
pad
Connect the thermal pad to a large area GND plane for improved thermal
performance.
Pad
Pad
—
(1) I = input; O = output; P = power; G = ground.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX UNIT
VIN
Unregulated input
–0.3
42
V
V
VOUT
Delay
PG
Regulated output
–0.3 VIN + 0.3 V(2)
Reset delay input, power-good adjustable threshold
Power-good outupt
–0.3
–0.3
–40
–65
6
20
V
V
TJ
Operating junction temperature
Storage temperature
150
150
°C
°C
Tstg
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. Theseare stress ratings
only and functional operation of the device at these or any other conditionsbeyond those indicated under recommended operating
conditions isnot implied. Exposure to absolute-maximum-rated conditions for extended periods may affect devicereliability.
(2) The absolute maximum rating is VIN + 0.3 V or 20 V, whichever is smaller
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per AEC Q100-002(1)
V(ESD)
Electrostatic discharge
All pins
Corner pins
V
Charged-device model (CDM), per AEC
Q100-011
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordancewith the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3
TYP
MAX
40
UNIT
VIN
Input voltage
V
V
VOUT
IOUT
VDelay
VPG
Output voltage
1.2
0
18
Output current
500
5.5
18
mA
V
Delay pin voltage, power-good adjustable threshold
Power-good outupt pin
Output capacitor(2)
0
0
V
COUT
ESR
CIN
2.2
0.001
0.1
220
2
µF
Ω
Output capacitor ESR requirements
Input capacitor(1)
1
µF
µF
°C
CDelay
TJ
Power-good delay capacitor
Operating junction temperature
1
–40
150
(1) For robust EMI performance the minimum input capacitance is 500 nF.
(2) Effective output capacitance of 1 µF minimum required for stability.
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6.4 Thermal Information
TPS7B87-Q1
THERMAL METRIC(1) (2)
KVU
5 PINS
29.7
40.2
8.6
DDA
8 PINS
41.8
55
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
RθJB
ψJT
Junction-to-board thermal resistance
17.3
4.5
Junction-to-top characterization parameter
Junction-to-board characterization parameter
2.9
ψJB
8.5
17.3
5.7
RθJC(bot) Junction-to-case (bottom) thermal resistance
1.5
(1) The thermal data is based on the JEDEC standard high K profile,JESD 51-7. Two-signal, two-plane, four-layer board with 2-oz. copper.
The copper pad is soldered tothe thermal land pattern. Also, correct attachment procedure must be incorporated.
(2) For more information about traditional and new thermal metrics,see the Semiconductor and IC PackageThermal Metrics application
report.
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6.5 Electrical Characteristics
specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 0 mA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, CIN = 1 µF typical
values are at TJ = 25°C
PARAMETER
Test Conditions
MIN TYP MAX UNIT
VIN = VOUT + 1 V to 40 V, IOUT = 100 µA to 450 mA, TJ =
25ºC(1)
–0.85
0.85
0.85
VIN = VOUT + 1 V to 40 V, IOUT = 100 µA to 500 mA, TJ =
25ºC(1)
–0.85
VOUT
Regulated output
%
%
VIN = VOUT + 1 V to 40 V, IOUT = 100 µA to 450 mA(1)
VIN = VOUT + 1 V to 40 V, IOUT = 100 µA to 500 mA(1)
–1.15
–1.15
1.15
1.15
VIN = VOUT + 1 V, IOUT = 100 µA to 450 mA , VOUT ≥ 3.3
V
0.425
ΔVOUT(ΔIOUT)
Load regulation
Line regulation
VIN = VOUT + 1 V, IOUT = 100 µA to 500 mA , VOUT ≥ 3.3
V
0.45
0.2
ΔVOUT(ΔVIN)
ΔVOUT
VIN = VOUT + 1 V to 40 V, IOUT = 100 µA
tR = tF = 1 µs; COUT = 10 µF, VOUT ≥ 3.3V
IOUT = 150 mA to 350 mA
%
Load transient response
settling time
100
µs
–2%
Load transient response
overshoot, undershoot(2)
tR = tF = 1 µs; COUT
10 µF
=
ΔVOUT
IOUT = 350 mA to 150 mA
IOUT = 0 mA to 500 mA
10% %VOUT
–10%
VIN = VOUT + 1 V to 40V, IOUT = 0 mA, TJ = 25ºC(3)
VIN = VOUT + 1 V to 40 V, IOUT = 0 mA(3)
IOUT = 500 µA
17
21
IQ
Quiescent current
26
35
µA
IOUT ≤ 1 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM) x 0.95
IOUT = 315 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM)
IOUT = 450 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM)
IOUT = 500 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM)
IOUT ≤ 1 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM) x 0.95
IOUT = 315 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM)
IOUT = 450 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM)
IOUT = 500 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM)
VIN rising
43
260
335
360
360
475
535
46
Dropout voltage fixed output
voltages (DDA Package)
VDO
mV
275
360
390
400
525
575
Dropout voltage fixed output
voltages (KVU Package)
VDO
mV
VUVLO(RISING)
VUVLO(FALLING)
VUVLO(HYST)
ICL
Rising input supply UVLO
Falling input supply UVLO
V UVLO(IN) hysteresis
2.6
2.7 2.82
V
VIN falling
2.38
2.5
2.6
V
230
mV
mA
dB
Output current limit
VIN = VOUT + 1 V, VOUT short to 90% x VOUT(NOM)
VIN - VOUT = 1 V, frequency = 1 kHz, IOUT = 450 mA
540
10
780
PSRR
Power supply rejection ratio
70
30
Power-good internal pull up
resistor
RPG
50
kΩ
V
VPG(OL)
PG pin low level output voltage VOUT ≤ 0.83 x VOUT
Default power-good threshold VOUT rising
0.4
95
VPG(TH,RISING)
85
83
VPG(TH,FALLING) Default power-good threshold VOUT falling
93 %VOUT
VPG(HYST)
VDLY(TH)
IDLY(CHARGE)
TJ
Power-good hysteresis
2
Threshold to release power-
good high
Voltage at DELAY pin rising
Voltage at DELAY pin = 1 V
1.17 1.21 1.25
V
Delay capacitor charging
current
1
1.5
2
µA
°C
°C
Junction temperature
–40
150
Junction shutdown
temperature
TSD(SHUTDOWN)
175
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6.5 Electrical Characteristics (continued)
specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 0 mA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, CIN = 1 µF typical
values are at TJ = 25°C
PARAMETER
Test Conditions
MIN TYP MAX UNIT
Hysteresis of thermal
shutdown
TSD(HYST)
20 °C
(1) Power dissipation is limited to 2 W for device production testing purposes. The power dissipation can be higher during normal
operation. See the thermal dissipation section for more information on how much power the device can dissipate while maintaining a
junction temperature below 150℃.
(2) Specified by design.
(3) For the adjustable output this is tested in unity gain and resistor current is not included.
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
TIMING POWER-GOOD
t(DLY_FIX)
t(Deglitch)
Power-good propagation delay
Power-good deglitch time
No capacitor connect at DELAY pin
No capacitor connect at DELAY pin
100
90
µs
µs
Delay capacitor value:
C(DELAY) = 100 nF
t(DLY)
Power-good propagation delay
80
ms
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6.7 Typical Characteristics
specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 100 µA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, and CIN = 1 µF
(unless otherwise noted)
0.3
0.25
0.2
5.015
5.01
5.005
5
500 mA
100 mA
-55èC
-40èC
0èC
85èC
150èC
25èC
125èC
0.15
0.1
0.05
0
4.995
4.99
4.985
4.98
4.975
-0.05
-0.1
-0.15
-0.2
-0.25
-0.3
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature èC
5
10
15
20 25
Input Voltage (V)
30
35
40
VOUT = 5 V, IOUT = 150 mA
Figure 6-2. Line Regulation vs VIN
Figure 6-1. Accuracy vs Temperature
5.015
5.015
5.01
5.005
5
-55èC
-40èC
0èC
25èC
85èC
125èC
150èC
-55èC
-40èC
0èC
25èC
85èC
125èC
150èC
5.01
5.005
5
4.995
4.99
4.985
4.98
4.975
4.995
4.99
4.985
4.98
4.975
5
10
15
20 25
Input Voltage (V)
30
35
40
5
10
15
20 25
Input Voltage (V)
30
35
40
VOUT = 5 V, IOUT = 5 mA
Figure 6-3. Line Regulation vs VIN
VOUT = 5 V, IOUT = 1 mA
Figure 6-4. Line Regulation vs VIN
5.015
5.01
5.005
5
5.01
5.0075
5.005
5.0025
5
-55èC
-40èC
0èC
85èC
150èC
-40 èC
25 èC
85 èC
25èC
125èC
4.995
4.99
4.985
4.98
4.975
4.9975
4.995
4.9925
4.99
0
25
50 75
Output Current (mA)
100
125
150
0
5
10
15
20
25
Input Voltage (V)
30
35
40
VOUT = 5 V
Figure 6-5. Load Regulation vs IOUT
COUT = 10 µF, VOUT = 5 V
Figure 6-6. Line Regulation at 50 mA
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6.7 Typical Characteristics (continued)
specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 100 µA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, and CIN = 1 µF
(unless otherwise noted)
5.01
5.0075
5.005
5.0025
5
550
500
450
400
350
300
250
200
150
100
50
-40 èC
25 èC
85 èC
-55 èC
-40 èC
0 èC
25 èC
85 èC
125 èC
150 èC
4.9975
4.995
4.9925
4.99
0
0
50 100 150 200 250 300 350 400 450 500
Output Current (mA)
0
5
10
15
20
25
Input Voltage (V)
30
35
40
VIN = 3 V
COUT = 10 µF, VOUT = 5 V
Figure 6-7. Line Regulation at 100 mA
Figure 6-8. Dropout Voltage (VDO) vs IOUT
90
80
70
60
50
40
30
20
10
10
5
2
1
0.5
0.2
0.1
0.05
0.02
0.01
IOUT
10 mA, 364.8 mVRMS
150 mA, 391.4 mVRMS
500 mA, 437.2 mVRMS
0.005
1 mA
10 mA
50 mA
150 mA
350 mA
500 mA
0.002
0.001
0
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
COUT = 10 µF (X7R 50 V), VOUT = 5 V
COUT = 10 µF (X7R 50 V), VOUT = 5 V
Figure 6-9. PSRR vs Frequency and IOUT
Figure 6-10. Noise vs Frequency
10
5
80
70
60
50
40
30
20
10
0
2
1
0.5
0.2
0.1
0.05
0.02
0.01
IOUT
10 mA, 252.5 mVRMS
150 mA, 267.6 mVRMS
500 mA, 293.8 mVRMS
0.005
0.002
0.001
6 V VIN
100
7 V VIN
10 VIN
13.5 V VIN
1M 10M
10
1k
10k
Frequency (Hz)
100k
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
COUT = 10 µF (X7R 50 V), IOUT = 500 mA, VOUT = 5 V
COUT = 10 µF (X7R 50 V), VOUT = 3.3 V
Figure 6-12. PSRR vs Frequency and VIN
Figure 6-11. Noise vs Frequency
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6.7 Typical Characteristics (continued)
specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 100 µA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, and CIN = 1 µF
(unless otherwise noted)
45
40
35
30
25
20
15
10
5
0.25
0.2
10
8
300
240
180
120
60
VIN
VOUT
VIN
VOUT
6
0.15
0.1
4
2
0.05
0
0
0
-2
-4
-6
-8
-10
-60
-0.05
-0.1
-0.15
-0.2
-120
-180
-240
-300
0
0
50 100 150 200 250 300 350 400 450 500
Time (ms)
0
500
1000
1500
Time (ms)
2000
2500
3000
VOUT = 5 V, IOUT = 100 mA, VIN = 5.5 V to 6.5 V,
rise time = 1 µs
VOUT = 5 V, IOUT = 1 mA, VIN = 13.5 V to 45 V,
slew rate = 2.7 V/µs
Figure 6-14. Line Transients
Figure 6-13. Line Transients
150
100
50
300
200
100
0
150
300
200
100
0
-40èC
25èC
150èC
IOUT
-40èC
25èC
150èC
IOUT
100
50
0
0
-50
-100
-150
-100
-200
-300
-50
-100
-150
-100
-200
-300
0
0.5
1
1.5
2
2.5
Time (ms)
3
3.5
4
4.5
5
0
20
40
60
80 100 120 140 160 180 200
Time (ms)
VOUT = 5 V, IOUT = 0 mA to 100 mA, slew rate = 1 A/µs,
COUT = 10 µF
VOUT = 5 V, IOUT = 0 mA to 100 mA, slew rate = 1 A/µs,
COUT = 10 µF
Figure 6-15. Load Transient, No Load to 100 mA
Figure 6-16. Load Transient, No Load to 100-mA Rising Edge
50
40
300
240
180
120
60
50
40
30
20
10
0
200
150
100
50
-40èC
25èC
150èC
IOUT
-40èC
25èC
150èC
IOUT
30
20
10
0
0
0
-50
-10
-20
-30
-40
-50
-60
-10
-20
-30
-40
-100
-150
-200
-250
-120
-180
-240
-300
0
40
80
120
Time (ms)
160
200
240
280
0
20
40
60
80 100 120 140 160 180 200
Time (ms)
VOUT = 5 V, IOUT = 45 mA to 105 mA, slew rate = 0.1 A/µs,
COUT = 10 µF
VOUT = 5 V, IOUT = 45 mA to 105 mA, slew rate = 0.1 A/µs,
COUT = 10 µF
Figure 6-17. Load Transient, 45 mA to 105 mA
Figure 6-18. Load Transient, 45-mA to 105-mA Rising Edge
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6.7 Typical Characteristics (continued)
specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 100 µA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, and CIN = 1 µF
(unless otherwise noted)
150
100
50
300
200
100
0
150
100
50
300
200
100
0
-40èC
25èC
150èC
IOUT
-40èC
25èC
150èC
IOUT
0
0
-50
-100
-150
-100
-200
-300
-50
-100
-150
-100
-200
-300
0
0.25
0.5
0.75
1
Time (ms)
1.25
1.5
1.75
2
0
20
40
60
80 100 120 140 160 180 200
Time (ms)
VOUT = 5 V, IOUT = 0 mA to 150 mA, slew rate = 1 A/µs,
COUT = 10 µF
VOUT = 5 V, IOUT = 0 mA to 150 mA, slew rate = 1 A/µs,
COUT = 10 µF
Figure 6-19. Load Transient, No Load to 150-mA
Figure 6-20. Load Transient, No Load to 150-mA Rising Edge
150
600
500
400
300
200
100
0
300
250
200
150
100
50
600
500
400
300
200
100
0
-40èC
25èC
150èC
IOUT
-40èC
25èC
150èC
IOUT
100
50
0
0
-50
-100
-200
-300
-400
-500
-600
-100
-150
-200
-250
-300
-50
-100
-150
0
0.5
1
1.5
2
2.5
Time (ms)
3
3.5
4
4.5
5
0
25
50
75 100 125 150 175 200 225 250
Time (ms)
VOUT = 5 V, IOUT = 0 mA to 500 mA, slew rate = 1 A/µs,
COUT = 10 µF
VOUT = 5 V, IOUT = 150 mA to 350 mA, slew rate = 0.1 A/µs,
COUT = 10 µF
Figure 6-22. Load Transient, No Load to 500 mA
660
Figure 6-21. Load Transient, 150-mA to 350-mA
150
100
50
900
-40èC
25èC
150èC
IOUT
659
658
657
656
655
654
653
652
651
650
750
600
450
300
150
0
0
-50
-100
-150
-200
-250
-150
-300
0
20
40
60
80 100 120 140 160 180 200
Time (ms)
Current Limit
105 135
-75
-45
-15
15
45
75
VOUT = 5 V, IOUT = 0 mA to 500 mA, slew rate = 1 A/µs,
COUT = 10 µF
Temperature (èC)
VIN = VOUT + 1 V, VOUT = 90% × VOUT(NOM)
Figure 6-24. Output Current Limit vs Temperature
Figure 6-23. Load Transient, No Load to 500-mA Rising Edge
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6.7 Typical Characteristics (continued)
specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 100 µA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, and CIN = 1 µF
(unless otherwise noted)
40
35
30
25
20
15
10
175
150
125
100
75
-55èC
-40èC
0èC
25èC
85èC
125èC
150èC
-55èC
-40èC
0èC
25èC
85èC
125èC
150èC
50
25
0
5
10
15
20 25
Input Voltage (V)
30
35
40
0
5
10
15
Input Voltage (V)
20
25
30
35
40
VOUT = 5 V
Figure 6-26. Quiescent Current (IQ) vs VIN
Figure 6-25. Quiescent Current (IQ) vs VIN
1300
281
280
279
278
277
276
275
274
273
272
271
-55 èC
-40 èC
0 èC
25 èC
85 èC
125 èC
150 èC
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
0
50 100 150 200 250 300 350 400 450 500
Output Current (mA)
-75
-50
-25
0
25
50
75
100 125 150
Temperature (èC)
Figure 6-27. Ground Current (IGND) vs IOUT
Figure 6-28. Ground Current at 100 mA
Falling Threshold
Rising Threshold
26
25
24
23
22
21
92
91
90
89
88
87
-75
-50
-25
0
25
50
75
100 125 150
Ambient Temperature (èC)
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature (èC)
Figure 6-30. PG Threshold vs Temperature
Figure 6-29. Ground Current at 500 µA
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6.7 Typical Characteristics (continued)
specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 100 µA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, and CIN = 1 µF
(unless otherwise noted)
20
17.5
15
900
800
700
600
500
400
300
200
100
0
2.8
2.75
2.7
Input Voltage
Output Voltage
Output Current
Falling Threshold
Rising Threshold
12.5
10
2.65
2.6
7.5
5
2.55
2.5
2.5
0
-2.5
-5
2.45
2.4
-100
0
250 500 750 1000 1250 1500 1750 2000 2250 2500
Time (ms)
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature (èC)
VIN = 13.5 V, VOUT = 5 V, IOUT = 150 mA, COUT = 10 µF
Figure 6-32. Undervoltage Lockout (UVLO) Threshold vs
Temperature
Figure 6-31. Startup Plot Inrush Current
1.58
1.57
1.56
1.55
1.54
1.53
1.52
20
18
16
14
12
10
8
6
4
0.2
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature èC
0.4
0.6
0.8
1
1.2
Injected current (mA)
1.4
1.6
1.8
VDELAY = 1 V
Figure 6-33. Delay Pin Current vs Temperature
Figure 6-34. Output Voltage vs Injected Current
10
5
2
1
OFF
0.5
0.2
0.1
0.05
Stable region
0.02
0.01
0.005
ON
0.002
0.001
0.0005
0.0002
0.0001
-50 -25
0
25
50
75 100 125 150 175 200
Temperature (èC)
1
2
3
4 5 67810
20 30 50 70 100 200300 500
COUT (mF)
Figure 6-35. Thermal Shutdown
Figure 6-36. Stability, ESR vs COUT
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7 Detailed Description
7.1 Overview
The TPS7B87-Q1 is a low-dropout linear regulator (LDO) with improved transient performance that allows
for quick response to changes in line or load conditions. The device aslo features a novel output overshoot
reduction feature that minimizes output overshoot during cold-crank conditions.
The integrated power-good and delay features allow for the system to notify down-stream components when the
power is good and assist in sequencing requirements.
During normal operation, the device has a tight DC accuracy of ±0.85% over line, load, and temperature. The
increased accuracy allows for the powering of sensitive analog loads or sensors.
7.2 Functional Block Diagram
IN
OUT
Current
Limit
R1
Thermal
Shutdown
œ
+
UVLO
R2
Bandgap
œ
+
VREF
VOUT
VSUBREG
PG
DELAY
œ
VREF
+
Cap
Control
GND
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7.3 Feature Description
7.3.1 Power-Good (PG)
The PG signal provides an easy solution to meet demanding sequencing requirements because PG alerts when
the output nears its nominal value. PG can be used to signal other devices in a system when the output voltage
is near, at, or above the set output voltage (VOUT(nom)). Figure 7-1 shows a simplified schematic. The PG signal
is an internal pullup resistor to the nominal output voltage and is active high. The PG circuit sets the PG pin into
a high-impedance state to indicate that the power is good.
OUT
-
+
PG
+
VREF
œ
Figure 7-1. Simplified Power-Good Schematic
7.3.2 Adjustable Power-Good Delay Timer (DELAY)
The power-good delay period is a function of the external capacitor on the DELAY pin. The adjustable delay
configures the amount of time required before the PG pin becomes high. This delay is configured by connecting
an external capacitor from this pin to GND. Figure 7-2 shows the typical timing diagram for the power-good delay
pin. If the DELAY pin is left floating, the power-good delay is t(DLY_FIX). For more information on how to program
the PG delay, see the Setting the Adjustable Power-Good Delay section.
VIN
V
(UVLO)
t < t(DEGLITCH)
V(PG_HYST)
V(PG_TH) rising
V(PG_ADJ) rising
V(PG_TH) falling
V(PG_ADJ) falling
VOUT
V
(DLY_TH)
DELAY
t(DEGLITCH)
t(DEGLITCH)
t
t
(DLY)
(DLY)
PG
Power Up
V(PG_TH) falling = V(PG_TH) rising – V(PG_HYST).
Input Voltage Drop
Undervoltage
Power Down
.
Figure 7-2. Typical Power-Good Timing Diagram
7.3.3 Undervoltage Lockout
The device has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a
controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input
drops during turn on, the UVLO has hysteresis as specified in the Electrical Characteristics table.
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7.3.4 Thermal Shutdown
The device contains a thermal shutdown protection circuit to disable the device when the junction temperature
(TJ) of the pass transistor rises to TSD(shutdown) (typical). Thermal shutdown hysteresis assures that the device
resets (turns on) when the temperature falls to TSD(reset) (typical).
The thermal time-constant of the semiconductor die is fairly short, thus the device may cycle on and off
when thermal shutdown is reached until power dissipation is reduced. Power dissipation during startup can
be high from large VIN – VOUT voltage drops across the device or from high inrush currents charging large
output capacitors. Under some conditions, the thermal shutdown protection disables the device before startup
completes.
For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating
Conditions table. Operation above this maximum temperature causes the device to exceed its operational
specifications. Although the internal protection circuitry of the device is designed to protect against thermal
overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device
into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability.
7.3.5 Current Limit
The device has an internal current limit circuit that protects the regulator during transient high-load current faults
or shorting events. The current limit is a brickwall scheme. In a high-load current fault, the brickwall scheme
limits the output current to the current limit (ICL). ICL is listed in the Electrical Characteristics table.
The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the
device begins to heat up because of the increase in power dissipation. When the device is in brickwall current
limit, the pass transistor dissipates power [(VIN – VOUT) × ICL]. If thermal shutdown is triggered, the device
turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If the
output current fault condition continues, the device cycles between current limit and thermal shutdown. For more
information on current limits, see the Know Your Limits application report.
Figure 7-3 shows a diagram of the current limit.
VOUT
Brickwall
VOUT(NOM)
0 V
IOUT
IRATED
0 mA
ICL
Figure 7-3. Current Limit
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7.4 Device Functional Modes
7.4.1 Device Functional Mode Comparison
The Device Functional Mode Comparison table shows the conditions that lead to the different modes of
operation. See the Electrical Characteristics table for parameter values.
Table 7-1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN
IOUT
TJ
Normal operation
Dropout operation
VIN > VOUT(nom) + VDO and VIN > VIN(min)
VIN(min) < VIN < VOUT(nom) + VDO
IOUT < IOUT(max)
IOUT < IOUT(max)
TJ < TSD(shutdown)
TJ < TSD(shutdown)
Disabled
(any true condition
disables the device)
VIN < VUVLO
Not applicable
TJ > TSD(shutdown)
7.4.2 Normal Operation
The device regulates to the nominal output voltage when the following conditions are met:
•
•
•
The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO)
The output current is less than the current limit (IOUT < ICL)
The device junction temperature is less than the thermal shutdown temperature (TJ < TSD
)
7.4.3 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage
tracks the input voltage. During this mode, the transient performance of the device becomes significantly
degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load
transients in dropout can result in large output-voltage deviations.
When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO
,
directly after being in a normal regulation state, but not during startup), the pass transistor is driven into the
ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output
voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time
while the device pulls the pass transistor back into the linear region.
7.4.4 Disabled
The output of the device can be shutdown by forcing the input voltage below the UVLO falling threshold (see
the Electrical Characteristics table). When disabled, the pass transistor is turned off and internal circuits are
shutdown.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
8.1.1 Input and Output Capacitor Selection
The TPS7B87-Q1 requires an output capacitor of 2.2 µF or larger (1 µF or larger capacitance) for stability
and an equivalent series resistance (ESR) between 0.001 Ω and 2 Ω. For best transient performance, use
X5R- and X7R-type ceramic capacitors because these capacitors have minimal variation in value and ESR over
temperature. When choosing a capacitor for a specific application, be mindful of the DC bias characteristics for
the capacitor. Higher output voltages cause a significant derating of the capacitor. For best performance, the
maximum recommended output capacitance is 220 µF.
Although an input capacitor is not required for stability, good analog design practice is to connect a capacitor
from IN to GND. Some input supplies have a high impedance, thus placing the input capacitor on the input
supply helps reduce the input impedance. This capacitor counteracts reactive input sources and improves
transient response, input ripple, and PSRR. If the input supply has a high impedance over a large range of
frequencies, several input capacitors can be used in parallel to lower the impedance over frequency. Use a
higher-value capacitor if large, fast, rise-time load transients are anticipated, or if the device is located several
inches from the input power source.
8.1.2 Dropout Voltage
Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output
current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the Recommended
Operating Conditions table. The pass transistor is in the ohmic or triode region of operation, and acts as a
switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed
output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than
the nominal output regulation, then the output voltage falls as well.
For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the
pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for
that current scales accordingly. The following equation calculates the RDS(ON) of the device.
VDO
RDS(ON)
=
IRATED
(1)
8.1.3 Reverse Current
Excessive reverse current can damage this device. Reverse current flows through the intrinsic body diode of the
pass transistor instead of the normal conducting channel. At high magnitudes, this current flow degrades the
long-term reliability of the device.
Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute
maximum rating of VOUT ≤ VIN + 0.3 V.
•
•
•
If the device has a large COUT and the input supply collapses with little or no load current
The output is biased when the input supply is not established
The output is biased above the input supply
If reverse current flow is expected in the application, external protection is recommended to protect the device.
Reverse current is not limited in the device, so external limiting is required if extended reverse voltage operation
is anticipated.
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8.1.4 Power Dissipation (PD)
Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed
circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few
or no other heat-generating devices that cause added thermal stress.
To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference
and load conditions. The following equation calculates power dissipation (PD).
PD = (VIN – VOUT) × IOUT
(2)
Note
Power dissipation can be minimized, and therefore greater efficiency can be achieved, by correct
selection of the system voltage rails. For the lowest power dissipation use the minimum input voltage
required for correct output regulation.
For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal
pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an
array of plated vias that conduct heat to additional copper planes for increased heat dissipation.
The maximum power dissipation determines the maximum allowable ambient temperature (TA) for the device.
According to the following equation, power dissipation and junction temperature are most often related by the
junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of
the ambient air (TA).
TJ = TA + (RθJA × PD)
(3)
Thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB
design, and therefore varies according to the total copper area, copper weight, and location of the planes.
The junction-to-ambient thermal resistance listed in the Thermal Information table is determined by the JEDEC
standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance.
8.1.4.1 Thermal Performance Versus Copper Area
The most used thermal resistance parameter RθJA is highly dependent on the heat-spreading capability built into
the particular PCB design, and therefore varies according to the total copper area, copper weight, and location
of the planes. The RθJA recorded in the Thermal Information table in the Specifications section is determined
by the JEDEC standard (see Figure 8-1), PCB, and copper-spreading area, and is only used as a relative
measure of package thermal performance. For a well-designed thermal layout, RθJA is actually the sum of the
package junction-to-case (bottom) thermal resistance (RθJCbot) plus the thermal resistance contribution by the
PCB copper.
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Mold
Compound
Die
Wire
Die
Attach
2oz
Signal
Trace
Lead
Frame
Internal Signal
or power plane
1oz copper
Thermal
Pad or Tab
of the LDO
Internal
GND plane
1oz copper
Bottom
Relief
2oz copper
Thermal
Vias
Figure 8-1. JEDEC Standard 2s2p PCB
Figure 8-2 through Figure 8-5 illustrate the functions of RθJA and ψJB versus copper area and thickness. These
plots are generated with a 101.6-mm x 101.6-mm x 1.6-mm PCB of two and four layers. For the 4-layer board,
inner planes use 1-oz copper thickness. Outer layers are simulated with both 1-oz and 2-oz copper thickness.
A 2x3 (DDA package) or a 3x4 (KVU package) array of thermal vias with a 300-µm drill diameter and 25-µm
copper plating is located beneath the thermal pad of the device. The thermal vias connect the top layer, the
bottom layer and, in the case of the 4-layer board, the first inner GND plane. Each of the layers has a copper
plane of equal area.
105
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
22
21
20
19
18
17
16
15
14
13
12
11
4 Layer PCB, 1 oz copper
4 Layer PCB, 2 oz copper
2 Layer PCB, 1 oz copper
2 Layer PCB, 2 oz copper
4 Layer PCB, 1 oz copper
4 Layer PCB, 2 oz copper
2 Layer PCB, 1 oz copper
2 Layer PCB, 2 oz copper
0
10
20
30
40
50
60
70
80
90 100
0
10
20
30
40
50
60
70
80
90 100
Cu Area Per Layer (cm2)
Cu Area Per Layer (cm2)
Figure 8-2. RθJA vs Copper Area (DDA Package)
Figure 8-3. ψJB vs Copper Area (DDA Package)
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20
18
16
14
12
10
8
95
85
75
65
55
45
35
25
4 Layer PCB, 1 oz copper
4 Layer PCB, 2 oz copper
2 Layer PCB, 1 oz copper
2 Layer PCB, 2 oz copper
4 Layer PCB, 1 oz copper
4 Layer PCB, 2 oz copper
2 Layer PCB, 1 oz copper
2 Layer PCB, 2 oz copper
6
15
0
4
10
20
30
40
50
60
70
80
90 100
0
10
20
30
40
50
60
70
80
90 100
Cu Area Per Layer (cm2)
Cu Area Per Layer (cm2)
Figure 8-4. RθJA vs Copper Area (KVU Package)
Figure 8-5. ψJB vs Copper Area (KVU Package)
8.1.4.2 Power Dissipation Versus Ambient Temperature
Figure 8-6 is based off of a JESD51-7 4-layer, high-K board. The allowable power dissipation was estimated
using the following equation. As discussed in the An empirical analysis of the impact of board layout on LDO
thermal performance application report, thermal dissipation can be improved in the JEDEC high-K layout by
adding top layer copper and increasing the number of thermal vias. If a good thermal layout is used, the
allowable thermal dissipation can be improved by up to 50%.
6 + 4à,# T 2& Q 150 °%
#
(4)
6.5
KVU Package
DDA Package
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
-40
-20
0
20
40
60
80
100 120 140
Ambient Temerature (èC)
Figure 8-6. TPS7B87-Q1 Allowable Power Dissipation
8.1.5 Estimating Junction Temperature
The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures
of the linear regulator when in-circuit on a typical PCB board application. These metrics are not thermal
resistance parameters and instead offer a practical and relative way to estimate junction temperature. These
psi metrics are determined to be significantly independent of the copper area available for heat-spreading.
The Thermal Information table lists the primary thermal metrics, which are the junction-to-top characterization
parameter (ψJT) and junction-to-board characterization parameter (ψJB). These parameters provide two methods
for calculating the junction temperature (TJ), as described in the following equations. Use the junction-to-top
characterization parameter (ψJT) with the temperature at the center-top of device package (TT) to calculate
the junction temperature. Use the junction-to-board characterization parameter (ψJB) with the PCB surface
temperature 1 mm from the device package (TB) to calculate the junction temperature.
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TJ = TT + ψJT × PD
where:
(5)
•
•
PD is the dissipated power
TT is the temperature at the center-top of the device package
TJ = TB + ψJB × PD
(6)
where
TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge
•
For detailed information on the thermal metrics and how to use them, see the Semiconductor and IC Package
Thermal Metrics application report.
8.1.6 Pulling Up the PG Pin to a Different Voltage
Because the power-good (PG) pin is pulled up internally to the output rail, this pin cannot be pulled up to any
voltage or wire AND'd like a typical open-drain PG output can be. If this signal must be pulled up to another logic
level then an external circuit can be implemented using a PMOS transistor and a pullup resistor. Implementing
the circuit shown in Figure 8-7 allows the outputs to be pulled up to any logic rail. If a PMOS transistor is used
make sure to pick a transistor with a low threshold voltage as this will determine the output low voltage. this can
also be done with a NMOS transistor, but it inverts the logic. This implementation also allows the outputs to be
AND'd together like the traditional power-good pins.
SENSE_OUT
Figure 8-7. Additional Components for the PG Pin to be Pulled Up to Another Rail
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8.1.7 Power-Good
8.1.7.1 Setting the Adjustable Power-Good Delay
The power-good delay time can be set in two ways: either by floating the DELAY pin or by connecting a
capacitor from this pin to GND. When the DELAY pin is floating, the time defaults to t(DLY_FIX). The delay time is
set by the following equation if a capacitor is connected between the DELAY pin and GND.
≈
’
VDLY(TH)
t = t(DLY _FIX) + CDELAY
∆
∆
«
÷
÷
◊
IDLY(CHARGE)
(7)
8.2 Typical Application
Figure 8-8 shows a typical application circuit for the TPS7B87-Q1. TI recommends a low-ESR ceramic capacitor
with a dielectric of type X5R or X7R.
IN
OUT
TPS7B87-Q1
DELAY
PG
I/O
GND
Figure 8-8. Typical Application Schematic for the TPS7B87-Q1
8.2.1 Design Requirements
For this design example, use the parameters listed in Table 8-1 as the input parameters.
Table 8-1. Design Parameters
DESIGN PARAMETER
Input voltage range
Output voltage
EXAMPLE VALUE
6 V to 40 V
5 V
Output current
350 mA
10 µF
Output capacitor
Power-good delay capacitor
100 nF
8.2.2 Detailed Design Procedure
8.2.2.1 Input Capacitor
The device requires an input decoupling capacitor, the value of which depends on the application. The typical
recommended value for the decoupling capacitor is 1 µF. The voltage rating must be greater than the maximum
input voltage.
8.2.2.2 Output Capacitor
The device requires an output capacitor to stabilize the output voltage. The capacitor value must be between
2.2 µF and 200 µF and the ESR range must be between 1 mΩ and 2 Ω. For this design, a low ESR, 10-µF
ceramic capacitor was used to improve transient performance.
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8.2.3 Application Curves
150
100
50
600
500
90
80
70
60
50
40
30
20
-40èC
25èC
150èC
IOUT
400
300
200
100
0
0
-50
-100
-150
1 mA
10 mA
50 mA
150 mA
350 mA
500 mA
10
0
25
50
75 100 125 150 175 200 225 250
Time (ms)
0
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
Figure 8-10. Transient Response
Figure 8-9. PSRR
9 Power Supply Recommendations
This device is designed for operation from an input voltage supply with a range between 3 V and 40 V. This input
supply must be well regulated. If the input supply is located more than a few inches from the TPS7B87-Q1, add
an electrolytic capacitor with a value of 22 µF and a ceramic bypass capacitor at the input.
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10 Layout
10.1 Layout Guidelines
For best overall performance, place all circuit components on the same side of the circuit board and as near
as practical to the respective LDO pin connections. Place ground return connections to the input and output
capacitor, and to the LDO ground pin as close as possible to each other, connected by a wide, component-side,
copper surface. The use of vias and long traces to the input and output capacitors is strongly discouraged and
negatively affects system performance. TI also recommends a ground reference plane either embedded in the
PCB itself or located on the bottom side of the PCB opposite the components. This reference plane serves
to assure accuracy of the output voltage, shield noise, and behaves similarly to a thermal plane to spread (or
sink) heat from the LDO device when connected to the thermal pad. In most applications, this ground plane is
necessary to meet thermal requirements.
10.1.1 Package Mounting
Solder pad footprint recommendations for the TPS7B87-Q1 are available at the end of this document and at
www.ti.com.
10.1.2 Board Layout Recommendations to Improve PSRR and Noise Performance
As depicted in Figure 10-1 and Figure 10-2, place the input and output capacitors close to the device for the
layout of the TPS7B87-Q1. In order to enhance the thermal performance, place as many vias as possible around
the device. These vias improve the heat transfer between the different GND planes in the PCB.
To improve AC performance such as PSRR, output noise, and transient response, TI recommends a board
design with separate ground planes for VIN and VOUT, with each ground plane connected only at the GND pin of
the device. In addition, the ground connection for the output capacitor must connect directly to the GND pin of
the device.
Minimize equivalent series inductance (ESL) and ESR in order to maximize performance and ensure stability.
Place each capacitor as close as possible to the device and on the same side of the PCB as the regulator itself.
Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. TI
strongly discourages the use of vias and long traces to connect the capacitors because may negatively affect
system performance and even cause instability.
If possible, and to ensure the maximum performance specified in this document, use the same layout pattern
used for the TPS7B87-Q1 evaluation board, available at www.ti.com.
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10.2 Layout Examples
GND
Denotes a via
Figure 10-1. DDA Package Fixed Output
Denotes a via
Figure 10-2. KVU Package Fixed Outupt
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Nomenclature
Table 11-1. Device Nomenclature(1)
PRODUCT
VOUT
xx is the nominal output voltage (for example, 33 = 3.3 V V; 50 = 5.0 V).
yyy is the package designator.
Q indicates that this device is a grade-1 device in accordance with the AEC-Q100 standard.
Q1 indicates that this device is an automotive grade (AEC-Q100) device.
TPS7B87xxQyyyRQ1
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder on www.ti.com.
11.1.2 Development Support
For the PSpice model, see the TPS7B4250 PSpice Transient Model.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
•
•
•
Texas Instruments, Various Applications for Voltage-Tracking LDO application report
Texas Instruments, TPS7B4250 Evaluation Module user's guide
Texas Instruments, TPS7B5250-Q1 Pin FMEA application report
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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29-Jul-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS7B8733QDDARQ1
TPS7B8733QKVURQ1
TPS7B8733QKVURQ1R2
TPS7B8750QDDARQ1
TPS7B8750QKVURQ1
TPS7B8750QKVURQ1R2
ACTIVE SO PowerPAD
DDA
KVU
KVU
DDA
KVU
KVU
8
5
5
8
5
5
2500 RoHS & Green
2500 RoHS & Green
2500 RoHS & Green
2500 RoHS & Green
2500 RoHS & Green
2500 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-2-260C-1 YEAR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
7B8733
ACTIVE
ACTIVE
TO-252
TO-252
SN
SN
7B8733
7B8733
7B8750
7B8750
7B8750
ACTIVE SO PowerPAD
NIPDAUAG
SN
ACTIVE
ACTIVE
TO-252
TO-252
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jul-2021
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jul-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS7B8733QDDARQ1
SO
Power
PAD
DDA
8
2500
330.0
12.8
6.4
5.2
2.1
8.0
12.0
Q1
TPS7B8733QKVURQ1R2 TO-252
KVU
DDA
5
8
2500
2500
330.0
330.0
16.4
12.8
6.9
6.4
10.5
5.2
2.7
2.1
8.0
8.0
16.0
12.0
Q2
Q1
TPS7B8750QDDARQ1
SO
Power
PAD
TPS7B8750QKVURQ1R2 TO-252
KVU
5
2500
330.0
16.4
6.9
10.5
2.7
8.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jul-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS7B8733QDDARQ1
TPS7B8733QKVURQ1R2
TPS7B8750QDDARQ1
TPS7B8750QKVURQ1R2
SO PowerPAD
TO-252
DDA
KVU
DDA
KVU
8
5
8
5
2500
2500
2500
2500
366.0
340.0
366.0
340.0
364.0
340.0
364.0
340.0
50.0
38.0
50.0
38.0
SO PowerPAD
TO-252
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DDA 8
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4202561/G
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