TPS7B8833QKVURQ1R2 [TI]

TPS7B88-Q1 500-mA, 40-V, Low-Dropout Regulator;


型号：	TPS7B8833QKVURQ1R2
厂家：	TEXAS INSTRUMENTS
描述：	TPS7B88-Q1 500-mA, 40-V, Low-Dropout Regulator
文件：	总31页 (文件大小：3161K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS7B88-Q1

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SBVS377 – JANUARY 2021

TPS7B88-Q1 500-mA, 40-V, Low-Dropout Regulator

1 Features

3 Description

•

AEC-Q100 qualified for automotive applications:

The TPS7B88-Q1 is a low-dropout linear regulator

designed to connect to the battery in automotive

applications. The device has an input voltage range

extending to 40 V, which allows the device to

withstand transients (such as load dump) that are

anticipated in automotive systems. With only a 17-µA

quiescent current at light loads, the device is an

optimal solution for powering always-on components

such as microcontrollers (MCUs) and controller area

network (CAN) transceivers in standby systems.

– Temperature grade 1: –40°C to +125°C, T_A

– Junction temperature: –40°C to +150°C, T_J

Input voltage range: 3 V to 40 V (42 V max)

Output voltage range: 3.3 V and 5 V (fixed)

Maximum output current: 500 mA

Output voltage accuracy: ±1.15% (max)

Low dropout voltage:

•

– 525 mV (max) at 450 mA

•

Low quiescent current:

– 17 µA (typ) at light loads

Excellent line transient response:

– ±2% V_OUTdeviation during cold-crank

– ±2% V_OUTdeviation (1-V/µs V_INslew rate)

Stable with a 2.2-µF or larger capacitor

Package 3-pin TO-252: (R_θJA): 30°C/W

The device has state-of-the-art transient response

that allows the output to quickly react to changes in

load or line (for example, during cold-crank

conditions). Additionally, the device has a novel

architecture that minimizes output overshoot when

recovering from dropout. During normal operation, the

device has a tight DC accuracy of ±1.15% over line,

load, and temperature.

•

2 Applications

The device is available in thermally conductive

packaging to allow the parts to efficiently transfer heat

to the circuit board.

•

Reconfigurable instrument clusters

Body control modules (BCM)

Always-on battery-connected applications:

– Automotive gateways

Device Information ⁽¹⁾

PART NUMBER

PACKAGE

BODY SIZE (NOM)

– Remote keyless entries (RKE)

TPS7B88-Q1

TO-252 (3)

6.60 mm × 6.10 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

0.25

0.2

OUT

V_IN

V_OUT

TPS7B88-Q1

GND

0.15

0.1

0.05

Output Equal to Reference Voltage

-0.05

-0.1

-0.15

-0.2

500

1000

1500

Time (ms)

2000

2500

3000

Line Transient Response (3-V/µs V_INSlew Rate)

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

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Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings ....................................... 4

6.2 ESD Ratings .............................................................. 4

6.3 Recommended Operating Conditions ........................4

6.4 Thermal Information ...................................................4

6.5 Electrical Characteristics ............................................5

6.6 Typical Characteristics................................................6

7 Detailed Description......................................................12

7.1 Overview...................................................................12

7.2 Functional Block Diagram.........................................12

7.3 Feature Description...................................................12

7.4 Device Functional Modes..........................................14

8 Application and Implementation..................................15

8.1 Application Information............................................. 15

8.2 Typical Application.................................................... 17

9 Power Supply Recommendations................................19

10 Layout...........................................................................20

10.1 Layout Guidelines................................................... 20

10.2 Layout Example...................................................... 21

11 Device and Documentation Support..........................22

11.1 Device Support........................................................22

11.2 Documentation Support.......................................... 22

11.3 Receiving Notification of Documentation Updates..22

11.4 Support Resources................................................. 22

11.5 Trademarks............................................................. 22

11.6 Electrostatic Discharge Caution..............................22

11.7 Glossary..................................................................22

12 Mechanical, Packaging, and Orderable

Information.................................................................... 22

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

DATE

REVISION

NOTES

January 2021

Initial Release

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5 Pin Configuration and Functions

Thermal pad

Not to scale

Figure 5-1. KVU Package, 3-Pin TO-252, Top View

Table 5-1. Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NAME

GND

KVU

Ground pin. Connect this pin to the thermal pad with a low-impedance connection.

Input power-supply voltage pin. For best transient response and to minimize input

impedance, use the recommended value or larger ceramic capacitor from IN to ground as

listed in the Recommended Operating Conditions table and the Input Capacitor section.

Place the input capacitor as close to the input of the device as possible

Regulated output voltage pin. A capacitor is required from OUT to ground for stability. For

best transient response, use the nominal recommended value or larger ceramic capacitor

from OUT to ground; see the Recommended Operating Conditions table and the Output

Capacitor section. Place the output capacitor as close to output of the device as possible.

If using a high ESR capacitor, decouple the output with a 100-nF ceramic capacitor.

OUT

Thermal pad

Pad

—

Connect the thermal pad to a large area GND plane for improved thermal performance.

(1) I = input; O = output; P = power; G = ground.

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX UNIT

V_IN

Unregulated input

–0.3

V_OUT

T_J

Regulated output

–0.3 V_IN+ 0.3 V⁽²⁾

Operating junction temperature

Storage temperature

–40

–65

150

°C

T_stg

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. Theseare stress ratings

only and functional operation of the device at these or any other conditionsbeyond those indicated under recommended operating

conditions isnot implied. Exposure to absolute-maximum-rated conditions for extended periods may affect devicereliability.

(2) The absolute maximum rating is VIN + 0.3 V or 20 V, whichever is smaller

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

V_(ESD)

Electrostatic discharge

All pins

Corner pins

Charged-device model (CDM), per AEC

Q100-011

±750

(1) AEC Q100-002 indicates that HBM stressing shall be in accordancewith the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

TYP

MAX

UNIT

V_IN

Input voltage

V_OUT

I_OUT

C_OUT

ESR

C_IN

Output voltage

1.2

Output current

500

220

µF

Output capacitor⁽²⁾

2.2

0.001

0.1

–40

Output capacitor ESR requirements

Input capacitor⁽¹⁾

µF

°C

T_J

Operating junction temperature

150

(1) For robust EMI performance the minimum input capacitance is 500 nF.

(2) Effective output capacitance of 1 µF minimum required for stability.

6.4 Thermal Information

TPS7B88-Q1

THERMAL METRIC^{(1) (2)}

KVU

3 PINS

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

39.5

8.6

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

2.6

ψ_JB

8.6

R_θJC(bot)

1.3

(1) The thermal data is based on the JEDEC standard high K profile,JESD 51-7. Two-signal, two-plane, four-layer board with 2-oz. copper.

The copper pad is soldered tothe thermal land pattern. Also, correct attachment procedure must be incorporated.

(2) For more information about traditional and new thermal metrics,see the Semiconductor and IC PackageThermal Metrics application

report.

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6.5 Electrical Characteristics

specified at T_J= –40°C to +150°C, V_IN= 13.5 V, I_OUT= 0 mA, C_OUT= 2.2 µF, 1 mΩ < C_OUTESR < 2 Ω, C_IN= 1 µF typical

values are at T_J= 25°C

PARAMETER

Test Conditions

MIN TYP MAX UNIT

V_IN= V_OUT+ 1 V to 40 V, I_OUT= 100 µA to 450 mA, T_J=

25ºC⁽¹⁾

–0.85

0.85

V_IN= V_OUT+ 1 V to 40 V, I_OUT= 100 µA to 500 mA, T_J=

25ºC⁽¹⁾

–0.85

V_OUT

Regulated output

V_IN= V_OUT+ 1 V to 40 V, I_OUT= 100 µA to 450 mA⁽¹⁾

V_IN= V_OUT+ 1 V to 40 V, I_OUT= 100 µA to 500 mA⁽¹⁾

–1.15

1.15

V_IN= V_OUT+ 1 V, I_OUT= 100 µA to 450 mA , V_OUT≥ 3.3

0.425

ΔV_OUT(ΔIOUT)

Load regulation

Line regulation

V_IN= V_OUT+ 1 V, I_OUT= 100 µA to 500 mA , V_OUT≥ 3.3

0.45

0.2

ΔV_OUT(ΔVIN)

ΔV_OUT

V_IN= V_OUT+ 1 V to 40 V, I_OUT= 100 µA

t_R= t_F= 1 µs; C_OUT= 10 µF, V_OUT≥ 3.3V

I_OUT= 150 mA to 350 mA

Load transient response

settling time

100

µs

–2%

Load transient response

overshoot, undershoot⁽²⁾

t_R= t_F= 1 µs; C_OUT

10 µF

ΔV_OUT

I_OUT= 350 mA to 150 mA

I_OUT= 0 mA to 500 mA

10% %V_OUT

–10%

V_IN= V_OUT+ 1 V to 40V, I_OUT= 0 mA, T_J= 25ºC⁽³⁾

V_IN= V_OUT+ 1 V to 40 V, I_OUT= 0 mA⁽³⁾

I_OUT= 500 µA

I_Q

Quiescent current

µA

I_OUT≤ 1 mA, V_OUT≥ 3.3 V, V_IN= V_OUT(NOM)x 0.95

I_OUT= 315 mA, V_OUT≥ 3.3 V, V_IN= V_OUT(NOM)

I_OUT= 450 mA, V_OUT≥ 3.3 V, V_IN= V_OUT(NOM)

I_OUT= 500 mA, V_OUT≥ 3.3 V, V_IN= V_OUT(NOM)

V_INrising

275

360

390

400

525

575

Dropout voltage fixed output

voltages (KVU Package)

V_DO

V_UVLO(RISING)

V_{UVLO(FALLING)}

V_UVLO(HYST)

I_CL

Rising input supply UVLO

Falling input supply UVLO

V _UVLO(IN)hysteresis

2.6

2.7 2.82

V_INfalling

2.38

2.5

2.6

780

150

230

°C

Output current limit

V_IN= V_OUT+ 1 V, V_OUTshort to 90% x V_OUT(NOM)

V_IN- V_OUT= 1 V, frequency = 1 kHz, I_OUT= 450 mA

540

–40

PSRR

Power supply rejection ratio

Junction temperature

T_J

Junction shutdown

temperature

T_SD(SHUTDOWN)

T_SD(HYST)

175

°C

Hysteresis of thermal

shutdown

(1) Power dissipation is limited to 2 W for device production testing purposes. The power dissipation can be higher during normal

operation. See the thermal dissipation section for more information on how much power the device can dissipate while maintaining a

junction temperature below 150℃.

(2) Specified by design.

(3) For the adjustable output this is tested in unity gain and resistor current is not included.

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6.6 Typical Characteristics

specified at T_J= –40°C to +150°C, V_IN= 13.5 V, I_OUT= 100 µA, C_OUT= 2.2 µF, 1 mΩ < C_OUTESR < 2 Ω, C_IN= 1 µF (unless

otherwise noted)

0.3

0.25

0.2

5.015

5.01

5.005

500 mA

100 mA

-55èC

-40èC

0èC

85èC

150èC

25èC

125èC

0.15

0.1

0.05

4.995

4.99

4.985

4.98

4.975

-0.05

-0.1

-0.15

-0.2

-0.25

-0.3

-60 -40 -20

20 40 60 80 100 120 140 160

Temperature èC

20 25

Input Voltage (V)

V_OUT= 5 V, I_OUT= 150 mA

Figure 6-2. Line Regulation vs V_IN

Figure 6-1. Accuracy vs Temperature

5.015

5.01

5.005

-55èC

-40èC

0èC

25èC

85èC

125èC

150èC

-55èC

-40èC

0èC

25èC

85èC

125èC

150èC

5.01

5.005

4.995

4.99

4.985

4.98

4.975

4.995

4.99

4.985

4.98

4.975

20 25

Input Voltage (V)

20 25

Input Voltage (V)

V_OUT= 5 V, I_OUT= 5 mA

Figure 6-3. Line Regulation vs V_IN

V_OUT= 5 V, I_OUT= 1 mA

Figure 6-4. Line Regulation vs V_IN

5.015

5.01

5.005

5.01

5.0075

5.005

5.0025

-55èC

-40èC

0èC

85èC

150èC

-40 èC

25 èC

85 èC

25èC

125èC

4.995

4.99

4.985

4.98

4.975

4.9975

4.995

4.9925

4.99

50 75

Output Current (mA)

100

125

150

Input Voltage (V)

V_OUT= 5 V

Figure 6-5. Load Regulation vs I_OUT

C_OUT= 10 µF, V_OUT= 5 V

Figure 6-6. Line Regulation at 50 mA

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6.6 Typical Characteristics (continued)

specified at T_J= –40°C to +150°C, V_IN= 13.5 V, I_OUT= 100 µA, C_OUT= 2.2 µF, 1 mΩ < C_OUTESR < 2 Ω, C_IN= 1 µF (unless

otherwise noted)

5.01

5.0075

5.005

5.0025

550

500

450

400

350

300

250

200

150

100

-40 èC

25 èC

85 èC

-55 èC

-40 èC

0 èC

25 èC

85 èC

125 èC

150 èC

4.9975

4.995

4.9925

4.99

50 100 150 200 250 300 350 400 450 500

Output Current (mA)

Input Voltage (V)

V_IN= 3 V

C_OUT= 10 µF, V_OUT= 5 V

Figure 6-7. Line Regulation at 100 mA

Figure 6-8. Dropout Voltage (V_DO) vs I_OUT

0.5

0.2

0.1

0.05

0.02

0.01

I_OUT

10 mA, 364.8 mV_RMS

150 mA, 391.4 mV_RMS

500 mA, 437.2 mV_RMS

0.005

1 mA

10 mA

50 mA

150 mA

350 mA

500 mA

0.002

0.001

100

10k

Frequency (Hz)

100k

10M

100

10k

Frequency (Hz)

100k

10M

C_OUT= 10 µF (X7R 50 V), V_OUT= 5 V

Figure 6-9. PSRR vs Frequency and I_OUT

Figure 6-10. Noise vs Frequency

0.5

0.2

0.1

0.05

0.02

0.01

I_OUT

10 mA, 252.5 mV_RMS

150 mA, 267.6 mV_RMS

500 mA, 293.8 mV_RMS

0.005

0.002

0.001

6 V V_IN

100

7 V V_IN

10 V_IN

13.5 V V_IN

1M 10M

10k

Frequency (Hz)

100k

100

10k

Frequency (Hz)

100k

10M

C_OUT= 10 µF (X7R 50 V), I_OUT= 500 mA, V_OUT= 5 V

C_OUT= 10 µF (X7R 50 V), V_OUT= 3.3 V

Figure 6-12. PSRR vs Frequency and V_IN

Figure 6-11. Noise vs Frequency

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6.6 Typical Characteristics (continued)

specified at T_J= –40°C to +150°C, V_IN= 13.5 V, I_OUT= 100 µA, C_OUT= 2.2 µF, 1 mΩ < C_OUTESR < 2 Ω, C_IN= 1 µF (unless

otherwise noted)

0.25

0.2

300

240

180

120

V_IN

V_OUT

V_IN

V_OUT

0.15

0.1

0.05

-2

-4

-6

-8

-10

-60

-0.05

-0.1

-0.15

-0.2

-120

-180

-240

-300

50 100 150 200 250 300 350 400 450 500

Time (ms)

500

1000

1500

Time (ms)

2000

2500

3000

V_OUT= 5 V, I_OUT= 100 mA, V_IN= 5.5 V to 6.5 V,

rise time = 1 µs

V_OUT= 5 V, I_OUT= 1 mA, V_IN= 13.5 V to 45 V,

slew rate = 2.7 V/µs

Figure 6-14. Line Transients

Figure 6-13. Line Transients

150

100

300

200

100

150

100

300

200

100

-40èC

25èC

150èC

I_OUT

25èC

150èC

I_OUT

-50

-100

-150

-100

-200

-300

-50

-100

-150

-100

-200

-300

0.5

1.5

2.5

Time (ms)

3.5

4.5

80 100 120 140 160 180 200

Time (ms)

V_OUT= 5 V, I_OUT= 0 mA to 100 mA, slew rate = 1 A/µs,

C_OUT= 10 µF

V_OUT= 5 V, I_OUT= 0 mA to 100 mA, slew rate = 1 A/µs,

C_OUT= 10 µF

Figure 6-15. Load Transient, No Load to 100 mA

Figure 6-16. Load Transient, No Load to 100-mA Rising Edge

300

200

150

100

-40èC

25èC

150èC

I_OUT

-40èC

25èC

150èC

I_OUT

240

180

120

-50

-10

-20

-30

-40

-50

-60

-10

-20

-30

-40

-100

-150

-200

-250

-120

-180

-240

-300

120

Time (ms)

160

200

240

280

80 100 120 140 160 180 200

Time (ms)

V_OUT= 5 V, I_OUT= 45 mA to 105 mA, slew rate = 0.1 A/µs,

C_OUT= 10 µF

V_OUT= 5 V, I_OUT= 45 mA to 105 mA, slew rate = 0.1 A/µs,

C_OUT= 10 µF

Figure 6-17. Load Transient, 45 mA to 105 mA

Figure 6-18. Load Transient, 45-mA to 105-mA Rising Edge

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6.6 Typical Characteristics (continued)

specified at T_J= –40°C to +150°C, V_IN= 13.5 V, I_OUT= 100 µA, C_OUT= 2.2 µF, 1 mΩ < C_OUTESR < 2 Ω, C_IN= 1 µF (unless

otherwise noted)

150

100

300

200

100

150

100

300

200

100

-40èC

25èC

150èC

I_OUT

-40èC

25èC

150èC

I_OUT

-50

-100

-150

-100

-200

-300

-50

-100

-150

-100

-200

-300

0.25

0.5

0.75

Time (ms)

1.25

1.5

1.75

80 100 120 140 160 180 200

Time (ms)

V_OUT= 5 V, I_OUT= 0 mA to 150 mA, slew rate = 1 A/µs,

C_OUT= 10 µF

V_OUT= 5 V, I_OUT= 0 mA to 150 mA, slew rate = 1 A/µs,

C_OUT= 10 µF

Figure 6-19. Load Transient, No Load to 150-mA

Figure 6-20. Load Transient, No Load to 150-mA Rising Edge

150

600

500

400

300

200

100

300

250

200

150

100

600

500

400

300

200

100

-40èC

25èC

150èC

I_OUT

-40èC

25èC

150èC

I_OUT

100

-50

-100

-200

-300

-400

-500

-600

-100

-150

-200

-250

-300

-100

-150

0.5

1.5

2.5

Time (ms)

3.5

4.5

75 100 125 150 175 200 225 250

Time (ms)

V_OUT= 5 V, I_OUT= 0 mA to 500 mA, slew rate = 1 A/µs,

C_OUT= 10 µF

V_OUT= 5 V, I_OUT= 150 mA to 350 mA, slew rate = 0.1 A/µs,

C_OUT= 10 µF

Figure 6-22. Load Transient, No Load to 500 mA

Figure 6-21. Load Transient, 150-mA to 350-mA

150

100

900

750

600

450

300

150

660

659

658

657

656

655

654

653

652

651

-40èC

25èC

150èC

I_OUT

-50

-100

-150

-200

-250

-150

-300

80 100 120 140 160 180 200

Time (ms)

Current Limit

105 135

650

-75

-45

-15

V_OUT= 5 V, I_OUT= 0 mA to 500 mA, slew rate = 1 A/µs,

C_OUT= 10 µF

Temperature (èC)

V_IN= V_OUT+ 1 V, V_OUT= 90% × V_OUT(NOM)

Figure 6-24. Output Current Limit vs Temperature

Figure 6-23. Load Transient, No Load to 500-mA Rising Edge

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6.6 Typical Characteristics (continued)

specified at T_J= –40°C to +150°C, V_IN= 13.5 V, I_OUT= 100 µA, C_OUT= 2.2 µF, 1 mΩ < C_OUTESR < 2 Ω, C_IN= 1 µF (unless

otherwise noted)

175

150

125

100

-55èC

-40èC

0èC

25èC

85èC

125èC

150èC

-55èC

-40èC

0èC

25èC

85èC

125èC

150èC

20 25

Input Voltage (V)

V_OUT= 5 V

Figure 6-26. Quiescent Current (I_Q) vs V_IN

Figure 6-25. Quiescent Current (I_Q) vs V_IN

1300

281

280

279

278

277

276

275

274

273

272

271

-55 èC

-40 èC

0 èC

25 èC

85 èC

125 èC

150 èC

1200

1100

1000

900

800

700

600

500

400

300

200

100

50 100 150 200 250 300 350 400 450 500

Output Current (mA)

-75

-50

-25

100 125 150

Temperature (èC)

Figure 6-27. Ground Current (I_GND) vs I_OUT

Figure 6-28. Ground Current at 100 mA

17.5

900

800

700

600

500

400

300

200

100

Input Voltage

Output Voltage

Output Current

12.5

7.5

2.5

-2.5

-5

-100

250 500 750 1000 1250 1500 1750 2000 2250 2500

Time (ms)

-75

-50

-25

100 125 150

V_IN= 13.5 V, V_OUT= 5 V, I_OUT= 150 mA, C_OUT= 10 µF

Ambient Temperature (èC)

Figure 6-30. Startup Plot Inrush Current

Figure 6-29. Ground Current at 500 µA

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6.6 Typical Characteristics (continued)

specified at T_J= –40°C to +150°C, V_IN= 13.5 V, I_OUT= 100 µA, C_OUT= 2.2 µF, 1 mΩ < C_OUTESR < 2 Ω, C_IN= 1 µF (unless

otherwise noted)

2.8

2.75

2.7

Falling Threshold

Rising Threshold

2.65

2.6

2.55

2.5

2.45

2.4

0.2

-60 -40 -20

20 40 60 80 100 120 140 160

Temperature (èC)

0.4

0.6

0.8

1.2

Injected current (mA)

1.4

1.6

1.8

Figure 6-31. Undervoltage Lockout (UVLO) Threshold vs

Temperature

Figure 6-32. Output Voltage vs Injected Current

OFF

0.5

0.2

0.1

0.05

Stable region

0.02

0.01

0.005

0.002

0.001

0.0005

0.0002

0.0001

-50 -25

75 100 125 150 175 200

Temperature (èC)

4 5 67810

20 30 50 70 100 200300 500

C_OUT(mF)

Figure 6-34. Stability, ESR vs C_OUT

Figure 6-33. Thermal Shutdown

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7 Detailed Description

7.1 Overview

The TPS7B88-Q1 is a low-dropout linear regulator (LDO) with improved transient performance that allows for

quick response to changes in line or load conditions. The device aslo features a novel output overshoot

reduction feature that minimizes output overshoot during cold-crank conditions.

During normal operation, the device has a tight DC accuracy of ±1.15% over line, load, and temperature. The

increased accuracy allows for the powering of sensitive analog loads or sensors.

7.2 Functional Block Diagram

OUT

Current

Limit

R₁

Thermal

Shutdown

UVLO

R₂

Bandgap

GND

7.3 Feature Description

7.3.1 Undervoltage Lockout

The device has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a

controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input

drops during turn on, the UVLO has hysteresis as specified in the Electrical Characteristics table.

7.3.2 Thermal Shutdown

The device contains a thermal shutdown protection circuit to disable the device when the junction temperature

(T_J) of the pass transistor rises to T_SD(shutdown)(typical). Thermal shutdown hysteresis assures that the device

resets (turns on) when the temperature falls to T_SD(reset)(typical).

The thermal time-constant of the semiconductor die is fairly short, thus the device may cycle on and off when

thermal shutdown is reached until power dissipation is reduced. Power dissipation during startup can be high

from large V_IN– V_OUTvoltage drops across the device or from high inrush currents charging large output

capacitors. Under some conditions, the thermal shutdown protection disables the device before startup

completes.

For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating

Conditions table. Operation above this maximum temperature causes the device to exceed its operational

specifications. Although the internal protection circuitry of the device is designed to protect against thermal

overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device

into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability.

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7.3.3 Current Limit

The device has an internal current limit circuit that protects the regulator during transient high-load current faults

or shorting events. The current limit is a brickwall scheme. In a high-load current fault, the brickwall scheme

limits the output current to the current limit (I_CL). I_CLis listed in the Electrical Characteristics table.

The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the

device begins to heat up because of the increase in power dissipation. When the device is in brickwall current

limit, the pass transistor dissipates power [(V_IN– V_OUT) × I_CL]. If thermal shutdown is triggered, the device turns

off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If the output

current fault condition continues, the device cycles between current limit and thermal shutdown. For more

information on current limits, see the Know Your Limits application report.

Figure 7-1 shows a diagram of the current limit.

V_OUT

Brickwall

V_OUT(NOM)

0 V

I_OUT

I_RATED

0 mA

I_CL

Figure 7-1. Current Limit

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7.4 Device Functional Modes

7.4.1 Device Functional Mode Comparison

The Device Functional Mode Comparison table shows the conditions that lead to the different modes of

operation. See the Electrical Characteristics table for parameter values.

Table 7-1. Device Functional Mode Comparison

PARAMETER

OPERATING MODE

V_IN

I_OUT

T_J

Normal operation

Dropout operation

V_IN> V_OUT(nom)+ V_DOand V_IN> V_IN(min)

V_IN(min)< V_IN< V_OUT(nom)+ V_DO

I_OUT< I_OUT(max)

T_J< T_SD(shutdown)

Disabled

(any true condition

disables the device)

V_IN< V_UVLO

Not applicable

T_J> T_SD(shutdown)

7.4.2 Normal Operation

The device regulates to the nominal output voltage when the following conditions are met:

•

The input voltage is greater than the nominal output voltage plus the dropout voltage (V_OUT(nom)+ V_DO)

The output current is less than the current limit (I_OUT< I_CL)

The device junction temperature is less than the thermal shutdown temperature (T_J< T_SD

)

7.4.3 Dropout Operation

If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other

conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage

tracks the input voltage. During this mode, the transient performance of the device becomes significantly

degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load

transients in dropout can result in large output-voltage deviations.

When the device is in a steady dropout state (defined as when the device is in dropout, V_IN< V_OUT(NOM)+ V_DO

directly after being in a normal regulation state, but not during startup), the pass transistor is driven into the

ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output

voltage plus the dropout voltage (V_OUT(NOM)+ V_DO), the output voltage can overshoot for a short period of time

while the device pulls the pass transistor back into the linear region.

7.4.4 Disabled

The output of the device can be shutdown by forcing the input voltage below the UVLO falling threshold (see the

Electrical Characteristics table). When disabled, the pass transistor is turned off and internal circuits are

shutdown.

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8 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

8.1 Application Information

8.1.1 Input and Output Capacitor Selection

The TPS7B88-Q1 requires an output capacitor of 2.2 µF or larger (1 µF or larger capacitance) for stability and an

equivalent series resistance (ESR) between 0.001 Ω and 2 Ω. For best transient performance, use X5R- and

X7R-type ceramic capacitors because these capacitors have minimal variation in value and ESR over

temperature. When choosing a capacitor for a specific application, be mindful of the DC bias characteristics for

the capacitor. Higher output voltages cause a significant derating of the capacitor. For best performance, the

maximum recommended output capacitance is 220 µF.

Although an input capacitor is not required for stability, good analog design practice is to connect a capacitor

from IN to GND. Some input supplies have a high impedance, thus placing the input capacitor on the input

supply helps reduce the input impedance. This capacitor counteracts reactive input sources and improves

transient response, input ripple, and PSRR. If the input supply has a high impedance over a large range of

frequencies, several input capacitors can be used in parallel to lower the impedance over frequency. Use a

higher-value capacitor if large, fast, rise-time load transients are anticipated, or if the device is located several

inches from the input power source.

8.1.2 Dropout Voltage

Dropout voltage (V_DO) is defined as the input voltage minus the output voltage (V_IN– V_OUT) at the rated output

current (I_RATED), where the pass transistor is fully on. I_RATEDis the maximum I_OUTlisted in the Recommended

Operating Conditions table. The pass transistor is in the ohmic or triode region of operation, and acts as a

switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed

output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than

the nominal output regulation, then the output voltage falls as well.

For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (R_DS(ON)) of the

pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for

that current scales accordingly. The following equation calculates the R_DS(ON)of the device.

V_DO

R_DS(ON)

I_RATED

(1)

8.1.3 Reverse Current

Excessive reverse current can damage this device. Reverse current flows through the intrinsic body diode of the

pass transistor instead of the normal conducting channel. At high magnitudes, this current flow degrades the

long-term reliability of the device.

Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute

maximum rating of V_OUT≤ V_IN+ 0.3 V.

•

If the device has a large C_OUTand the input supply collapses with little or no load current

The output is biased when the input supply is not established

The output is biased above the input supply

If reverse current flow is expected in the application, external protection is recommended to protect the device.

Reverse current is not limited in the device, so external limiting is required if extended reverse voltage operation

is anticipated.

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8.1.4 Power Dissipation (P_D)

Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed

circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few

or no other heat-generating devices that cause added thermal stress.

To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference

and load conditions. The following equation calculates power dissipation (P_D).

P_D= (V_IN– V_OUT) × I_OUT

(2)

Note

Power dissipation can be minimized, and therefore greater efficiency can be achieved, by correct

selection of the system voltage rails. For the lowest power dissipation use the minimum input voltage

required for correct output regulation.

For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal

pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an

array of plated vias that conduct heat to additional copper planes for increased heat dissipation.

The maximum power dissipation determines the maximum allowable ambient temperature (T_A) for the device.

According to the following equation, power dissipation and junction temperature are most often related by the

junction-to-ambient thermal resistance (R_θJA) of the combined PCB and device package and the temperature of

the ambient air (T_A).

T_J= T_A+ (R_θJA× P_D)

(3)

Thermal resistance (R_θJA) is highly dependent on the heat-spreading capability built into the particular PCB

design, and therefore varies according to the total copper area, copper weight, and location of the planes. The

junction-to-ambient thermal resistance listed in the Thermal Information table is determined by the JEDEC

standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance.

8.1.4.1 Power Dissipation Versus Ambient Temperature

Figure 8-1 is based off of a JESD51-7 4-layer, high-K board. The allowable power dissipation was estimated

using the following equation. As disscussed in the An empirical analysis of the impact of board layout on LDO

thermal performance application report, thermal dissipation can be improved in the JEDEC high-K layout by

adding top layer copper and increasing the number of thermal vias. If a good thermal layout is used, the

allowable thermal dissipation can be improved by up to 50%.

6 + 4_à,#T 2_&Q 150 °%

(4)

6.5

KVU Package

5.5

4.5

3.5

2.5

1.5

0.5

-40

-20

100 120 140

Ambient Temerature (èC)

Figure 8-1. TPS7B88-Q1 Allowable Power Dissipation

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8.1.5 Estimating Junction Temperature

The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures

of the linear regulator when in-circuit on a typical PCB board application. These metrics are not thermal

resistance parameters and instead offer a practical and relative way to estimate junction temperature. These psi

metrics are determined to be significantly independent of the copper area available for heat-spreading. The

Thermal Information table lists the primary thermal metrics, which are the junction-to-top characterization

parameter (ψ_JT) and junction-to-board characterization parameter (ψ_JB). These parameters provide two methods

for calculating the junction temperature (T_J), as described in the following equations. Use the junction-to-top

characterization parameter (ψ_JT) with the temperature at the center-top of device package (T_T) to calculate the

junction temperature. Use the junction-to-board characterization parameter (ψ_JB) with the PCB surface

temperature 1 mm from the device package (T_B) to calculate the junction temperature.

T_J= T_T+ ψ_JT× P_D

(5)

where:

•

P_Dis the dissipated power

T_Tis the temperature at the center-top of the device package

T_J= T_B+ ψ_JB× P_D

(6)

where

•

T_Bis the PCB surface temperature measured 1 mm from the device package and centered on the package

edge

For detailed information on the thermal metrics and how to use them, see the Semiconductor and IC Package

Thermal Metrics application report.

8.2 Typical Application

Figure 8-2 shows a typical application circuit for the TPS7B88-Q1. TI recommends a low-ESR ceramic capacitor

with a dielectric of type X5R or X7R.

OUT

TPS7B88-Q1

GND

Figure 8-2. Typical Application Schematic for the TPS7B88-Q1

8.2.1 Design Requirements

For this design example, use the parameters listed in Table 8-1 as the input parameters.

Table 8-1. Design Parameters

DESIGN PARAMETER

Input voltage range

Output voltage

EXAMPLE VALUE

6 V to 40 V

5 V

Output current

350 mA

10 µF

Output capacitor

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8.2.2 Detailed Design Procedure

8.2.2.1 Input Capacitor

The device requires an input decoupling capacitor, the value of which depends on the application. The typical

recommended value for the decoupling capacitor is 1 µF. The voltage rating must be greater than the maximum

input voltage.

8.2.2.2 Output Capacitor

The device requires an output capacitor to stabilize the output voltage. The capacitor value must be between

2.2 µF and 200 µF and the ESR range must be between 1 mΩ and 2 Ω. For this design, a low ESR, 10-µF

ceramic capacitor was used to improve transient performance.

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8.2.3 Application Curves

900

800

700

600

500

400

300

200

100

Input Voltage

Output Voltage

Output Current

17.5

12.5

7.5

2.5

-2.5

-5

-100

1 mA

10 mA

50 mA

150 mA

350 mA

500 mA

250 500 750 1000 1250 1500 1750 2000 2250 2500

Time (ms)

100

10k

Frequency (Hz)

100k

10M

Figure 8-3. Power-Up Waveform

Figure 8-4. PSRR

150

100

600

-40èC

25èC

150èC

I_OUT

500

400

300

200

100

-50

-100

-150

75 100 125 150 175 200 225 250

Time (ms)

Figure 8-5. Transient Response

9 Power Supply Recommendations

This device is designed for operation from an input voltage supply with a range between 3 V and 40 V. This input

supply must be well regulated. If the input supply is located more than a few inches from the TPS7B88-Q1, add

an electrolytic capacitor with a value of 22 µF and a ceramic bypass capacitor at the input.

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10 Layout

10.1 Layout Guidelines

For best overall performance, place all circuit components on the same side of the circuit board and as near as

practical to the respective LDO pin connections. Place ground return connections to the input and output

capacitor, and to the LDO ground pin as close as possible to each other, connected by a wide, component-side,

copper surface. The use of vias and long traces to the input and output capacitors is strongly discouraged and

negatively affects system performance. TI also recommends a ground reference plane either embedded in the

PCB itself or located on the bottom side of the PCB opposite the components. This reference plane serves to

assure accuracy of the output voltage, shield noise, and behaves similarly to a thermal plane to spread (or sink)

heat from the LDO device when connected to the thermal pad. In most applications, this ground plane is

necessary to meet thermal requirements.

10.1.1 Package Mounting

Solder pad footprint recommendations for the TPS7B88-Q1 are available at the end of this document and at

www.ti.com.

10.1.2 Board Layout Recommendations to Improve PSRR and Noise Performance

As depicted in Figure 10-1 , place the input and output capacitors close to the device for the layout of the

TPS7B88-Q1. In order to enhance the thermal performance, place as many vias as possible around the device.

These vias improve the heat transfer between the different GND planes in the PCB.

To improve AC performance such as PSRR, output noise, and transient response, TI recommends a board

design with separate ground planes for V_INand V_OUT, with each ground plane connected only at the GND pin of

the device. In addition, the ground connection for the output capacitor must connect directly to the GND pin of

the device.

Minimize equivalent series inductance (ESL) and ESR in order to maximize performance and ensure stability.

Place each capacitor as close as possible to the device and on the same side of the PCB as the regulator itself.

Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. TI

strongly discourages the use of vias and long traces to connect the capacitors because may negatively affect

system performance and even cause instability.

If possible, and to ensure the maximum performance specified in this document, use the same layout pattern

used for the TPS7B88-Q1 evaluation board, available at www.ti.com.

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10.2 Layout Example

GND

V_IN

V_OUT

Denotes a via

Figure 10-1. KVU Package Fixed Output

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11 Device and Documentation Support

11.1 Device Support

11.1.1 Device Nomenclature

Table 11-1. Device Nomenclature ⁽¹⁾

PRODUCT

V_OUT

xx is the nominal output voltage (for example, 33 = 3.3 V V; 50 = 5.0 V).

Q indicates that this device is a grade-1 device in accordance with the AEC-Q100 standard.

Q1 indicates that this device is an automotive grade (AEC-Q100) device.

TPS7B88xxQKVURQ1

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the

device product folder on www.ti.com.

11.1.2 Development Support

For the PSpice model, see the TPS7B4250 PSpice Transient Model.

11.2 Documentation Support

11.2.1 Related Documentation

For related documentation see the following:

•

Texas Instruments, Various Applications for Voltage-Tracking LDO application report

Texas Instruments, TPS7B4250 Evaluation Module user's guide

Texas Instruments, TPS7B5250-Q1 Pin FMEA application report

11.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

11.4 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

11.5 Trademarks

TI E2E^™is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

11.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

11.7 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

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19-Sep-2021

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS7B8833QKVURQ1

TPS7B8833QKVURQ1R2

TPS7B8850QKVURQ1

TPS7B8850QKVURQ1R2

ACTIVE

TO-252

KVU

2500 RoHS & Green

Level-3-260C-168 HR

-40 to 125

-40 to 150

-40 to 125

-40 to 150

7B8833

7B8850

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

19-Sep-2021

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

20-Sep-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS7B8833QKVURQ1R2 TO-252

TPS7B8850QKVURQ1R2 TO-252

KVU

2500

330.0

16.4

6.9

10.5

2.7

8.0

16.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

20-Sep-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS7B8833QKVURQ1R2

TPS7B8850QKVURQ1R2

TO-252

KVU

2500

340.0

38.0

Pack Materials-Page 2

PACKAGE OUTLINE

KVU0003A

TO-252 - 2.52 mm max height

TO-252

10.41

9.40

6.22

5.97

1.27

0.89

2.29

6.70

5.460 6.35

4.953

4.58

0.890

0.635

1.02

0.61

NOTE 3

OPTIONAL

0.25

C A B

0.61

0.46

2.52 MAX

0.61

0.46

SEE DETAIL A

5.21 MIN

4.32

MIN

EXPOSED

THERMAL PAD

NOTE 3

0.51

GAGE PLANE

0.13

0.00

1.78

1.40

0 -8

7.000

DETAIL A

TYPICAL

4218915/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Shape may vary per different assembly sites.

4. Reference JEDEC registration TO-252.

www.ti.com

EXAMPLE BOARD LAYOUT

KVU0003A

TO-252 - 2.52 mm max height

TO-252

2X (2.75)

(6.15)

2X (1)

SYMM

(4.58)

(5.55)

(R0.05) TYP

(4.2)

(2.5)

PKG

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:6X

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

EXPOSED

METAL

EXPOSED

METAL

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4218915/A 02/2017

NOTES: (continued)

5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature numbers

SLMA002(www.ti.com/lit/slm002) and SLMA004 (www.ti.com/lit/slma004).

6. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

KVU0003A

TO-252 - 2.52 mm max height

TO-252

(1.18) TYP

(0.14)

2X (2.75)

2X (1)

(R0.05)

(1.33) TYP

SYMM

(4.58)

20X (1.13)

20X (0.98)

(4.2)

PKG

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

65% PRINTED SOLDER COVERAGE BY AREA

SCALE:8X

4218915/A 02/2017

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

8. Board assembly site may have different recommendations for stencil design.

www.ti.com

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