TPS7H4001MDDWTSHP [TI]
耐辐射 QMLV、3V 至 7V 输入、18A 同步降压转换器 | DDW | 44 | -55 to 125;
| 型号： | TPS7H4001MDDWTSHP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 耐辐射 QMLV、3V 至 7V 输入、18A 同步降压转换器 | DDW | 44 | -55 to 125 转换器 |
| 文件： | 总66页 (文件大小：3527K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS7H4001-SP
ZHCSL64D –APRIL 2019 –REVISED MAY 2023
TPS7H4001-SP 耐辐射3V 至7V 输入、
18A 同步降压转换器
1 特性
2 应用
• 辐射性能：
– 耐辐射水平高达
• 太空卫星负载点电源
3 说明
TID 100krad(Si)
TPS7H4001-SP 是一款具有集成式低电阻高侧和低侧
MOSFET 的7V、18A 耐辐射同步降压转换器。通过电
流模式控制，可实现高效率并能减少元件数量。
– SEL、SEB 和SEGR 抗扰度
LET = 75MeV-cm2/mg
– SET 和SEFI 的
LET 特征值高达75MeV-cm2/mg
• 峰值效率：95.5%（100kHz 时，VO = 1V）
• 电源轨：3V 至7V（输入电压）
• 灵活的开关频率选项：
输出电压启动斜坡由 SS/TR 引脚控制，该引脚既支持
独立电源运行，又支持跟踪模式。正确配置使能与电源
正常引脚也可实现电源定序。TPS7H4001-SP 可配置
为初级-次级模式，并且通过 SYNC2 引脚，无需外部
时钟即可并行配置四个器件。
– 100kHz 至1MHz 可调内部振荡器
– 外部同步功能：100kHz 至1MHz
– 可将SYNC 引脚配置为500kHz 时钟频率、90°
相位差以并联多达4 个器件
高侧 FET 的逐周期电流限制可在过载情况下保护器
件，并通过低侧拉电流保护功能防止电流失控，增强限
制效果。当芯片温度超过热限值时，热关断会禁用此器
件。
• 在CDFP、KGD（已知合格芯片）和HTSSOP
(QMLP) 选项的温度、辐射以及线路和负载调节范
围内提供0.6V ±1.5% 的基准电压
器件信息
器件型号(1)
• 在HTSSOP (SHP) 选项的温度、辐射以及线路和
负载调节范围内提供0.6V ±1.7% 的基准电压
• 单调启动至预偏置输出
• 可调斜坡补偿和软启动
• 可实现电源定序的可调输入使能和电源正常输出
等级
封装
5962-1820501VXC
5962R1820501VXC
QMLV
34 引脚陶瓷
7.62mm ×
QMLV-RHA
21.59mm(2)
质量= 2.612g(3)
TPS7H4001HKY/EM
工程样片
TPS7H4001MDDWTSHP SHP-RHA
44 引脚塑料
6.10mm ×
14.00mm(2)
VIN
5962R1820502PYE
QMLP-RHA
PWRGD
质量= 243.8mg(3)
VOUT
PVIN
VIN
PWRGD
PHASE
QMLV-RHA
KGD
5962R1820501V9A
TPS7H4001Y/EM
裸片
工程样片
EN
VSENSE
EN
(1) 有关更多信息，请查看器件选项表。
(2) 尺寸值为标称值。
TPS7H4001-SP
RSC
(3) 质量误差在±10% 以内。
SSTR
RT
PGND
GND
THERMAL PAD
COMP
功能图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSEN7
TPS7H4001-SP
ZHCSL64D –APRIL 2019 –REVISED MAY 2023
www.ti.com.cn
Table of Contents
8.1 Overview...................................................................26
8.2 Functional Block Diagram.........................................27
8.3 Feature Description...................................................27
8.4 Device Functional Modes..........................................38
9 Application and Implementation..................................39
9.1 Application Information............................................. 39
9.2 Typical Application.................................................... 39
9.3 Power Supply Recommendations.............................49
9.4 Layout....................................................................... 49
10 Device and Documentation Support..........................52
10.1 Documentation Support.......................................... 52
10.2 接收文档更新通知................................................... 52
10.3 支持资源..................................................................52
10.4 Trademarks.............................................................52
10.5 静电放电警告.......................................................... 52
10.6 术语表..................................................................... 52
11 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Options Table...................................................... 4
6 Pin Configuration and Functions...................................5
7 Specifications................................................................ 11
7.1 Absolute Maximum Ratings...................................... 11
7.2 ESD Ratings..............................................................11
7.3 Recommended Operating Conditions.......................11
7.4 Thermal Information..................................................12
7.5 Electrical Characteristics - All Devices......................12
7.6 Electrical Characteristics: CDFP and KGD Options..14
7.7 Electrical Characteristics: HTSSOP (SHP) Option... 15
7.8 Electrical Characteristics: HTSSOP (QMLP)
Option..........................................................................16
7.9 Quality Conformance Inspection...............................17
7.10 Typical Characteristics............................................18
8 Detailed Description......................................................26
Information.................................................................... 53
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision C (November 2022) to Revision D (May 2023)
Page
• 更新了特性、器件信息 和电气特性部分，以包括HTSSOP (QMLP) 封装选项.................................................1
• 向说明部分中的器件信息 表添加了QMLP 可订购器件 5962R1820502PYE.................................................... 1
• 更新了说明 部分中的器件信息 表.......................................................................................................................1
• Added Device Options Table section to data sheet............................................................................................ 4
• Updated Voltage Reference section to include HTSSOP (SHP) option........................................................... 27
Changes from Revision B (September 2022) to Revision C (November 2022)
Page
• 将SHP 级HTSSOP 封装选项从“预告信息”更改为“量产数据”..................................................................1
• 向说明部分中的器件信息 表中添加了可订购 EM 芯片TPS7H4001Y/EM.........................................................1
• Updated footnote for Pin Functions table to specify CDFP package option.......................................................5
Changes from Revision A (November 2020) to Revision B (September 2022)
Page
• 更新了特性、说明、器件信息、引脚配置和功能、热性能信息、电气特性和布局指南部分，以包括HTSSOP
(SHP) 封装选项.................................................................................................................................................. 1
• Updated ESD CDM standard from JEDEC specification JESD22-C101 to ANSI/ESDA/JEDEC JS-002.........11
Changes from Revision * (April 2020) to Revision A (November 2020)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• 更新了特性 部分的辐射性能............................................................................................................................... 1
• 更新了应用 部分................................................................................................................................................. 1
• 更新了说明 部分中的器件信息 表.......................................................................................................................1
• Added bare die information to Pin Configuration and Functions section............................................................5
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSEN7
2
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• Added additional thermal resistance parameters to Thermal Information table............................................... 12
• Updated specification for Junction-to-case (bottom) thermal resistance in Thermal Information table ........... 12
• Updated all minimum limits for Enable threshold in Electrical Characteristics table.........................................12
• Updated 2.55 mV maximum limit for Error amplifier input offset voltage in Electrical Characteistics table...... 12
• Removed footnote in Electrical Characteristics table for Error amplifier transconductance, source and sink
curents specifications....................................................................................................................................... 12
• Updated footnote in Electrical Characteristics table for COMP to Iswitch gm specification to "Bench verified.
Not tested in production."..................................................................................................................................12
• Updated all maximum limits for Internally set frequency in Electrical Characteristics table............................. 12
• Updated all maximum limits for Externally set frequency for RT = 1.07 MΩ (1%) in Electrical
Characteristics table......................................................................................................................................... 12
• Updated all limits for Externally set frequency for RT = 165 kΩ (1%) in Electrical Characteristics table..........12
• Added Externally set frequency specification for RT = 73.2 kΩ (1%), VIN = 5 V, TID = 100 krad(Si) in
Electrical Characteristics table..........................................................................................................................12
• Added footnote in Electrical Characteristics table for SYNC1/SYNC2 in low level threshold for PVIN = VIN =
7 V.................................................................................................................................................................... 12
• Added footnote in Electrical Characteristics table for SYNC1/SYNC2 in high level threshold for PVIN = VIN =
7 V ................................................................................................................................................................... 12
• Removed footnote in Electrical Characteristics table for SYNC1 in frequency range specification and added
test conditions...................................................................................................................................................12
• Updated 235 ns maximum limit for Minimum on time for VIN = 5 V in Electrical Characteristics table............ 12
• Added footnote to Electrical Characteristics table for SS/TR to VSENSE matching........................................ 12
• Added footnote in Electrical Characteristics table for High-side switch resistance with PVIN = VIN = 7 V...... 14
• Added footnote in Electrical Characteristics table for Low-side switch resistance with PVIN = VIN = 7 V.......14
• Updated all typical and maximum limits for Low-side switch resistance for PVIN = VIN = 7 V, lead length = 3
mm in Electrical Characteristics table...............................................................................................................14
• Updated footnote in Electrical Characteristics table for High-side switch current limit threshold and Low-side
switch sourcing overcurrent threshold specifications to "Bench verified. Not tested in production."................ 14
• Added footnote in Electrical Characteristics table for Low-side switch sinking overcurrent threshold..............14
• Updated RT equation in Internal Oscillator Mode section................................................................................ 30
• Changed title of Master-Slave Operation Mode section to Primary-Secondary Operation Mode ....................31
• Updated input ripple current equation in Input Capacitor Selection section..................................................... 42
• Added Documentation Support to the Device and Documentation Support section........................................ 52
Copyright © 2023 Texas Instruments Incorporated
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English Data Sheet: SLVSEN7
TPS7H4001-SP
ZHCSL64D –APRIL 2019 –REVISED MAY 2023
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5 Device Options Table
Generic Part
Number
Orderable Part
Radiation Rating(2)
Grade(3)
Package(1)
Number
HKY Package CDFP
(34) Ceramic
QMLV-RHA
5962R1820501VXC
5962R1820501V9A
Total ionizing dose (TID) characterization up
to 100 krad(Si) and destructive single event
effects (DSEE) free up to LET = 75 MeV-
cm2/mg
QMLV-RHA
QMLP-RHA
KGD
HTSSOP (44) Plastic 5962R1820502PYE
TPS7H4001-SP
TPS7H4001MDDWT
SHP-RHA
HTSSOP (44) Plastic
SHP
HKY Package CDFP
TPS7H4001HKY/EM
(34) Ceramic
None
None
Engineering sample(4)
Engineering sample(4)
KGD
TPS7H4001Y/EM
(1) For all available packages, see the orderable addendum at the end of the data sheet.
(2) Refer to the device product folder for full radiation testing results in the associated TID and SEE reports.
(3) For additional information about part grade, view SLYB235.
(4) These units are intended for engineering evaluation only. These samples are processed to a non-compliant flow (i.e. no burn-in, 25°C
testing only). These units are not for qualification, production, radiation testing, or flight use. Parts are not warranted for performance
over temperature or operating life.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSEN7
4
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6 Pin Configuration and Functions
GND
GND
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
1
1
2
3
4
5
34
33
GND
REFCAP
NC
2
EN
RT
COMP
VSENSE
SS/TR
RSC
NC
NC
3
32
31
30
29
EN
REFCAP
COMP
VSENSE
SS/TR
RSC
PWRGD
GND
PH
4
VIN
RT
5
VIN
6
SYNC1
VIN
7
SYNC2
PVIN
PWRGD
PH
6
7
SYNC1
SYNC2
GND
8
28
27
9
Thermal Pad
(Bottom Side)
35
PVIN
10
11
12
13
14
15
16
17
18
19
20
21
22
PH
8
PVIN
PVIN
PVIN
PVIN
PVIN
PGND
PGND
PGND
PGND
PGND
PGND
PGND
26
25
24
23
22
21
PH
PVIN
PVIN
9
PowerPADTM
PH
10
11
PH
PH
PVIN
PH
PH
PH
PGND
PH
12
13
PH
PGND
PGND
PH
PH
PH
PH
14
15
16
17
PH
20
19
18
PGND
PGND
PGND
PH
PGND Pad
(Bottom Side)
36
PH Pad
(Bottom Side)
37
PH
PH
PH
PH
PH
图6-1. HKY Package
34-Pin CDFP
图6-2. DDW Package
44-Pin HTSSOP
Top View
Top View
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TPS7H4001-SP
ZHCSL64D –APRIL 2019 –REVISED MAY 2023
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表6-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
GND
EN
CDFP
HTSSOP
1
2
3
1, 2, 10, 35
Return for control circuitry.(1)
—
4
5
I
EN pin is internally pulled up allowing for the pin to be floated to enable the device.
A resistor connected between RT and GND sets the switching frequency of the converter.
The switching frequency range is 100 kHz to 1 MHz. When an external clock is used, RT
must be selected such that the set switching frequency coincides with the frequency of the
applied clock. Leaving this pin floating sets the internal switching frequency to 500 kHz and
SYNC1 and SYNC2 become output clocks at 500 kHz, with SYNC1 aligned with the
converter switching and SYNC2 90° out of phase.
RT
VIN
I/O
I
4
5
6,7
8
Input power for the control circuitry of the switching regulator.
SYNC1 is an input when an external clock is provided. The frequency of the external clock
should match the switching frequency that is set by the resistor between RT and GND. With
an external clock applied, the converter switching action is 180° out of phase with the
external clock. When RT is floating, SYNC1 serves as an output of a 500-kHz clock signal
that is in phase with the converter switching action. SYNC1 can be used in combination with
SYNC2 in order to connect up to four devices in parallel.
SYNC1
I/O
6
9
SYNC2 is used for connecting multiple devices in parallel. For the primary device, with RT
floating, SYNC2 outputs 500-kHz signal that is 90° out of phase with the SYNC1 output
clock. For the secondary devices, in which RT is populated, SYNC2 is used to configure the
phase of the input clock signal on SYNC1. When SYNC2 is connected to VIN, the internal
clock of the secondary device is in phase with clock provided at SYNC1. When SYNC2 is
connected to GND, the input clock signal at SYNC1 is internally inverted.
SYNC2
I/O
I
PVIN
PGND
PH
7-11
12-17
18-28
29
11-15
16-22
23-34
36
Input power for the output stage of the switching regulator.
Return for low-side power MOSFET.
Switch phase node.
—
O
Power Good fault pin. Asserts low if output voltage is low due to thermal shutdown, dropout,
overvoltage, or EN shutdown, or during soft-start.
PWRGD
RSC
O
30
31
37
38
I/O A resistor to GND sets the desired slope compensation.
Soft-start and tracking. An external capacitor connected to this pin sets the internal voltage
I/O reference rise time. The voltage on this pin overrides the internal reference. It can be used
for tracking and sequencing.
SS/TR
VSENSE
COMP
32
33
39
40
I
Inverting input of the gm error amplifier.
Error amplifier output and input to the output switch current comparator. Connect frequency
compensation to this pin.
I/O
REFCAP
34
41
O
Required 470-nF external capacitor for internal reference.
PowerPADTM
Yes
Used for heat sinking by soldering to GND copper on printed circuit board.
—
—
THERMAL
PAD
35
Thermal pad internally connected to GND.
—
—
PGND PAD
PH PAD
36
37
—
Return for low-side power MOSFET. Connect to PGND pins.
Switch phase node. Connect to PH pins.
—
—
—
O
3, 42-44
No connect. This pin is not internally connected. It is recommended to connect these pins to
GND to prevent charge buildup; however, these pins can also be left open or tied to any
voltage between GND and VIN.
NC
—
(1) Thermal pad and package lid are internally connected to GND for CDFP option.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSEN7
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表6-2. Bare Die Information
BOND PAD
DIE THICKNESS
BACKSIDE FINISH
Silicon with backgrind
BACKSIDE POTENTIAL
METALLIZATION
COMPOSITION
BOND PAD THICKNESS
15 mils
GND
AlCu
1050 nm
图6-3. TPS7H4001-SP Bare Die Diagram
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ZHCSL64D –APRIL 2019 –REVISED MAY 2023
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表6-3. Bond Pad Coordinates in Microns
DESCRIPTION
GND
GND
N/C
PAD NUMBER
X MIN
958.995
806.445
653.895
501.345
348.795
196.245
64.125
Y MIN
7185.51
7185.51
7185.51
7185.51
7185.51
7185.51
6969.06
6265.53
6080.445
5927.895
5775.345
5622.795
5119.785
4881.735
4299.39
4299.39
4299.39
4299.39
3858.93
3858.93
3858.93
3858.93
3698.73
3698.73
3698.73
3698.73
3259.17
3259.17
3259.17
3259.17
3098.97
3098.97
3098.97
3098.97
2659.41
2659.41
2659.41
2659.41
2499.21
2499.21
2499.21
2499.21
1643.76
1643.76
1643.76
X MAX
1098.945
946.395
793.845
641.295
488.745
336.195
204.075
204.075
204.075
204.075
204.075
204.075
204.075
207.99
Y MAX
7325.46
7325.46
7325.46
7325.46
7325.46
7325.46
7109.01
6405.48
6220.395
6067.845
5915.295
5762.745
5259.735
5021.685
4439.34
4439.34
4439.34
4439.34
3998.88
3998.88
3998.88
3998.88
3838.68
3838.68
3838.68
3838.68
3399.12
3399.12
3399.12
3399.12
3238.92
3238.92
3238.92
3238.92
2799.36
2799.36
2799.36
2799.36
2639.16
2639.16
2639.16
2639.16
1783.71
1783.71
1783.71
1
2
3
GND
GND
N/C
4
5
6
EN
7
RT
8
64.125
VIN
9
64.125
VIN
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
64.125
VIN
64.125
VIN
64.125
SYNC1
SYNC2
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
PGND
PGND
PGND
64.125
68.04
398.475
556.425
714.375
872.325
398.475
556.425
714.375
872.325
398.475
556.425
714.375
872.325
398.475
556.425
714.375
872.325
398.475
556.425
714.375
872.325
398.475
556.425
714.375
872.325
398.475
556.425
714.375
872.325
270.855
428.805
586.755
538.425
696.375
854.325
1012.275
538.425
696.375
854.325
1012.275
538.425
696.375
854.325
1012.275
538.425
696.375
854.325
1012.275
538.425
696.375
854.325
1012.275
538.425
696.375
854.325
1012.275
538.425
696.375
854.325
1012.275
410.805
568.755
726.705
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English Data Sheet: SLVSEN7
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表6-3. Bond Pad Coordinates in Microns (continued)
DESCRIPTION
PAD NUMBER
X MIN
Y MIN
1643.76
1643.76
1492.65
1492.65
1492.65
1492.65
1492.65
1023.66
1023.66
1023.66
1023.66
1023.66
872.55
872.55
872.55
872.55
403.56
252.45
403.56
252.45
403.56
252.45
403.56
252.45
403.56
872.55
106.02
543.69
732.42
106.02
543.69
106.02
106.02
543.69
543.69
543.69
732.42
732.42
732.42
732.42
1163.79
1163.79
1163.79
1163.79
1163.79
X MAX
884.655
1042.605
410.805
568.755
726.705
884.655
1042.605
410.805
568.755
726.705
884.655
1042.605
410.805
568.755
726.705
884.655
410.805
568.755
568.755
726.705
726.705
884.655
884.655
1042.605
1042.605
1042.605
1383.075
1383.075
1383.075
1541.025
1541.025
1698.975
1856.925
2014.875
1856.925
1698.975
2014.875
1856.925
1698.975
1541.025
2014.875
1856.925
1698.975
1541.025
1383.075
Y MAX
1783.71
1783.71
1632.6
1632.6
1632.6
1632.6
1632.6
1163.61
1163.61
1163.61
1163.61
1163.61
1012.5
1012.5
1012.5
1012.5
543.51
392.4
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PH
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
744.705
902.655
270.855
428.805
586.755
744.705
902.655
270.855
428.805
586.755
744.705
902.655
270.855
428.805
586.755
744.705
270.855
428.805
428.805
586.755
586.755
744.705
744.705
902.655
902.655
902.655
1243.125
1243.125
1243.125
1401.075
1401.075
1559.025
1716.975
1874.925
1716.975
1559.025
1874.925
1716.975
1559.025
1401.075
1874.925
1716.975
1559.025
1401.075
1243.125
543.51
392.4
543.51
392.4
543.51
392.4
543.51
1012.5
245.97
683.64
872.37
245.97
683.64
245.97
245.97
683.64
683.64
683.64
872.37
872.37
872.37
872.37
1303.74
1303.74
1303.74
1303.74
1303.74
PH
PH
PH
PH
PH
PH
PH
PH
PH
PH
PH
PH
PH
PH
PH
PH
PH
PH
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表6-3. Bond Pad Coordinates in Microns (continued)
DESCRIPTION
PH
PAD NUMBER
X MIN
Y MIN
X MAX
Y MAX
1492.47
91
1874.925
1716.975
1559.025
1401.075
1243.125
1874.925
1716.975
1559.025
1401.075
1243.125
1839.915
1681.965
1524.015
1366.065
1839.915
1681.965
1524.015
1366.065
1839.915
1681.965
1524.015
1366.065
1839.915
1681.965
1524.015
1366.065
1839.915
1681.965
1524.015
1366.065
1839.915
1681.965
1524.015
1366.065
1839.915
1681.965
1524.015
1366.065
1954.305
1954.305
1954.305
1954.305
1954.305
1954.305
1352.52
2014.875
1856.925
1698.975
1541.025
1383.075
2014.875
1856.925
1698.975
1541.025
1383.075
1979.865
1821.915
1663.965
1506.015
1979.865
1821.915
1663.965
1506.015
1979.865
1821.915
1663.965
1506.015
1979.865
1821.915
1663.965
1506.015
1979.865
1821.915
1663.965
1506.015
1979.865
1821.915
1663.965
1506.015
1979.865
1821.915
1663.965
1506.015
2094.255
2094.255
2094.255
2094.255
2094.255
2094.255
PH
92
1352.52
1492.47
PH
93
1352.52
1492.47
PH
94
1352.52
1492.47
PH
95
1352.52
1492.47
PH
96
1786.68
1926.63
PH
97
1786.68
1926.63
PH
98
1786.68
1926.63
PH
99
1786.68
1926.63
PH
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
1786.68
1926.63
PH
2356.245
2356.245
2356.245
2356.245
2802.375
2802.375
2802.375
2802.375
2956.005
2956.005
2956.005
2956.005
3402.135
3402.135
3402.135
3402.135
3555.765
3555.765
3555.765
3555.765
4001.895
4001.895
4001.895
4001.895
4155.525
4155.525
4155.525
4155.525
5335.605
5533.56
2496.195
2496.195
2496.195
2496.195
2942.325
2942.325
2942.325
2942.325
3095.955
3095.955
3095.955
3095.955
3542.085
3542.085
3542.085
3542.085
3695.715
3695.715
3695.715
3695.715
4141.845
4141.845
4141.845
4141.845
4295.475
4295.475
4295.475
4295.475
5475.555
5673.51
PH
PH
PH
PH
PH
PH
PH
PH
PH
PH
PH
PH
PH
PH
PH
PH
PH
PH
PH
PH
PH
PH
PH
PH
PH
PH
PH
PWRGD
RSC
SS/TR
VSENSE
COMP
REFCAP
5731.515
5910.615
6116.715
6948.45
5871.465
6050.565
6256.665
7088.4
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7 Specifications
7.1 Absolute Maximum Ratings
over operating temperature (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–1
MAX
UNIT
VIN
7.5
PVIN
EN
7.5
7.5
RSC
VSENSE
3.3
3.3
Input voltage
COMP
3.3
V
PWRGD
7.5
SS/TR
3.3
RT
3.3
SYNC1
7.5
SYNC2
7.5
REFCAP
3.3
Output voltage
PH
7.5
7.5
V
PH 10-ns transient
–3
Vdiff
(GND to exposed thermal pad)
0.2
V
A
–0.2
PH
Current limit
±100
Source current
RT
µA
A
PH
Current limit
Current limit
±200
PVIN
COMP
PWRGD
A
Sink current
µA
mA
°C
°C
5
–0.1
–55
–65
Operating junction temperature
Storage temperature, Tstg
150
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
7.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
NOM
MAX
18
UNIT
A
IOUT
TJ
Maximum switching current
Junction operating temperature
125
°C
–55
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7.4 Thermal Information
TPS7H4001-SP
CDFP
THERMAL METRIC(1)
HTSSOP
44 PINS
23.7
UNIT
34 PINS
25.3
9.5
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJC(bot)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-case (bottom) thermal resistance
Junction-to-board thermal resistance
12.4
2.5
1.2
9.5
6.8
Junction-to-top characterization parameter
Junction-to-board characterization parameter
3.4
0.2
ψJT
9.3
6.7
ψJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953)
7.5 Electrical Characteristics - All Devices
TJ = –55°C to 125°C, VIN = PVIN = 3 V to 7 V (unless otherwise noted)
PARAMETER
SUPPLY VOLTAGE (VIN AND PVIN PINS)
PVIN operating input voltage
TEST CONDITIONS
SUBGROUP(1)
MIN
TYP
MAX
UNIT
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
3.0
2.425
425
7.0
2.575
475
7.0
V
V
PVIN internal UVLO threshold
PVIN internal UVLO hysteresis
VIN operating input voltage
PVIN rising
Load = 0 A
2.50
450
mV
V
3.0
VIN internal UVLO threshold
VIN rising
2.71
134
2.75
150
2.32
4
2.80
178
2.85
6
V
VIN internal UVLO hysteresis
VIN shutdown supply current
mV
mA
mA
VEN = 0 V
VSENSE = VBG
VIN operating –non switching supply current
ENABLE AND UVLO (EN PIN)
Rising
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1.110
1.080
4.8
1.14
1.11
6.1
1.172
1.148
7.6
Enable threshold
V
Falling
Input current
VEN = 1.1 V
VEN = 1.3 V
µA
µA
Hysteresis current
2.4
3.0
3.9
ERROR AMPLIFIER
Error amplifier input offset voltage
VSENSE pin input current
Error amplifier transconductance (gm)
Error amplifier DC gain(2)
Error amplifier source
VSENSE = 0.6 V
VSENSE = 0.6 V
1, 2, 3
2.55
15
mV
nA
–2
–15
1150
1, 2, 3
9, 10, 11
1800
10000
140
140
7
2400
µS
–2 μA < ICOMP < 2 μA, V(COMP) = 1 V
VSENSE = 0.6 V
V/V
µA
V(COMP) = 1 V, 100-mV input overdrive
V(COMP) = 1 V, 100-mV input overdrive
1, 2, 3
1, 2, 3
100
100
190
190
Error amplifier sink
µA
Error amplifier output resistance
MΩ
3
1
2
28
29
30
38
49
50
52
–55℃
COMP to Iswitch gm(3)
SLOPE COMPENSATION
Slope compensation(4)
COMP = 0.5 V
40
S
25℃
41
125℃
fSW = 100 kHz, RSC = 1.1 MΩ
fSW = 500 kHz, RSC = 196 kΩ
fSW = 1000 kHz, RSC = 80.6 kΩ
–1.2
–6.0
A/µs
–16.0
THERMAL SHUTDOWN
Thermal shutdown
190
18
°C
°C
Thermal shutdown hysteresis
INTERNAL SWITCHING FREQUENCY
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TJ = –55°C to 125°C, VIN = PVIN = 3 V to 7 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SUBGROUP(1)
4, 5, 6
MIN
444
449
80
TYP
473
502
98
MAX
515
UNIT
VIN = 3 V
Internally set frequency
RT = Open
kHz
VIN = 5 V
4, 5, 6
560
VIN = 3 V
4, 5, 6
125
RT = 1.07 MΩ(1%)
RT = 165 kΩ(1%)
VIN = 5 V
VIN = 3 V
VIN = 5 V
VIN = 3 V
VIN = 5 V
4, 5, 6
80
100
495
523
850
986
125
4, 5, 6
455
475
689
760
535
4, 5, 6
615
Externally set frequency
kHz
4, 5, 6
1011
1212
4, 5, 6
RT = 73.2 kΩ(1%)
VIN = 5 V, TID = 100
krad(Si)
4
760
1145
1425
EXTERNAL SYNCHRONIZATION
SYNC1/SYNC2 out low-to-high rise time (10%/
90%)
Cload = 25 pF
Cload = 25 pF
9, 10, 11
9, 10, 11
70
10
180
21
ns
ns
SYNC1/SYNC2 out high-to-low fall time (90%/
10%)
SYNC2 to SYNC1 rising edge phase shift
SYNC1 falling edge delay(3)
9, 10, 11
9, 10, 11
1, 2, 3
77
165
85
94
°
°
180
185
SYNC1/SYNC2 out high level threshold
SYNC1/SYNC2 out low level threshold
IOH = 50 µA
V
VIN –0.3
IOL = 50 µA
1, 2, 3
600
800
800
800
mV
PVIN = VIN = 3 V
PVIN = VIN = 5 V
PVIN = VIN = 7 V(3)
PVIN = VIN = 3 V
PVIN = VIN = 5 V
PVIN = VIN = 7 V(3)
PVIN = VIN = 5 V
SYNC1/SYNC2 in low level threshold
SYNC1/SYNC2 in high level threshold
1, 2, 3
1, 2, 3
mV
V
2.25
3.5
4.9
100
40
SYNC1 in frequency range
SYNC1 in duty cycle range
PH (PH PIN)
4, 5, 6
4, 5, 6
1000
60
kHz
%
Duty cycle of external clock
Measured at 10% to 90% of VIN,
IPH = 2 A, VIN = 3 V
9, 10, 11
9, 10, 11
190
190
235
225
Minimum on time
ns
Measured at 10% to 90% of VIN,
IPH = 2 A, VIN = 5 V
SOFT START AND TRACKING (SS/TR PIN)
SS charge current
1, 2, 3
1, 2, 3
1.5
90
2.5
30
3
µA
SS/TR to VSENSE matching(3)
POWER GOOD (PWRGD PIN)
V(SS/TR) = 0.3 V
90
mV
VSENSE falling (fault)
91
94
VSENSE rising (good)
97
VSENSE threshold
1, 2, 3
%VREF
VSENSE rising (fault)
109
106
30
111
VSENSE falling (good)
VSENSE = VREF, V(PWRGD) = 5 V
I(PWRGD) = 2 mA
103
Output high leakage
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
181
0.3
1
nA
V
Output low
Minimum VIN for valid output
Minimum SS/TR voltage for PWRGD
0.6
V
V(PWRGD) < 0.5 V at 100 μA
1.1
V
(1) For subgroup definitions, see Quality Conformance Inspection table.
(2) Ensured by design only. Not tested in production.
(3) Bench verified. Not tested in production.
(4) Example values are shown in the table. Actual values are application specific and should be calculated as detailed in the Slope
Compensation section.
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MAX UNIT
7.6 Electrical Characteristics: CDFP and KGD Options
TJ = –55°C to 125°C, VIN = PVIN = 3 V to 7 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SUBGROUP(1)
MIN
TYP
VOLTAGE REFERENCE
Internal voltage reference initial
tolerance
0 A ≤Iout ≤18 A, 0 A ≤Iout ≤18
1
0.599
0.605
0.612
V
25°C
A, 25°C
–55°C
125°C
3
0.595
0.600
1.191
0.602
0.607
1.209
0.609
0.613
1.226
Internal voltage reference
V
V
0 A ≤Iout ≤18 A
REFCAP = 470 nF
2
REFCAP voltage
1, 2, 3
MOSFET
3
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
1
2
16
22
30
14
20
27
13
17
23
8
22
25
34
19
22
30
18
21
28
11
12
18
10
11
17
7
–55°C
25°C
PVIN = VIN = 3 V,
lead length = 3 mm
125°C
–55°C
25°C
PVIN = VIN = 5 V,
lead length = 3 mm
High-side switch resistance(2)
mΩ
125°C
–55°C
25°C
PVIN = VIN = 7 V,
lead length = 3
mm(3)
125°C
–55°C
25°C
PVIN = VIN = 3 V,
lead length = 3 mm
9
125°C
–55°C
25°C
14
7
PVIN = VIN = 5 V,
lead length = 3 mm
Low-side switch resistance(2)
9
mΩ
125°C
–55°C
25°C
13
5
PVIN = VIN = 7 V,
lead length = 3
mm(3)
8
10
15
125°C
13
OVERCURRENT PROTECTION
High-side switch current limit threshold(3) VIN = 7 V
1, 2, 3
1, 2, 3
25
29
32
37
A
A
Low-side switch sourcing overcurrent
VIN = 7 V
21
threshold(3)
Low-side switch sinking overcurrent
VIN = 7 V
1, 2, 3
4.5
6
A
threshold(3)
(1) For subgroup definitions, see Quality Conformance Inspection table.
(2) Measured at pins
(3) Bench verified. Not tested in production.
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7.7 Electrical Characteristics: HTSSOP (SHP) Option
TJ = –55°C to 125°C, VIN = PVIN = 3 V to 7 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SUBGROUP(1)
MIN
TYP
MAX UNIT
VOLTAGE REFERENCE
Internal voltage reference initial
tolerance
1
0.598
0.605
0.613
V
0 A ≤Iout ≤18 A, 25°C
-55°C
125°C
3
0.594
0.599
1.189
0.602
0.607
1.209
0.609
0.614
1.228
Internal voltage reference
V
V
0 A ≤Iout ≤18 A
2
REFCAP voltage
REFCAP = 470 nF
1, 2, 3
MOSFET
3
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
1
2
16
19
23
14
17
20
13
15
19
7
18
21
27
16
19
23
15
18
22
11
12
17
10
11
15
9
–55°C
25°C
PVIN = VIN = 3 V
PVIN = VIN = 5 V
PVIN = VIN = 7 V(3)
PVIN = VIN = 3 V
PVIN = VIN = 5 V
PVIN = VIN = 7 V(3)
125°C
–55°C
25°C
High-side switch resistance(2)
mΩ
125°C
–55°C
25°C
125°C
–55°C
25°C
9
125°C
–55°C
25°C
13
6
Low-side switch resistance(2)
9
mΩ
125°C
–55°C
25°C
12
5
8
10
14
125°C
11
OVERCURRENT PROTECTION
High-side switch current limit threshold(3) VIN = 7 V
1, 2, 3
1, 2, 3
27
25
34
32
A
A
Low-side switch sourcing overcurrent
VIN = 7 V
threshold(3)
Low-side switch sinking overcurrent
VIN = 7 V
1, 2, 3
3.5
6
A
threshold(3)
(1) For subgroup definitions, see Quality Conformance Inspection table.
(2) Measured at pins.
(3) Bench verified. Not tested in production.
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MAX UNIT
7.8 Electrical Characteristics: HTSSOP (QMLP) Option
TJ = –55°C to 125°C, VIN = PVIN = 3 V to 7 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SUBGROUP(1)
MIN
TYP
VOLTAGE REFERENCE
Internal voltage reference initial
tolerance
1
0.599
0.605
0.612
V
0 A ≤Iout ≤18 A, 25°C
-55°C
125°C
3
0.595
0.600
1.189
0.602
0.607
1.209
0.609
0.613
1.228
Internal voltage reference
V
V
0 A ≤Iout ≤18 A
2
REFCAP voltage
REFCAP = 470 nF
1, 2, 3
MOSFET
3
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
1
2
16
19
23
14
17
20
13
15
19
7
18
21
27
16
19
23
15
18
22
11
12
17
10
11
15
9
–55°C
25°C
PVIN = VIN = 3 V
PVIN = VIN = 5 V
PVIN = VIN = 7 V(3)
PVIN = VIN = 3 V
PVIN = VIN = 5 V
PVIN = VIN = 7 V(3)
125°C
–55°C
25°C
High-side switch resistance(2)
mΩ
125°C
–55°C
25°C
125°C
–55°C
25°C
9
125°C
–55°C
25°C
13
6
Low-side switch resistance(2)
9
mΩ
125°C
–55°C
25°C
12
5
8
10
14
125°C
11
OVERCURRENT PROTECTION
High-side switch current limit threshold(3) VIN = 7 V
1, 2, 3
1, 2, 3
27
25
34
32
A
A
Low-side switch sourcing overcurrent
VIN = 7 V
threshold(3)
Low-side switch sinking overcurrent
VIN = 7 V
1, 2, 3
3.5
6
A
threshold(3)
(1) For subgroup definitions, see Quality Conformance Inspection table.
(2) Measured at pins.
(3) Bench verified. Not tested in production.
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7.9 Quality Conformance Inspection
MIL-STD-883, Method 5005 - Group A
SUBGROUP
DESCRIPTION
Static tests at
TEMP (°C)
25
1
2
Static tests at
125
3
Static tests at
–55
25
4
Dynamic tests at
Dynamic tests at
Dynamic tests at
Functional tests at
Functional tests at
Functional tests at
Switching tests at
Switching tests at
Switching tests at
5
125
6
–55
25
7
8A
8B
9
125
–55
25
10
11
125
–55
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7.10 Typical Characteristics
Typical characteristics taken with the CDFP package option. Efficiency data was collected using the
TPS7H4001EVM-CVAL with 2 inductors in parallel. For 100-kHz data, each inductor was L = 10 µH, part number
= SER1390-103ML. For 500-kHz and 1000-kHz data, each inductor was L = 1.8 µH, part number =
SER1360-182KL.
604.8
604.7
604.7
604.7
604.6
604.6
604.6
604.6
604.5
604.5
606.0
605.5
605.0
604.5
604.0
603.5
603.0
602.5
602.0
601.5
601.0
-55 èC
25 èC
125 èC
3
3.5
4
4.5
5
VIN (V)
5.5
6
6.5
7
3
3.5
4
4.5
5
VIN(V)
5.5
6
6.5
7
图7-1. Internal VREF Initial Tolerance
图7-2. Internal VREF Variation
515
2.5
2.4
2.3
2.2
2.1
2
-55 èC
25 èC
125 èC
510
505
500
495
490
485
480
475
470
1.9
1.8
1.7
1.6
-55 èC
25 èC
125 èC
3
3.5
4
VIN (V)
4.5
5
3
3.5
4
4.5
5
VIN (V)
5.5
6
6.5
7
图7-3. Internal Frequency Variation
图7-4. VIN Shutdown Supply Current Variation
3.2
3.2
3.2
3.2
3.1
3.1
3.1
3.0
3.0
3.0
6.3
6.3
6.2
6.2
6.1
6.1
-55 èC
25 èC
125 èC
-55 èC
6.0
25 èC
125 èC
6.0
5.9
5.9
5.8
3
3.5
4
4.5
5
VIN (V)
5.5
6
6.5
7
3
3.5
4
4.5
5
VIN (V)
5.5
6
6.5
7
图7-5. Enable Hysteresis Current Variation
图7-6. Enable Pull-Up Current Variation
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1.18
1.14
1.13
1.12
1.11
-55 èC
25 èC
-55 èC
25 èC
125 èC
125 èC
1.17
1.16
1.15
1.14
3
3.5
4
4.5
5
VIN (V)
5.5
6
6.5
7
3
3.5
4
4.5
5
VIN (V)
5.5
6
6.5
7
图7-7. Enable Threshold Rising Variation
图7-8. Enable Threshold Falling Variation
3.2
2.4
2.3
2.2
2.2
2.2
-55 èC
25 èC
3.0
125 èC
2.8
2.6
2.4
2.2
2.0
1.8
2.1
-55 èC
25 èC
2.1
125 èC
2.0
2.0
1.9
3
3.5
4
4.5
5
VIN (V)
5.5
6
6.5
7
3
3.5
4
4.5
5
VIN (V)
5.5
6
6.5
7
图7-9. VIN Non-Switching Current Variation
图7-10. SS Charge Current Variation
42.5
40.0
37.5
24.8
-55 èC
25 èC
125 èC
24.5
24.2
24.0
23.8
23.5
23.2
23.0
22.8
22.5
-55 èC
35.0
25 èC
125 èC
32.5
30.0
27.5
25.0
22.5
20.0
3
3.5
4
4.5
5
VIN (V)
5.5
6
6.5
7
3
3.5
4
4.5
5
VIN (V)
5.5
6
6.5
7
图7-11. SS/TR to VSENSE Matching Variation
图7-12. High-Side Current Limit Variation
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30.5
6.8
6.6
6.4
6.2
6.0
5.8
5.6
-55 èC
-55 èC
25 èC
125 èC
25 èC
30.0
125 èC
29.5
29.0
28.5
28.0
27.5
27.0
3
3.5
4
4.5
5
VIN (V)
5.5
6
6.5
7
3
3.5
4
4.5
5
VIN (V)
5.5
6
6.5
7
图7-13. Low-Side Sourcing Current Limit Variation 图7-14. Low-Side Sinking Current Limit Variation
14.0
12.0
10.0
8.0
28.0
26.0
24.0
22.0
20.0
18.0
16.0
14.0
12.0
-55 èC
25 èC
125 èC
-55 èC
25 èC
125 èC
6.0
4.0
3
3.5
4
4.5
5
VIN (V)
5.5
6
6.5
7
3
3.5
4
4.5
5
VIN (V)
5.5
6
6.5
7
图7-15. Low-Side Switch Resistance Variation
图7-16. High-Side Switch Resistance Variation
100%
90%
80%
70%
60%
50%
40%
30%
100%
90%
80%
70%
60%
50%
40%
30%
20%
20%
-55 èC
-55 èC
25 èC
25 èC
10%
10%
125 èC
125 èC
0
0
0
2
4
6
8
Output Current (A)
10
12
14
16
18
0
2
4
6
8
Output Current (A)
10
12
14
16
18
图7-17. Efficiency for VIN = 3.3 V, VOUT = 1 V at 图7-18. Efficiency for VIN = 5 V, VOUT = 1 V at 100-
100-kHz Switching Frequency kHz Switching Frequency
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100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
-55 èC
25 èC
-55 èC
25 èC
125 èC
125 èC
0
0
2
4
6
8
Output Current (A)
10
12
14
16
18
0
2
4
6
8
Output Current (A)
10
12
14
16
18
图7-19. Efficiency for VIN = 5 V, VOUT = 1.8 V at
图7-20. Efficiency for VIN = 5 V, VOUT = 2.5 V at
100-kHz Switching Frequency
100-kHz Switching Frequency
100%
90%
80%
70%
60%
50%
40%
30%
100%
90%
80%
70%
60%
50%
40%
30%
20%
20%
-55 èC
-55 èC
25 èC
25 èC
10%
10%
125 èC
125 èC
0
0
0
2
4
6
8
Output Current (A)
10
12
14
16
18
0
2
4
6
8
Output Current (A)
10
12
14
16
18
图7-21. Efficiency for VIN = 3 V, VOUT = 1 V at 500- 图7-22. Efficiency for VIN = 3 V, VOUT = 1.5 V at
kHz Switching Frequency 500-kHz Switching Frequency
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
-55 èC
25 èC
125 èC
-55 èC
25 èC
125 èC
0
2
4
6
8
Output Current (A)
10
12
14
16
18
0
2
4
6
8
Output Current (A)
10
12
14
16
18
图7-23. Efficiency for VIN = 3 V, VOUT = 1.8 V at
图7-24. Efficiency for VIN = 3 V, VOUT = 2.5 V at
500-kHz Switching Frequency
500-kHz Switching Frequency
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100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
-55 èC
25 èC
125 èC
-55 èC
25 èC
125 èC
0
2
4
6
8
Output Current (A)
10
12
14
16
18
0
2
4
6
8
Output Current (A)
10
12
14
16
18
图7-25. Efficiency for VIN = 5 V, VOUT = 1 V at 500- 图7-26. Efficiency for VIN = 5 V, VOUT = 1.5 V at
kHz Switching Frequency 500-kHz Switching Frequency
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
-55 èC
25 èC
125 èC
-55 èC
25 èC
125 èC
0
2
4
6
8
Output Current (A)
10
12
14
16
18
0
2
4
6
8
Output Current (A)
10
12
14
16
18
图7-27. Efficiency for VIN = 5 V, VOUT = 1.8 V at
图7-28. Efficiency for VIN = 5 V, VOUT = 2.5 V at
500-kHz Switching Frequency
500-kHz Switching Frequency
100%
90%
80%
70%
60%
50%
40%
30%
100%
90%
80%
70%
60%
50%
40%
30%
20%
20%
-55 èC
-55 èC
25 èC
25 èC
10%
10%
125 èC
125 èC
0
0
0
2
4
6
8
Output Current (A)
10
12
14
16
18
0
2
4
6
8
Output Current (A)
10
12
14
16
18
图7-29. Efficiency for VIN = 5 V, VOUT = 3.3 V at 图7-30. Efficiency for VIN = 7 V, VOUT = 1 V at 500-
500-kHz Switching Frequency kHz Switching Frequency
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100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
-55 èC
25 èC
-55 èC
25 èC
125 èC
125 èC
0
0
2
4
6
8
Output Current (A)
10
12
14
16
18
0
2
4
6
8
Output Current (A)
10
12
14
16
18
图7-31. Efficiency for VIN = 7 V, VOUT = 1.5 V at
图7-32. Efficiency for VIN = 7 V, VOUT = 1.8 V at
500-kHz Switching Frequency
500-kHz Switching Frequency
100%
90%
80%
70%
60%
50%
40%
30%
100%
90%
80%
70%
60%
50%
40%
30%
20%
20%
-55 èC
-55 èC
25 èC
25 èC
10%
10%
125 èC
125 èC
0
0
0
2
4
6
8
Output Current (A)
10
12
14
16
18
0
2
4
6
8
Output Current (A)
10
12
14
16
18
图7-33. Efficiency for VIN = 7 V, VOUT = 2.5 V at
图7-34. Efficiency for VIN = 7 V, VOUT = 3.3 V at
500-kHz Switching Frequency
500-kHz Switching Frequency
100%
90%
80%
70%
60%
50%
40%
30%
100%
90%
80%
70%
60%
50%
40%
30%
20%
20%
-55 èC
-55 èC
25 èC
25 èC
10%
10%
125 èC
125 èC
0
0
0
2
4
6
8
Output Current (A)
10
12
14
16
18
0
2
4
6
8
Output Current (A)
10
12
14
16
18
图7-35. Efficiency for VIN = 3 V, VOUT = 1 V at
图7-36. Efficiency for VIN = 3 V, VOUT = 1.5 V at
1000-kHz Switching Frequency
1000-kHz Switching Frequency
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100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
-55 èC
25 èC
125 èC
-55 èC
25 èC
125 èC
0
2
4
6
8
Output Current (A)
10
12
14
16
18
0
2
4
6
8
Output Current (A)
10
12
14
16
18
图7-37. Efficiency for VIN = 3 V, VOUT = 1.8 V at
图7-38. Efficiency for VIN = 3 V, VOUT = 2.5 V at
1000-kHz Switching Frequency
1000-kHz Switching Frequency
100%
90%
80%
70%
60%
50%
40%
30%
100%
90%
80%
70%
60%
50%
40%
30%
20%
20%
-55 èC
-55 èC
25 èC
25 èC
10%
10%
125 èC
125 èC
0
0
0
2
4
6
8
Output Current (A)
10
12
14
16
18
0
2
4
6
8
Output Current (A)
10
12
14
16
18
图7-39. Efficiency for VIN = 5 V, VOUT = 1 V at
图7-40. Efficiency for VIN = 5 V, VOUT = 1.5 V at
1000-kHz Switching Frequency
1000-kHz Switching Frequency
100%
90%
80%
70%
60%
50%
40%
30%
100%
90%
80%
70%
60%
50%
40%
30%
20%
20%
-55 èC
-55 èC
25 èC
25 èC
10%
10%
125 èC
125 èC
0
0
0
2
4
6
8
Output Current (A)
10
12
14
16
18
0
2
4
6
8
Output Current (A)
10
12
14
16
18
图7-41. Efficiency for VIN = 5 V, VOUT = 1.8 V at
图7-42. Efficiency for VIN = 5 V, VOUT = 2.5 V at
1000-kHz Switching Frequency
1000-kHz Switching Frequency
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100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
-55 èC
25 èC
-55 èC
25 èC
125 èC
125 èC
0
0
2
4
6
8
Output Current (A)
10
12
14
16
18
0
2
4
6
8
Output Current (A)
10
12
14
16
18
图7-43. Efficiency for VIN = 5 V, VOUT = 3.3 V at
图7-44. Efficiency for VIN = 7 V, VOUT = 1.8 V at
1000-kHz Switching Frequency
1000-kHz Switching Frequency
100%
90%
80%
70%
60%
50%
40%
30%
100%
90%
80%
70%
60%
50%
40%
30%
20%
20%
-55 èC
-55 èC
25 èC
25 èC
10%
10%
125 èC
125 èC
0
0
0
2
4
6
8
Output Current (A)
10
12
14
16
18
0
2
4
6
8
Output Current (A)
10
12
14
16
18
图7-45. Efficiency for VIN = 7 V, VOUT = 2.5 V at
图7-46. Efficiency for VIN = 7 V, VOUT = 3.3 V at
1000-kHz Switching Frequency
1000-kHz Switching Frequency
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
100 kHz
500 kHz
0
2
4
6
8
10
Output Current (A)
12
14
16
18
图7-47. Efficiency for VIN = 5 V, VOUT = 1 V at 100-kHz and 500-kHz Switching Frequency
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8 Detailed Description
8.1 Overview
The device is a 7-V, 18-A synchronous step-down (buck) converter with two integrated MOSFETs; a PMOS for
the high side and a NMOS for the low side. To improve performance during line and load transients, the device
implements a constant frequency, peak current mode control, which also simplifies external frequency
compensation. The wide switching frequency, 100 kHz to 1 MHz, allows for efficiency and size optimization when
selecting the output filter components. The integrated MOSFETs allow for high-efficiency power supply designs
with continuous output currents up to 18 A. The MOSFETs have been sized to optimize efficiency for lower duty
cycle applications.
The device is designed for safe monotonic startup into prebiased loads. The default start up is when VIN is
typically 2.75 V. The EN pin has an internal pullup current source that can be used to adjust the input voltage
UVLO with two external resistors. In addition, the EN pin can be floating for the device to operate with the
internal pullup current. The total operating current for the device is approximately 4 mA when not switching and
under no load. When the device is disabled, the supply current is typically 2.3 mA.
The device has a power-good comparator (PWRGD) with hysteresis, which monitors the output voltage through
the VSENSE pin. The PWRGD pin is an open-drain MOSFET, which is pulled low when the VSENSE pin voltage
is less than 91% or greater than 109% of the reference voltage VREF and asserts high when the VSENSE pin
voltage is 94% to 106% of the VREF.
The SS/TR (soft-start/tracking) pin is used to minimize inrush currents or provide power-supply sequencing
during power-up. A small-value capacitor or resistor divider should be coupled to the pin for soft-start or critical
power-supply sequencing requirements. If VSENSE is greater than the voltage at SS during startup, the device
will enter into a pulse-skipping mode.
The device is protected from output overvoltage, overload, and thermal fault conditions. The device minimizes
excessive output overvoltage transients by taking advantage of the overvoltage circuit power-good comparator.
When the overvoltage comparator is activated, the high-side MOSFET is turned off and prevented from turning
on until the VSENSE pin voltage is lower than 106% of the VREF. The device implements both high-side
MOSFET overload protection and bidirectional low-side MOSFET overload protections, which help control the
inductor current and avoid current runaway. The device also shuts down if the junction temperature is higher
than thermal shutdown trip point. The device is restarted under control of the soft-start circuit automatically when
the junction temperature drops 18°C (typical) below the thermal shutdown trip point.
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8.2 Functional Block Diagram
VIN
PVIN PVIN
PWRGD
EN
UVLO
Thermal
Shutdown
Shutdown
Enable
Comparator
Ip
Ih
2.75 V
Shutdown
UV
OV
Logic
1.14 V
UVLO
2.49 V
Current
Sense
Minimum Clamp
Pulse Skip
ERROR
AMPLIFIER
VIN
VSENSE
SS/TR
V/I
PVIN
SS/TR
Hysteretic
Control
VSENSE
HS MOSFET
Current
Comparator
Voltage
Reference
Power Stage
REFCAP
& Deadtime
Control
Logic
PH
PH
PVIN
Slope
Compensation
Overload Recovery
and
RT Bias
Oscillator
LS MOSFET
Current Limit
Clamp
Current
Sense
SYNC
Detect
PGND
PGND
COMP
RSC
Thermal Pad/GND
RT
SYNC1 SYNC2
8.3 Feature Description
8.3.1 VIN and Power VIN Pins (VIN and PVIN)
The device allows for a variety of applications by using the VIN and PVIN pins together or separately. The VIN
pin voltage supplies the internal control circuits of the device. The PVIN pin voltage provides the input voltage to
the power converter system. Both pins have an input voltage range from 3 V to 7 V. A voltage divider connected
to the EN pin can adjust the input voltage UVLO appropriately. Adjusting the input voltage UVLO on the PVIN pin
helps to provide consistent power-up behavior.
8.3.2 Voltage Reference
The device generates an internal 1.21-V bandgap reference that is utilized throughout the various control logic
blocks. This is the voltage present on the REFCAP and SS/TR pins during steady state operation. This voltage is
divided down to 0.604 V to produce the reference for the error amplifier. The error amplifier reference is
measured at the COMP pin to account for offsets in the error amplifier and maintains regulation within ±1.5%
across line, load, temperature, and TID (or ±1.7% for the SHP option) as shown in the Specifications. A 470-nF
capacitor to ground is required at the REFCAP pin for proper electrical operation as well as to ensure robust
SET performance of the device.
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8.3.3 Adjusting the Output Voltage
The output voltage is set with a resistor divider from the output (VOUT) to the VSENSE pin. TI recommends to
use 1% tolerance or better resistors. Start with a 10 kΩ for RTOP and use 方程式 1 to calculate RBOTTOM. To
improve efficiency at light loads, consider using larger-value resistors. If the values are too high, the regulator is
more susceptible to noise and voltage errors from the VSENSE input current are noticeable.
VREF
RBOTTOM
=
× RTOP
VOUT F VREF
(1)
where
• VREF = 0.604 V
8.3.4 Safe Start-Up Into Prebiased Outputs
The device prevents the low-side MOSFET from discharging a prebiased output lower than the configured output
voltage through the VSENSE pin.
8.3.5 Error Amplifier
The device uses a transconductance error amplifier. The error amplifier compares the VSENSE pin voltage to
the lower of the SS/TR pin voltage or the internal 0.604-V voltage reference. The transconductance of the error
amplifier is 1800 μA/V during normal operation. The frequency compensation network is connected between the
COMP pin and ground. The error amplifier DC gain is typically 10,000 V/V.
8.3.6 Enable and Adjust UVLO
The EN pin provides electrical on and off control of the device. When the EN pin voltage exceeds the threshold
voltage, the device enables operation. If the EN pin voltage is pulled below the threshold voltage, the regulator
stops switching and enters low Iq state. The EN pin has an internal pullup current source, allowing the user to
float the EN pin for enabling the device. If an application requires controlling the EN pin, use open-drain or open-
collector output logic to interface with the pin.
The device implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin voltage
falls below the internal VIN UVLO threshold. The internal VIN UVLO threshold has a hysteresis of 150-mV
typical.
If an application requires either a higher UVLO threshold on the VIN pin or a secondary UVLO on the PVIN in
split-rail applications, then the EN pin can be configured as shown in 图 8-1, 图 8-2, and 图 8-3. A ceramic
capacitor in parallel with the bottom resistor R2 is recommended to reduce noise on the EN pin as used in the
TPS7H4001-SP Evaluation Module. See the TPS7H4001EVM-CVAL Evaluation Module (EVM) User's Guide
(SLVUBO5) for more information.
The EN pin has a small pullup current, Ip, which sets the default state of the pin to enable when no external
components are connected. The pullup current is also used to control the voltage hysteresis for the UVLO
function because it increases by Ih after the EN pin crosses the enable threshold. Calculate the UVLO thresholds
with 方程式2 and 方程式3.
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TPS7H4001-SP
VIN
EN
ip
i
h
R1
R2
Copyright © 2017, Texas Instruments Incorporated
图8-1. Adjustable VIN UVLO
TPS7H4001-SP
PVIN
ip
i
h
R1
R2
EN
Copyright © 2017, Texas Instruments Incorporated
图8-2. Adjustable PVIN UVLO
TPS7H4001-SP
PVIN
VIN
ip
i
h
R1
EN
R2
Copyright © 2017, Texas Instruments Incorporated
图8-3. Adjustable VIN and PVIN UVLO
VENFALLING
VENRISING
VENFALLING
VENRISING
VSTART
×
F VSTOP
A + Ih
R1 =
Ip @1 F
(2)
(3)
R1 × VENFALLING
R2 =
VSTOP F VENFALLING + R1kIp + Iho
where
• Ih = 3 μA
• Ip = 6.1 μA
• VENRISING = 1.14 V
• VENFALLING = 1.11 V
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8.3.7 Adjustable Switching Frequency and Synchronization (SYNC)
The switching frequency of the device supports three modes of operations. The modes of operation are set by
the conditions on the RT, SYNC1, and SYNC2 pins. At a high level, these modes can be described as internal
oscillator, external synchronization, and primary-secondary operation modes.
8.3.7.1 Internal Oscillator Mode
In internal oscillator mode, a resistor is connected between the RT pin and GND to configure the switching
frequency, fSW, of the device. The switching frequency is adjustable from 100 kHz to 1 MHz depending on the
RT resistor value, which can be calculated using 方程式 4. 图 8-4 shows the relationship curve between the RT
resistor value and the configurable switching frequency range. It is recommended that the SYNC2 pin be
connected to GND for this mode of operation.
1.159
RT = 223260 × fSW
(4)
where
• RT in kΩ
• fSW in kHz
1100
1000
900
800
700
600
500
400
300
200
100
0
100 200 300 400 500 600 700 800 900 1000
Switching Frequency (kHz)
图8-4. RT vs Switching Frequency
8.3.7.2 External Synchronization Mode
In external synchronization mode, a resistor is connected between the RT pin and GND corresponding to the
external clock frequency as indicated in 方程式 4 and 图 8-4. Low tolerance resistor values should be used for
this purpose as this is necessary for proper slope compensation. The SYNC1 pin requires a toggling signal for
this mode to be effective. The input signal gets internally inverted and as a result, the switching frequency of the
device is 180° out of phase with that of SYNC1 pin. During the mode of operation, the SYNC1 pin connects to
the input clock and the SYNC2 pin must be connected to either GND or VIN depending on whether it is desired
to invert the clock SYNC1 receives. When SYNC2 is connected to GND, the clock provided on SYNC1 is
inverted. When SYNC2 is connected to VIN, the input clock signal on SYNC1 does not get inverted. As a result,
external synchronization mode can be used to connect 2, 3, or 4 devices in parallel using an external clock (at
any frequency between 100 kHz and 1 MHz) as long as the clocks used for each device are in the proper out of
phase configuration. If no external clock signal is detected for 20 µs, then the TPS7H4001-SP transitions to its
internal clock and a switching frequency that is determined by the value of the RT resistor. If no external clock is
available, then the primary-secondary operation mode can also be used to connect devices in parallel.
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8.3.7.3 Primary-Secondary Operation Mode
In primary-secondary mode, the RT pin of the primary device must be left floating. This sets the internal
switching frequency of the device, fSW to a typical 500 kHz and the SYNC1 pin becomes an output clock at the
same frequency and phase as fSW. In addition, the SYNC2 pin becomes an output clock at the same frequency
but at 90° out of phase with respect to SYNC1. This SYNC1 and SYNC2 output clock signals, in combination
with the state of the SYNC2 pins of the secondary devices, can be used to connect 2, 3, or 4 devices in parallel
configuration. 图 8-5 shows the SYNC1 and SYNC2 clock signals when the RT pin is floating in the primary
device and how the signals can be used to generate the 90° out of phase clocks needed to connect 4 devices in
parallel configuration (1 primary and 3 secondaries). The SYNC1b and SYNC2b indicate the clock signals being
inverted either internally or due to the state of the SYNC2 pin in the secondary devices. When SYNC2 is
connected to GND, the inverse functionality of the input clock signal in SYNC1 remains the same. When SYNC2
is connected to VIN, the input clock signal in SYNC1 does not get inverted. The RT pin of the secondary devices
must have a resistor to GND corresponding to 500 kHz as indicated in 方程式 4 and 图 8-4. Low tolerance
resistor values should be used for this purpose as this is necessary for proper slope compensation.
90°
270°
90°
270°
Primary fsw
SYNC1
Primary fsw
Secondary 1 fsw
Secondary 2 fsw
Secondary 3 fsw
SYNC2
180°
180°
图8-5. SYNC1 and SYNC2 Clock Signals in Primary-Secondary Mode
图 8-6 shows the SYNC1 and SYNC2 output signals from the primary device as well as signals and connections
needed to operate 4 devices in parallel configuration. The fSW clock signal by each device represents the
switching frequency signal for the respective device.
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TPS7H4001-SP
RT
fsw Primary
SYNC1_PRIMARY
SYNC2_PRIMARY
SYNC1
SYNC2
Primary
TPS7H4001-SP
RT
SYNC2_PRIMARY
SYNC1
SYNC2
90°
VIN
fsw Secondary 1
Secondary 1
TPS7H4001-SP
SYNC1_PRIMARY
RT
180°
SYNC1
SYNC2
fsw Secondary 2
Secondary 2
TPS7H4001-SP
RT
SYNC2_PRIMARY
sw Secondary 3
270°
SYNC1
SYNC2
f
Secondary 3
图8-6. Parallel Operation With SYNC1 and SYNC2 Pins
The 3 modes previously described are summarized in 表8-1.
表8-1. Switching Frequency, SYNC, and RT Pin Usage Table
MODE
RT PIN
SYNC1 PIN
SYNC2 PIN
SWITCHING FREQUENCY
Configurable using internal
oscillator from 100 kHz to 1
MHz depending on RT
resistor value
Internal oscillator
Floating
GND
Resistor to GND based
on 图8-4
Internally synchronized to
external clock between 100
kHz to 1 MHz
External
synchronization
External input clock. Signal
will be inverted internally
GND or VIN
Outputs 500-kHz clock in
Outputs 500-kHz clock at
Primary
Float
phase with internal switching 90° out of phase with
500 kHz
frequency
internal switching frequency
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8.3.8 Soft-Start (SS/TR)
The device uses the lower voltage of the internal voltage reference or the SS/TR pin voltage as the reference
voltage and regulates the output accordingly. A CSS capacitor on the SS/TR pin to GND implements a soft-start
time. 方程式 5 shows the equation for the nominal soft-start time, tSS. This is the time it will take VOUT to go
from 10% to 90% of the programmed voltage. The voltage reference (VREF) is 0.604 V and the soft-start charge
current (ISS) is 2.5 μA. When calculating the soft-start time tSS, it is important to take into account the variation
of the parameters CSS, VREF and ISS as these may cause tSS to deviate from the nominal value in the actual
implementation.
0.8 × CSS (nF) × VREF (V)
:
;
tSS ms =
ISS (µA)
(5)
When any of the following four scenarios occur the SS/TR pin is discharged:
• the input UVLO is triggered,
• the EN pin is pulled below 1.05 V,
• the high-side switch current limit threshold is exceeded, or
• a thermal shutdown event occurs
With the exception of the scenario where the high-side current limit threshold is exceeded, the device will then
stop switching and enter into low current operation. At the subsequent power-up, when the shutdown condition is
removed, the device does not start switching until it has discharged its SS/TR pin to ground ensuring proper soft-
start behavior.
The device will enter into a pulse-skipping mode during startup in the event that VSENSE is greater than the
voltage at the SS/TR pin. During this period, the high-side switch will remain off and the low-side switch will
remain on until VSENSE again falls below the voltage at SS/TR.
8.3.9 Power Good (PWRGD)
The PWRGD pin is an open-drain output. When the VSENSE pin is between 94% and 106% of the internal
voltage reference, the PWRGD pin pulldown is deasserted and the pin floats. TI recommends to use a pullup
resistor between 10 kΩ to 100 kΩ to a voltage source that is equal to or less than VIN. The PWRGD is in a
defined state when the VIN input voltage is greater than 1 V but has reduced current sinking capability. The
PWRGD achieves full current sinking capability when the VIN input voltage is above 3 V.
The PWRGD pin is pulled low when VSENSE is lower than 91% or greater than 109% of the nominal internal
reference voltage. Also, the PWRGD is pulled low if:
• the input UVLO or thermal shutdown are asserted,
• the EN pin is pulled low, or
• the SS/TR pin is below 1.1 V.
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8.3.10 Sequencing
Many of the common power-supply sequencing methods can be implemented using the SS/TR, EN, and
PWRGD pins.
The sequential method is shown in 图8-7 using two TPS7H4001-SP devices. The PWRGD pin of the first device
is coupled to the EN pin of the second device, which enables the second power supply after the primary supply
reaches regulation.
TPS7H4001-SP
TPS7H4001-SP
VIN
PWRGD
EN
EN
SS/TR
SS/TR
PWRGD
Copyright © 2017, Texas Instruments Incorporated
图8-7. Sequential Start-Up Sequence
图 8-8 shows the method implementing ratiometric sequencing by connecting the SS/TR pins of two devices
together. The regulator outputs ramp up and reach regulation at the same time. When calculating the soft-start
time, the pullup current source must be doubled in 方程式 5 as there is only one SS/TR capacitor. A similar
situation applies if a resistor divider is used in the EN pin, that is, only one resistor divider is needed and the
factor of 2 must be taken into account when calculating the resistor values. This ratiometric connection is the one
used in primary mode as described in the Adjustable Switching Frequency and Synchronization (SYNC) section.
TPS7H4001-SP
EN
SS/TR
PWRGD
TPS7H4001-SP
EN
SS/TR
PWRGD
Copyright © 2017, Texas Instruments Incorporated
图8-8. Ratiometric Start-Up Sequence
Ratiometric and simultaneous power-supply sequencing can be implemented by connecting the resistor network
of R1 and R2 (shown in 图 8-9) to the output of the power supply that needs to be tracked or another voltage
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reference source. Using 方程式 6 and 方程式 7, the tracking resistors can be calculated to initiate the VOUT2
slightly before, after, or at the same time as VOUT1. 方程式 8 is the voltage difference between VOUT1 and
VOUT2.
To design a ratiometric start-up in which the VOUT2 voltage is slightly greater than the VOUT1 voltage when
VOUT2 reaches regulation, use a negative number in 方程式 6 and 方程式 7 for ΔV. 方程式 8 results in a
positive number for applications where the VOUT2 is slightly lower than VOUT1 when VOUT2 regulation is
achieved.
The ΔV variable is 0 V for simultaneous sequencing. To minimize the effect of the inherent SS/TR to VSENSE
offset (VSS-OFFSET = 30 mV) in the soft-start circuit and the offset created by the pullup current source (ISS = 2.5
μA) and tracking resistors, the VSS-OFFSET and ISS are included as variables in the equations.
To ensure proper operation of the device, the calculated R1 value from 方程式 6 must be greater than the value
calculated in 方程式9.
VOUT2 + ¿V VSSFOFFSET
R1 =
×
VREF
VREF × R1
VOUT2 + ¿V F VREF
ISS
(6)
R2 =
(7)
(8)
(9)
¿V = VOUT F VOUT2
1
R1 > 2800 × VOUT F 180 × ¿V
1
TPS7H4001-SP
EN
VOUT1
SS/TR
VSENSE1
PWRGD
TPS7H4001-SP
EN
VOUT2
R1
R2
VSENSE2
SS/TR
PWRGD
Copyright © 2017, Texas Instruments Incorporated
图8-9. Ratiometric and Simultaneous Start-Up Sequence
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8.3.11 Output Overvoltage Protection (OVP)
The device incorporates an output OVP circuit to minimize output voltage overshoot. For example, when the
power supply output is overloaded, the error amplifier compares the actual output voltage to the internal
reference voltage. If the VSENSE pin voltage is lower than the internal reference voltage for a considerable time,
the output of the error amplifier demands maximum output current. After the condition is removed, the regulator
output rises and the error amplifier output transitions to the steady-state voltage. In some applications with small
output capacitance, the power supply output voltage can respond faster than the error amplifier. This leads to the
possibility of an output overshoot. The OVP feature minimizes the overshoot by comparing the VSENSE pin
voltage to the OVP threshold. If the VSENSE pin voltage is greater than the OVP threshold, the high-side
MOSFET is turned off, preventing current from flowing to the output and minimizing output overshoot. When the
VSENSE voltage drops lower than the OVP threshold, the high-side MOSFET is allowed to turn on at the next
clock cycle.
8.3.12 Overcurrent Protection
The device is protected from overcurrent conditions with cycle-by-cycle current limiting on both the high-side and
low-side MOSFET.
8.3.12.1 High-Side MOSFET Overcurrent Protection
The device implements current mode control, which uses the COMP pin voltage to control the turn off of the
high-side MOSFET and the turn on of the low-side MOSFET on a cycle-by-cycle basis. Each cycle the switch
current and the current reference generated by the COMP pin voltage are compared, when the peak switch
current intersects the current reference, the high-side switch is turned off. In the event of an overcurrent
detection, the following sequence of events occurs:
• The SS/TR pin is discharged
• When the voltage at SS/TR falls below VSENSE, the device will stop switching
• As VOUT decreases, VSENSE does as well. At the point when VSENSE is equal to the voltage at SS/TR, the
device will begin switching again.
8.3.12.2 Low-Side MOSFET Overcurrent Protection
While the low-side MOSFET is turned on its conduction current is monitored by the internal circuitry. During
normal operation the low-side MOSFET sources current to the load. At the end of every clock cycle, the low-side
MOSFET sourcing current is compared to the internally set low-side sourcing current limit. If the low-side
sourcing current is exceeded, the high-side MOSFET is not turned on and the low-side MOSFET stays on for the
next cycle. The high-side MOSFET is turned on again when the low-side current is below the low-side sourcing
current limit at the start of a cycle.
The low-side MOSFET may also sink current from the load. If the low-side sinking current limit is exceeded, the
low-side MOSFET is turned off immediately for the rest of that clock cycle. In this scenario, both MOSFETs are
off until the start of the next cycle.
When the low-side MOSFET turns off, the switch node voltage increases and forward biases the high-side
MOSFET parallel diode (the high-side MOSFET is still off at this stage).
8.3.13 Thermal Shutdown
The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds
190°C (typical). The device reinitiates the power-up sequence when the junction temperature drops below 172°C
(typical).
8.3.14 Turn-On Behavior
Minimum on-time specification determines the maximum operating frequency of the design. During soft-start, if
the required duty cycle is less than the minimum controllable on-time, the device can enter into a pulse-skipping
mode. Thus, instantaneous output pulses can be higher or lower than the desired voltage. This behavior is only
evident when operating at high frequency with high bandwidth. When the minimum on-pulse is greater than the
minimum controllable on-time, the turn-on behavior is normal.
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8.3.15 Slope Compensation
The device adds a compensating ramp to the switch current signal for all duty cycles. The slope compensation
adjusts the peak current during the charging of the inductor to avoid instability of the system. As a result, the
ideal slope compensation is defined as the output voltage divided by the inductor size as shown in 方程式 10.
The slope compensation, SC, can be configured with a resistor to GND connected to the RSC pin. The RSC
resistor value, in kΩ, can be calculated using 方程式11, where SC is in A/µs and fSW is in kHz.
di VOUT
SCideal
=
=
dt
L
(10)
(11)
24000 1040
RSC =
+
F 30
fSW
SC
8.3.15.1 Slope Compensation Requirements
All the design parameters are relevant when configuring the slope compensation. The first requirement is that
the inductor peak current ILpeak must be less than the compensated maximum high side FET current, ILmax as
shown in 方程式12.
ILpeak < ILmax
(12)
ILpeak can be calculated as shown in 方程式13, where KL relates Iripple the inductor ripple current, to IO the output
current, as shown in 方程式14.
Iripple
KL × IO
2
ILpeak = IO +
= IO +
2
(13)
Iripple
KL =
IO
(14)
ILmax is defined as the difference between the high side current limit specified in the Electrical Characteristics,
and the change in current due to the ramp, ISC as shown in 方程式 15. ISC can be calculated using 方程式 16,
where tON is the on time for the high side FET. tON depends on the switching frequency and is related to the duty
cycle as shown in 方程式17.
ILmax = IHS_IL F ISC
(15)
ISC = SC × tON
(16)
1
1
VOUT
VIN
tON
=
× D =
×
fSW
fSW
(17)
The last requirement related to the slope compensation is related to the maximum value for KL depending on the
SC value selected so that the desired IO can be supported. In other words, the maximum value for KL such that
ILpeak is less than ILmax. By substituting 方程式 16 and 方程式 17 into the combinations of 方程式 13 and 方程式
15, the equation for the maximum value for KL can be derived as shown in 方程式18.
SC VOUT
IHS_IL
F
@
F 0.25A
fSW VIN
KLmax < 2 f
F 1j
IO
(18)
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8.3.16 Small Signal Model for Frequency Compensation
The device uses a transconductance amplifier for the error amplifier and readily supports two of the commonly
used frequency compensation circuits shown in 图8-10. In Type 2A, one additional high-frequency pole is added
to attenuate high-frequency noise.
The following design guidelines are provided for advanced users who prefer to compensate using the general
method.
VOUT
R1
VSENSE
Type 2A
Type 2B
COMP
Coea
Vref
R3
C1
gm
C2
R3
C1
ea
Roea
R2
图8-10. Types of Frequency Compensation
The general design guidelines for device loop compensation are as follows:
1. Determine the crossover frequency fco. A good starting point is one-tenth of the switching frequency, ƒSW
.
2. R3 can be determined by:
tN × fco × VOUT × COUT
R3 =
gmea × VREF × gmps
(19)
where gmea is the transconductance of the error amplifier (1800 μS), gmps is the transconductance of the
power stage (40 S) and VREF is the reference voltage (0.604 V).
3. Place a compensation zero at the dominant pole calculated in 方程式20 using C1 and R3.
C1 can be determined by 方程式21.
1
fp =
COUT × RL × tN
(20)
(21)
COUT × RL
R3
C1 =
4. C2 is optional. It can be used to cancel the zero from the equivalent series resistance (ESR) of the output
capacitor COUT
.
COUT × RESR
R3
C2 =
(22)
8.4 Device Functional Modes
8.4.1 Fixed-Frequency PWM Control
The device uses fixed frequency, peak current mode control. As a synchronous buck converter, the device
normally operates in continuous current mode under all load conditions. The output voltage is compared through
external resistors on the VSENSE pin to an internal voltage reference by an error amplifier, which drives the
COMP pin. An internal oscillator initiates the turn on of the high-side power switch. The error amplifier output is
converted into a current reference, which compares to the high-side power switch current. When the power
switch current reaches the current reference generated by the COMP voltage level, the high-side power switch is
turned off and the low-side power switch is turned on.
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9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The TPS7H4001-SP device is a highly-integrated synchronous step-down DC-DC converter. The device is used
to convert a higher DC-DC input voltage to a lower DC output voltage with a maximum output current of 18 A.
The TPS7H4001-SP user's guide is available on the TI website, TPS7H4001EVM-CVAL Evaluation Module
(EVM) User's Guide (SLVUBO5). The guide highlights standard EVM test results, schematic, and BOM for
reference.
9.2 Typical Application
VIN
PWRGD
VOUT
PWRGD
PHASE
PVIN
VIN
EN
VSENSE
EN
TPS7H4001-SP
RSC
SSTR
RT
PGND
GND
THERMAL PAD
COMP
图9-1. Typical Application Schematic
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9.2.1 Design Requirements
This example highlights a design using the TPS7H4001-SP based on its evaluation module. For more details,
please refer to the EVM user's guide, TPS7H4001EVM-CVAL Evaluation Module (EVM) User's Guide
(SLVUBO5). A few parameters must be known in order to start the design process. These parameters are
typically determined at the system level. For this example, we start with the following known parameters:
表9-1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Output voltage
1 V
Maximum output current
Transient response 9-A load step
Input voltage
18 A
ΔVOUT = 5%
5 V
Output voltage ripple
20 mVp-p
4.5 V
Start input voltage (rising VIN)
Stop input voltage (falling VIN)
Switching frequency
4.3 V
500 kHz
9.2.2 Detailed Design Procedure
9.2.2.1 Operating Frequency
The first step is to decide on a switching frequency for the regulator. There is a trade off between higher and
lower switching frequencies. Higher switching frequencies may produce smaller a solution size using lower
valued inductors and smaller output capacitors compared to a power supply that switches at a lower frequency.
However, the higher switching frequency causes extra switching losses, which hurt the converter’s efficiency
and thermal performance. In this design, a switching frequency of 500 kHz is selected. Since the regulator can
internally generate a 500-kHz switching frequency, no RT resistor is necessary but can be used if desired.
9.2.2.2 Output Inductor Selection
To calculate the value of the output inductor, use 方程式 23. KL is a coefficient that represents the amount of
inductor ripple current relative to the maximum output current, IO as shown in 方程式 14. The inductor ripple
current is filtered by the output capacitor, therefore, choosing high inductor ripple currents impact the selection of
the output capacitor since the output capacitor must have a ripple current rating equal to or greater than the
inductor ripple current. In general, the inductor ripple value is at the discretion of the designer depending on
specific system needs. Typical values for KL range from 0.1 to 0.5. For low output currents, the value of KL could
be increased to reduce the value of the output inductor.
V
F VOUT
VOUT
V × fSW
INMAX
INMAX
L =
×
IO × KL
(23)
For this design example, use KL = 0.1 and the inductor value is calculated to be 0.9 µH for nominal VIN = 5 V.
For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded.
The RMS and peak inductor current can be found from 方程式25 and 方程式26.
V
INMAX
F VOUT
VOUT
V × fSW
INMAX
Iripple
=
×
L
(24)
(25)
2
:
;
F VOUT
INMAX
1
VOUT × V
2
¨
IO
ILrms
=
+
× F
G
12
V
× L × fSW
INMAX
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Iripple
ILpeak = IO +
2
(26)
For this design, the RMS inductor current is 18 A and the peak inductor current is 18.9 A. To satisfy this
requirement, two Coilcraft SER1360 inductors are used in parallel. These inductors have a saturation current
rating of 17 A and a RMS current rating of 9.5 A.
The current flowing through the inductor is the inductor ripple current plus the output current. During power up,
faults or transient load conditions, the inductor current can increase above the calculated peak inductor current
level calculated previously. In transient conditions, the inductor current can increase up to the switch current limit
of the device. For this reason, the most conservative approach is to specify an inductor with a saturation current
rating equal to or greater than the switch current limit rather than the peak inductor current.
9.2.2.3 Output Capacitor Selection
There are several considerations in determining the value of the output capacitor. The selection of the output
capacitor is driven by both the desired output voltage ripple and the allowable voltage deviation due to a large
and abrupt change in load current. For space applications, the value of capacitance also has to account for the
mitigation of single event effects (SEE). The output capacitance needs to be selected based on the more
stringent of these three criteria. It is also important to note that the value of the output capacitor directly
influences the modulator pole of the converter frequency response, as shown in Small Signal Model for
Frequency Compensation.
The desired response to a large change in the load current is the first criteria. The output capacitor needs to
supply the load with current when the regulator can not. This situation would occur if there are desired hold-up
times for the regulator where the output capacitor must hold the output voltage above a certain level for a
specified amount of time after the input power is removed. The regulator is also temporarily not able to supply
sufficient output current if there is a large, fast increase in the current needs of the load such as a transition from
no load to full load. The output capacitor must be sized to supply the extra current to the load until the control
loop responds to the load change. 方程式 27 shows the minimum output capacitance, from the electrical point of
view, necessary to accomplish this.
2 × ¿IO
COUT
>
fSW × ¿VOUT
(27)
Where ΔIO is the change in output current, fSW is the regulator switching frequency, and ΔVOUT is the
allowable change in the output voltage. For this example, the transient load response is specified as a 5%
change in VOUT for a load step of 9 A. Also in this example, ΔIO = 9 A and ΔVOUT = 0.05 × 1 = 0.05 V. Using
these numbers gives a minimum capacitance of 720 μF. This value does not take the ESR of the output
capacitor into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to
ignore in this calculation. However, for space applications and large capacitance values, tantalum capacitors are
typically used, which have a certain ESR value to take into consideration.
方程式 28 calculates the minimum output capacitance needed to meet the output voltage ripple specification.
Where fSW is the switching frequency, VOUTripple is the maximum allowable output voltage ripple, and Iripple is the
inductor ripple current. In this case, the maximum output voltage ripple is 20 mV and the inductor ripple current is
1.8 A. Under these conditions, 方程式28 yields 22.5 µF.
Iripple
8 × fSW VOUT
1
COUT
>
×
ripple
(28)
Additional capacitance de-ratings for aging, temperature and DC bias should be factored in, which increases this
minimum value. Capacitors generally have limits to the amount of ripple current they can handle without failing or
producing excess heat. An output capacitor that can support the inductor ripple current must be specified. Some
capacitor data sheets specify the RMS (Root Mean Square) value of the maximum ripple current. 方程式 25 can
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be used to calculate the RMS ripple current the output capacitor needs to support. For this application, 方程式25
yields 519 mA.
方程式 29 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification. 方程式29 indicates the ESR should be less than 11.11 mΩ.
VOUT
ripple
RESR
<
Iripple
(29)
For this specific design, taking into consideration the stringent requirements for space applications, a total output
capacitance of 2 mF with an equivalent ESR of approximately 2 mΩhas been selected.
9.2.2.4 Input Capacitor Selection
The TPS7H4001-SP requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 4.7
µF of effective capacitance on the PVIN input voltage pins, and 4.7 µF on the VIN input voltage pin. In some
applications additional bulk capacitance may also be required for the PVIN input. The effective capacitance
includes any DC bias effects. The voltage rating of the input capacitor must be greater than the maximum input
voltage. The capacitor must also have a ripple current rating greater than the maximum input current ripple of the
TPS7H4001-SP. The input ripple current can be calculated using 方程式30.
VOUT
(V
F VOUT )
IN_MIN
ICINrms = IO × ¨
×
V
IN_MIN
V
IN_MIN
(30)
The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the
capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that
is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors
because they have a high capacitance to volume ratio and are fairly stable over temperature. The output
capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor
decreases as the DC bias across a capacitor increases. For this example design, a ceramic capacitor with at
least a 25-V voltage rating is required to support the maximum input voltage. For this example, six 22-μF and
two 470-µF 25-V capacitors in parallel have been selected as the VIN and PVIN inputs are tied together so the
TPS7H4001-SP may operate from a single supply. The input capacitance value determines the input ripple
voltage of the regulator. The input voltage ripple can be calculated using 方程式 31. Using the design example
values, IOMAX = 18 A, CIN = 1.072 mF, fSW = 500 kHz, yields an input voltage ripple of 8.4 mV and a RMS input
ripple current of 7.2 A.
IOMAX × 0.25
¿VIN =
CIN × fSW
(31)
9.2.2.5 Soft-Start Capacitor Selection
The soft-start capacitor CSS, determines the minimum amount of time it takes for the output voltage to reach its
nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This
is also used if the output capacitance is very large and would require large amounts of current to quickly charge
the capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the
TPS7H4001-SP reach the current limit or excessive current draw from the input power supply may cause the
input voltage rail to sag. Limiting the output voltage slew rate solves both of these problems. The soft-start
capacitor value can be calculated using 方程式 5. The example circuit has the soft-start time set to an arbitrary
value of about 2 ms, which requires a 10-nF capacitor. In TPS7H4001-SP, ISS is 2.5-µA typical, and VREF is
0.604 V.
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9.2.2.6 Undervoltage Lockout (UVLO) Set Point
The UVLO can be adjusted using the external voltage divider network formed by R1 and R2. R1 is connected
between VIN and the EN pin of the TPS7H4001-SP and R2 is connected between EN and GND. The UVLO has
two thresholds, one for power up when the input voltage is rising and one for power down or brown outs when
the input voltage is falling. For the example design, the supply should turn on and start switching once the input
voltage increases above selected voltage (UVLO start or enable). After the regulator starts switching, it should
continue to do so until the input voltage falls below (UVLO stop or disable) voltage. 方程式 2 and 方程式 3 can
be used to calculate the values for the upper and lower resistor values. For the stop voltages specified in 表 9-1,
the nearest standard resistor value for R1 is 10 kΩand for R2 is 3.4 kΩ.
9.2.2.7 Output Voltage Feedback Resistor Selection
The resistor divider network RTOP and RBOTTOM is used to set the output voltage. For the example design, 10 kΩ
was selected for RTOP. Using 方程式 1, RBOTTOM is calculated as 15.32 kΩ. The nearest standard 1% resistor is
15.4 kΩ.
9.2.2.7.1 Minimum Output Voltage
Due to the internal design of the TPS7H4001-SP, there is a minimum output voltage limit for any given input
voltage. The output voltage can never be lower than the internal voltage reference of 0.604 V. Above 0.604 V,
the output voltage may be limited by the minimum controllable on time. The minimum output voltage in this case
is given by 方程式32.
VOU TMIN = V
× tON ,MIN × fsw
INMIN
(32)
In this equation:
• VOUTMIN is the minimum output voltage
• VINMIN is the minimum input voltage for the application
• tON,MIN is the minimum on-time for the device, for which the maximum specification is 235 ns
• fsw is the switching frequency of the application.
9.2.2.8 Compensation Component Selection
There are several industry techniques used to compensate DC-DC regulators. For this design, type 2B
compensation is used as shown in the Small Signal Model for Frequency Compensation section.
A good starting rule of thumb is to set the crossover frequency to one-tenth of the switching frequency. This will
generally provide good transient response and ensure that the modulator poles do not degrade phase margin.
The compensation components can be calculated using 方程式 19 and 方程式 21. The values calculated for R3
and C1 are 8.66 kΩand 12 nF, respectively.
An additional high frequency pole can be used if necessary by adding a capacitor in parallel with the series
combination of R3 and C1. The pole frequency is given by 方程式33.
1
fp =
tN × R3 × C2
(33)
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9.2.3 Parallel Operation
The TPS7H4001-SP can be configured in primary-secondary mode to provide up to 72-A output current. For
more details, please refer to the EVM user's guide, TPS7H4001QEVM-CVAL Evaluation Module (EVM) User's
Guide (SLVUBW7). 图9-2 shows a parallel configuration that can be used to provide 36-A output.
VIN
PVIN
VIN
PWRGD
PHASE
VOUT
L
COUT
RTOP
R1
VSENSE
EN
VSENSE
RBOTTOM
EN
TPS7H4001-SP
(Primary)
R2
SYNC1
SYNC2
REFCAP
RSC
470 nF
SSTR
SSTR
RT
PGND
GND
RSC
COMP
THERMAL PAD
COMP
CSS
R3
C1
C2
VIN
PVIN
VIN
PWRGD
PHASE
L
COUT
VSENSE
VSENSE
EN
EN
TPS7H4001-SP
(Secondary)
SYNC1
SYNC2
REFCAP
RSC
470 nF
SSTR
SSTR
RT
PGND
GND
RSC
COMP
THERMAL PAD
COMP
RT
图9-2. Parallel Configuration Showing Primary and Secondary
The design procedure to configure the primary-secondary operation using the internal oscillator is as follows:
• The RT pin of the primary device must be left floating. This achieves two purposes, to set the frequency to
500 kHz (typical) using the internal oscillator and to configure the SYNC1 and SYNC2 pins of the primary
device as output pins with a 500-kHz clock, in-phase and 90° out of phase, respectively to the internal
oscillator of the primary device. For more details, see Adjustable Switching Frequency and Synchronization
(SYNC) section.
• The RT pin on secondary device should be connected to a resistor such that the frequency of the secondary
device matches the primary's frequency, 500 kHz in this case. See 图8-4 for reference.
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• SYNC1 and/or SYNC2 pin of the primary device must be connected to the SYNC1 pin of the secondary
device(s).
• Only a single feedback network is connected to the VSENSE pin of the primary device. Therefore, all
VSENSE pins must be connected.
• Only a single compensation network is needed connected to the COMP pin of the primary device. Therefore
all COMP pins must be connected.
• Only a single soft-start capacitor is needed connected to the SS pin of the primary device. Therefore all SS
pins must be connected.
• Only a single enable signal (or resistor divider) is needed connected to the EN pin of the primary device.
Therefore all EN pins must be connected.
• Since the primary device controls the compensation, soft-start and enable networks, the factor of n must be
taken into account when calculating the components associated with these pins, where n is the number of
devices in parallel.
The primary-secondary mode can also be implemented using an external clock. In such case, a different
frequency other than 500 kHz can be used. When using an external clock, the RT and SYNC pin configurations
vary as follows:
• RT pins of both primary and secondary device must be connected to a resistor matching the frequency of the
external clock being used. See 图8-4 for reference.
• The external clock is connected to the SYNC1 pin of the primary device. A 10-kΩresistor to GND should be
connected to the SYNC1 pin as well.
• For two devices in parallel, an inverted clock (180° out of phase respect to the primary device) must be
connected to the SYNC1 pin of the secondary device. A 10-kΩresistor to GND should be connected to the
SYNC1 pin as well. The SYNC2 pins of the primary and secondary devices should be connected to VIN.
• Another option for two devices in parallel is to use a single clock connected to the SYNC1 pins of both
devices, with the SYNC2 pin of the primary device connected to VIN and the SYNC2 pin of the secondary
device connected to GND.
• For four devices in parallel, the SYNC1 pin of each device can be supplied with a separate clock, each phase
shifted 90° with respect to the other. In this configuration, all SYNC2 pins should be connected to VIN. There
is also an option where two clocks can be used, where the second clock is phase shifted 90° with respect to
the first. In this instance, the table below details how the SYNC1 and SYNC2 pins of each device should be
configured.
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VIN
PVIN
VIN
PWRGD
PHASE
VOUT
L
COUT
RTOP
R1
VSENSE
EN
VSENSE
RBOTTOM
EN
TPS7H4001-SP
(Primary)
R2
EXT. SYNC
SYNC1
SYNC2
REFCAP
RSC
VIN
SS/TR
470 nF
SS/TR
RT
PGND
GND
RSC
COMP
R3
C1
THERMAL PAD
COMP
CSS
RT
C2
VIN
PVIN
VIN
PWRGD
PHASE
L
COUT
VSENSE
VSENSE
EN
EN
TPS7H4001-SP
(Secondary)
SYNC1
SYNC2
REFCAP
RSC
470 nF
SS/TR
COMP
SS/TR
RT
PGND
GND
RSC
THERMAL PAD
COMP
RT
图9-3. Parallel Configuration With External Sync
表9-2. Pin Connections for Four Parallel Devices Using External Sync and Two Clocks
Device
SYNC1 Pin
SYNC2 Pin
1
2
3
4
Clock 1
VIN
Clock 2
VIN
Clock 1
GND
Clock 2
GND
The operation of multiple devices in parallel has an impact on some of the component calculations. For instance,
since the enable pins are all connected together, the UVLO calculation as presented in the Enable and Adjust
UVLO section will be modified according to the following equations, in which n is the number of paralleled
devices:
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VENFALLING
VSTART
×
F VSTOP
VENRISING
VENFALLING
VENRISING
R1 =
n × Ip @1 F
A + (n × Ih)
(34)
(35)
R1 × VENFALLING
R2 =
:
;
VSTOP F VENFALLING + n × R1 (Ip + Ih)
Also, since all SS/TR pins will be connected for the paralleled devices, the soft-start calculation presented in the
Soft-Start (SS/TR) section will be modified according to the following equation:
0.8 × CSS (nF) × VREF (V)
:
;
tSS ms =
n × ISS (JA)
(36)
The compensation design is detailed in the Small Signal Model for Frequency Compensation section. The
equation for R3 changes when the COMP pins of the devices in parallel are connected:
tN × fco × VOUT × COUT
n × gmea × VREF × n × gmps n2 × gmea × VREF × gmps
tN × fco × VOUT × COUT
R3 =
=
(37)
Note that for parallel operation, the equations for the other compensation components, C1 and C2, will remain
unchanged and still be calculated as shown in 方程式21 and 方程式22 due to the updated R3 calculation.
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9.2.4 Application Curve
The evaluation module for the TPS7H4001-SP was used to capture a load step response of the device. The
testing conditions were:
• VIN = PVIN = 5 V
• VOUT = 1 V
• Load step = 9 A to 18 A
• Switching frequency = 500 kHz
图9-4. 9-A Step Response for 500-kHz Switching Operation
图9-5. Switch Node Waveform (PH) and Output Voltage Ripple for 500-kHz Switching Operation
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9.3 Power Supply Recommendations
The TPS7H4001-SP is designed to operate from an input voltage supply range between 3 V and 7 V. This
supply voltage must be well regulated. Power supplies must be well bypassed for proper electrical performance.
This includes a minimum of one 4.7 µF (after de-rating) ceramic capacitor, type X5R or better from PVIN to
GND, and from VIN to GND. Additional local ceramic bypass capacitance may be required in systems with small
input ripple specifications, as well as additional bulk capacitance if the TPS7H4001-SP device is located more
than a few inches away from its input power supply. Bypass capacitors should be placed as close as possible to
the input pins and have a low impedance path to GND.
Larger values of bypass capacitance will improve the response to radiation induced transients. The TPS7H4001-
SP Evaluation Module uses 6 × 22-µF capacitors in addition to 2 × 470-µF capacitors in parallel on the PVIN
input. In systems with an auxiliary power rail available, the power stage input, PVIN, and the analog power input,
VIN, may operate from separate input supplies.
9.4 Layout
9.4.1 Layout Guidelines
• Layout is a critical portion of good power supply design. See the Layout Example section for a PCB layout
example.
• It is recommended to include a large topside area filled with ground. This top layer ground area should be
connected to the internal ground layer(s) using vias at the input bypass capacitor, the output filter capacitor,
and directly under the TPS7H4001-SP device to provide a thermal path from the exposed thermal pad land to
ground. For operation at full rated load, the top side ground area together with the internal ground plane must
provide adequate heat dissipating area.
• The GND pin should be tied directly to the thermal pad under the IC.
• There are several signals paths that conduct fast changing currents or voltages that can interact with stray
inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help
eliminate these problems, the PVIN pin should be bypassed to ground with a low ESR ceramic bypass
capacitor with X5R or X7R dielectric.
• Care should be taken to minimize the loop area formed by the bypass capacitor connections, the PVIN pins,
and the ground connections.
• The VIN pin must also be bypassed to ground using a low ESR ceramic capacitor with X5R or X7R dielectric.
Make sure to connect this capacitor to the quieter analog ground trace rather than the power ground trace of
the PVIN bypass capacitor.
• Since the PH connection is the switching node, the output inductor should be located close to the PH pins
and the area of the PCB conductor minimized to prevent excessive capacitive coupling.
• The output filter capacitor ground should use the same power ground trace as the PVIN input bypass
capacitor. Try to minimize this conductor length while maintaining adequate width.
• It is critical to keep the feedback trace away from inductor EMI and other noise sources. Run the feedback
trace as far from the inductor, phase (PH) node, and noisy power traces as possible. Avoid routing this trace
directly under the output inductor if possible. If not possible, ensure that the trace is routed on another layer
with a ground layer separating the trace and inductor.
• Keep the resistive divider used to generate VSENSE voltage as close to the device pin as possible in order to
reduce noise pickup.
• The RT and COMP pins are sensitive to noise as well, so components around these pins should be located
as close as possible to the IC and routed with minimal lengths of trace.
• Make all of the power (high current) traces as short, direct, and thick as possible.
• It may be possible to obtain acceptable performance with alternate PCB layouts, however this layout has
been shown to produce good results and is meant as a guideline.
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9.4.2 Layout Example
1
34
33
GND
REFCAP
2
3
4
5
EN
RT
COMP
VSENSE
SS/TR
RSC
32
31
30
29
VIN
Trace away from
switching node
SYNC1
SYNC2
PVIN
PWRGD
PH
6
7
28
27
Thermal Pad
VOUT
(Bottom Side)
35
PVIN
PH
8
L
26
25
24
23
22
21
PH
PVIN
PVIN
9
10
11
PH
As close to the
device as
possible
COUT
PVIN
PH
PH
PGND
12
13
RTOP
PGND
PGND
PH
PH
PH
14
15
16
17
20
19
18
PGND
PGND
PGND
Close to device
and loop as
small as possible
PGND Pad
(Bottom Side)
36
PH Pad
(Bottom Side)
37
RBOTTOM
PH
PH
图9-6. PCB Layout Example for CDFP package
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GND
GND
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
1
NC
2
NC
NC
3
EN
REFCAP
COMP
VSENSE
SS/TR
RSC
4
RT
5
VIN
6
Route VSENSE trace away from
switching node (PH)
VIN
7
SYNC1
SYNC2
GND
8
PWRGD
GND
9
10
11
12
13
14
15
16
17
18
19
20
21
22
PVIN
PVIN
PVIN
PVIN
PVIN
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PowerPADTM
Place bypass
capacitor as
close to PVIN
as possible
L
COUT
RTOP
RBOT
Place inductor and
output capacitor close to
device in order to
minimize the current loop
图9-7. PCB Layout Example for HTSSOP Package
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English Data Sheet: SLVSEN7
TPS7H4001-SP
ZHCSL64D –APRIL 2019 –REVISED MAY 2023
www.ti.com.cn
10 Device and Documentation Support
10.1 Documentation Support
10.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, TPS7H4001EVM-CVAL Evaluation Module (EVM) user's guide
• Texas Instruments, TPS7H4001QEVM-CVAL Evaluation Module User's Guide user's guide
• Texas Instruments, TPS7H4001-SP Single-Event Effects Test Report radiation report
• Texas Instruments, TPS7H4001-SP Total Ionizing Dose (TID) radiation report
• Texas Instruments, TPS7H4001-SP Neutron Displacement Damage Characterization radiation report
• Texas Instruments, TPS7H4001-SP Model user's guide
• Texas Instruments, Texas Instruments Engineering Evaluation Units versus MIL-PRF-38535 QML Class V
Processing brochure
10.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
10.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
10.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSEN7
52
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Product Folder Links: TPS7H4001-SP
TPS7H4001-SP
ZHCSL64D –APRIL 2019 –REVISED MAY 2023
www.ti.com.cn
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
53
Product Folder Links: TPS7H4001-SP
English Data Sheet: SLVSEN7
TPS7H4001-SP
ZHCSL64D –APRIL 2019 –REVISED MAY 2023
www.ti.com.cn
PACKAGE OUTLINE
DDW0044F
PowerPADTM TSSOP - 1.2 mm max height
S
C
A
L
E
1
.
2
5
0
PLASTIC SMALL OUTLINE
8.3
7.9
TYP
A
PIN 1 ID
AREA
42X 0.635
44
1
14.1
13.9
NOTE 3
2X
13.335
22
B
23
0.27
0.17
44X
6.2
6.0
0.1 C
SEATING PLANE
0.08
C A B
(0.15) TYP
C
2.94
2.42
SEE DETAIL A
22
23
EXPOSED
THERMAL PAD
7.96
7.44
45
0.25
1.2 MAX
GAGE PLANE
0.75
0.50
0.15
0.05
0 - 8
2X (0.33)
NOTE 4
DETAIL A
TYPICAL
1
44
2X (0.96)
NOTE 4
4228322/A 12/2021
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Features may differ or may not be present.
www.ti.com
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSEN7
54
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Product Folder Links: TPS7H4001-SP
TPS7H4001-SP
ZHCSL64D –APRIL 2019 –REVISED MAY 2023
www.ti.com.cn
EXAMPLE BOARD LAYOUT
DDW0044F
PowerPAD TM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(5.2)
NOTE 8
SOLDER MASK
DEFINED PAD
(2.94)
SEE DETAILS
SYMM
44X (1.45)
44X (0.4)
1
44
42X (0.635)
(14)
NOTE 8
(1.1) TYP
SYMM
45
(7.96)
(R0.05) TYP
(
0.2) TYP
VIA
23
22
METAL COVERED
BY SOLDER MASK
(1.15)
TYP
(7.5)
LAND PATTERN EXAMPLE
SCALE:6X
METAL UNDER
SOLDER MASK
SOLDER MASK
METAL
SOLDER MASK
OPENING
OPENING
0.05 MIN
AROUND
0.05 MAX
AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4228322/A 12/2021
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
7. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
8. Size of metal pad may vary due to creepage requirement.
www.ti.com
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
55
Product Folder Links: TPS7H4001-SP
English Data Sheet: SLVSEN7
TPS7H4001-SP
ZHCSL64D –APRIL 2019 –REVISED MAY 2023
www.ti.com.cn
EXAMPLE STENCIL DESIGN
DDW0044F
PowerPAD TM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(2.94)
BASED ON
0.125 THICK
STENCIL
44X (1.45)
1
44
44X (0.4)
42X (0.635)
45
SYMM
(7.96)
BASED ON
0.125 THICK
STENCIL
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
22
23
METAL COVERED
BY SOLDER MASK
SYMM
(7.5)
SOLDER PASTE EXAMPLE
PAD 45:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:6X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
3.29 X 8.90
2.94 X 7.96 (SHOWN)
2.68 X 7.27
0.125
0.15
0.175
2.48 X 6.73
4228322/A 12/2021
NOTES: (continued)
9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
10. Board assembly site may have different recommendations for stencil design.
www.ti.com
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSEN7
56
Submit Document Feedback
Product Folder Links: TPS7H4001-SP
PACKAGE OPTION ADDENDUM
www.ti.com
30-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
5962-1820501VXC
ACTIVE
CFP
HKY
34
1
RoHS & Green
AU
N / A for Pkg Type
-55 to 125
5962-1820501VXC
TPS7H4001MHKYV
Samples
5962R1820501V9A
5962R1820501VXC
ACTIVE
ACTIVE
XCEPT
CFP
KGD
HKY
0
25
1
RoHS & Green
RoHS & Green
Call TI
AU
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
Samples
Samples
34
5962R1820501VXC
TPS7H4001MHKYV
5962R1820502PYE
TPS7H4001HKY/EM
TPS7H4001MDDWTSHP
TPS7H4001Y/EM
ACTIVE
ACTIVE
ACTIVE
ACTIVE
HTSSOP
CFP
DDW
HKY
DDW
KGD
44
34
44
0
250
1
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
NIPDAU
AU
Level-3-260C-168 HR
N / A for Pkg Type
Level-3-260C-168 HR
N / A for Pkg Type
-55 to 125
25 to 25
R1820502PYE
TPS7H4001HKY/EM
7H4001SHP
Samples
Samples
Samples
Samples
HTSSOP
XCEPT
250
5
NIPDAU
Call TI
-55 to 125
25 to 25
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Jun-2023
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Apr-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
5962-1820501VXC
5962R1820501VXC
TPS7H4001HKY/EM
HKY
HKY
HKY
CFP
CFP
CFP
34
34
34
1
1
1
506.98
506.98
506.98
32.77
32.77
32.77
9910
9910
9910
NA
NA
NA
Pack Materials-Page 1
PACKAGE OUTLINE
HKY0034A
CFP - 2.55 mm max height
S
C
A
L
E
0
.
8
0
0
CERAMIC FLATPACK
7.82
7.42
B
A
15X 1.27
1
34
21.84
21.34
2X 20.32
(19.3)
18
17
0.48
34X
(7.24)
2.55
1.98
METAL LID
0.38
0.2
METAL LID
C A B
0.18
0.10
2X (1.518)
1.04
0.84
C
2X (1.59)
18
17
2X (2.32)
2X (8.378)
(1.883)
PKG
(15.31)
34
1
PKG
BACKSIDE
METALIZATION
(THERMAL PAD)
PIN 1 ID
(4.62)
27 0.5
4224746/C 11/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermetically sealed with a metal lid. The lid is connected to Pin 1.
4. The leads are gold plated.
5. Metal lid is connected to backside pad metallization
www.ti.com
EXAMPLE BOARD LAYOUT
HKY0034A
CFP - 2.55 mm max height
CERAMIC FLATPACK
PKG
(1.16) TYP
(1.2) TYP
PKG
(0.683)
(8.382)
(1.09)
(0.977)
HEATSINK LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:7X
4224746/C 11/2020
www.ti.com
GENERIC PACKAGE VIEW
DDW 44
6.1 x 14, 0.635 mm pitch
PowerPAD TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224876/A
www.ti.com
PACKAGE OUTLINE
DDW0044F
PowerPADTM TSSOP - 1.2 mm max height
S
C
A
L
E
1
.
2
5
0
PLASTIC SMALL OUTLINE
8.3
7.9
TYP
A
PIN 1 ID
AREA
42X 0.635
44
1
14.1
13.9
NOTE 3
2X
13.335
22
B
23
0.27
0.17
44X
6.2
6.0
0.1 C
SEATING PLANE
0.08
C A B
(0.15) TYP
C
2.94
2.42
SEE DETAIL A
22
23
EXPOSED
THERMAL PAD
7.96
7.44
45
0.25
1.2 MAX
GAGE PLANE
0.75
0.50
0.15
0.05
0 - 8
2X (0.33)
NOTE 4
DETAIL A
TYPICAL
44
1
2X (0.96)
NOTE 4
4228322/A 12/2021
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Features may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DDW0044F
PowerPADTM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(5.2)
NOTE 8
SOLDER MASK
DEFINED PAD
(2.94)
SEE DETAILS
SYMM
44X (1.45)
44X (0.4)
1
44
42X (0.635)
(14)
NOTE 8
(1.1) TYP
SYMM
45
(7.96)
(R0.05) TYP
(
0.2) TYP
VIA
23
22
METAL COVERED
BY SOLDER MASK
(1.15)
TYP
(7.5)
LAND PATTERN EXAMPLE
SCALE:6X
METAL UNDER
SOLDER MASK
SOLDER MASK
METAL
SOLDER MASK
OPENING
OPENING
0.05 MIN
AROUND
0.05 MAX
AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4228322/A 12/2021
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
7. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
8. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
DDW0044F
PowerPADTM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(2.94)
BASED ON
0.125 THICK
STENCIL
44X (1.45)
44X (0.4)
1
44
42X (0.635)
45
SYMM
(7.96)
BASED ON
0.125 THICK
STENCIL
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
22
23
METAL COVERED
BY SOLDER MASK
SYMM
(7.5)
SOLDER PASTE EXAMPLE
PAD 45:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:6X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
3.29 X 8.90
2.94 X 7.96 (SHOWN)
2.68 X 7.27
0.125
0.15
0.175
2.48 X 6.73
4228322/A 12/2021
NOTES: (continued)
9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
10. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
相关型号：
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