TPS82085SILT [TI]
TPS82085 3-A High Efficiency Step-Down Converter MicroSiP with Integrated Inductor;
| 型号： | TPS82085SILT |
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| 描述： | TPS82085 3-A High Efficiency Step-Down Converter MicroSiP with Integrated Inductor |
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TPS82085
SLVSCN4B –OCTOBER 2014–REVISED AUGUST 2015
TPS82085 3-A High Efficiency Step-Down Converter MicroSiP™ with Integrated Inductor
1 Features
3 Description
The TPS82085 device is a 3-A step-down converter
MicroSiP™ module optimized for small solution size
and high efficiency. The power module integrates a
synchronous step-down converter and an inductor to
simplify design, reduce external components and
save PCB area. The low profile and compact solution
is suitable for automated assembly by standard
surface mount equipment.
1
•
•
•
•
•
•
•
•
•
•
•
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•
•
3-A, Low Profile MicroSiP™ Power Module
DCS-Control™ Topology
Up to 95% Efficiency
17-µA Operating Quiescent Current
-40°C to 125°C Operating Temperature Range
Hiccup Short Circuit Protection
2.5-V to 6-V Input Voltage Range
0.8-V to VIN Adjustable Output Voltage
Power Save Mode for Light Load Efficiency
100% Duty Cycle for Lowest Dropout
Output Discharge Function
To maximize efficiency, the converter operates in
PWM mode with a nominal switching frequency of
2.4MHz and automatically enters Power Save Mode
operation at light load currents. In Power Save Mode,
the device operates with typically 17-µA quiescent
current. Using the DCS-Control™ topology, the
device achieves excellent load transient performance
and accurate output voltage regulation. The EN and
PG pins, which support sequencing configurations,
bring a flexible system design. An integrated soft
startup reduces the inrush current required from the
input supply. Over temperature protection and Hiccup
short circuit protection deliver a robust and reliable
solution.
Power Good Output
Integrated Soft Startup
Over Temperature Protection
3.0-mm x 2.8-mm x 1.3-mm 8-Pin µSiL Package
2 Applications
•
•
•
•
Battery Powered Applications
Solid State Drives
Device Information(1)
Processor Supply
PART NUMBER
PACKAGE
BODY SIZE (NOM)
Mobile Phones
TPS82085
µSiL (8)
3.0 mm x 2.8 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
space
space
1.8 V Output Application
1.8 V Output Efficiency
TPS82085
VIN
VOUT
100
VIN
EN
VOUT
2.5V to 6V
1.8V/3A
C1
10µF
C2
22µF
R1
200k
R3
499k
FB
90
80
R2
160k
GND
PG
POWER GOOD
70
VIN = 3.0 V
VIN = 3.5 V
VIN = 4.0 V
VIN = 5.0 V
60
1m
10m
100m
1
5
Load (A)
D002
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS82085
SLVSCN4B –OCTOBER 2014–REVISED AUGUST 2015
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Table of Contents
7.4 Device Functional Modes.......................................... 9
Application and Implementation ........................ 10
8.1 Application Information............................................ 10
8.2 Typical Applications ................................................ 10
Power Supply Recommendations...................... 15
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommend Operating Conditions........................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics.......................................... 5
6.6 Typical Characteristics.............................................. 6
Detailed Description .............................................. 7
7.1 Overview ................................................................... 7
7.2 Functional Block Diagram ......................................... 7
7.3 Feature Description................................................... 7
8
9
10 Layout................................................................... 15
10.1 Layout Guidelines ................................................. 15
10.2 Layout Example .................................................... 15
10.3 Thermal Consideration.......................................... 16
11 Device and Documentation Support ................. 17
11.1 Device Support...................................................... 17
11.2 Community Resources.......................................... 17
11.3 Trademarks........................................................... 17
11.4 Electrostatic Discharge Caution............................ 17
11.5 Glossary................................................................ 17
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 17
4 Revision History
Changes from Revision A (April 2015) to Revision B
Page
•
Changed the ESD Ratings Charged device model (CDM) From: ±500 V To: ±1000 V......................................................... 4
Changes from Original (October 2014) to Revision A
Page
•
Changed the data sheet From: 3-page Product Preview To: Production data ..................................................................... 1
2
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5 Pin Configuration and Functions
µSiL Package
(Top View)
EN
PG
1
2
3
4
8
VOUT
FB
7
6
5
VIN
VIN
GND
GND
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
Enable pin. Pull High to enable the device. Pull Low to disable the device. This pin has an
internal pull-down resistor of typically 400 kΩ when the device is disabled.
EN
1
I
Power good open drain output pin. A pull-up resistor can be connected to any voltage less
than 6V. Leave it open if it is not used.
PG
2
O
VIN
3,4
5,6
PWR
Input voltage pin.
Ground pin.
GND
Feedback reference pin. An external resistor divider connected to this pin programs the
output voltage.
FB
7
8
I
VOUT
PWR
Output voltage pin.
Exposed
Thermal Pad
The exposed thermal pad must be connected to the GND pin. Must be soldered to achieve
appropriate power dissipation and mechanical reliability.
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6 Specifications
6.1 Absolute Maximum Ratings(1)
MIN
MAX
7
UNIT
V
Voltage at pins(2)
Sink current
EN, PG, VIN, FB, VOUT
PG
-0.3
1.0
125
125
mA
°C
Module operating temperature range
Storage temperature range
-40
-40
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground pin.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-
C101(2)
±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommend Operating Conditions
Over operating free-air temperature range, unless otherwise noted.
MIN
MAX
UNIT
VIN
Input voltage range
2.5
6
6
V
V
VPG
VOUT
IOUT
TJ
Power good pull-up resistor voltage
Output voltage range
Output current range(1)
0.8
0
VIN
3
V
A
Module operating temperature range(1)
-40
125
°C
(1) The module operating temperature range includes module self temperature rise and IC junction temperature rise. In applications where
high power dissipation is present, the maximum operating temperature or maximum output current must be derated.
6.4 Thermal Information
µSiL
THERMAL METRIC(1)
UNIT
8-Pin
68.7
n/a
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
RθJC(top)
RθJB
n/a
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.4
ψJB
30.0
n/a
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953
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6.5 Electrical Characteristics
TJ = -40°C to 125°C and VIN = 2.5V to 6V. Typical values are at TJ = 25°C and VIN = 3.6V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY
VIN
Input voltage range
2.5
6
V
No load, device not switching
TJ = -40°C to 85°C, VIN = 2.5 V to 5.5 V
IQ
Quiescent current into VIN
Shutdown current into VIN
17
25
µA
EN = Low,
TJ = -40°C to 85°C, VIN = 2.5 V to 5.5 V
ISD
0.7
5
µA
VIN falling
VIN rising
TJ rising
TJ falling
2.1
2.3
2.2
2.4
150
20
2.3
2.5
V
V
VUVLO
Under voltage lock out threshold
Thermal shutdown threshold
Thermal shutdown hysteresis
°C
°C
TJSD
LOGIC INTERFACE EN
VIH
High-level input voltage
1.0
0.8
0.7
V
V
VIL
Low-level input voltage
0.4
Ilkg(EN)
RPD
Input leakage current into EN pin
Pull-down resistance at EN pin
EN = High
EN = Low
0.01
400
0.16
µA
kΩ
SOFT START, POWER GOOD
tSS
Soft start time
Time from EN high to 95% of VOUT nominal
VOUT rising, referenced to VOUT nominal
VOUT falling, referenced to VOUT nominal
Isink = 1mA
0.8
95%
90%
ms
93%
88%
98%
93%
0.4
VPG
Power good threshold
VPG,OL Low-level output voltage
V
Ilkg(PG)
OUTPUT
VOUT
Input leakage current into PG pin
VPG = 5V
0.01
0.16
µA
Output voltage range
0.8
792
792
VIN
808
817
0.1
V
PWM mode
800
800
VFB
Feedback regulation voltage
mV
PSM mode, COUT = 22 µF
VFB = 0.8 V
Ilkg(FB)
RDIS
Feedback input leakage current
Output discharge resistor
Line regulation
0.01
260
µA
Ω
EN = Low, VOUT = 1.8 V
IOUT = 1 A, VIN = 2.5 V to 6 V
IOUT = 0.5 A to 3 A
0.02
0.16
%/V
%/A
Load regulation
POWER SWITCH
High-side FET on-resistance
ISW = 50 0mA
ISW = 500 mA
100% mode
31
23
56
45
mΩ
mΩ
mΩ
A
RDS(on)
Low-side FET on-resistance
Dropout resistance
RDP
ILIMF
fSW
69
High-side FET switch current limit
PWM switching frequency
3.7
4.6
2.4
5.5
IOUT = 1 A
MHz
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6.6 Typical Characteristics
0.10
25
20
15
10
5
0.08
0.06
0.04
0.02
TJ = -40°C
TJ = -40°C
TJ = 25°C
TJ = 85°C
TJ = 25°C
TJ = 85°C
0.00
0
2.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Input Voltage (V)
Input Voltage (V)
D017
D020
Figure 1. Dropout Resistance
Figure 2. Quiescent Current
2.5
TJ = -40°C
TJ = 25°C
TJ = 85°C
2.0
1.5
1.0
0.5
0.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Input Voltage (V)
D021
Figure 3. Shutdown Current
6
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7 Detailed Description
7.1 Overview
The TPS82085 synchronous step-down converter power module is based on DCS-Control™ (Direct Control with
Seamless transition into Power Save Mode). This is an advanced regulation topology that combines the
advantages of hysteretic, voltage and current mode control.
The DCS-Control™ topology operates in PWM (Pulse Width Modulation) mode for medium to heavy load
conditions and in PSM (Power Save Mode) at light load currents. In PWM, the converter operates with its
nominal switching frequency of 2.4 MHz having a controlled frequency variation over the input voltage range. As
the load current decreases, the converter enters Power Save Mode, reducing the switching frequency and
minimizing the IC's quiescent current to achieve high efficiency over the entire load current range. DCS-Control™
supports both operation modes using a single building block and therefore has a seamless transition from PWM
to PSM without effects on the output voltage. The TPS82085 offers excellent DC voltage regulation and load
transient regulation, combined with low output voltage ripple, minimizing interference with RF circuits.
7.2 Functional Block Diagram
PG
Hiccup
Counter
VFB
VIN
VREF
High Side
Current Sense
Bandgap
Undervoltage Lockout
Thermal Shutdown
EN
L(2)
400kΩ(1)
MOSFET Driver
Control Logic
Ramp
Direct Control
and
Compensation
Comparator
VOUT
FB
Timer
ton
Error Amplifier
VREF
260Ω
DCS - Control TM
EN Output Discharge
Logic
GND
Note:
(1) When the device is enabled, the 400 kΩ resistor is disconnected.
(2) The integrated inductor in the module, L = 0.47µH.
7.3 Feature Description
7.3.1 PWM and PSM Operation
The TPS82085 includes a fixed on-time (tON) circuitry. This tON, in steady-state operation in PWM and PSM
modes, is estimated as:
VOUT
tON = 420ns´
V
IN
(1)
In PWM mode, the TPS82085 operates with pulse width modulation in continuous conduction mode (CCM) with
a tON shown in Equation 1 at medium and heavy load currents. A PWM switching frequency of typically 2.4 MHz
is achieved by this tON circuitry. The device operates in PWM mode as long as the output current is higher than
half the inductor's ripple current estimated by Equation 2.
VIN - VOUT
DIL = tON
´
L
(2)
To maintain high efficiency at light loads, the device enters Power Save Mode seamlessly when the load current
decreases. This happens when the load current becomes smaller than half the inductor's ripple current. In PSM,
the converter operates with a reduced switching frequency and with a minimum quiescent current to maintain
high efficiency. The on time in PSM is also based on the same tON circuitry. The switching frequency in PSM is
estimated as:
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Feature Description (continued)
2´IOUT
fPFM
=
V
VIN - VOUT
2
IN
tON
´
´
VOUT
L
(3)
In PSM, the output voltage rises slightly above the nominal output voltage in PWM mode. This effect is reduced
by increasing the output capacitance. The output voltage accuracy in PSM operation is reflected in the electrical
specification table and given for a 22-µF output capacitor.
7.3.2 Low Dropout Operation (100% Duty Cycle)
The device offers a low input to output voltage differential by entering 100% duty cycle mode. In this mode, the
high-side MOSFET switch is constantly turned on. This is particularly useful in battery powered applications to
achieve longest operation time by taking full advantage of the whole battery voltage range. The minimum input
voltage to maintain a minimum output voltage is given by:
VIN(min) = VOUT(min) + IOUT x RDP
(4)
Where
RDP = Resistance from VIN to VOUT, including high-side FET on-resistance and DC resistance of the inductor.
VOUT(min) = Minimum output voltage the load can accept.
7.3.3 Soft Startup
The TPS82085 has an internal soft start circuit which ramps up the output voltage to the nominal voltage during
a soft start time of typically 0.8ms. This avoids excessive inrush current and creates a smooth output voltage
slope. It also prevents excessive voltage drops of primary cells and rechargeable batteries with high internal
impedance. The device is able to monotonically start into a pre-biased output capacitor. The device starts with
the applied bias voltage and ramps the output voltage to its nominal value.
7.3.4 Switch Current Limit and Short Circuit Protection (Hiccup-Mode)
The switch current limit prevents the device from high inductor current and from drawing excessive current from
the battery or input voltage rail. Excessive current might occur with a heavy load/shorted output circuit condition.
If the inductor peak current reaches the switch current limit, the high-side FET is turned off and the low-side FET
is turned on to ramp down the inductor current. Once this switch current limits is triggered 32 times, the devices
stop switching and enables the output discharge. The devices then automatically start a new startup after a
typical delay time of 66μs has passed. This is named HICCUP short circuit protection. The devices repeat this
mode until the high load condition disappears.
7.3.5 Undervoltage Lockout
To avoid mis-operation of the device at low input voltages, an under voltage lockout is implemented, which shuts
down the devices at voltages lower than VUVLO with a hysteresis of 200 mV.
7.3.6 Thermal Shutdown
The device goes into thermal shutdown and stops switching once the junction temperature exceeds TJSD. Once
the device temperature falls below the threshold by 20°C, the device returns to normal operation automatically.
8
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7.4 Device Functional Modes
7.4.1 Enable and Disable
The device is enabled by setting the EN pin to a logic High. Accordingly, shutdown mode is forced if the EN pin
is pulled Low with a shutdown current of typically 0.7 μA. An internal resistor of 260 Ω discharges the output via
the VOUT pin smoothly when the device is disabled. The output discharge function also works when thermal
shutdown, undervoltage lockout or short circuit protection are triggered.
An internal pull-down resistor of 400 kΩ is connected to the EN pin when the EN pin is Low. The pull-down
resistor is disconnected when the EN pin is High.
7.4.2 Power Good Output
The device has a power good (PG) output. The PG pin goes high impedance once the output is above 95% of
the nominal voltage, and is driven low once the output voltage falls below typically 90% of the nominal voltage.
The PG pin is an open drain output and is specified to sink up to 1 mA. The power good output requires a pull-up
resistor connecting to any voltage rail less than 6 V.
The PG pin goes low when the device is disabled or in thermal shutdown. When the device is in UVLO, the PG
pin is high impedance. The PG signal can be used for sequencing of multiple rails by connecting it to the EN pin
of other converters. Leave the PG pin floating when it is not used.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS82085 is a synchronous step-down converter power module whose output voltage is adjusted by
component selection. The following section discusses the design of the external components to complete the
power supply design for several input and output voltage options by using typical applications as a reference.
8.2 Typical Applications
8.2.1 1.2-V Output Application
TPS82085
VIN
VOUT
VIN
EN
VOUT
2.5V to 6V
1.2V/3A
C1
10µF
C2
22µF
R1
R3
80.6k 499k
FB
R2
162k
GND
PG
POWER GOOD
Figure 4. 1.2-V Output Application
8.2.1.1 Design Requirements
For this design example, use the input parameters shown in Table 1.
Table 1. Design Parameters
DESIGN PARAMETER
Input voltage range
EXAMPLE VALUE
2.5 V to 6 V
1.2 V
Output voltage
Output ripple voltage
Output current rating
< 20 mV
3 A
Table 2 lists the components used for the example.
Table 2. List of Components
REFERENCE
DESCRIPTION
MANUFACTURER
C1
10µF, Ceramic Capacitor, 10V, X7R, size 0805, GRM21BR71A106KE51
Murata
22µF, Ceramic Capacitor, 6.3V, X7R, size 0805, CL21B226MQQNNNE
or
Samsung
or
C2
22µF, Ceramic Capacitor, 6.3V, X7S, size 0805, C2012X7S1A226M125AC
TDK
R1
R2
R3
Depending on the output voltage, 1% accuracy
162kΩ, 1% accuracy
Std
Std
Std
499kΩ, 1% accuracy
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8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Setting the Output Voltage
The output voltage is set by an external resistor divider according to the following equations:
R1
R1
æ
ö
æ
ö
VOUT = VFB
´
1 +
= 0.8 V ´ 1 +
ç
÷
ç
÷
R2
R2
è
ø
è
ø
(5)
R2 should not be higher than 180 kΩ to achieve high efficiency at light load while providing acceptable noise
sensitivity. Larger currents through R2 improve noise sensitivity and output voltage accuracy. Figure 4 shows a
recommended external resistor divider value for a 1.2-V output. Choose appropriate resistor values for other
output voltages.
8.2.1.2.2 Input and Output Capacitor Selection
For best output and input voltage filtering, ceramic capacitors are required. The input capacitor minimizes input
voltage ripple, suppresses input voltage spikes and provides a stable system rail for the device. A 10-µF or larger
input capacitor is required. The output capacitor value can range from 22 µF up to more than 150 µF. The
recommended typical output capacitor value is 22µF. Values over 150 µF may be possible with a reduced load
during startup in order to avoid triggering the Hiccup short circuit protection. A feed forward capacitor is not
required for proper operation.
Ceramic capacitor has a DC-Bias effect, which has a strong influence on the final effective capacitance. Choose
the right capacitor carefully in combination with considering its package size and voltage rating. Ensure that the
input effective capacitance is at least 5µF and the output effective capacitance is at least 8µF.
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8.2.1.3 Application Performance Curves
TA = 25°C, VIN = 5 V, VOUT = 1.2 V, unless otherwise noted.
100
90
100
90
80
70
60
80
70
VIN = 3.0 V
VIN = 3.5 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 3.0 V
VIN = 3.5 V
VIN = 4.0 V
VIN = 5.0 V
60
1m
10m
100m
1
5
1m
10m
100m
1
5
Load (A)
Load (A)
D001
D002
VOUT = 1.2 V
VOUT = 1.8 V
Figure 5. Efficiency
Figure 6. Efficiency
100
100
90
80
70
60
90
80
70
60
VIN = 3.0 V
VIN = 3.5 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 3.5 V
VIN = 4.0 V
VIN = 5.0 V
1m
10m
100m
1
5
1m
10m
100m
1
5
Load (A)
Load (A)
D004
D003
VOUT = 3.3 V
VOUT = 2.6 V
Figure 8. Efficiency
Figure 7. Efficiency
4
3
2
1
0
4
3
2
1
0
VIN = 3.0 V
VIN = 3.5 V
VIN = 5.0 V
VIN = 3.0 V
VIN = 3.5 V
VIN = 5.0 V
60
70
80
90
100
110
120
130
60
70
80
90
100
110
120
130
Board Temperature (°C)
Board Temperature (°C)
D018
D019
VOUT = 1.2 V
ψJB = 30°C/W
VOUT = 2.6 V
ψJB = 30 °C/W
Figure 9. Thermal Derating
Figure 10. Thermal Derating
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1.0
1.0
0.5
0.5
0.0
0.0
-0.5
-0.5
TA = -40°C
TA = 25°C
TA = 85°C
TA = -40°C
TA = 25°C
TA = 85°C
-1.0
-1.0
1m
10m
100m
1
5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Load (A)
Input Voltage (V)
D005
D006
IOUT = 1 A
Figure 11. Load Regulation
Figure 12. Line Regulation
VIN
50mV/DIV
AC
VIN
20mV/DIV
AC
VOUT
10mV/DIV
AC
VOUT
10mV/DIV
AC
Time - 250ns/DIV
7LPHꢀꢁꢀꢂꢀVꢃ',9
D007
D008
IOUT = 2 A
IOUT = 25 mA
Figure 13. Input and Output Ripple in PWM Mode
Figure 14. Input and Output Ripple in PSM Mode
IOUT
2A/DIV
IOUT
1A/DIV
VOUT
10mV/DIV
AC
VOUT
50mV/DIV
AC
Time - 10ms/DIV
7LPHꢀꢁꢀꢂꢃꢀVꢄ',9
D009
D010
IOUT = 25 mA to 3 A
IOUT = 25 mA to 3 A
Figure 15. Load Sweep
Figure 16. Load Transient
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EN
2V/DIV
IOUT
2A/DIV
VOUT
500mV/DIV
VOUT
20mV/DIV
AC
IOUT
2A/DIV
7LPHꢀꢁꢀꢂꢃꢀVꢄ',9
Time - 2ms/DIV
D011
D012
IOUT = 0.5 A to 2.5 A
IOUT = no load
Figure 17. Load Transient
Figure 18. Startup / Shutdown without Load
EN
2V/DIV
VOUT
600mV/DIV
VOUT
500mV/DIV
IOUT
2A/DIV
IOUT
2.5A/DIV
7LPHꢀꢁꢀꢂꢃꢃꢀVꢄ',9
7LPHꢀꢁꢀꢂꢃꢃꢀVꢄ',9
D013
D014
Load = 0.4 Ω
IOUT = 3 A
Figure 19. Startup / Shutdown with Resistive Load
Figure 20. Short Circuit, HICCUP Protection Entry / Exit
100
80
60
40
20
0
0.004
IOUT = 100 mA
IOUT = 2.5 A
0.003
0.002
0.001
0
IOUT = 100 mA
IOUT = 2.5 A
100
1k
10k
100k
1M
2M
4M
6M
8M
10M
Frequency (Hz)
Frequency (Hz)
D015
D016
Figure 21. Power Supply Rejection Ratio (PSRR)
Figure 22. Spurious Output Noise
14
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TPS82085
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SLVSCN4B –OCTOBER 2014–REVISED AUGUST 2015
9 Power Supply Recommendations
The devices are designed to operate from an input supply voltage range between 2.5 V and 6 V. The average
input current of the TPS82085 is calculated as:
VOUT ´IOUT
1
IIN
=
´
h
V
IN
(6)
Ensure that the power supply has a sufficient current rating for the application.
10 Layout
10.1 Layout Guidelines
•
It is recommended to place all components as close as possible to the IC. Specially, the input capacitor
placement must be closest to the VIN and GND pins of the device.
•
•
Use wide and short traces for the main current paths to reduce the parasitic inductance and resistance.
To enhance heat dissipation of the device, the exposed thermal pad should be connected to bottom or
internal layer ground planes using vias.
•
•
Refer to Figure 23 for an example of component placement, routing and thermal design.
The recommended land pattern for the TPS82085 is shown at the end of this data sheet. For best
manufacturing results, it is important to create the pads as solder mask defined (SMD). This keeps each pad
the same size and avoids solder pulling the device during reflow.
10.2 Layout Example
R2
R1
VOUT
C2
EN
VOUT
PG
VIN
VIN
FB
GND
GND
VIN
GND
C1
Total Solution Size
35 mm2
Figure 23. TPS82085 PCB Layout
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10.3 Thermal Consideration
The TPS82085's output current needs to be derating when the device operates in a high ambient temperature or
deliver high output power. The amount of current derated is dependent upon the input voltage, output power,
PCB layout design and environmental thermal condition. Care should especially be taken in applications where
the localized PCB temperature exceeds 65°C.
The TPS82085 module temperature must be kept less than the maximum rating of 125°C. Three basic
approaches for enhancing thermal performance are listed below:
•
•
•
Improve the power dissipation capability of the PCB design.
Improve the thermal coupling of the component to the PCB.
Introduce airflow into the system.
To estimate approximate module temperature of TPS82085, apply the typical efficiency stated in this datasheet
to the desired application condition for the module power dissipation, then calculate the module temperature rise
by multiplying the power dissipation by its thermal resistance. For more details on how to use the thermal
parameters in real applications, see the application notes: SZZA017 and SPRA953.
Figure 24 and Figure 25 shows the thermal measurement on the TPS82085EVM-672. It gives a guideline on the
temperature rise when the TPS82085 is operated in free air at 25°C ambient under certain application conditions.
The temperatures are checked at Spot and Area as listed below:
•
•
Spot: temperature of the EVM board.
Area: temperature of the TPS82085.
R2
R1
R2
R1
C2
C2
C1
C1
VIN = 5 V
VOUT = 1.2 V
IOUT = 3 A
VIN = 5 V
VOUT = 3.3 V
IOUT = 3 A
Figure 24. Thermal Measurement
Figure 25. Thermal Measurement
16
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SLVSCN4B –OCTOBER 2014–REVISED AUGUST 2015
11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
MicroSiP, DCS-Control, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
SIL0008C
MicroSiP TM - 1.33 mm max height
S
C
A
L
E
4
.
0
0
0
MICRO SYSTEM IN PACKAGE
2.9
2.7
A
B
PIN 1 INDEX
AREA
(2.5)
3.1
2.9
PICK AREA
NOTE 3
(2)
1.33 MAX
C
0.08 C
1.1±0.1
SYMM
EXPOSED
THERMAL PAD
(0.05)
TYP
5
4
SYMM
2X
1.9±0.1
1.95
1
8
0.42
0.38
6X 0.65
8X
(45 X0.25)
PIN 1 ID
0.1
C A
C
B
0.05
0.52
0.48
8X
4221448/D 04/2015
MicroSiP is a trademark of Texas Instruments
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Pick and place nozzle 1.3 mm or smaller recommended.
4. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
SIL0008C
MicroSiP TM - 1.33 mm max height
MICRO SYSTEM IN PACKAGE
(1.1)
8X (0.5)
8
1
8X (0.4)
SYMM
(1.9)
(0.75)
6X (0.65)
5
4
SYMM
(2.2)
(
0.2) VIA
TYP
LAND PATTERN EXAMPLE
SOLDER MASK DEFINED
SCALE:20X
0.05 MIN
ALL SIDES
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
(R0.05) TYP
DETAIL
NOT TO SCALE
4221448/D 04/2015
NOTES: (continued)
5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
SIL0008C
MicroSiP TM - 1.33 mm max height
MICRO SYSTEM IN PACKAGE
SOLDER MASK EDGE
(R0.05) TYP
(1.04)
8X (0.5)
8X (0.4)
(0.85)
METAL
TYP
SYMM
(1.05)
6X (0.65)
SYMM
(2.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
85% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4221448/D 04/2015
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
6-Aug-2015
PACKAGING INFORMATION
Orderable Device
TPS82085SILR
TPS82085SILT
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
uSiP
uSiP
SIL
8
8
3000
Green (RoHS
& no Sb/Br)
Call TI
Level-2-260C-1 YEAR
GE
TXI085*EC
ACTIVE
SIL
250
Green (RoHS
& no Sb/Br)
Call TI
Level-2-260C-1 YEAR
-40 to 125
GE
TXI085*EC
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Aug-2015
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Aug-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS82085SILR
uSiP
SIL
8
3000
330.0
12.4
3.0
3.2
1.45
4.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Aug-2015
*All dimensions are nominal
Device
Package Type Package Drawing Pins
uSiP SIL
SPQ
Length (mm) Width (mm) Height (mm)
383.0 353.0 58.0
TPS82085SILR
8
3000
Pack Materials-Page 2
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