TPS82690SIPR [TI]
500-mA, HIGH-EFFICIENCY MicroSiP? STEP-DOWN CONVERTER (PROFILE <1mm); 500毫安，高效MicroSiP ？降压转换器（PROFILE \u003c仅1mm）
| 型号： | TPS82690SIPR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 500-mA, HIGH-EFFICIENCY MicroSiP? STEP-DOWN CONVERTER (PROFILE <1mm) |
| 文件： | 总23页 (文件大小：885K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS82690
TPS82695
TPS82697
www.ti.com
SLVSA66B –JUNE 2011–REVISED FEBRUARY 2012
500-mA, HIGH-EFFICIENCY MicroSiP™ STEP-DOWN CONVERTER (PROFILE <1mm)
Check for Samples: TPS82690, TPS82695, TPS82697
1
FEATURES
DESCRIPTION
2
•
Total Solution Size <6.7 mm2
The TPS8269xSIP device is a complete 500mA,
DC/DC step-down power supply intended for
low-power applications. Included in the package are
the switching regulator, inductor and input/output
capacitors. No additional components are required to
finish the design.
•
•
•
•
•
•
•
•
•
•
95% Efficiency at 4MHz Operation
24μA Quiescent Current
High Duty-Cycle Operation
Best in Class Load and Line Transient
±2% Total DC Voltage Accuracy
Automatic PFM/PWM Mode Switching
Low Ripple Light-Load PFM Mode
Excellent AC Load Regulation
Internal Soft Start, 130-µs Start-Up Time
The TPS8269xSIP is based on a high-frequency
synchronous step-down dc-dc converter optimized for
battery-powered
portable
applications.
The
MicroSIP™ DC/DC converter operates at a regulated
4-MHz switching frequency and enters the
power-save mode operation at light load currents to
maintain high efficiency over the entire load current
range.
Integrated Active Power-Down Sequencing
(Optional)
•
•
Current Overload and Thermal Shutdown
Protection
The PFM mode extends the battery life by reducing
the quiescent current to 24μA (typ) during light load
operation. For noise-sensitive applications, the device
has PWM spread spectrum capability providing a
lower noise regulated output, as well as low noise at
the input. These features, combined with high PSRR
and AC load regulation performance, make this
device suitable to replace a linear regulator to obtain
better power conversion efficiency.
Sub 1-mm Profile Solution
APPLICATIONS
•
•
•
LDO Replacement
Cell Phones, Smart-Phones
PoL Applications
The TPS8269xSIP is packaged in a compact (2.3mm
x 2.9mm) and low profile (1.0mm) BGA package
suitable for automated assembly by standard surface
mount equipment.
TPS82690SIP
150
135
120
105
90
100
95
90
85
80
75
70
65
VI = 3.6 V,
= 2.85 V
DC/DC Converter
L
Efficiency
PFM/PWM Operation
V
O
V
V
BAT
3.25 V .. 4.35 V
OUT
2.85 V @ 500mA
SW
VIN
CI
CO
FB
GND
EN
MODE
SELECTION
ENABLE
MODE
75
GND
60
Figure 1. Typical Application
Power Loss
PFM/PWM Operation
45
30
60
55
50
15
0
0.1
1
10
- Load Current - mA
100
1000
I
O
Figure 2. Efficiency vs. Load Current
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
MicroSiP, MicroSIP are trademarks of Texas Instruments.
2
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2012, Texas Instruments Incorporated
TPS82690
TPS82695
TPS82697
SLVSA66B –JUNE 2011–REVISED FEBRUARY 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION(1)
PART
NUMBER
OUTPUT
DEVICE
SPECIFIC FEATURE
PACKAGE
MARKING
TA
ORDERING(3)
VOLTAGE(2)
TPS82695
TPS82690(4)
TPS82696(4)
TPS82697(4)
2.5V
2.85V
2.9V
TPS82695SIP
TPS82690SIP
TPS82696SIP
TPS82697SIP
UF
RC
-40°C to 85°C
2.8V
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Internal tap points are available to facilitate output voltages in 25mV increments.
(3) The SIP package is available in tape and reel. Add a R suffix (e.g. TPS82690SIPR) to order quantities of 3000 parts. Add a T suffix (e.g.
TPS82690SIPT) to order quantities of 250 parts.
(4) Product preview. Contact TI factory for more information
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
UNIT
Voltage at VIN(2)(3)
Voltage at VOUT(3)
Voltage at EN, MODE
Peak output current
Power dissipation
Operating temperature range(4)
Maximum internal operating temperature
Storage temperature range
Human body model
–0.3 V to 6 V
–0.3 V to 3.6 V
–0.3 V to VI + 0.3 V
500 mA
VI
IO
(3)
Internally limited
–40°C to 85°C
125°C
TA
TINT (max)
Tstg
–55°C to 125°C
2 kV
(5)
ESD rating
Charge device model
1 kV
Machine model
200 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Operation above 4.35V input voltage for extended periods may affect device reliability. See input capacitor selection section for more
details.
(3) All voltage values are with respect to network ground terminal.
(4) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA(max)) is dependent on the maximum operating temperature (TINT(max)), the
maximum power dissipation of the device in the application (PD(max)), and the junction-to-ambient thermal resistance of the part/package
in the application (θJA), as given by the following equation: TA(max)= TJ(max)–(θJA X PD(max)). To achieve optimum performance, it is
recommended to operate the device with a maximum internal temperature of 105°C.
(5) The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. The machine model is a 200-pF
capacitor discharged directly into each pin.
2
Copyright © 2011–2012, Texas Instruments Incorporated
TPS82690
TPS82695
TPS82697
www.ti.com
SLVSA66B –JUNE 2011–REVISED FEBRUARY 2012
THERMAL INFORMATION
TPS82690/95/97
UNITS
THERMAL METRIC(1)
SIP (8-Pins)
Junction-to-ambient (top) thermal resistance
Junction-to-ambient (bottom) thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
125
70
–
θJA
θJCtop
θJB
–
–
–
–
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
θJCbot
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
RECOMMENDED OPERATING CONDITIONS
MIN
2.3
0
NOM
MAX UNIT
VI
IO
Input voltage range
4.35(1)
500
5
V
Output current range
mA
µF
µF
°C
°C
Additional output capacitance (PFM/PWM operation)(2)
Additional output capacitance (PWM operation)(2)
Ambient temperature
0
0
8
TA
TJ
–40
–40
+85
+125
Operating junction temperature
(1) Operation above 4.35V input voltage for extended periods may affect device reliability. See input capacitor selection section for more
details.
(2) In certain applications larger capacitor values can be tolerable, see output capacitor selection section for more details.
ELECTRICAL CHARACTERISTICS
Minimum and maximum values are at VI = 2.3V to 4.35V, VO = 2.5V, EN = 1.8V, AUTO mode and TA = –40°C to 85°C; Circuit
of Parameter Measurement Information section (unless otherwise noted). Typical values are at VI = 3.6V, VO = 2.5V, EN =
1.8V, AUTO mode and TA = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY CURRENT
IO = 0mA. Device not switching
24
4.5
0.5
50
μA
mA
μA
Operating quiescent
current
IQ
TPS82690
TPS8269X
IO = 0mA, PWM mode
EN = GND
ISD
Shutdown current
5
2.1
TPS82690
TPS82695
TPS82697
2.05
2.1
V
V
Undervoltage
lockout threshold
UVLO
TPS82696
2.15
PROTECTION
Thermal shutdown
140
10
°C
°C
TPS8269X
Thermal shutdown
hysteresis
Peak input current
limit
ILIM
TPS8269X
TPS8269X
750
15
mA
mA
Input current limit
under short-circuit
conditions
ISC
VO shorted to ground
ENABLE, MODE
High-level input
voltage
VIH
VIL
1.0
3.6
V
V
Low-level input
voltage
TPS8269X
TPS8269X
0.4
1.5
Input leakage
current
Input connected to GND or VIN
0.01
4
μA
OSCILLATOR
fSW Oscillator frequency
IO = 0mA. PWM operation. TA = 25°C
4.4
MHz
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ELECTRICAL CHARACTERISTICS (continued)
Minimum and maximum values are at VI = 2.3V to 4.35V, VO = 2.5V, EN = 1.8V, AUTO mode and TA = –40°C to 85°C; Circuit
of Parameter Measurement Information section (unless otherwise noted). Typical values are at VI = 3.6V, VO = 2.5V, EN =
1.8V, AUTO mode and TA = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
0.98×VNOM
0.98×VNOM
TYP
VNOM
VNOM
MAX UNIT
OUTPUT
3.25V ≤ VI ≤ 4.35V, 0mA ≤ IO ≤ 500 mA
PFM/PWM operation
1.04×VNOM
V
V
3.25V ≤ VI ≤ 4.35V, 0mA ≤ IO ≤ 500 mA
Additional output capacitor, CO= 4.7μF 6.3V 0402
(muRata GRM155R60J475M)
1.03×VNOM
TPS82690
TPS82697
PFM/PWM operation
3.25V ≤ VI ≤ 5.5V, 0mA ≤ IO ≤ 500 mA
PFM/PWM operation
0.98×VNOM
0.98×VNOM
0.98×VNOM
0.97×VNOM
0.98×VNOM
0.97×VNOM
VNOM
VNOM
VNOM
VNOM
VNOM
VNOM
1.05×VNOM
1.02×VNOM
1.04×VNOM
1.05×VNOM
1.02×VNOM
1.05×VNOM
V
V
V
V
V
V
3.25V ≤ VI ≤ 5.5V, 0mA ≤ IO ≤ 500 mA
PWM operation
3.0V ≤ VI ≤ 4.35V, 0mA ≤ IO ≤ 500 mA
PFM/PWM operation
Regulated DC
output voltage
3.0V ≤ VI ≤ 5.5V, 0mA ≤ IO ≤ 500 mA
PFM/PWM operation
TPS82695
V(OUT)
3.0V ≤ VI ≤ 5.5V, 0mA ≤ IO ≤ 500 mA
PWM operation
3.25V ≤ VI ≤ 5.5V, 0mA ≤ IO ≤ 500 mA
PFM/PWM operation
3.25V ≤ VI ≤ 4.35V, 0mA ≤ IO ≤ 500 mA
Additional output capacitor, CO= 4.7μF 6.3V 0402
(muRata GRM155R60J475M)
TPS82696
TPS8269X
0.97×VNOM
0.97×VNOM
VNOM
1.04×VNOM
1.03×VNOM
V
PFM/PWM operation
3.25V ≤ VI ≤ 5.5V, 0mA ≤ IO ≤ 500 mA
PWM operation
VNOM
V
Line regulation
Load regulation
VI = VO + 0.5V (min 3.25V) to 5.5V, IO = 200 mA
IO = 0mA to 500 mA. PWM operation
0.18
%/V
–0.0002
%/mA
Feedback input
resistance
TPS8269X
TPS8269X
480
kΩ
Input-to-output
On-resistance
rDS(on)
VI = 3.25 V. Device not switching
IO = 1mA
390
70
mΩ
mVPP
Power-save mode
ripple voltage
IO = 1mA
ΔVO
TPS8269X
Additional output capacitor, CO= 4.7μF 6.3V 0402
(muRata GRM155R60J475M)
35
mVPP
IO = 0mA, Time from active EN to VO
130
350
μs
μs
TPS82690
TPS82696
TPS82697
Start-up time
Time from active EN to full load current operation
permitted
Discharge resistor
for power-down
sequence
rDIS
TPS8269X
100
150
Ω
4
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TPS82690
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TPS82697
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SLVSA66B –JUNE 2011–REVISED FEBRUARY 2012
PIN ASSIGNMENTS
SIP-8
(TOP VIEW)
SIP-8
(BOTTOM VIEW)
A1
A2
B2
C2
A3
A3
A2
B2
C2
A1
B1
C1
VOUT
MODE
GND
VIN
EN
VIN
EN
VOUT
MODE
GND
B1
C1
C3
C3
GND
GND
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
VOUT
VIN
NO.
A1
O
I
Power output pin. Apply output load between this pin and GND.
A2, A3
The VIN pins supply current to the TPS8269xSIP's internal regulator.
This is the enable pin of the device. Connecting this pin to ground forces the converter into
shutdown mode. Pulling this pin to VI enables the device. This pin must not be left floating and
must be terminated.
EN
B2
I
This is the mode selection pin of the device. This pin must not be left floating and must be
terminated.
MODE = LOW: The device is operating in regulated frequency pulse width modulation mode
(PWM) at high-load currents and in pulse frequency modulation mode (PFM) at light load
currents.
MODE
GND
B1
I
MODE = HIGH: Low-noise mode enabled, regulated frequency PWM operation forced.
Ground pin.
C1, C2, C3
–
FUNCTIONAL BLOCK DIAGRAM
MODE
EN
VIN
CI
4.7µF
DC/DC CONVERTER
Undervoltage
VIN
Lockout
Bias Supply
Soft-Start
Negative Inductor
Current Detect
Bandgap
VREF = 0.8 V
Power Save Mode
Switching
Current Limit
Detect
Thermal
Shutdown
Frequency
Control
R
1
-
L
Gate Driver
VOUT
Anti
Shoot-Through
1µH
R
VREF
2
CO
4.7µF
+
Feedback Divider
GND
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SLVSA66B –JUNE 2011–REVISED FEBRUARY 2012
www.ti.com
PARAMETER MEASUREMENT INFORMATION
TPS8269XSIP
DC/DC Converter
L
V
SW
VOUT
VIN
BAT
CI
CO
FB
GND
EN
MODE
ENABLE
MODE
SELECTION
GND
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
vs Load current
vs Load current
vs Input voltage
3, 4
5, 6
η
Efficiency
7
Peak-to-peak output ripple voltage
DC output voltage
vs Load current
vs Load current
8, 9
VO
10, 11, 120
Combined line/load transient
response
13, 14
Load transient response
AC load transient response
PFM/PWM boundaries
Quiescent current
15, 16, 17, 18
19, 20, 21, 22, 23, 24, 25
vs Input voltage
vs Input voltage
vs Input voltage
vs Load current
26
27
IQ
fs
PWM switching frequency
PFM switching frequency
Start-up
28
29
30, 31
32
PSRR
Power supply rejection ratio
vs. Frequency
6
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SLVSA66B –JUNE 2011–REVISED FEBRUARY 2012
TYPICAL CHARACTERISTICS (continued)
TPS82695
EFFICIENCY
vs
TPS82695
EFFICIENCY
vs
LOAD CURRENT
LOAD CURRENT
100
90
80
70
60
50
40
30
20
10
100
V = 3 V
V
= 2.5 V
I
O
90 Forced PWM
80
70
60
50
40
30
20
V = 3.2 V
I
V = 3 V
I
V = 3.6 V
I
V = 3.2 V
I
V = 4.2 V
I
V = 3.6 V
I
V = 3.6 V
I
Forced PWM Operation
V = 4.2 V
I
10
0
V
= 2.5 V
O
0
0.1
1
10
100
1000
1
10
100
1000
IO - Load Current - mA
IO - Load Current - mA
Figure 3.
Figure 4.
EFFICIENCY
vs
EFFICIENCY
vs
LOAD CURRENT
LOAD CURRENT
100
90
80
70
60
50
40
30
20
100
V
= 2.85 V
V
= 2.85 V
O
O
90
80
70
V = 3 V
I
Forced PWM
V = 3 V
I
V = 3.2 V
I
V = 3.2 V
I
Forced PWM
V = 3.6 V
I
60 V = 4.2 V
I
V = 3.6 V
I
Forced PWM
50
40
30
20
10
V = 4.2 V
I
Forced PWM
V = 3.6 V
I
Forced PWM Operation
10
0
0
0.1
1
10
I
100
- Load Current - mA
1000
1
10
- Load Current - mA
100
1000
I
O
O
Figure 5.
Figure 6.
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TYPICAL CHARACTERISTICS (continued)
EFFICIENCY
PEAK-TO-PEAK OUTPUT RIPPLE VOLTAGE
vs
vs
INPUT VOLTAGE
LOAD CURRENT
100
90
80
70
60
50
40
30
20
10
0
100
98
96
94
92
90
88
86
V
= 2.85 V
V
= 2.85 V
O
O
PFM/PWM Operation
I
= 100 mA
O
V = 3.3 V
I
I
= 300 mA
O
V = 4.5 V
I
I
= 1 mA
O
I
= 10 mA
O
V = 3.6 V
I
84
82
PFM/PWM Operation
50 100 150 200 250 300 350 400 450 500
2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9
0
V - Input Voltage - V
I
I
- Load Current - mA
O
Figure 7.
Figure 8.
PEAK-TO-PEAK OUTPUT RIPPLE VOLTAGE
DC OUTPUT VOLTAGE
vs
vs
LOAD CURRENT
LOAD CURRENT
2.936
2.907
2.879
2.85
55
50
45
40
35
30
25
20
15
10
V
= 2.85 V
V
= 2.85 V
O
O
PFM/PWM Operation
C
(additional) = 4.7 mF 0402 6.3 V X5R
O
V = 3.2 V
I
V = 3.3 V
I
V = 4.5 V
I
V = 3.6 V
I
V = 4.5 V
I
2.822
V = 3.6 V
I
V = 3 V
I
2.793
2.765
5
0
PFM/PWM Operation
50 100 150 200 250 300 350 400 450 500
0
0.1
1
10
- Load Current - mA
100
1000
I
- Load Current - mA
I
O
O
Figure 9.
Figure 10.
8
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SLVSA66B –JUNE 2011–REVISED FEBRUARY 2012
TYPICAL CHARACTERISTICS (continued)
DC OUTPUT VOLTAGE
DC OUTPUT VOLTAGE
vs
vs
LOAD CURRENT
LOAD CURRENT
2.936
2.907
2.879
2.85
2.907
2.879
V = 3 V
I
V = 3 V, T = 25°C
I
A
V = 3 V, T = 85°C
V = 3.2 V
I
I
A
V = 4.5 V
I
V = 3.2 V, T = 25°C
I
A
V = 3.6 V
I
2.85
V = 3.1 V, T = 85°C
I
A
2.822
2.793
2.822
V = 3.2 V, T = 85°C
I
A
V
= 2.85 V
O
2.793
2.765
C
(additional) = 4.7 mF 0402 3.6 V X5R
O
PFM/PWM Operation
2.765
2.736
V
= 2.85 V
O
PFM/PWM Operation
0.1
1
10
- Load Current - mA
100
1000
0.1
1
10
- Load Current - mA
100
1000
I
I
O
O
Figure 11.
Figure 12.
COMBINED LINE/LOAD TRANSIENT RESPONSE
COMBINED LINE/LOAD TRANSIENT RESPONSE
V
= 2.85 V
MODE = Low
V = 2.85 V
O
MODE = Low
O
10 to 400 mA Load Step
10 to 400 mA Load Step
3.15V to 3.75V mA Line Step
3.3V to 3.9V mA Line Step
Figure 13.
Figure 14.
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TYPICAL CHARACTERISTICS (continued)
LOAD TRANSIENT RESPONSE IN
PFM/PWM OPERATION
LOAD TRANSIENT RESPONSE IN
PFM/PWM OPERATION
10 to 400 mA Load Step
V = 3.6 V,
I
V
= 2.85 V
O
5 to 250 mA Load Step
V = 3.6 V,
I
V
= 2.85 V
O
MODE = Low
MODE = Low
Figure 15.
Figure 16.
LOAD TRANSIENT RESPONSE IN
PFM/PWM OPERATION
LOAD TRANSIENT RESPONSE IN
PFM/PWM OPERATION
10 to 400 mA Load Step
10 to 400 mA Load Step
V = 3.25 V,
V = 4.8 V,
I
I
V
= 2.85 V
V = 2.85 V
O
O
MODE = Low
MODE = Low
Figure 17.
Figure 18.
10
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SLVSA66B –JUNE 2011–REVISED FEBRUARY 2012
TYPICAL CHARACTERISTICS (continued)
AC LOAD TRANSIENT RESPONSE
AC LOAD TRANSIENT RESPONSE
V
V
= 3.6 V,
= 2.5 V
V
V
= 3.0 V,
= 2.5 V
I
I
O
O
5 to 500 mA Load Sweep
5 to 500 mA Load Sweep
MODE = Low
MODE = Low
Figure 19.
Figure 20.
AC LOAD TRANSIENT RESPONSE
AC LOAD TRANSIENT RESPONSE
V
V
= 2.85 V,
= 2.5 V
V = 3.05 V,
I
I
V
= 2.85 V
O
O
5 to 600 mA Load Sweep
5 to 600 mA Load Sweep
MODE = Low
MODE = Low
Figure 21.
Figure 22.
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TYPICAL CHARACTERISTICS (continued)
AC LOAD TRANSIENT RESPONSE
AC LOAD TRANSIENT RESPONSE
V = 3.15 V,
V = 3.6 V,
I
I
V
= 2.85 V
V
= 2.85 V
O
O
5 to 500 mA Load Sweep
5 to 500 mA Load Sweep
MODE = Low
MODE = Low
Figure 23.
Figure 24.
AC LOAD TRANSIENT RESPONSE
PFM/PWM BOUNDARIES
280
V
= 2.85 V
O
V = 3.6 V,
260
240
220
200
180
160
140
120
100
80
I
V
= 2.85 V
O
Always PWM
5 to 500 mA Load Sweep
PFM to PWM
Mode Change
The switching mode changes
at these borders
Always PFM
PWM to PFM
Mode Change
60
MODE = Low
C
= add. 4.7µF 6.3V X5R 0402
O
40
20
0
3.2
3.4
3.6
3.8
4.0
4.2
4.4
4.6
4.8
V - Input Voltage - V
I
Figure 25.
Figure 26.
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TYPICAL CHARACTERISTICS (continued)
QUIESCENT CURRENT
PWM SWITCHING FREQUENCY
vs
vs
INPUT VOLTAGE
INPUT VOLTAGE
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
4.2
4
T
= 85°C
A
3.8
3.6
3.4
3.2
3
T
= 25°C
A
I
= 500 mA
O
I
= 300 mA
O
2.8
2.6
2.4
2.2
2
I
= 150 mA
T
= -40°C
O
A
I
= 50 mA
O
6
4
V
= 2.85 V
O
MODE = High
2
1.8
1.6
0
2.7
3
3.3
3.6
3.9
V - Input Voltage - V
4.2
4.5
4.8
2.9
3.1
3.3
3.5
3.7
V - Input Voltage - V
3.9
4.1 4.3 4.5
I
I
Figure 27.
Figure 28.
PFM SWITCHING FREQUENCY
vs
LOAD CURRENT
START-UP
4.5
4
V = 4.5 V
I
V
= 2.85 V
O
MODE = Low
3.5
3
V = 3.6 V,
I
V
I
= 2.85 V,
O
= 0 mA
O
V = 3.6 V
I
2.5
2
1.5
1
V = 3.2 V
I
MODE = Low
0.5
0
0
40 80 120 160 200 240 280 320 360 400
- Load Current - mA
I
O
Figure 29.
Figure 30.
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TYPICAL CHARACTERISTICS (continued)
POWER SUPPLY REJECTION RATIO
vs
START-UP
FREQUENCY
60
55
50
45
40
35
30
25
20
15
10
5
I
= 20 mA
O
PWM Operation
V = 3.6 V,
I
V
= 2.85 V,
O
I
= 250 mA
O
R
= 39 W
L
PWM Operation
I
= 400 mA
O
PWM Operation
MODE = Low
I
= 20 mA
O
PFM Operation
0
0.1
1
10
f - Frequency - kHz
100
1000
Figure 31.
Figure 32.
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SLVSA66B –JUNE 2011–REVISED FEBRUARY 2012
DETAILED DESCRIPTION
OPERATION
The TPS8269xSIP is a standalone synchronous step-down converter operating at a regulated 4-MHz frequency
pulse width modulation (PWM) at moderate to heavy load currents (up to 500mA output current). At light load
currents, the TPS8269xSIP's converter operates in power-save mode with pulse frequency modulation (PFM).
The converter uses a unique frequency locked ring oscillating modulator to achieve best-in-class load and line
response. One key advantage of the non-linear architecture is that there is no traditional feed-back loop. The
loop response to change in VO is essentially instantaneous, which explains the transient response. Although this
type of operation normally results in a switching frequency that varies with input voltage and load current, an
internal frequency lock loop (FLL) holds the switching frequency constant over a large range of operating
conditions.
Combined with best in class load and line transient response characteristics, the low quiescent current of the
device (ca. 24μA) allows to maintain high efficiency at light load, while preserving fast transient response for
applications requiring tight output regulation.
The TPS8269xSIP integrates an input current limit to protect the device against heavy load or short circuits and
features an undervoltage lockout circuit to prevent the device from misoperation at low input voltages.
POWER-SAVE MODE
If the load current decreases, the converter will enter Power Save Mode operation automatically. During
power-save mode the converter operates in discontinuous current (DCM) with a minimum of one pulse, which
produces low output ripple compared with other PFM architectures.
When in power-save mode, the converter resumes its operation when the output voltage trips below the nominal
voltage. It ramps up the output voltage with a minimum of one pulse and goes into power-save mode when the
output voltage is within its regulation limits again.
PFM mode is left and PWM operation is entered as the output current can no longer be supported in PFM mode.
As a consequence, the DC output voltage is typically positioned ca. 1.5% above the nominal output voltage and
the transition between PFM and PWM is seamless.
PFM Mode at Light Load
PFM Ripple
Nominal DC Output Voltage
PWM Mode at Heavy Load
Figure 33. Operation in PFM Mode and Transfer to PWM Mode
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MODE SELECTION
The MODE pin allows to select the operating mode of the device. Connecting this pin to GND enables the
automatic PWM and power-save mode operation. The converter operates in regulated frequency PWM mode at
moderate to heavy loads and in the PFM mode during light loads, which maintains high efficiency over a wide
load current range.
Pulling the MODE pin high forces the converter to operate in the PWM mode even at light load currents. The
advantage is that the converter operates with a fixed frequency that allows simple filtering of the switching
frequency for noise-sensitive applications. In this mode, the efficiency is lower compared to the power-save
mode during light loads.
For additional flexibility, it is possible to switch from power-save mode to PWM mode during operation. This
allows efficient power management by adjusting the operation of the converter to the specific system
requirements.
LOW DROPOUT, 100% DUTY CYCLE OPERATION
The device starts to enter 100% duty cycle mode once input and output voltage come close together. In order to
maintain the output voltage, the DC/DC converter's high-side MOSFET is turned on 100% for one or more
cycles.
With further decreasing VIN the high-side switch is constantly turned on, thereby providing a low input-to-output
voltage difference. This is particularly useful in battery-powered applications to achieve longest operation time by
taking full advantage of the whole battery voltage range.
SOFT START
The TPS8269xSIP has an internal soft-start circuit that limits the inrush current during start-up. This limits input
voltage drops when a battery or a high-impedance power source is connected to the input of the MicroSiP™
converter.
The soft-start system progressively increases the switching on-time from a minimum pulse-width of 35ns as a
function of the output voltage. This mode of operation continues for c.a. 100μs after enable. Should the output
voltage not have reached its target value by that time, such as in the case of heavy load, the soft-start transitions
to a second mode of operation.
If the output voltage has raised above 0.5V (approximately), the converter increases the input current limit
thereby enabling the power supply to come-up properly. The start-up time mainly depends on the capacitance
present at the output node and load current.
ENABLE
The TPS8269xSIP device starts operation when EN is set high and starts up with the soft start as previously
described. For proper operation, the EN pin must be terminated and must not be left floating.
Pulling the EN pin low forces the device into shutdown. In this mode, all internal circuits are turned off and VIN
current reduces to the device leakage current, typically a few hundred nanoamps.
The TPS8269xSIP device can actively discharge the output capacitor when it turns off (refer to Ordering
Information Table). The integrated discharge resistor has a typical resistance of 100 Ω. The required time to
ramp-down the output voltage depends on the load current and the capacitance present at the output node.
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APPLICATION INFORMATION
INPUT CAPACITOR SELECTION
Because of the pulsating input current nature of the buck converter, a low ESR input capacitor is required to
prevent large voltage transients that can cause misbehavior of the device or interference in other circuits in the
system.
For most applications, the input capacitor that is integrated into the TPS8269x should be sufficient. If the
application exhibits a noisy or erratic switching frequency, experiment with additional input ceramic capacitance
to find a remedy.
The TPS8269x uses a tiny ceramic input capacitor. When a ceramic capacitor is combined with trace or cable
inductance, such as from a wall adapter, a load step at the output can induce ringing at the VIN pin. This ringing
can couple to the output and be mistaken as loop instability or can even damage the part. In this circumstance,
additional "bulk" capacitance, such as electrolytic or tantalum, should be placed between the input of the
converter and the power source lead to reduce ringing that can occur between the inductance of the power
source leads and CI.
OUTPUT CAPACITOR SELECTION
The advanced, fast-response, voltage mode, control scheme of the TPS8269x allows the use of a tiny ceramic
output capacitor (CO). For most applications, the output capacitor integrated in the TPS8269x is sufficient.
At nominal load current, the device operates in PWM mode; the overall output voltage ripple is the sum of the
voltage step that is caused by the output capacitor ESL and the ripple current that flows through the output
capacitor impedance. At light loads, the output capacitor limits the output ripple voltage and provides holdup
during large load transitions.
The TPS8269x is designed as a Point-Of-Load (POL) regulator, to operate stand-alone without requiring any
additional capacitance. Adding a 4.7μF ceramic output capacitor (X7R or X5R dielectric) generally works from a
converter stability point of view, helps to minimize the output ripple voltage in PFM mode and improves the
converter's transient response under when input and output voltage are close together.
For best operation (i.e. optimum efficiency over the entire load current range, proper PFM/PWM auto transition),
the TPS8269xSIP requires a minimum output ripple voltage in PFM mode. The typical output voltage ripple is ca.
1% of the nominal output voltage VO. The PFM pulses are time controlled resulting in a PFM output voltage
ripple and PFM frequency that depends (first order) on the capacitance seen at the MicroSiPTM DC/DC
converter's output.
In applications requiring additional output bypass capacitors located close to the load, care should be taken to
ensure proper operation. If the converter exhibits marginal stability or erratic switching frequency, experiment
with additional low value series resistance (e.g. 50 to 100mΩ) in the output path to find a remedy.
Because the damping factor in the output path is directly related to several resistive parameters (e.g. inductor
DCR, power-stage rDS(on), PWB DC resistance, load switches rDS(on) …) that are temperature dependant, the
converter small and large signal behavior must be checked over the input voltage range, load current range and
temperature range.
The easiest sanity test is to evaluate, directly at the converter’s output, the following aspects:
•
•
PFM/PWM efficiency
PFM/PWM and forced PWM load transient response
During the recovery time from a load transient, the output voltage can be monitored for settling time, overshoot or
ringing that helps judge the converter’s stability. Without any ringing, the loop has usually more than 45° of phase
margin.
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LAYOUT CONSIDERATION
In making the pad size for the SiP LGA balls, it is recommended that the layout use non-solder-mask defined
(NSMD) land. With this method, the solder mask opening is made larger than the desired land area, and the
opening size is defined by the copper pad width. Figure 34 shows the appropriate diameters for a MicroSiPTM
layout.
Figure 34. Recommended Land Pattern Image and Dimensions
(5)
(6)
SOLDER PAD
SOLDER MASK
OPENING
COPPER
THICKNESS
STENCIL
COPPER PAD
STENCIL THICKNESS
DEFINITIONS(1)(2)(3)(4)
OPENING
Non-solder-mask
defined (NSMD)
0.30mm
0.360mm
1oz max (0.032mm)
0.34mm diameter
0.1mm thick
(1) Circuit traces from non-solder-mask defined PWB lands should be 75μm to 100μm wide in the exposed area inside the solder mask
opening. Wider trace widths reduce device stand off and affect reliability.
(2) Best reliability results are achieved when the PWB laminate glass transition temperature is above the operating the range of the
intended application.
(3) Recommend solder paste is Type 3 or Type 4.
(4) For a PWB using a Ni/Au surface finish, the gold thickness should be less than 0.5mm to avoid a reduction in thermal fatigue
performance.
(5) Solder mask thickness should be less than 20 μm on top of the copper circuit pattern.
(6) For best solder stencil performance use laser cut stencils with electro polishing. Chemically etched stencils give inferior solder paste
volume control.
SURFACE MOUNT INFORMATION
The TPS8269x MicroSiP™ DC/DC converter uses an open frame construction that is designed for a fully
automated assembly process and that features a large surface area for pick and place operations. See the "Pick
Area" in the package drawings.
Package height and weight have been kept to a minimum thereby to allow the MicroSiP™ device to be handled
similarly to a 0805 component.
See JEDEC/IPC standard J-STD-20b for reflow recommendations.
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SLVSA66B –JUNE 2011–REVISED FEBRUARY 2012
THERMAL INFORMATION
The die temperature of the TPS8269x must be lower than the maximum rating of 125°C, so care should be taken
in the layout of the circuit to ensure good heat sinking of the TPS8269x.
To estimate the junction temperature, approximate the power dissipation within the TPS8269x by applying the
typical efficiency stated in this datasheet to the desired output power; or, by taking a power measurement if you
have an actual TPS8269x device and TPS8269xEVM evaluation module. Then calculate the internal temperature
rise of the TPS8269x above the surface of the printed circuit board by multiplying the TPS8269x power
dissipation by the thermal resistance.
The actual thermal resistance of the TPS8269x to the printed circuit board depends on the layout of the circuit
board, but the thermal resistance given in the Thermal Information Table can be used as a guide.
Three basic approaches for enhancing thermal performance are listed below:
•
•
•
Improve the power dissipation capability of the PCB design.
Improve the thermal coupling of the component to the PCB.
Introduce airflow into the system.
PACKAGE SUMMARY
SIP PACKAGE
TOP VIEW
BOTTOM VIEW
A1
YML
C1
B1
A1
C2
C3
D
B2
A2
E
A3
CC
LSB
Code:
•
•
•
CC — Customer Code (device/voltage specific)
YML — Y: Year, M: Month, L: Lot trace code
LSB — L: Lot trace code, S: Site code, B: Board locator
MicroSiPTM DC/DC MODULE PACKAGE DIMENSIONS
The TPS8269x device is available in an 8-bump ball grid array (BGA) package. The package dimensions are:
•
•
D = 2.30 ±0.05 mm
E = 2.90 ±0.05 mm
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Note: Page numbers of current version may differ from previous versions.
Changes from Original (June 2011) to Revision A
Page
•
Deleted Product Preview status from TPS82695 device in Ordering Information table. ...................................................... 2
Changes from Revision A (October 2011) to Revision B
Page
•
•
Added device number TPS82697 ......................................................................................................................................... 1
Added Efficiency vs Load Current Graphs. Figure 3 and Figure 4 ....................................................................................... 6
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PACKAGE OPTION ADDENDUM
www.ti.com
26-May-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TPS82690SIPR
TPS82690SIPT
TPS82695SIPR
TPS82695SIPT
PREVIEW
PREVIEW
ACTIVE
uSiP
uSiP
uSiP
uSiP
SIP
SIP
SIP
SIP
8
8
8
8
3000
250
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
3000
250
ACTIVE
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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