TPS9103_09 [TI]
POWER SUPPLY FOR GAAS POWER AMPLIFIERS;
| 型号： | TPS9103_09 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | POWER SUPPLY FOR GAAS POWER AMPLIFIERS 放大器 功率放大器 |
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TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A – OCTOBER 1995 – REVISED JULY 1996
PW PACKAGE
(TOP VIEW)
Charge Pump Provides Negative Gate Bias
for Depletion-Mode GaAs Power Amplifiers
Buffered Clock Output to Drive Additional
External Charge Pump
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
GATE_BIAS
V
DD
CLK
BCLK
GND
BATT_OUT
BATT_OUT
BATT_OUT
SW_EN
OSC_EN
EN
V
CC
135-mΩ High-Side Switch Controls Supply
Voltage to the GaAs Power Amplifier
C1–
C1+
BATT_IN
BATT_IN
BATT_IN
PGP
Power-Good Circuitry Prevents High-Side
Switch Turn-on Until Negative Gate Bias is
Present
Charge Pump Can Be Driven From the
Internal Oscillator or An External Clock
PG
GND
10-µA Maximum Standby Current
Low-Profile (1.2-mm Max Height), 20-Pin
TSSOP Package
description
The TPS9103 is a highly integrated power supply for depletion-mode GaAs power amplifiers (PA) in cellular
handsets and other wireless communications equipment. Functional integration and low-profile packaging
combine to minimize circuit-board area and component height requirements. The device includes: a p-channel
MOSFET configured as a high-side switch to control the application of power to the PA; a driver for the high-side
switch with a logic-compatible input; a charge pump to provide negative gate-bias voltage; and logic to prevent
turn-on of the high-side switch until gate bias is present. The high-side switch has a typical on-state resistance
of 135 mΩ.
The TPS9103 is available in a 20-pin thin shrink small-outline package (TSSOP) or in chip form. Contact factory
for die sales. The device operates over a junction temperature range of –25°C to 125°C.
AVAILABLE OPTIONS
PACKAGED DEVICE
CHIP FORM
T
A
TSS0P
(PW)
(Y)
–25°C to 85°C
TPS9103PWLE
TPS9103Y
The PW package is only available left-end taped and reeled
(indicated by the LE suffix on the device type).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A – OCTOBER 1995 – REVISED JULY 1996
functional block diagram
14, 15, 16
3
3
5, 6, 7
BATT_IN
BATT_OUT
V
CC
UVLO
2
V
CC
13
9
18
20
SW_EN
PG
BCLK
UVDLO
V
DD
EN
11
12
8
V
ref
REF
+
OSC
OSC_EN
PGP
19
CLK
PG
Comparator
R
Inverting
Charge
Pump
4
3
0.6R
C1+
C1–
1
GATE_BIAS
10, 17
GND
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A – OCTOBER 1995 – REVISED JULY 1996
TPS9103Y chip information
This chip, when properly assembled, displays characteristics similar to the TPS9103. Thermal compression or
ultrasonic bonding may be used on the doped-aluminum bonding pads. The chips may be mounted with
conductive epoxy or a gold-silicon preform. Contact factory for die sales.
BONDING PAD ASSIGNMENTS
(1 )
(3)
(2)
(20)
(18)
(19)
V
CC
V
DD
2
20
4
3
C1+
C1–
1
(4)
GATE_BIAS
5, 6, 7
BATT_IN
PGP
14, 15, 16
8
9
BATT_OUT
TPS9103Y
PG
11
12
13
(17)
EN
OSC_EN
SW_EN
CLK
18
19
BCLK
116
(16)
10, 17
GND
(5)
(15)
CHIP THICKNESS: 15 TYPICAL
BONDING PADS: 4 × 4 MINIMUM
max = 150°C
(6)
T
J
TOLERANCES ARE ±10%.
(14)
(13)
ALL DIMENSIONS ARE IN MILS.
(7)
(8)
(9)
(10)
(11)
(12)
83
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A – OCTOBER 1995 – REVISED JULY 1996
Terminal Functions
TERMINAL
NAME
GATE_BIAS
DESCRIPTION
NO.
1
Negative gate-bias output voltage
V
CC
2
Logic supply voltage
C1–
3
External capacitor connection (inverting charge pump)
External capacitor connection (inverting charge pump)
High-side switch input voltage
High-side switch input voltage
High-side switch input voltage
Program input for power-good threshold
Power-good output
C1+
4
BATT_IN
BATT_IN
BATT_IN
PGP
5
6
7
8
PG
9
GND
10
11
12
13
14
15
16
17
18
19
20
Ground
EN
Chip-enable input
OSC_EN
SW_EN
BATT_OUT
BATT_OUT
BATT_OUT
GND
Oscillator-enable input
High-side switch enable input
High-side switch output voltage
High-side switch output voltage
High-side switch output voltage
Ground
BCLK
Buffered clock output
CLK
Clock (bidirectional)
V
DD
Charge-pump supply voltage
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A – OCTOBER 1995 – REVISED JULY 1996
detailed description
high-side switch and driver (BATT_IN, BATT_OUT, SW_EN)
The high-side switch is a p-channel MOSFET with a maximum on-state resistance of 180 mΩ
(V
= 6 V and V
= 3.3 V). The driver pulls the gate of the high-side switch to GATE_BIAS instead of
I(BATT_IN)
CC
ground to reduce the MOSFET on-state resistance. Gate breakdown considerations limit the voltage between
BATT_IN and GATE_BIAS to 15 V. Extremely fast switching times are not required in this application, and the
high-sideswitch/driverisdesignedtoprovide2µsmaximumswitchingtimeswithminimumpowerconsumption.
The GaAs depletion-mode MOSFETs in the PA are protected from damage at power-up by internal logic that
inhibits the driver until negative gate bias is available. The control input SW_EN is compatible with 3-V and 5-V
CMOS logic; a logic-high input turns the high-side switch on.
oscillator (OSC_EN, CLK)
The internal oscillator drives the charge pump at 50 kHz with a nominal duty cycle of 50% when both the EN
and OSC_EN inputs are logic lows. CLK outputs the internal oscillator signal (no buffer). A logic-high input to
OSC_EN disables the internal oscillator and allows the charge pump to operate from an external clock
connected to CLK. When an external clock with negative overshoot is applied, a Schottky diode must be added
to limit the amplitude of the overshoot.
charge pump (GATE_BIAS, C1+, C1–)
The inverting charge pump generates the negative gate-bias voltage output at GATE_BIAS.
chip enable (EN)
A logic high on EN shuts down the internal functions of the TPS9103 and turns the bias system off, reducing
the supply current to less than 10 µA. A low input on EN causes normal operation to resume.
power good (PG, PGP)
PG output is logic high when GATE_BIAS is in regulation. PG output is logic low when GATE_BIAS is not in
regulation. The high-side switch is disabled and PG is forced to logic low whenever the magnitude of
GATE_BIAS is less than 0.6 × V . A modified threshold for the power-good function can be achieved by
DD
programming PGP with an external resistor.
undervoltage lockout for V
and V
(UVLO and UVDLO)
DD
CC
Undervoltage lockout prevents operation at supply voltages too low for proper operation. When UVLO or
UVDLO is active, all power-switch drives are forced to the off state and bias is removed from unneeded
functions. Hysteresis is provided to minimize cycling on and off because of source impedance loading when the
supply voltage is close to the threshold.
buffered clock output (BCLK)
The buffered clock output is a driver for an external charge pump. When the optional external charge pump is
not needed, BCLK should be left unconnected. For more details, see the application section.
supply input for inverting charge pump (V
)
DD
V
is the supply voltage for the inverting charge pump. In normal operation, V
is connected to V . If the
DD
DD CC
negative gate-bias needs to be larger than V
connected to V . This can be supplied from an external charge pump driven from BCLK.
(i.e., more negative), then a higher voltage supply needs to be
CC
DD
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A – OCTOBER 1995 – REVISED JULY 1996
DISSIPATION RATING TABLE
DERATING FACTOR
T
≤ 25°C
T
A
= 70°C
T = 85°C
A
POWER RATING
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING
A
PW
645 mW
6.5 mW/°C
353 mW
255 mW
Maximum values are calculated using a derating factor based on R
mounted on an FR4 board with no special thermal considerations.
= 154°C/W for the package. These devices are
θJA
700
PW Package
= 154°C/W
R
θJA
600
500
400
300
200
100
0
25
35
45
55
65
75
85
T
A
– Free-Air Temperature – °C
Figure 1. Dissipation vs Free-Air Temperature
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
High-side switch input voltage range, BATT_IN (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 15 V
Supply voltage range, V , V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
CC DD
Differential voltage, |BATT_IN|–|GATE_BIAS| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
Input voltage range, SW_EN, EN, CLK, OSC_EN, PG . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V + 0.3 V
CC
GATE_BIAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5.5 V
Output current, PG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA
Output current, BCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Output current, GATE_BIAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA
Output current, BATT_OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 A
Peak output current, BATT_OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 A
Maximum external clock frequency, CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 kHz
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25°C to 150°C
J
stg
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to device GND.
2. Differential voltage calculated: |V max| + |GATE_BIAS|
I
6
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TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A – OCTOBER 1995 – REVISED JULY 1996
recommended operating conditions
MIN NOM
MAX
9
UNIT
V
Input voltage, BATT_IN
3
2.7
–2
0
Supply voltage, V
V
5.5
–5
10
2
V
CC, DD
Output voltage, GATE_BIAS, V
V
O
Continuous output current, GATE_BIAS
Continuous output current, BATT_OUT
Charge-pump capacitor value at C1+/C1–
External clock frequency, CLK
mA
A
0
0.33
25
2
µF
kHz
V
75
High-level input voltage, V
IH
Low-level input voltage, V
SW_EN, EN, OSC_EN, CLK
0.8
1
V
IL
Input current, I
–1
µA
°C
I
Operating junction temperature, T
–25
125
J
electrical characteristics over recommended operating junction temperature range,
BATT_IN = 6 V, V = V = 3.3 V, I = 0.5 A, I = 2 mA,
CC
DD
O(BATT_OUT)
O(GATE_BIAS)
EN = OSC_EN = 0 V, SW_EN = V , C1 = 0.33 µF (unless otherwise noted)
CC
charge pump
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
Output voltage
–3 –3.10
95
–3.3
Output resistance
Ω
high-side switch
PARAMETER
TEST CONDITIONS
MIN
TYP
135
MAX
180
210
220
260
1
UNIT
T
= 25°C
A
T
A
= –25°C to 85°C
= 25°C,
Dran-to-source on-state resistance
mΩ
V
= 3 V
T
A
160
I(BATT_IN)
T
A
= –25°C to 85°C, BATT_IN = 3 V
V
= 9 V,
= 9 V,
T
A
= 25°C,
= 85°C,
SW_EN = 0 V
SW_EN = 0 V
I(BATT_IN)
I(BATT_IN)
Leakage current
µA
V
T
A
10
Delay to high-level output
Delay to low-level output
SW_EN from 0 to V
CC
0.2
0.9
2
µs
µs
SW_EN from V
to 0
2
CC
oscillator
PARAMETER
Frequency
TEST CONDITIONS
MIN
35
40%
TYP
MAX
60
UNIT
V
V
= 2.7 V to 5.5 V
= 2.7 V to 5.5 V
50
kHz
CC
Duty cycle
50%
60%
CC
buffered clock output (BCLK)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Ω
Output resistance
10
High-level output voltage
Low-level output voltage
I(BCLK) = 30 mA
I(BCLK) = 30 mA
V
CC
–0.3
V
0.3
V
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A – OCTOBER 1995 – REVISED JULY 1996
power good (PG)
PARAMETER
Threshold voltage
TEST CONDITIONS
= 2.7 V to 5.5 V
MIN
TYP
MAX
UNIT
V
V
DD
0.60 × V
DD
On-state voltage
Off-state voltage
Hysteresis
I
= 500 µA,
=–500µA,
V
= 2.7 V to 5.5 V
= 2.7 V to 5.5 V
0.3
V
O(PG)
CC
CC
I
V
V
CC
–0.3
V
O(PG)
130
mV
power good (PGP)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Input impedance
85
kΩ
undervoltage lockout (UVLO + UVDLO)
PARAMETER
Start threshold voltage
Hysteresis
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
V
CC
increasing
2.4
2.7
130
mV
supply current (I
and I
)
CC
DD
PARAMETER
TEST CONDITIONS
MIN
TYP
1
MAX
10
UNIT
µA
Standby mode
EN = V
CC
= V
Undervoltage lockout
Operating mode
V
< 2.3 V
35
50
µA
CC
No load
DD
300
500
µA
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A – OCTOBER 1995 – REVISED JULY 1996
PARAMETER MEASUREMENT INFORMATION
5
6
7
14
15
16
BATT_IN
BATT_OUT
BATT_OUT
BATT_OUT
V
I(BATT_IN)
I
BATT_IN
BATT_IN
O(BATT_OUT)
C1
0.1 µF
2
V
CC
V
CC
1
20
+
GATE_BIAS
V
DD
C3
C4
I
O(GATE_BIAS)
C5
0.1 µF
C6
4.7 µF
4.7 µF
0.1 µF
4
3
+
C1+
TSP9103
C2
9
0.33 µF
C1–
V
CC
PG
PGP
10 kΩ
10 kΩ
10 kΩ
13
11
12
8
SW_EN
19
18
EN
CLK
OSC_EN
BCLK
I
O(BCLK)
GND GND
17 10
Figure 2. Test Circuit
4
3
V
CC
2
1
0
– 1
– 2
GATE BIAS
25 30
– 3
0
5
10
15
20
35
40 45
50
t – Time – ms
Figure 3. GATE_BIAS Output Voltage Rise Time
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A – OCTOBER 1995 – REVISED JULY 1996
PARAMETER MEASUREMENT INFORMATION
I
V
– GATE_BIAS = 5 mA
O
= V
= 5 V
CC
DD
20 mV/div
0
5
10
15
20
25
30
35
40
t – Time – µs
Figure 4. Ripple on GATE_BIAS
10
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TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A – OCTOBER 1995 – REVISED JULY 1996
TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
FIGURE
vs Gate-source voltage, dc
5
6
r
Static drain-source on-state resistance
Oscillator frequency
DS(on)
vs Temperature
vs Supply voltage
vs Temperature
vs Output current
vs CLK frequency
vs Temperature
vs Supply voltage
vs Temperature
7
F
osc
8
9
V
V
Output voltage
O
10
11
12
13
Threshold voltage
IT
Supply current (I
+ I )
CC DD
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
HIGH-SIDE SWITCH
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
TEMPERATURE
180
190
180
GATE-SOURCE VOLTAGE,
160
140
120
100
80
dc (V
–V
)
I(BATT_IN)
O(GATE_BIAS)
170
160
150
140
130
120
110
100
60
– 50 – 25
0
25
50
75
100
125
– 12
– 11
V
dc (V
– 10
– 9
– 8
– 7
– 6
T – Temperature –°C
– Gate-Source Voltage,
GS
–V
)
O(GATE_BIAS) I(BATT_IN)
Figure 5
Figure 6
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A – OCTOBER 1995 – REVISED JULY 1996
TYPICAL CHARACTERISTICS
OSCILLATOR FREQUENCY
vs
OSCILLATOR FREQUENCY
vs
SUPPLY VOLTAGE
TEMPERATURE
49
49.5
49
3.3 V
48
47
46
48.5
48
2.7 V
5 V
47.5
47
2.5
3
3.5
4
4.5
5
5.5
– 50 – 25
0
25
50
75
100
125
V
CC
– Supply Voltage – V
T – Temperature – °C
Figure 7
Figure 8
GATE BIAS
OUTPUT VOLTAGE
vs
GATE BIAS
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
CLK FREQUENCY
0
– 1
– 2
– 3
– 4
– 5
– 6
– 3
– 3.05
– 3.1
V
= 2.7 V
= 3.3 V
CC
– 3.15
– 3.2
V
CC
V
= 5 V
CC
– 3.25
– 3.3
0
1
2
3
4
5
6
7
8
9
10
25 30 35 40 45 50 55 60 65 70 75
f – CLK Frequency – kHz
I
O
– Output Current – mA
Figure 9
Figure 10
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A – OCTOBER 1995 – REVISED JULY 1996
TYPICAL CHARACTERISTICS
UNDERVOLTAGE LOCKOUT (V , V
)
CC DD
SUPPLY CURRENT (I
vs
+ I
)
THRESHOLD VOLTAGE
CC
DD
vs
SUPPLY VOLTAGE
TEMPERATURE
2.65
2.63
450
400
350
2.61
2.59
300
2.57
250
200
2.55
– 50 – 25
0
25
50
75
100
125
2.7
3.2
3.7
4.2
4.7
5.2
5.7
T – Temperature – °C
Supply Voltage – V
Figure 11
Figure 12
SUPPLY CURRENT (I
vs
+ I
)
CC
DD
TEMPERATURE
500
450
400
350
300
250
200
5.5 V
3.3 V
– 50 – 25
0
25
50
75
100
125
T – Temperature – °C
Figure 13
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A – OCTOBER 1995 – REVISED JULY 1996
THERMAL INFORMATION
Implementation of integrated circuits in low-profile and fine-pitch packages requires special attention to power
dissipation. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and convection
surfaces, and the presence of other heat-generating components affect the power-dissipation limits of a given
component.
Three basic approaches for enhancing thermal performance are listed below:
Improving the power-dissipation capability of the PWB design
Improving the thermal coupling of the component to the PWB
Introducing airflow in to the system
Using the given R
for this IC, the maximum power dissipation can be calculated with the equation:
θJA
T max
J
T
A
P max
D
R
JA
2
I
R
where I is the
For the TPS9103, the power dissipation is in the PMOSFET. To calculate the power, use:
current through the device and R is the internal resistance as shown in the electrical characteristics table.
For a V of 6 V, the resistance at 85°C is 0.210 Ω. At a current of 2 A, the peak power dissipation is:
I
2
P
2
0.210
0.84 W
D
Assuming a duty cycle of 1/8 or 0.125, the average power is:
0.84 W 0.125
0.105 W
The change in temperature is:
∆T = 0.105 W × 154°C/W = 16.2°C
and the junction temperature is:
T = 85°C + 16.2°C =101.2°C
J
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A – OCTOBER 1995 – REVISED JULY 1996
APPLICATION INFORMATION
introduction
Traditionally the RF power amplifier (PA) is powered directly from the battery, with a switching arrangement for
powering down when not in use. GaAs FET PAs require a negative bias voltage that must be present before
the supply is connected, or there is risk of destroying the FET. Logic must be provided to ensure the presence
of the negative bias voltage.
A secondary charge pump is necessary for systems in which the supply voltage is insufficiently high – the
negative bias produced from the charge pump is inadequate. In mobile telephony a second charge pump
(regulated or unregulated) may also be needed, e.g. for varicap diodes/VCOs and some preamplifiers. The
need for larger dynamic range or control-voltage range can become critical in certain applications.
the TPS9103 approach
TheTPS9103integratesaP-channelMOSFEThigh-sideswitchtogetherwithaselectableoscillatorandcharge
pump for the GaAs FET power-amplifier gate bias, which is monitored.
Complete precautions are taken to ensure that the PA supply is not enabled unless the gate bias is present while
V
and V
are also good. This protects the PA from inadvertent damage–without a major system size/cost
CC
DD
increase.
The bias regulation monitor is flexible, accommodating both fixed and programmable approaches. The fixed
resistors, provided internally, set the trip voltage to –0.6 x V . If V is 5 V, then the trip voltage is –3 V. Should
DD
DD
another value be preferred, it can be set by applying voltage divider to PGP. See the section “dimensioning the
external voltage divider” for more details.
The charge pump clock is also flexible. The on-chip oscillator runs at a nominal 50 kHz, or alternatively an
external oscillator can be connected to CLK. When an external clock is used, OSC_EN should be taken high
to disable the oscillator. When OSC_EN is low and the on-chip oscillator is used, CLK provides an unbuffered
clock output.
The circuit provides for a secondary charge pump driver. The buffered BCLK output can be used (with four
external components) to provide a higher supply, both for those system functions that require it and for those
GaAs PAs that need a more negative bias than is made possible by inverting the existing supply. This is
facilitated by use of single-cell Li-ion batteries.
Figure 14 shows the TPS9103 in a typical application.
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A – OCTOBER 1995 – REVISED JULY 1996
APPLICATION INFORMATION
5
6
7
14
15
16
Battery
4 V to 8 V
BATT_IN
PA Drain
BATT_OUT
BATT_OUT
BATT_OUT
BATT_IN
BATT_IN
C1
0.1 µF
13
4
XMIT
SW_EN
C1+
1
PA Gate–3 V
GATE_BIAS
C5
0.1 µF
C6
4.7 µF
TSP9103
C2
0.33 µF
+
3
C1–
2
20
11
12
9
V
3.3 V
CC
V
PG
PGP
CC
+
C3
C4
0.1 µF
8
V
DD
4.7 µF
19
18
EN
CLK
OSC_EN
BCLK
GND GND
17 10
Figure 14. Typical Application
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A – OCTOBER 1995 – REVISED JULY 1996
APPLICATION INFORMATION
capacitors of the internal inverting charge pump (see Figure 15)
This charge pump inverts the voltage at V
and provides a negative output voltage at GATE_BIAS.
DD
TPS9103
C +
Charge
GATE_BIAS
Pump
C2
C6
+
C –
Figure 15. Internal Inverting Charge Pump
The output capacitor C6 limits the voltage ripple at GATE_BIAS:
I
O(GATE_BIAS)
V
Ripple
C6
f
With a capacitor C6 of 4.7 µF and an output current of 10 mA, the voltage ripple at GATE_BIAS is 42 mV.
The capacitor C2 can be calculated using an equivalent resistance method:
1
C2
R
equivalent
f
Using 0.33 µF for C2, the equivalent resistance is:
1
R
60.6
equivalent
0.33
Add the internal resistance of the switches (35 Ω) to get a total resistance seen by the current:
60 35 95
F
50 kHz
R
TOTAL
With a total resistance of 95 Ω and 10 mA flowing through it, a voltage drop of 0.95 V occurs. With 5 V on V
the output is –4.05 V with a 42 mV ripple.
,
DD
The capacitors should have a low equivalent series resistance (ESR) to maintain low ripple and low noise.
Careful layout is required. In most instances it is advisable to add a small decoupling capacitor C5 close to the
GATE_BIAS.Anadditional0.1-µFcapacitoratotherlocationsmaybenecessaryifthepoweramplifierislocated
away from the TPS9103.
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A – OCTOBER 1995 – REVISED JULY 1996
APPLICATION INFORMATION
dimensioning of the external charge pump
For systems in which the bias voltage requirement is not met by inverting the power rail, the BCLK output can
be used (with four passive components) to generate a higher V
to produce the bias voltage. This voltage is also available for other parts of the main circuitry (see Figure 16).
The higher voltage is then inverted as before
DD.
With the TPS9103, an external charge pump could be used to increase the voltage at V , thereby deriving a
DD
higher negative voltage at GATE_BIAS than would otherwise be available.
V
CC
D1
BCLK
V
V
DD
1
D2
C7
+
C8
Figure 16. External Charge Pump
When BCLK is low, node 1 charges up to V
– V
. When BCLK goes high, node 1 is 2 V
– V
. The
diode
CC
diode
CC
capacitor C8 charges up to 2 V
– 2 V
. This voltage can then be connected to V
.
CC
diode
DD
The magnitude of V
of V
is determined by the value of C8. Capacitor value must be large enough that
DD
ripple
the discharge during one period is not as great as the maximum voltage variation allowable. The discharge of
C8 depends on the load current.
I
O(GATE_BIAS)
C8
V
ripple
f
With a supply voltage of V
= 3.3 V, a maximum voltage variation (V
) of 2% = 66 mV and a load of
ripple
CC
I
= 10 mA, the value of C8 is 3 µF. A 4.7 µF meets this requirement.
CC
The capacitance of C7 can be calculated using an equivalent resistance method:
1
C7
R
equivalent
f
Using 0.22 µF for C7, the equivalent resistance is:
1
R
90
equivalent
0.22
Add the equivalent resistance to the internal resistance of the switch (10 Ω):
= 90 + 10 = 100 Ω
F
50 kHz
R
TOTAL
With a total resistance of 100 Ω and with 10 mA flowing through it, a voltage drop of 1 V occurs. Thus with 3.3
V on V the output is 4.2 V with a 42-mV ripple.
CC
Care must be taken that the maximum voltages are not exceeded when using BCLK as a charge pump (see
Figure 17).
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A – OCTOBER 1995 – REVISED JULY 1996
APPLICATION INFORMATION
5
6
7
14
15
16
Battery
4 V to 8 V
BATT_IN
PA Drain
BATT_OUT
BATT_OUT
BATT_OUT
BATT_IN
BATT_IN
C1
0.1 µF
1
13
4
PA Gate–3 V
GATE_BIAS
XMIT
SW_EN
C1+
C5
0.1 µF
C6
+
4.7 µF
TSP9103
C2
0.33 µF
3
2
C1–
9
8
PG
V
CC
3.3 V
V
CC
PGP
+
C3
4.7 µF
C4
0.1 µF
19
20
18
CLK
11
12
V
EN
DD
OSC_EN
BCLK
C7
0.22 µF
+
GND GND
17 10
C8
4.7 µF
Figure 17. TPS9103 Configured With External Charge Pump
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A – OCTOBER 1995 – REVISED JULY 1996
dimensioning the external voltage divider
Drain voltage should only be applied to the power amplifier when the complete negative voltage from the
GATE_BIAS output is provided to the gate of the GaAs power amplifier. For that reason there is an internal
voltage divider R/0.6R and a PG comparator in the TPS9103 (see Figure 15). When the voltage at the inverting
input of the comparator reaches zero, the output goes high and the high-side MOSFET switches on, provided
a SW_EN high signal is applied. For example, when the supply voltage at V
switched on when the voltage at GATE_BIAS reaches –3 V.
is 5 V, the high-side switch is
DD
This trip point can be changed to another value by using an external voltage divider connected between V
,
DD
GATE_BIAS, and PGP. The resistor values should be low enough to minimize the error that is present when
the internal resistor values (typ R = 100 kΩ ± 30%) are taken into consideration. Therefore, the external resistor
values, R1 and R2, are chosen within the 10-kΩ range.
TPS9103
V
DD
R1
R2
R
PG Comparator
PGP
0.6 R
GATE_BIAS
Figure 18. External Voltage Divider for Setting the Trip Point
R1 = 10 kΩ. The value of R2 can then be calculated using:
0.6 R1
R
V
trip
R2
[
]
R
0.6
V
R1
V
R1
DD
trip
where V
= supply voltage, and V = chosen value to trip PG comparator.
DD
trip
The values of the internal resistor can vary about 30%, and can move the trip point. In a worst-case condition,
with a resistor variation of 30%, the shifting of the trip point can be calculated to:
R1 1.3
R1
R
0.6 R2
R2 0.78
0.6 R2
R2 0.6 R
R1
R1
R
V
V
trip_point
DD
R
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A – OCTOBER 1995 – REVISED JULY 1996
MECHANICAL DATA
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0,32
0,19
0,65
M
0,13
14
8
0,15 NOM
4,50
4,30
6,70
6,10
Gage Plane
0,25
1
7
0°–8°
0,75
A
0,50
Seating Plane
0,10
1,20 MAX
0,10 MIN
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
A MAX
A MIN
4040064/D 10/95
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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