TPS92410D 概述
用于离线 LED 驱动器的开关控制型、直接驱动、线性控制器 | D | 13 | -40 to 150 LED驱动器
TPS92410D 数据手册
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TPS92410
ZHCSCM9 –MAY 2014
TPS92410 用于离线 LED 驱动器的开关控制直接驱动线性控制器
1 特性
3 说明
1
•
乘法器适用于优良 PFC、线路调节和低 THD
VIN 范围从 9.5V 至 450V
与相位调光器兼容
模拟调光输入时关闭 LED
可编程过压保护
TPS92410 是一款具有高压启动功能的先进线性驱动
器,适用于低功耗离线 LED 照明应用。 该器件可与
TPS92411 直接驱动开关结合使用,用于调节流过
LED 的平均电流。
•
•
•
•
•
•
•
•
•
TPS92410 设有基准电压,可用于设定电流级别和温
度折返阈值。 此器件内含乘法器,可用于获取优异的
功率因数同时保持良好的线路调节性能。 其它特性包
括:欠压锁定、过压保护、正向相位调光器检测、切换
到恒流模式、温度折返以及热关断。
高精度 3V 基准
温度折返
热关断
无需电感器
13 引脚,高压,SOIC 封装
器件信息(1)
2 应用
部件号
封装
封装尺寸(标称值)
TPS92410D
SOIC (13)
8.65mm x 6.00mm
•
•
LED 驱动器
(1) 要了解所有可用封装,请见数据表末尾的可订购产品附录。
LED 照明灯泡更换
简化电路原理图
120 VRMS
±
+
VIN
DRAIN
VS
TPS92411
RSET
RSNS
VIN
CPS
CDD
DOV
VIN
DRAIN
VS
TPS92411
MULT
RSET
RSNS
VREF
ADIM
TPS92410
GDL
CS
VIN
DRAIN
VS
TPS92411
TSNS
VCC
RSET
RSNS
COMP GND
RCS
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SLUSBW9
TPS92410
ZHCSCM9 –MAY 2014
www.ti.com.cn
目录
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 13
Application and Implementation ........................ 13
8.1 Application Information............................................ 13
8.2 Typical Application ................................................. 14
Power Supply Recommendations...................... 18
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 Handling Ratings ...................................................... 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 7
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
8
9
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Example .................................................... 18
11 器件和文档支持 ..................................................... 19
11.1 商标....................................................................... 19
11.2 静电放电警告......................................................... 19
11.3 术语表 ................................................................... 19
12 机械封装和可订购信息 .......................................... 20
7
4 修订历史记录
日期
修订版本
注释
2014 年 6 月
*
最初发布。
2
Copyright © 2014, Texas Instruments Incorporated
TPS92410
www.ti.com.cn
ZHCSCM9 –MAY 2014
5 Pin Configuration and Functions
SOIC HV
13 PIN
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
VIN
CPS
CDD
DOV
GDL
VCC
MULT
VREF
ADIM
TSNS
CS
GND
COMP
8
Pin Functions
PIN
NAME
TYPE(1)
DESCRIPTION
NO.
Analog input used to set the reference of the linear controller. A 0-V to 1.5-V signal on ADIM sets the current
sense reference level.
ADIM
9
I
A capacitor to ground sets the time interval for dimmer detection. Tie to GND if no phase dimmer operation
is required.
CDD
COMP
CPS
CS
2
7
1
5
3
I/O
I/O
I/O
I
Compensation for control loop. Connect a capacitor from the COMP pin to ground.
A capacitor to ground sets the length of the CDD pin charge pulse. Leave open if no phase dimmer
operation is required.
Current sense input used for linear regulator.
Input to monitor linear MOSFET drain voltage. A resistor divider from the DOV pin to the drain connection of
the MOSFET monitors MOSFET over-voltage. Add a capacitor to GND for filtering.
DOV
I
GDL
4
6
O
G
I
Gate drive for an external linear MOSFET.
GND
MULT
TSNS
VCC
VIN
Chip ground return.
11
8
AC input to the multiplier. Tap a resistor divider off the rectified line to this pin.
Thermal sense input. Connect to a resistor and NTC thermistor for thermal foldback.
Pre-regulated voltage. Connect a bypass capacitor to ground.
High voltage input. Provides power to the device.
I
12
14
10
I/O
P
VREF
O
3-V voltage supply reference. Source used for TSNS input.
(1) I = Input, O = Output, P = Supply, G = Ground
Copyright © 2014, Texas Instruments Incorporated
3
TPS92410
ZHCSCM9 –MAY 2014
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
MAX UNIT
Input voltage
VIN
700
18
18
7.7
6
V
VCC
GDL
Output voltage
V
MULT, VREF, ADIM, COMP, CPS, CDD, TSNS
DOV
CS
Source current
Sink current
1
mA
mA
°C
CS
1
(2)
Operating junction temperature, TJ
–40
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Maximum junction temperature is internally limited by the device.
6.2 Handling Ratings
MIN
–65
–1
MAX UNIT
Tstg
Storage temperature range
Electrostatic discharge
150
1
°C
kV
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(2)
(1)
V(ESD)
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins(3)
–250
250
V
(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges
into the device.
(2) Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500V HBM allows safe
manufacturing with a standard ESD control process. Terminals listed as 1000V may actually have higher performance.
(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250V CDM allows safe
manufacturing with a standard ESD control process. Terminals listed as 250V may actually have higher performance.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
450
3
UNIT
V
VIN
Input voltage
9.5
VMULT
VADIM
TJ
Multiplier peak input voltage
Analog dimming input voltage
Operating junction temperature
V
0
3
V
-40
125
°C
6.4 Thermal Information
TPS92410
D (13)
84.8
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
39.8
39.5
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
8.9
ψJB
39.0
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
4
Copyright © 2014, Texas Instruments Incorporated
TPS92410
www.ti.com.cn
ZHCSCM9 –MAY 2014
6.5 Electrical Characteristics
–40°C ≤ TJ ≤ 125°C, VVIN = 100 V, VADIM = VMULT = 1 V (unless otherwise noted)
PARAMETER
SUPPLY VOLTAGE (VIN)
TEST CONDITIONS
MIN
TYP
MAX UNIT
VCC
Pre-regulator output voltage
10.15
V
Rising threshold, VVIN = VVCC
8
8.3
VCCUVLO
Supply votlage undervoltage protection Falling threshold, VVIN = VVCC
Hysteresis
5
5.85
2.15
2.5
V
IVIN
Input voltage bias current
Supply bias current
VVCC = 12 V
50
μA
μA
IVCC
305
145
500
Supply standby current
VCC supply current limit
VVIN = 0 V, VVCC = 7 V (UVLO)
VVCC = 7.5 V
IVCCLIM
8
25
mA
VVCC stepped from 6.075 V to 110% of
VCCUVLO,rising
Tplh(UVLO)
VCC supply glitch filter rising
16.2
μs
MULTIPLIER (MULT)
VMULT,LINEAR
VCOMP,LINEAR
RMULT
Multiplier linear range
0
3.5
3.25
700
V
V
COMP pin linear range
Input impedance
1.5
500
580
kΩ
VMULT = 1.5 V, VCOMP = 2.25 V,
k = VMULT_OUT/[(VCOMP–1.5 V) ×
AMULT
Multiplier gain
0.95
1.43
1.85
1/V
VMULT
]
VMULT,OFFSET
MULTOUT,mx
Multiplier output offset
VMULT = 0 V, VCOMP = 2.25 V
13.7
2.43
mV
V
VADIM = VTSNS = open; VCOMP = 4 V,
VMULT = 3.5 V
Multiplier Output Clamp Voltage
2.25
2.85
2.65
VOLTAGE REFERENCE (VREF)
VVREF
Reference voltage
Line regulation
Load regulation
IVREF = 100 μA
3
3.15
1%
V
VREFLINE
VREFLOAD
8.5 V ≤ VVIN ≤ 100 V
10 μA ≤ IREF ≤ 200 μA
1%
TRANSCONDUCTANCE AMPLIFIER (ADIM, COMP)
ADIMLIM
IADIM
ADIM operating voltage limit
Pull-up current
1.425
18
1.5
0.5
40
1.575
1
V
μA
mV
mV
μS
mV
ADIMSD
ADIMSD,HYS
gM
ADIM linear shutdown threshold
ADIM shutdown hysteresis
Transconductance
Falling
70
20
43.3
VOFFSET
Input offset voltage
VADIM = 0.5 V
-20
20
VCOMP = 2.25 V, VMULT = 0V,
VADIM = VTSNS = 2 V
IOUT,SOURCE
Output source current
Output sink current
65
μA
IOUT,SINK
ISTART
DIMMER DETECT (MULT, CPS, CDD)
VCOMP = 2.25 V, VTSNS = 0 V
VCOMP = 0 V, VADIM = 0 V
75
485
ICPS
Charge current for CPS pin
6.7
5.7
10
10
1
13.3
13.3
1.33
ICDD,c
ICDD,d
Charge current for CDD pin
Discharge current for CDD pin
μA
0.67
VMULT stepped from 0 V to 1 V,
minimum slew rate required
Dv/Dt
Maximum detection threshold
1/100
V/μs
VOFFSET
VTH,CDD
VTH,CPS
RCSP
Detector offset voltage
CDD threshold
0.41
1.5
V
CPS threshold
1.5
Pull down RDS(on)
314
Ω
Copyright © 2014, Texas Instruments Incorporated
5
TPS92410
ZHCSCM9 –MAY 2014
www.ti.com.cn
MAX UNIT
Electrical Characteristics (continued)
–40°C ≤ TJ ≤ 125°C, VVIN = 100 V, VADIM = VMULT = 1 V (unless otherwise noted)
PARAMETER
DRAIN OVER-VOLTAGE (DOV)
TEST CONDITIONS
MIN
TYP
VTH,DOV
Drain over-voltage threshold
Internal DOV hysteresis
1.38
1.5
1.62
V
VHYS,DOV
20
mV
VDOV = 1.5 V, Device in over-voltage
mode
IHYS,DOV
VREF,DOV
Drain over-voltage source current
0.7
1
1.5
μA
Linear CS reference during over-
voltage
VDOV = 1.75 V
0.1
V
THERMAL FOLDBACK (TSNS)
TSNSLIM TSNS operating voltage limit
1.425
1.5
2.1
1.575
V
VADIM = VTSNS = 1 V, Measure
reference to the linear error amplifier
mV
µA
VTSNS = 0 V, Measure reference to the
linear error amplifier
3.6
0.5
ITSNS
Pull-up current
1
LINEAR CURRENT SENSE (CS)
VCS(max)
VCS(max)
VIO
CS voltage level (CC dimming mode)
2.5 V = VADIM = VTSNS
2.5 V = VADIM = VTSNS
VREF = 1 V
1.425
1.125
–17
1.5
1.291
2.57
0
1.575
1.425
17
V
CS voltage level (PFC mode)
Input offset voltage
mV
V
VCMR–
Minimum input common mode range
GATE DRIVER (GDL)
VOH
High-level output voltage, GDL
ILOAD = –1 mA
ILOAD = 1 mA
VGDL= 4 V
6.5
8.2
0.152
8.1
V
VOL
Low-level output voltage, GDL
Output source current
Output sink current
0.45
IOUT(src)
IOUT(snk)
THERMAL SHUTDOWN
TSD Thermal shutdown
Thermal shutdown hysteresis
2.5
2.5
mA
VGDL= 4 V
11.9
175
10
°C
6
Copyright © 2014, Texas Instruments Incorporated
TPS92410
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ZHCSCM9 –MAY 2014
6.6 Typical Characteristics
Unless otherwise stated, –40°C ≤ TA = TJ ≤ +125°C. All characterization circuits are fully EMI compliant and phase dimmable.
55
53
51
49
47
45
60
59
58
57
56
55
190
200
210
220
230
240
250
260
85
95
105
115
125
135
Input Voltage (VAC)
Input Voltage (VAC)
6.8 W Input
C009
C004
230 VAC
Middle stack = 80 V
11.2 W Input
Top stack = 160 V
VADIM = 1.5 V
120VAC
Middle stack = 40 V
Top stack = 80 V
VADIM = 1.5 V
Bottom stack= 40 V
Bottom stack= 20 V
Figure 2. System Input Current vs Input Voltage
Figure 1. System Input Current vs Input Voltage
60
50
40
30
20
10
0
60
50
40
30
20
10
0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
ADIM Voltage (V)
ADIM Voltage (V)
C010
C005
230 VAC
Middle stack = 80 V
11.2 W Input
Top stack = 160 V
120VAC
Middle stack = 40 V
6.8 W Input
Top stack = 80 V
Bottom stack= 40 V
Bottom stack= 20 V
Figure 4. System Input Current vs ADIM Voltage
Figure 3. System Input Current vs ADIM Voltage
60
50
40
30
20
10
0
60
50
40
30
20
10
0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
TSNS Voltage (V)
TSNS Voltage (V)
C011
C012
120VAC
Middle stack = 40 V
6.8 W Input
Top stack = 80 V
VADIM = 1.5 V
230 VAC
Middle stack = 80 V
11. W Input
Top stack = 160 V
VADIM = 1.5 V
Bottom stack= 20 V
Bottom stack= 40 V
Figure 5. System Input Current vs TSNS Voltage
Figure 6. System Input Current vs TSNS Voltage
Copyright © 2014, Texas Instruments Incorporated
7
TPS92410
ZHCSCM9 –MAY 2014
www.ti.com.cn
Typical Characteristics (continued)
Unless otherwise stated, –40°C ≤ TA = TJ ≤ +125°C. All characterization circuits are fully EMI compliant and phase dimmable.
3.4
3.2
3.0
2.8
2.6
14
12
10
8
6
-40 -25 -10
5
20 35 50 65 80 95 110 125
5
20 35 50 65 80 95 110 125
±40 ±25 ±10
Junction Temperature (C)
Junction Temperature (C)
C013
C014
Figure 7. VREF Voltage vs Temperature
Figure 8. VCC Voltage vs Temperature
10
9
8
7
6
5
4
3
2
1
1.60
1.55
1.50
1.45
1.40
5
20 35 50 65 80 95 110 125
5
20 35 50 65 80 95 110 125
±40 ±25 ±10
±40 ±25 ±10
Junction Temperature (C)
Junction Temperature (C)
C015
C016
VIN = 100 V
GDL Not Operating
Figure 9. VIN Bias Current vs Temperature
Figure 10. Over-voltage Threshold vs Temperature
8
Copyright © 2014, Texas Instruments Incorporated
TPS92410
www.ti.com.cn
ZHCSCM9 –MAY 2014
7 Detailed Description
7.1 Overview
The TPS92410 device is a high-voltage linear regulator driver that can be used for offline LED drivers. It includes
a feature that forces the regulator current to follow the rectified AC voltage to achieve high power-factor and low
total harmonic distortion (THD). When the device detects multiple forward phase dimmer edges, the regulator
current changes to a DC level to maintain a DC current draw to provide for a triac dimmer's hold current
requirements. The TPS92410 device also includes linear MOSFET over-voltage protection to protect the
MOSFET if the LEDs are shorted. It includes a thermal foldback feature to protect the entire circuit in the event it
becomes overheated. Analog dimming capability allows light output to be controlled by a microcontroller or a 0 V
to 10 V dimmer. The device also includes a precision voltage reference.
7.2 Functional Block Diagram
VCC
VIN
UVLO
SD
HV Bias
Regulator
Thermal
Shutdown
1.5 V
OVP
DOV
3-V
Reference
VREF
ADIM
SD
40 mV/20 mV
SD
A0
Min
(A0, A1, A2) .
.
TSNS
A1
A2
MULT
1.5 V
AMUX
Sel
+
GDL
SD
gM
Dimmer Detection
CS
R
Edge
dv/dt
MULT
Timer
GND
S
Q
CPS CDD
COMP
Copyright © 2014, Texas Instruments Incorporated
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ZHCSCM9 –MAY 2014
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7.3 Feature Description
7.3.1 Setting the Linear Regulator Current/Input Power (CS)
The input power (PIN) can be set with a resistor from the CS pin to ground. Calculate the value of the RCS resistor
using the following equation (see Figure 11):
V
IN(rms ) × 1.428
RCS
=
P
IN
where
•
VIN(rms) is the nominal rms input voltage to the circuit
(1)
This sets the input power level due to the linear regulator for a standard application with VADIM and VTSNS greater
than or equal to 1.5 V. If either pin is pulled below 1.5 V the input power scales accordingly to the ratio of
VTSNS/ADIM/1.5 V. The actual input power of the circuit is higher due to variables such as VIN bias current,
resistor, diode, and other losses. When using forward phase dimmers there can be a significant current spike
through the MOSFET and RCS depending on the dv/dt of the dimmer edge. The magnitude and duration of this
current spike should be measured in any application and a resistor should be chosen that is rated for the peak
current required in any final design.
7.3.2 Over-Voltage Protecton (DOV)
The DOV pin can be used to set an over-voltage protection threshold for the external linear MOSFET. During
normal operation DOV is not active, but in the event that the LEDs become shorted resulting in excessive voltage
and power dissipation in the MOSFET over-voltage protection becomes active. During an over-voltage event, the
CS pin regulation voltage defaults to 100 mV to reduce power dissipation in the MOSFET but still provide some
light with the remaining LEDs. For this reason it is recommended to use a nominal value for CS for normal
operation higher than 100 mV. A resistor divider to DOV between the MOSFET drain and system ground sets
this over-voltage level as shown in Figure 11. During an over-voltage event the DOV pin sources 1 µA to provide
some hysteresis. The level and hysteresis can be set using the following equations:
VOVP - 1.5 V
RDRAIN = RGROUND
×
1.5 V
(2)
VHYS-DOV = 20 µA × RDRAIN
where
•
•
•
VOVP is the desired maximum drain voltage
RDRAIN is the resistor from DOV to the drain
RGROUND is the resistor from DOV to system ground
(3)
Include a capacitor from the DOV pin to system ground to prevent the circuit from transitioning into over-voltage
protection mode during the start-up sequence. A recommended value for the RGND resistor is 121 kΩ in parallel
with a 4.7-µF capacitor for most applications. RDRAIN can then be calculated. To calculate the values of RGND
and CGND for a particular application you need to set the time constant to be longer than it takes to charge up
the highest voltage LED string capacitor to prevent a false trip of the over-voltage protection during start-up. This
time constant and the resulting RC can be found using the following equations:
CUPPER × VUPPER
dt =
IUPPER
(4)
RGND × CGND = 5 × dt
where
•
•
•
•
dt is the time constant to charge the LED capacitor
CUPPER is the highest voltage LED string capacitor
VUPPER is the highest string voltage
IUPPER is the highest voltage LED string current
(5)
Choose RGND to be in the 100 kΩ to 150 kΩ range and calculate CGND. Then RDRAIN can be calculated. Over-
voltage protection should be adjusted for the minimum string voltages for analog dimming applications or simply
disabled by connecting DOV to ground.
10
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TPS92410
www.ti.com.cn
ZHCSCM9 –MAY 2014
Feature Description (continued)
CS
GDL
VS
RDRAIN
DOV
CGND
RGND
RCS
Figure 11. CS and DOV Over-voltage Connections
7.3.3 Input Undervoltage Lockout (UVLO)
The TPS92410 device includes input UVLO protection. This protection prevents the device from operating until a
voltage on the VIN pin exceeds 8.0 V. The circuit has 2.15 V of hysteresis to prevent false triggering.
7.3.4 Reference Voltage (VREF)
The TPS92410 includes a 3-V reference feature which can be used to set the DC level on the ADIM pin. It can
also source current for the TSNS divider for the thermal foldback circuitry using the TSNS pin. The VREF pin can
supply a maximum current of approximately 3 mA but should be limited to less than 200 μA to minimize power
dissipation. All current sourced from VREF is supplied by VIN so power dissipation can become significant when
sourcing higher currents.
7.3.5 Forward Phase Dimmer Detection (CPS, CDD)
An edge-detect circuit senses when a forward phase dimmer is connected to the input. This detection feature
allows the device to operate with a wide variety of dimmers that operate in either forward or reverse phase. The
CCPS and CCDD capacitors assist in this function while preventing a false dimmer detect caused by line glitches
and spikes in applications without a phase dimmer. Connect a 0.1-μF capacitor between CPS to GND and a 1-
μF capacitor from CDD to GND for most applications to use this feature. This results in a time constant of 15 ms
for CPS and 150 ms for CDD. If this feature is not required leave CPS open and ground CDD.
The dimmer detect function operates by applying a 10 µA charging current to both the CPS and CDD capacitors.
If no edges are detected the CPS capacitor charges to a 1.5 V threshold at which point the CDD pin switches
from sourcing 10 µA to sinking 1 µA. This prevents the CDD pin from charging to the 1.5-V threshold that
switches the device to dimmer detect mode. When a forward phase dimmer is present the edge is detected at
the MULT pin. Each time an edge is detected the CPS pin is discharged and then begins charging again. When
enough consecutive edges are present to keep the CPS pin below 1.5 V for longer than the CDD time constant
the CDD pin reaches 1.5 V and the device switches to dimmer detect mode. The current regulation level
between constant current dimmer detect mode and standard PFC operation can be different depending on
dimmer angle. A time constant too long can result in a mild light difference at turn-on due to a slightly different
light level between PFC mode at turn-on and dimmer detect mode. A time constant too short could result in
unintentionally switching to dimmer detect mode on noisy lines. The easiest way to implement a dimmer detect
circuit is to use a CPS time constant just a bit longer than TPER, the period of half of the sine wave input voltage.
But other time constants may be used if required. To change the time constants use the following equations:
CCPS × 1.5 V
dtCPS
=
10 µA
(6)
TPER
11
dtCDD = infinite (for dtCPS
<
)
(7)
11
Copyright © 2014, Texas Instruments Incorporated
TPS92410
ZHCSCM9 –MAY 2014
www.ti.com.cn
Feature Description (continued)
CCDD × 1.5 V
TPER
11
dtCDD
=
(for
< dtCPS < TPER )
:
;
11 µA × dtCPS F (1 µA × TPER
)
(8)
(9)
CCDD × 1.5 V
10 µA
dtCDD
=
(for dtCPS > TPER )
7.3.6 Analog Dimming Input and Setting VCS (ADIM)
If a default CS voltage of lower than 1.291 V is required, it can be set using the ADIM pin. A resistor divider from
the reference sets ADIM to any voltage lower than 1.5 V. During normal operation, the CS voltage is equal to
0.86 times the voltage applied to ADIM. The ADIM pin can also be used for analog dimming using a variable
voltage between 40 mV and 1.5 V to dynamically change the CS voltage. If the device pulls the ADIM pin below
40 mV, the device pulls the linear MOSFET gate low to shut off the LEDs. Tie an unused ADIM pin to VREF with
a 200-kΩ resistor. If a larger analog dimming range is required, use the TSNS pin for analog dimming because it
does not disable the linear regulator when the voltage drops below 40 mV. The ADIM and TSNS pins function
identically with the exception of the GDL disable threshold on the ADIM pin.
7.3.7 Thermal Foldback (TSNS)
The thermal foldback function of the TPS92410 device behaves similarly to the ADIM function. However, rather
than using a resistor divider, a NTC thermistor connects TSNS to system ground. Calculate the temperature at
which the circuit begins to reduce current by determining the temperature at which the the TSNS pin drops below
1.5 V (when the ADIM pin is 1.5 V or higher). With a valid external voltage on the ADIM pin (< 1.5 V), the current
begins to reduce when the TSNS voltage drops lower than the ADIM voltage. As described in the Analog
Dimming Input and Setting VCS (ADIM) section, the TSNS pin and the ADIM pin may be used interchangeably. If
the TSNS pin is used for analog dimming, the ADIM pin may be used for thermal foldback.
7.3.8 Internal Regulator (VCC)
The VCC pin functions as the output of the internal supply for the device. Connect a 10-µF capacitor between the
VCC pin and ground to keep VCC charged for phase dimming applications. For analog dimming or non-dimming
applications a 4.7-µF capacitor is sufficient.
7.3.9 Error Amplifier (COMP)
The COMP pin functions as the output of the internal gM error amplifier. To ensure stability over all conditions,
connect a 4.7-µF capacitor between the COMP pin and ground. The bandwidth of the PFC can be calculated
using the following equation:
gM
BW =
tNꢀ× CCOMP
(10)
7.3.10 Linear MOSFET Gate Drive (GDL)
The GDL pin functions as the gate drive for the linear MOSFET that regulates current. Connect the GDL pin to
the gate of the power MOSFET. To reduce EMI, connect a 10-Ω resistor in series with a 1-µF capacitor between
the GDL pin and the CS pin with a diode connected between them that returns to the VCC pin as show in
Figure 12. If phase dimming is not required, the diode can be omitted. Choose a linear MOSFET with a voltage
rating of at least 250 V for a 120-VAC input application. Choose a linear MOSFET with a voltage rating of at least
400 V for a 230-VAC input application. The MOSFET voltage rating must take into account the MOV clamp
voltage in protected applications as this may be higher than the MOSFET and damage may occur during a surge
event. The Safe Operating Area (SOA) of the MOSFET must also be taken into account. During start-up the
MOSFET experiences high voltages as the LED capacitors charge. This leads to high power dissipation during
start-up that the MOSFET must withstand. Use with forward phase dimmers also causes a significant current
spike in the MOSFET when the dimmer fires. The magnitude and duration of this current spike is dependent
upon many factors and should be measured in any design to confirm the MOSFET is rated properly for long life
operation. MOSFET parasitics should also be considered. A very large MOSFET with high parasitic capacitances
can cause erroneous switching of the TPS92411 floating drivers.
12
Copyright © 2014, Texas Instruments Incorporated
TPS92410
www.ti.com.cn
ZHCSCM9 –MAY 2014
Feature Description (continued)
7.3.11 EMI Filter
The input EMI filter requirements are specific to each design. A capacitor is needed for filtering and may also
require an input resistor. For forward phase applications a snubber across the capacitor is likely to be required.
The input resistor and snubber resistor need to have a pulse rating high enough for the particular application
both during start-up and during forward phase dimming.
7.3.12 Thermal Shutdown
The TPS92410 device includes thermal shutdown protection. If the die temperature reaches approximately
175°C the device shuts down. When the die temperature cools to approximately 165°C, the device resumes
normal operation.
7.4 Device Functional Modes
7.4.1 Multiplier Mode
When the MULT pin detects full rectified AC voltage, the CS voltage follows the rectified AC waveform around its
regulation point. This behavior forces the current that is drawn from the line to follow the AC input voltage
waveform. This action results in high power factor and low total harmonic distortion (THD). Line transients are
rejected by the time constant that is initially set on the dimmer detect circuit to ensure dimmer detect mode is not
engaged by random voltage spikes on the line.
7.4.2 Dimmer Detect Mode
When a forward phase dimmer is present there is a sharp edge presented to the MULT pin each cycle. This
forces the dimmer detect circuit past its time constant and the device enters dimming mode. The CS voltage is
then set at a DC level to prevent dimmer misfire
8 Application and Implementation
8.1 Application Information
The TPS92410 is a linear controller designed to be used in conjunction with the TPS92411 switch for high
voltage off-line LED drive applications. Typical uses include 120 VAC and 230 VAC input LED drivers with either
analog or phase dimming. However like any linear controller it may also be used with a DC input voltage up to
450 V. The following applications are for typical off-line LED drivers with 120 VAC and 230 VAC input voltages.
Copyright © 2014, Texas Instruments Incorporated
13
TPS92410
ZHCSCM9 –MAY 2014
www.ti.com.cn
8.2 Typical Application
8.2.1 120-VAC Input, 6.6-W LED Driver
22 ꢀ
200 V
VIN
DRAIN
VS
120 VRMS
1.82 0ꢀ
TPS92411
±
+
RSET
RSNS
1 0ꢀ
33 µF
100 V
200 V
VIN
DRAIN
VS
1.65 0ꢀ
1 0ꢀ
TPS92411
0.15 µF(1)
250 V
68 µF
50 V
RSET
RSNS
0.047 µF
250 V
(1)
442
200 V
VIN
DRAIN
VS
1.43 0ꢀ
1 0ꢀ
TPS92411
120 µF
25 V
RSET
RSNS
2 0ꢀ
VIN
CPS
CDD
DOV
0.1 PF(1)
MULT
1 PF(1)
30.1 Nꢀ
0.1 PF
2 0ꢀ
121 Nꢀ 4.7 PF
VREF
TPS92410
ADIM
TSNS
30.1 Nꢀ
GDL
10 ꢀ
VCC(1)
CS
470 Nꢀ
NTC
(1)
VCC
COMP GND
1 PF
55 N
4.7 PF
10 PF
25 V
RCS
30.1 ꢀ
128 ꢀ
(1) Required only for forward phase dimmer capability.
Figure 12. 120-V Application Schematic
14
Copyright © 2014, Texas Instruments Incorporated
TPS92410
www.ti.com.cn
ZHCSCM9 –MAY 2014
Typical Application (continued)
8.2.1.1 Design Requirements
This application requires a 6.6-W input power, high-efficiency, phase-dimmable LED lamp for use on 120-V
systems.
8.2.1.2 Detailed Design Procedure
The TPS92411 components are chosen using the guidelines in the TPS92411 datasheet. Most of the values
used for the TPS92410 are recommended values for any 120-V system. Connect the input voltage directly to the
rectified AC while the MULT pin is connected to a 2-MΩ, 30.1-kΩ resistor divider from the rectified AC to ground.
The VREF pin should have a 0.1-µF capacitor tied to ground for decoupling. The VCC pin should be decoupled
using a 10-µF ceramic capacitor to ground and the COMP pin should have a 4.7-µF ceramic capacitor to ground.
Connect a 0.1-µF ceramic capacitor from the CPS pin to ground. Connect a 1-µF ceramic capacitor from the
CDD pin to ground to enable phase dimmable operation. This results in a 150 ms dimmer detect time constant.
The over-voltage protection using the DOV pin can be set using Equation 3. In this case a MOSFET drain over-
voltage level of approximately 27 V is chosen. A 4.7-µF capacitor should be placed in parallel with a 121-kΩ
resistor from the DOV pin to ground to set a time constant and for filtering for all applications.
Choose RDRAIN for the appropriate voltage, in this case 2 MΩ is chosen. Connect a 10-Ω resistor in series with a
1-µF ceramic capacitor from GDL to CS for stability and to help reduce EMI. Place a diode from the center point
of these two components to the VCC pin to clamp the voltage on the GDL pin and the CS pin that can become
high with some forward phase dimmers. A rating of at least 20 V and 100 mA is recommended with a peak-
repetitive current rating of at least 2 A. A 55-kΩ resistor should be connected between the MOSFET source and
the CS pin for additional protection. Connect a 30.1-kΩ resistor from the TSNS pin to the VREF pin. The NTC
thermistor to ground should be selected so that the desired foldback temperature results in a thermistor value of
30.1 kΩ. RCS is then calculated using Equation 1. RCS = 25 Ω is very close, a 30.1 Ω in parallel with a 182 Ω
resulting in about 25.83 Ω was chosen.
8.2.1.3 Application Curves
1.00
0.99
0.98
0.97
0.96
0.95
10
8
6
4
2
0
85
95
105
115
125
135
85
95
105
115
125
135
Input Voltage (VAC)
Top stack = 80 V
Bottom stack= 20 V
Input Voltage (VAC)
Top stack = 80 V
Bottom stack= 20 V
C002
C003
120VAC
Middle stack = 40 V
6.8 W Input
120VAC
Middle stack = 40 V
6.8 W Input
VADIM = 1.5 V
VADIM = 1.5 V
Figure 13. Power Factor vs Input Voltage
Figure 14. Total Harmonic Distortion vs Input Voltage
Copyright © 2014, Texas Instruments Incorporated
15
TPS92410
ZHCSCM9 –MAY 2014
www.ti.com.cn
Typical Application (continued)
8.2.2 230-VAC Input, 11-W LED Driver
200 V
Q3
200 V
1 Nꢀ
680 pF
1 0ꢀ
VGS = 4 V
10 Nꢀ
22 µF
200 V
68 ꢀ
VIN
DRAIN
TPS92411
230 VRMS
1.91 0ꢀ
1 0ꢀ
0.1 µF
100 V
12 V 12 V
±
+
RSET
RSNS
VS
200 V
47 µF
100 V
VIN
DRAIN
VS
1.82 0ꢀ
1 0ꢀ
TPS92411
0.15 µF(1)
400 V
RSET
RSNS
0.033 µF
400 V
(1)
410
200 V
VIN
DRAIN
VS
1.69 0ꢀ
1 0ꢀ
TPS92411
100 µF
50 V
RSET
RSNS
4 0ꢀ
VIN
CPS
CDD
DOV
0.1 PF(1)
MULT
1 PF(1)
30.1 Nꢀ
0.1 PF
4 0ꢀ
121 Nꢀ 4.7 PF
VREF
ADIM
30.1 Nꢀ
GDL
TSNS
10 ꢀ
470 Nꢀ
VCC(1)
CS
NTC
VCC
COMP GND
1 PF
(1)
55 N
4.7 PF
10 PF
25 V
RCS
30.1 ꢀ
(1) Required only for forward phase dimmer capability.
Figure 15. 230-V Application Schematic
16
Copyright © 2014, Texas Instruments Incorporated
TPS92410
www.ti.com.cn
ZHCSCM9 –MAY 2014
Typical Application (continued)
8.2.2.1 Design Requirements
This application requires a 11-W input power, high-efficiency, phase-dimmable LED lamp for use on 230-V
systems.
8.2.2.2 Detailed Design Procedure
The TPS92411 components are chosen using the guidelines in the TPS92411 datasheet. Most of the values
used for the TPS92410 are recommended values for any 230-V system. The input voltage should be connected
directly to rectified AC while the MULT pin is connected to a 4-MΩ, 30.1-kΩ resistor divider between rectified AC
and ground. The VREF pin should have a 0.1-µF capacitor connected to ground to provide decoupling. The VCC
pin should be decoupled using a 10-µF ceramic capacitor to ground and the COMP pin should have a 4.7-µF
ceramic capacitor to ground. Connect a 0.1-µF ceramic capacitor from the CPS pin to ground. Connect a 1-µF
ceramic capacitor from CDD to ground to enable phase dimmable operation. This results in a 150 ms dimmer
detect time constant. The over-voltage protection using the DOV pin can be set using Equation 3. This case
includes a MOSFET drain over-voltage level of approximately 51 V. A 4.7-µF capacitor should be placed in
parallel with a 121-kΩ resistor from the DOV pin to ground to set a time constant and for filtering for all
applications.
Choose RDRAIN for the appropriate voltage, this case uses a value of 4-MΩ. A 10-Ω resistor in series with a 1-µF
ceramic capacitor from GDL to CS adds stability and helps reduce EMI. A diode should be placed from the
center point of these two components to the VCC pin to clamp the voltage on the GDL pin and the CS pin that
can become high with some forward phase dimmers. A rating of at least 20 V and 100 mA is recommended with
a peak-repetitive current rating of at least 2 A. A 55-kΩ resistor should be connected between the MOSFET
source and the CS pin for additional protection. Connect a 30.1-kΩ resistor from the TSNS pin to the VREF pin.
The NTC thermistor to ground should be selected so that the desired foldback temperature results in a thermistor
value of 30.1 kΩ. RCS is then calculated using Equation 1. RCS = 30.1 Ω is very close and was chosen for this
design.
8.2.2.3 Application Curves
1.00
0.99
0.98
0.97
0.96
0.95
15
12
9
6
3
0
190
200
210
220
230
240
250
260
190
200
210
220
230
240
250
260
Input Voltage (VAC)
Input Voltage (VAC)
C007
C008
Top stack = 160 V
Middle stack = 80 V
11.2 W Input
230 VAC
Top stack = 160 V
Middle stack = 80 V
11.2 W Input
230 VAC
Bottom stack= 40 V
VADIM = 1.5 V
Bottom stack= 40 V
VADIM = 1.5 V
Figure 16. Power Factor vs Input Voltage
Figure 17. Total Harmonic Distortion vs Input Voltage
Copyright © 2014, Texas Instruments Incorporated
17
TPS92410
ZHCSCM9 –MAY 2014
www.ti.com.cn
9 Power Supply Recommendations
For testing purposes any benchtop adjustable AC power supply with a power rating higher than what is required
by the circuit is suitable. An example would be an Hewlett Packard 6811B or equivalent. An isolated supply is
recommended for safety purposes.
10 Layout
Proper layout is important in any regulator design. The TPS92410 is a linear regulator which simplifies layout
compared to a switching regulator, however some consideration should be taken.
10.1 Layout Guidelines
Components between CPS, CDD, DOV, COMP, VREF, MULT, and VCC to ground (GND) should be placed
directly next to the device as shown in Figure 18. The linear MOSFET as well as the GDL and CS traces should
be placed as close the TPS92410 as possible as well.
10.2 Layout Example
To source of
bottom
TPS92411
To rectified AC
1
14
CPS
VIN
2
3
CDD
DOV
12
11
10
9
VCC
4
GDL
MULT
5
6
CS
VREF
ADIM
To VCC
GND
7
COMP
TSNS
8
Figure 18. Recommended Component Placement
18
版权 © 2014, Texas Instruments Incorporated
TPS92410
www.ti.com.cn
ZHCSCM9 –MAY 2014
11 器件和文档支持
11.1 商标
11.2 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时,应将导线一起截短或将装置放置于导电泡棉中,以防止 MOS 门极遭受静电损
伤。
11.3 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
版权 © 2014, Texas Instruments Incorporated
19
TPS92410
ZHCSCM9 –MAY 2014
www.ti.com.cn
12 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本,请查阅左侧的导航栏。
20
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IMPORTANT NOTICE
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Copyright © 2014, 德州仪器半导体技术(上海)有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS92410D
ACTIVE
ACTIVE
SOIC
SOIC
D
D
13
13
50
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 150
-40 to 150
TPS92410D
TPS92410D
TPS92410DR
2500 RoHS & Green
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
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TPS92410DR | TI | 用于离线 LED 驱动器的开关控制型、直接驱动、线性控制器 | D | 13 | -40 to 150 | 获取价格 | |
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TPS92411DDA | TI | 适用于 LED 离线交流线性直接驱动的浮动开关,具有低纹波电流 | DDA | 8 | -40 to 150 | 获取价格 | |
TPS92411DDAR | TI | 适用于 LED 离线交流线性直接驱动的浮动开关,具有低纹波电流 | DDA | 8 | -40 to 150 | 获取价格 | |
TPS92411PDBVR | TI | 适用于 LED 离线交流线性直接驱动的浮动开关,具有低纹波电流 | DBV | 5 | -40 to 150 | 获取价格 | |
TPS92411PDBVT | TI | 适用于 LED 离线交流线性直接驱动的浮动开关,具有低纹波电流 | DBV | 5 | -40 to 150 | 获取价格 | |
TPS92411PDDA | TI | 适用于 LED 离线交流线性直接驱动的浮动开关,具有低纹波电流 | DDA | 8 | -40 to 150 | 获取价格 | |
TPS92411PDDAR | TI | 适用于 LED 离线交流线性直接驱动的浮动开关,具有低纹波电流 | DDA | 8 | -40 to 150 | 获取价格 |
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