TPS92519-Q1_技术文档

TPS92519-Q1

ZHCSMX7A –AUGUST 2021 –REVISED DECEMBER 2021

TPS92519-Q1 4.5V 至65V、双路、汽车类2A 同步降压LED 驱动器

TPS92519-Q1 包含高级故障保护功能：逐周期开关电

流限制、自举欠压和热关断。该器件包括一个开漏故障

输出以指示输出开路和短路情况。

1 特性

• 符合面向汽车应用的AEC-Q100 标准

– 1 级：–40°C 至125°C 的工作环境温度范围

– 器件HBM 分类等级H1C

– 器件CDM 分类等级C2

• 提供功能安全

TPS92519-Q1 采用 8.1mm × 11mm 热增强型 32 引脚

HTSSOP 封装，具有 2.75mm × 3.45mm 的底部外露

焊盘。

器件信息

– 可帮助进行功能安全系统设计的文档

• 4.5V 至65V 的宽输入电压范围

• 输出电流高达2A，精度为4%

• 自适应导通时间平均电流控制

• 标称开关频率

器件型号⁽¹⁾

封装尺寸（标称值）

封装

TPS92519-Q1

HTSSOP

8.1mm × 11mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

– 通道1 和通道2 为385kHz 和435kHz

– 通道1 和通道2 为2MHz 和2.1MHz

• 高级调光操作

LED+

C_COMP2

1

2

32

COMP2

UDIM2

CSN2

C_OUT2

R_CS2

31

30

CSP2

BST2

C_UV2

3

– 精确模拟调光

R_UV22

R_UV21

PGND

– 支持外部PWM 调光输入

– 针对外部分流调光（包括LED 矩阵管理器）进

行优化

L₂

4

GND

V_BST

C_BST2

29

28

SW2

C_IN2

5V

5

6

7

VIN2

GND

V5A

27

26

25

24

23

22

R_ADJ21

• 开关逐周期过流保护

• 开关过热保护

• LED 开路和短路故障监控和报告

FLT2

IADJ2

FSET

EN

C_V5D

5V

Supply

8

9

V5D

R_ADJ11R_ADJ22

C_V5A

IADJ1

FLT1

2 应用

10

11

12

GND

VIN1

R_ADJ12

• 汽车前照灯和自适应LED 驱动模块

21

20

V_BST

SW1

C_IN1

3 说明

13

GND

PGND

C_BST1

L₁

14

C_UV1

15

19

18

R_UV11

BST1

CSP1

R_UV12

TPS92519-Q1 是一款单片双路同步降压 LED 驱动

器，具有4.5V 至65V 宽工作输入电压范围，可独立为

两串串联的LED 供电。

UDIM1

R_CS1

C_COMP1

C_OUT1

16

17

COMP1

CSN1

TPS92519-Q1 实施自适应导通时间平均电流模式控制

功能，经设计可与分流 FET 调光技术和基于 LED 矩阵

管理器的动态光束前照灯兼容。自适应导通时间控制功

能可提供近乎恒定的开关频率，可使用 FSET 输入来

设置该开关频率。电感器电流感应和闭环反馈功能可在

较宽的输入电压、输出电压和环境温度范围内实现

±4% 以上的精度。

LED+

简化版原理图

高性能 LED 驱动器可使用模拟调光或 PWM 调光技术

来单独调制 LED 电流。通过在高阻抗模拟调整 (IADJ)

输入范围内将电压从 140mV 改变为 2.45V，可获得超

过 16:1 范围的线性模拟调光响应。通过使用所需占空

比和频率直接调制对应的 UDIM 输入引脚，实现 LED

电流的 PWM 调光。该器件支持高频分流 FET 调光，

并与使用LED 矩阵管理器的像素控制技术兼容。

TPS92519-Q1 支持两个或更多通道的并行运行，从而

实现驱动大电流 LED 或激光二极管所需的灵活性。电

流基于 IADJ 输入在并行通道之间共享，不受元件容差

和寄生效应的影响。

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLUSEG1

TPS92519-Q1

ZHCSMX7A –AUGUST 2021 –REVISED DECEMBER 2021

www.ti.com.cn

Table of Contents

7.4 Device Functional Modes..........................................27

8 Application and Implementation..................................28

8.1 Application Information............................................. 28

8.2 Typical Application.................................................... 32

9 Power Supply Recommendations................................37

10 Layout...........................................................................37

10.1 Layout Guidelines................................................... 37

10.2 Layout Example...................................................... 38

11 Device and Documentation Support..........................39

11.1 Documentation Support.......................................... 39

11.2 Receiving Notification of Documentation Updates..39

11.3 支持资源..................................................................39

11.4 Trademarks............................................................. 39

11.5 术语表..................................................................... 39

12 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 5

6.1 Absolute Maximum Ratings........................................ 5

6.2 ESD Ratings............................................................... 5

6.3 Recommended Operating Conditions.........................5

6.4 Thermal Information....................................................6

6.5 Electrical Characteristics.............................................6

6.6 Typical Characteristics................................................9

7 Detailed Description......................................................13

7.1 Overview...................................................................13

7.2 Functional Block Diagram.........................................14

7.3 Feature Description...................................................14

Information.................................................................... 39

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision * (August 2021) to Revision A (December 2021)

Page

• 将状态从“预告信息”更改为“量产数据”....................................................................................................... 1

2

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5 Pin Configuration and Functions

COMP2

UDIM2

PGND

VIN2

1

32

CSN2

CSP2

BST2

SW2

2

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

3

4

5

SW2

VIN2

6

FLT2

IADJ2

FSET

EN

GND

7

V5A

8

V5D

9

GND

10

11

12

13

14

15

16

IADJ1

FLT1

SW1

VIN1

PGND

UDIM1

COMP1

SW1

BST1

CSP1

CSN1

图5-1. DAP Package 32-Pin HTSSOP Top View

表5-1. Pin Functions

NO.

DAP

19

I/O

DESCRIPTION

NAME

BST1

BST2

P

Supply input for high-side MOSFET gate drive circuit. Connect a ceramic capacitor

between BSTx and SWx pins. An internal diode is connected between V5D and BSTx.

30

P

COMP1

COMP2

CSN1

CSN2

CSP1

16

I/O

Output of internal transconductance error amplifier. Connect an integral compensation

network to ensure stability.

1

I/O

17

I

Negative input (–) of internal rail-to-rail transconductance error amplifier. Connect

directly to the negative node of the LED current sense resistor, R_CS

.

32

18

Positive input (+) of internal rail-to-rail transconductance error amplifier. Connect

directly to the positive node of the LED current sense resistor, R_CS

.

CSP2

31

An active high logic input enables the devices. Pull this pin low to enter low power sleep

state.

EN

24

I

FLT1

FLT2

22

27

O

Open-drain fault indicator. Connect to V5D with a resistor to create an active low fault

signal output.

Frequency select input. Connect to V5D to operate at nominal frequency of 440 kHz.

Connect to GND to operate at nominal frequency of 2.1 MHz.

FSET

GND

25

I

Signal ground. Return for the internal voltage reference and analog circuits. Connect to

circuit ground to complete return path.

7, 10

G

IADJ1

IADJ2

23

26

I

Analog adjust input. Input below 100 mV disables the channel. The analog input can be

varied between 140 mV to 2.4 V to set current reference from 10 mV to 173 mV.

Connect a 0.1-μF capacitor from pin to GND.

PGND

SW1

3, 4, 13, 14

20, 21

G

P

Ground returns for low-side MOSFETs

Switching output of the regulator. Internally connected to both power MOSFETs.

Connect to the power inductor.

SW2

28, 29

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表5-1. Pin Functions (continued)

NO.

DAP

15

I/O

DESCRIPTION

NAME

UDIM1

UDIM2

I

Undervoltage lockout and external PWM dimming input. Connect to VIN through a

resistor divider to implement input undervoltage protection. Diode couple external PWM

signal to enable dimming. Locally decouple to GND using a 1-nF ceramic capacitor. Do

not float.

2

Analog supply voltage. Locally decouple to GND using a 100-nF to 1-µF ceramic

capacitor located close to the controller.

V5A

V5D

8

9

P

Digital supply voltage. Locally decouple to GND using a 2.2-µF to 4.7-µF ceramic

capacitor located close to the controller.

VIN1

VIN2

11, 12

5, 6

P

Power inputs and connections to high-side MOSFET drain node. Connect to the power

supply and bypass capacitors C_IN. The path from the VIN pin to high frequency bypass

C_INand PGND must be as short as possible.

4

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6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

–0.5

–3.5

–0.3

MAX

5.5

70

UNIT

V

Supply Voltage

Boot voltage

V5A, V5D to GND

BSTx to SWx

V

BSTx to PGND

V

SWx to PGND

65

V

Switch node voltage

Drain node voltage

Current

SWx to PGND (< 10ns)

VINx to PGND

V

65

1.5

430

0.5

65

V

CSNx to VINx (< 10µs)

GND to CSPx, GND to CSNx (< 10µs)

CSNx - VINx

A

mA

V

CSPx, CSNx to GND

CSPx to CSNx

V

–0.5

–0.3

0.3

65

V

Inputs

UDIMx to GND

V

COMPx, IADJx, FSET, EN to GND

FLTx to GND

5.5

150

260

150

V

Outputs

V

Junction temperature

Lead temperature

Storage temperature

T_J

°C

Soldering, 10 s

T_stg

–65

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

6.2 ESD Ratings

VALUE UNIT

Human body model (HBM), per AEC Q100-002⁽¹⁾

±2000

±750

±500

V_(ESD)Electrostatic discharge

Corner pins (1, 16, 17, and 32)

Other pins

V

Charged device model (CDM), per

AEC Q100-011

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)

MIN

4.5

20

NOM

MAX

63

UNIT

V

V_IN

Input voltage

V_5A, V_5D

d_V5x/dt

Bias supply

5

5.3

V

Bias supply slew-rate

V/s

∆V_(CSP-

CSN)

Sensed inductor current ripple

20

mV

dv_CSP/dt

I_LED

CSP slew-rate

10

2

V/µs

A

LED current

f_UDIM

T_A

External PWM dimming frequency

Ambient temperature

Junction temperature

1000

125

150

Hz

°C

–40

T_J

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UNIT

6.4 Thermal Information

DEVICE

DAP (HTSSOP)

32

THERMAL METRIC⁽¹⁾

R_θJA

Junction-to-ambient thermal resistance^{(2) (3)}

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

26.2

°C/W

R_θJC(top)

R_θJB

16.3

8.3

0.2

8.2

1.8

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

Ψ_JT

Ψ_JB

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) The package thermal impedance is calculated in accordance with JESD51-7 standard with a 4-layer board and 2 W power dissipation.

(3) A heatsink or airflow would yield a much better R_θJA

.

6.5 Electrical Characteristics

-40°C ≤T_J≤150°C_,V_5D= V_5A= 5 V_,V_IN= 24 V, V_UDIMx= 5 V_,C_V5D=C_V5A= 4.7 µF C_BSTx= 0.1 µF, C_COMPx= 1 nF_,R_CSx

100 mΩ, no load on SWx, FLTx pin floating (unless otherwise noted)

=

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

EXTERNAL ANALOG AND GATE DRIVE SUPPLIES (V5D, V5A)

Rising

4.10

4.00

100

4

4.26

V

V_V5D,A(UVLO)V_5Dand V_5AUVLO threshold

Falling

3.84

V

Hysteresis

mV

mA

nA

µA

μA

I_V5A(STBY)

I_V5D(STBY)

I_V5A(SLEEP)

I_V5D(SLEEP)

Analog supply stand-by current

Gate drive supply stand-by current

Analog supply sleep state current

Gate drive supply sleep state current

V_UDIM1= V_UDIM2= 0 V

V_EN= 0 V

5.5

1.3

300

24

0.9

14

V_EN= 0 V

17

I_VINx(SLEEP)VIN pin sleep state current

I_V5D(SW)Gate drive supply switching current

V_INx= 15 V, V_EN= 0 V

2

4

V_V5D= 5 V, V_FSET= 5 V, CH1

and CH2 switching

6

10

mA

ENABLE INPUT (EN)

Enable voltage rising threshold

1.8

V

V_EN

Enable voltgae falling threshold

Enable input bias current

0.8

mV

µA

I_EN

10

HIGH-SIDE FET (SWx, BOOTx)

V_INx= 6 V, V_BSTx= 11 V, I_HSx

100 mA

=

R_DSx(ON-HS)High-side MOSFET on resistance

240

2.95

184

250

465

3.30

245

300

mΩ

V

Falling, V_INx= 6 V, V_SWx= 0 V

2.60

115

200

V_BSTx(UV)

Bootstrap UVLO threshold

Hysteresis, V_INx= 6 V, V_SWx= 0

V

mV

µA

I_Q(xBST)

Bootstrap pin quiescent current

V_BSTx= 5 V, V_SWx= 0 V

LOW-SIDE FET (SWx)

R_DSx(ON-LS)Low-side MOSFET on resistance

HIGH-SIDE FET CURRENT LIMIT

V_INx= 6 V, I_LSx= 100 mA

240

465

mΩ

I_HSx(ILIM)

t_HSx(LEB)

t_HSx(RES)

High-side current limit threshold

V_INx= 6 V

2.8

35

3.5

60

20

4.2

80

A

High-side current sense leading-edge

blanking period

ns

Current limit response time

LOW-SIDE FET CURRENT LIMIT

6

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6.5 Electrical Characteristics (continued)

-40°C ≤T_J≤150°C_,V_5D= V_5A= 5 V_,V_IN= 24 V, V_UDIMx= 5 V_,C_V5D=C_V5A= 4.7 µF C_BSTx= 0.1 µF, C_COMPx= 1 nF_,R_CSx

100 mΩ, no load on SWx, FLTx pin floating (unless otherwise noted)

=

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I_LSx(ILIM)

t_LSx(LEB)

Low-side sinking current limit threshold V_INx= 6 V

1.67

2.50

3.5

A

Low-side current sense leading-edge

V_INx= 6 V

76

ns

blanking period

SWITCHING FREQUENCY (FSET)

Frequency set input rising threshold

1.8

V

V_FSET

Frequency set input falling threshold

Frequency set input bias current

0.8

I_FSET

10

µA

V_FSET= 0 V, V_IN= 50 V, V_CSP

38 V

=

384

ns

µs

ns

µs

t_ON(SW1)

Channel 1 on-time

Channel 2 on-time

V_FSET= 5 V, V_IN= 50 V, V_CSP

25 V

1.36

365

V_FSET= 0 V, V_IN= 50 V, V_CSP

38 V

t_ON(SW2)

V_FSET= 5 V, V_IN= 50 V, V_CSP

25 V

1.20

ANALOG ADJUST SETTING AND CURRENT SENSE AMPLIFIER (IADJx, CSPx, CSNx)

V_IADJx(CLP)

IADJx internal limit

2.38

2.45

140

100

2.52

V

Rising, V_INx= 6 V

Falling, V_INx= 6 V

mV

V_IADJx(SD)

Shutdown threshold

V_CSPx= 6 V,

V_IADJx> 2.45V

167.5

83.0

29.0

6.5

173.0

88.5

34.5

12.5

178.5

94.0

40.0

18.5

mV

V_CSPx= 6 V,

V_IADJx= 1.22V

V_(CSPx-CSNx)Current sense threshold

V_CSPx= 6 V,

V_IADJx= 460mV

V_CSPx= 6 V,

V_IADJx= 150mV

g_mx(LV)

Level shift amplifier transconductance V_INx= 63 V, V_CSNx= 5 V

50

1.71

1.50

µA/V

V

Rising

Output short circuit detection threshold

Falling

V_CSPx(SHT)

V

ON-TIME GENERATOR

t_ONx(MIN)

Minimum on-time.

V_INx= 4.5 V

90

57

110

78

130

86

ns

OFF-TIME GENERATOR

t_OFFx(MIN)

Minimum off-time

PWM DIMMING and PROGRAMMABLE UVLO INPUT (DIMx)

Rising

2.45

2.35

1.22

1.02

2.52

1.27

V

V_UDIMx(DO)

UDIM dropout detection threshold

Falling

Rising

Falling

1.95

V_UDIMx(EN)

UDIM undervoltage lockout threshold

0.97

6.3

UDIM source current (UVLO

hysteresis)

I_UDIMx(UVLO)

V_UDIMx= 1.5 V

10

12

µA

ERROR AMPLIFIER (COMPx)

g_MTransconductance

V_INx= 63 V

450

45

µA/V

µA

V_INx= 63 V, V_{(CSPx–CSNx)}= 0 V,

V_IADJx= 1.4 V

I_COMPx(SRC)COMPx current source capacity

I_COMPx(SINK)COMPx current sink capacity

V_INx= 63 V, V_{(CSPx–CSNx)}= 200

mV, V_IADJx= 1.4 V

45

µA

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6.5 Electrical Characteristics (continued)

-40°C ≤T_J≤150°C_,V_5D= V_5A= 5 V_,V_IN= 24 V, V_UDIMx= 5 V_,C_V5D=C_V5A= 4.7 µF C_BSTx= 0.1 µF, C_COMPx= 1 nF_,R_CSx

100 mΩ, no load on SWx, FLTx pin floating (unless otherwise noted)

=

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

MHz

mV

V

EA_x(BW)

EA_(VD)

EA_(CM)

Bandwidth

Unity gain

3

Input differential sense range

Input common mode range

225

–225

V_INx= 63 V

V_UDIMx= 0 V

Rising

0

V_INx–0.5

I_COMPx(LKG)COMPx leakage current

2.5

2.45

425

3.2

nA

V

V_COMPx(ST)COMPx startup threshold

Hysteresis

Rising

mV

V

3.0

COMPx over-voltage detection

V_COMPx(OV)

threshold

Hysteresis

75

mV

R_COMPx(DCH)COMPx discharge FET resistance

V_COMPx(RST)Reset voltage

230

100

Ω

Falling

mV

FAULT INDICATOR (FLT)

R_(FLTx)

T_OC

Fault pin pull-down resistance

Hiccup retry delay time

3

7

Ω

3.6

ms

THERMAL SHUTDOWN

T_SDThermal shutdown threshold

175

°C

8

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6.6 Typical Characteristics

T_A= T_J= 25°C, V_5D= V_5A= 5 V, V_IN= 24 V, V_UDIMx= 5 V, C_V5D= C_V5A= 4.7 µF C_BSTx= 0.1 µF, C_COMPx= 1 nF, R_CSx= 100

mΩ, no load on SWx, FLTx pin floating (unless otherwise noted)

174.5

174

10

7.5

5

173.5

173

2.5

0

-2.5

-5

172.5

172

-7.5

-10

171.5

-40 -20

0

20

40

60

80 100 120 140 160

0.024

0.524

1.024

1.524

2.024

2.524

Temperature (°C)

V_IADJ(V)

V_CSN= 3 V

V_IN= 60 V

图6-1. V_(CSP–CSN)Current Sense Threshold vs Temperature

图6-2. V_(CSP–CSN)Current Sense Error vs IADJ Count

24

1000

1 LED

3 LED

6 LED

9 LED

12 LED

15 LED

21

18

15

12

9

800

600

400

200

0

6

3

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

-200

Average Inductor Current (A)

0

0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7

CSN Voltage, V_CSN(V)

3

L = 68 µH

V_IN= 60 V

V_IADJ=0 V

图6-4. Minimum Ripple Voltage vs Average Inductor Current

图6-3. CSN Source Current vs CSN Voltage

4.22

4.18

4.14

4.1

19.8

19.5

19.2

18.9

18.6

18.3

18

Rising

Falling

4.06

4.02

3.98

3.94

3.9

17.7

17.4

17.1

16.8

16.5

16.2

-40 -20

0

20

40

60

80 100 120 140 160

-40 -20

0

20

40

60

80 100 120 140 160

Temperature (°C)

图6-5. V_5D,APOR Threshold vs Temperature

图6-6. V5D Sleep Current vs Temperature

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6.6 Typical Characteristics (continued)

T_A= T_J= 25°C, V_5D= V_5A= 5 V, V_IN= 24 V, V_UDIMx= 5 V, C_V5D= C_V5A= 4.7 µF C_BSTx= 0.1 µF, C_COMPx= 1 nF, R_CSx= 100

mΩ, no load on SWx, FLTx pin floating (unless otherwise noted)

400

380

360

340

320

300

280

260

240

220

200

180

2.965

2.955

2.945

2.935

2.925

2.915

2.905

2.895

2.885

2.875

-40 -20

0

20

40

60

80 100 120 140 160

Temperature (°C)

-40 -20

0

20

40

60

80 100 120 140 160

Temperature (°C)

图6-7. High Side MOSFET On Resistance vs Temperature

图6-8. Bootstrap UVLO Threshold vs Temperature

220

215

210

205

200

195

190

185

180

175

170

165

160

155

3.8

3.7

3.6

3.5

3.4

3.3

3.2

-40 -20

0

20

40

60

80 100 120 140 160

-40 -20

0

20

40

60

80 100 120 140 160

Temperature (°C)

图6-9. Bootstrap UVLO Hysteresis vs Temperature

400

图6-10. High-Side Current Limit Threshold vs Temperature

3

375

350

325

300

275

250

225

200

175

150

2.8

2.6

2.4

2.2

2

-40 -20

0

20

40

60

80 100 120 140 160

Temperature (°C)

-40 -20

0

20

40

60

80 100 120 140 160

Temperature (°C)

图6-11. Low-Side MOSFET On Resistance vs Temperature

图6-12. Low-Side Sinking Current Limit Threshold vs

Temperature

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6.6 Typical Characteristics (continued)

T_A= T_J= 25°C, V_5D= V_5A= 5 V, V_IN= 24 V, V_UDIMx= 5 V, C_V5D= C_V5A= 4.7 µF C_BSTx= 0.1 µF, C_COMPx= 1 nF, R_CSx= 100

mΩ, no load on SWx, FLTx pin floating (unless otherwise noted)

2.452

2.451

2.45

113

112.5

112

2.449

2.448

2.447

2.446

2.445

111.5

111

110.5

110

109.5

-40 -20

0

20

40

60

80 100 120 140 160

-40 -20

0

20

40

60

80 100 120 140 160

Temperature (°C)

图6-13. IADJ Internal Limit vs Temperature

图6-14. Minimum On-time vs Temperature

80

79

78

77

76

75

74

1.4

1.3

1.2

1.1

1

Rising

Falling

0.9

0.8

-40 -20

0

20

40

60

80 100 120 140 160

-40 -20

0

20

40

60

80 100 120 140 160

Temperature (°C)

图6-16. UDIM Undervoltage Lockout Threshold vs Temperature

图6-15. Minimum Off-time vs Temperature

2.58

2.53

2.48

2.43

2.38

2.33

2.28

3.24

3.23

3.22

3.21

3.2

Rising

Falling

3.19

3.18

3.17

3.16

-40 -20

0

20

40

60

80 100 120 140 160

-40 -20

0

20

40

60

80 100 120 140 160

Temperature (°C)

图6-17. UDIM Dropout Detection Threshold vs Temperature

图6-18. COMP Overvoltage Detection Threshold vs

Temperature

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6.6 Typical Characteristics (continued)

T_A= T_J= 25°C, V_5D= V_5A= 5 V, V_IN= 24 V, V_UDIMx= 5 V, C_V5D= C_V5A= 4.7 µF C_BSTx= 0.1 µF, C_COMPx= 1 nF, R_CSx= 100

mΩ, no load on SWx, FLTx pin floating (unless otherwise noted)

0.975

0.95

0.925

0.9

30

27.5

25

22.5

20

0.875

0.85

0.825

0.8

17.5

15

12.5

10

3 LEDs

6 LEDs

9 LEDs

12 LEDs

7.5

5

0.775

0.75

0

200 400 600 800 1000 1200 1400 1600 1800

LED Current (mA)

2.5

0

-40 -20

V_FPIN= 5 V

V_IN= 60 V

0

20

40

60

80 100 120 140 160

Temperature (°C)

图6-20. Efficiency vs LED Current

图6-19. COMP Leakage Current vs Temperature

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7 Detailed Description

7.1 Overview

The TPS92519-Q1 is a dual synchronous buck LED driver with a 4.5-V to 65-V input voltage range. The device

can deliver up to 2 A of continuous current per channel and power two independent strings of one to 16 series-

connected LEDs. The device implements an adaptive on-time current regulation control technique to achieve

fast transient response. This architecture uses a comparator and a one-shot on-timer that varies inversely with

input and output voltage to maintain a near-constant frequency. With the FSET pin connected to V5D the on-time

generator ensure near constant frequency of 385 kHz for channel 1 and 440 kHz for channel 2. With the FSET

pin grounded the on-time generator is programmed to operate channel 1 at approximately 2 MHz and channel 2

at 2.15 MHz. The on-time between two channels is offset to ensure low EMI signature. The integrated low offset

rail-to-rail error amplifier enables closed-loop regulation of LED current and ensures better than 4% accuracy

over a wide input, output, and temperature range.

The LED current reference is set by forcing voltage on IADJ input and can be varied from 140 mV to 2.45 V to

achieve over a 16:1 linear analog dimming range. Pulse Width Modulation (PWM) dimming of the LED current is

achieved by modulating the duty cycle of external voltage signal at UDIMx input. The external UDIMx input acts

as an enable and directly controls the LED current. This device optimizes the inductor current response and is

capable of achieving over a 1000:1 PWM dimming ratio.

The device incorporates an enhanced programmable fault feature including the following:

• Cycle-by-cycle switch overcurrent limit

• Input undervoltage protection

• Boot undervoltage protection

• Comp overvoltage protection

• Output open circuit indication

• Output short circuit indication

In addition, Thermal Shutdown (TSD) protection is implemented to limit the junction temperature at 175°C

(typical). The open-drain fault output, FLTx, indicates the status of the LEDs and is forced low whenever an

output open or short fault is detected by the device.

Toggling the enable input, EN, low forces the device in low-power sleep state. In this state, both channels are

disabled and analog supply, V5A, is disconnected to reduce the bias current drawn by the device.

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7.2 Functional Block Diagram

V5D

BST1

VIN1

+

UVLO

por

Rising: 4.1 V

Falling: 4.0 V

Hys: 100 mV

uvlo

V_BG

ch1_en

V5A

Analog Supply

Sleep Enable

Bandgap

2V_BG

LEB

bstuv1

lsilim1

hsilim1

slp_o

Control

and

Switch

Fault

Thermal

Sensor

Current

Limit

Circuit

+

œ

3 V

Logic

SW1

V_IADJ1

+

IADJ1

Current

Limit

Circuit

V_BG

PWM &

Dropout

Detection

pwm1

dropout1

+

V5D

LEB

V5A

2V_BG

V_IN1

PGND

On Time

Control

V_IN1

10 ꢀA

ton1

UDIM1

EN

CSP1

CSN1

Valley Current

Control

2V_BG

Toffmin1

slp

R

V-I Converter

V_IADJ1

V_CSN1

+

FSET

FLT1

+

ton1

ton2

pwm1

open1

LED Fault

Detection

short1

Logic

14R

COMP1

open1

Channel 1

short1

open2

short2

FLT2

BST2

VIN2

SW2

V_IADJ2

+

IADJ2

PGND

CSP2

CSN2

COMP2

Channel 2

Input

UVLO &

PWM

pwm2

dropout2

UDIM2

7.3 Feature Description

7.3.1 Buck Converter Switching Operation

The following operating description of the TPS92519-Q1 refers to the Functional Block Diagram and the

waveforms in 图 7-1. The main control loop of the TPS92519-Q1 is based on an adaptive on-time pulse width

modulation (PWM) technique that combines a constant on-time control with an inductor valley current sense

circuit for pseudo-fixed frequency operation. This proprietary control technique enables closed-loop regulation of

LED current and fast dynamic response necessary to meet the requirements for LED pixel control and LED

matrix beam applications.

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V_(CSP-CSN)

I_L(PK)ìR_CS

V

_IN- V_CSN

L

V_CSN

ìR_CS

L

ìR_CS

V_VAL

t

V_SW

V_IN

0

t

t_ON

t_OFF

t_SW

图7-1. Adaptive On Time Control Buck Converter Waveforms

In steady state, the high-side MOSFET is turned on at the beginning of each cycle. The on-time duration of this

MOSFET is controlled by an internal one-shot timer and the high-side MOSFET is turned off after the timer

expires. The one-shot timer duration is set by the output voltage measured at the CSP pin, V_CSP, and the input

voltage measured at the VIN pin, V_IN, to maintain a pseudo-fixed frequency. During the on-time interval, the

inductor current increases with a slope proportional to the voltage applied across its terminals (V_IN–V_CSP).

The low-side MOSFET is turned on after a fixed deadtime and the inductor current then decreases with the

constant slope proportional to the output voltage, V_CSP. Inductor current measured by the external sense resistor

is compared to the valley threshold, V_VAL, by an internal high-speed comparator. This MOSFET is turned off and

the one-shot timer is initiated when the sensed inductor current falls below the valley threshold voltage. The

high-side MOSFET is turned on again after a fixed deadtime.

The internal rail-to-rail error amplifier sets the valley threshold voltage and regulates the average inductor current

based on a reference set by IADJx input. A simple integral loop compensation circuit consisting of a capacitor

connected from the COMP pin to GND provides a stable and high-bandwidth response. As the inductor current

is directly sensed by an external resistor, the device operation is not sensitive to the ESR of the output

capacitors and is compatible with common multi-layered ceramic capacitors (MLCC).

7.3.2 Switching Frequency and Adaptive On-Time Control

The TPS92519-Q1 uses an adaptive on-time control scheme and does not have a dedicated on-board oscillator.

The one-shot timer is programmed by the voltage on FSET input. The on-time is calculated internally using 方程

式 1 and is inversely proportional to the measured input voltage, V_IN, and proportional to the measured CSP

voltage, V_CSP

.

V_CSP

t_ON= k ì

V

IN

(1)

Constant, κ, is set by the FSET pin logic.

2.606ì10^-6for channel 1

2.285ì10^-6for channel 2

¤

Œ

k =

V_FSET> 1.8 V

‹

Œ

›

4.890ì10^-7for channel 1

4.676ì10^-7for channel 2

¤

Œ

V_FSET< 0.8 V

‹

Œ

›

(2)

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Given the duty ratio of the buck converter is V_CSP/ V_IN, the switching period, T_SW, remains nearly constant over

all operating points. Use 方程式3 to calculate the switching period.

V

IN

T_SW= t_ON

ì

= k

V_CSP

(3)

(4)

Use 方程式4 to calculate the switching frequency.

1

f_SW

=

k

7.3.3 Minimum On-Time, Off-Time, and Inductor Ripple

Buck converter operation is impacted by minimum on-time, minimum off-time, and minimum peak-to-peak

inductor ripple limitations. The converter reaches the minimum on-time when operating with high input voltage

and low-output voltage. In this control scheme, the off-time continues to increase and the switching frequency

reduces to regulate the inductor current and LED current to the desired value.

V_OUT(MIN)

f_SW(MIN)

=

; t_ON= t_ON(MIN)

t_ON(MIN)ì V

IN(MAX)

(5)

The converter reaches the minimum off-time when operating in dropout (low input voltage and high output

voltage). As the on-time and off-time are fixed, the duty cycle is constant and the buck converter operates in

open-loop mode. The inductor current and LED current are not in regulation. The converter continues to switch

unless disabled by the IADJx input.

The behavior and response of valley comparator is dependent on sensed peak-to-peak voltage ripple,

ΔV_(CSP-CSN), and is a function of current sense resistor, R_CS, and peak-to-peak inductor current ripple,

Δi_L(PK-PK). To ensure periodic switching, the sensed peak-to-peak ripple must exceed the minimum value. At

high (near 100%) or low (near 0%) duty cycles, the inductor current ripple is not sufficient to ensure periodic

switching. Under such operating conditions, the converter transitions from periodic switching to a burst

sequence, forcing multiple on-time and off-time cycles at a rate higher than the programmed frequency. Although

the converter cannot operate in a periodic manner, the closed-loop control continues regulating the average LED

current with a larger ripple value corresponding to higher peak-to-peak inductor ripple. TI recommends choosing

an inductor, output capacitor, and switching frequency to ensure minimum sensed peak-to-peak ripple voltage

under nominal operating condition is greater than 20 mV. The Application and Implementation section

summarizes the detailed design procedure.

7.3.4 Enable

The TPS92519-Q1 has an enable input EN for start-up and shutdown control of the output. If the enable input is

greater than 1.8 V then both channels are enabled. If the enable pin is pulled below 0.8 V, the channels are

disabled and the TPS92519-Q1 is switched to a low I_Qshutdown mode. In this mode, the device draws a 2-μA

typical current from the VIN pin and 17-μA typical from V5D pin. TI does not recommend leaving EN pin

floating.

7.3.5 LED Current Regulation and Error Amplifier

The reference voltage, V_IADJ, is internally scaled by a gain factor of 1/14 through a resistor network. An internal

rail-to-rail error amplifier generates an error signal proportional to the difference between the scaled reference

voltage (V_IADJ/ 14) and the inductor current measured by the differential voltage drop between CSP and CSN,

V_(CSP-CSN). This error drives the COMP pin voltage, V_COMP, and directly controls the valley threshold of the

inductor current. Zero average DC error and closed-loop regulation is achieved by implementing an integral

compensation network consisting of a capacitor connected from the output of the error amplifier to GND. As a

good starting point, TI recommends a capacitor value between 1 nF and 10 nF between the COMP pin and

GND. The choice of compensation network must ensure a minimum of 60° of phase margin and 10 dB of gain

margin. The Application and Implementation section summarizes the detailed design procedure.

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CSPx

CSNx

Current Sense Amplifier

g_M

Valley Current

Control

10k

+

COMPx

V_IADJx(CLP)

Division by 14

V-I Converter

+

V_IADJx

0.14 V to 2.45 V

140k

图7-2. Closed-loop LED Current Regulation

LED current is dependent on the current sense resistor, R_CS. Use 方程式6 to calculate the LED current.

V _CSP-CSN

V

(

)

IADJ

I_LED

=

R_CS

14ìR_CS

(6)

LED current accuracy is a function of the tolerance of the external sense resistor, R_CS, and the variation in the

sense threshold, V_(CSP-CSN), caused by internal mismatch and temperature dependency of the analog

components. The TPS92519-Q1 is capable of achieving LED current accuracy of ±4% at full scale over

common-mode range and a junction temperature range of –40°C to 150°C.

7.3.6 Start-up Sequence

The start-up circuit allows the COMP pin voltage to gradually increase, thus reducing the LED current overshoot

and current surges. The switching operation is initiated after the COMP pin voltage exceeds 2.45 V. A 450-mV

hysteresis window allows the device to operate when COMP voltage is within the expected operating range of

2.2 V to 2.7 V. Switching is disabled on detection of low COMP voltage to avoid excessive negative inductor

current.

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V_IADJ

0.1

V_UDIM

2.45

0

V_COMP

2.45

450 mV

t

V_SW

V_IN

0

t

I_LED

t

图7-3. Soft-Start Sequence

The duration of soft start, t_ss, depends on the size of the compensation capacitor and the error amplifier source

current, I_COMP(SRC)

.

2.45ìC_COMP

I_COMP(SRC)

t_SS

=

(7)

The source current, I_COMP(SRC)is a function of the transconductance, g_M, of the error amplifier and error

generated between the reference and the current sensed voltage.

V

≈

’

IADJ

I_COMP(SRC)= g_Mì

- V

^(CSP^-^CSN)÷

∆

«

14

◊

(8)

With no current flowing through the LEDs, the soft start duration depends on the choice of compensation

capacitor, C_COMP, and the reference voltage, V_IADJ

.

The open drain fault indicator, FLTx, is set low when the COMP voltage deviates from the nominal range and

exceeds V_COMP(OV)threshold. This setting indicates a fault condition where the converter is operating in open-

loop and the LED current is out of regulation. The corresponding channel can be disabled by setting IADJx input

below 100 mV or controlling the UDIMx input.

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7.3.7 Analog Dimming and Forced Continuous Conduction Mode

Analog dimming is accomplished by modulating the voltage connected to IADJx input. The TPS92519-Q1

improves the linear range of analog dimming by supporting forced continuous conduction mode of operation.

With synchronous MOSFETs, the inductor current is allowed to go negative for part of the switching cycle, thus

enabling linear dimming with over 16:1 dimming range.

7.3.8 External PWM Dimming and Input Undervoltage Lockout (UVLO)

The UDIM pin is a multi-function input that features an accurate input voltage detection based on bandgap

thresholds with programmable hysteresis as shown in 图 7-4. This pin functions as the external PWM dimming

input for the LEDs and monitors VIN to detect dropout and undervoltage conditions. When the rising pin voltage

exceeds the 2.45-V threshold, 10 µA (typical) of current is driven out of the UDIM pin into the resistor divider

providing programmable hysteresis. TI recommends a bypass capacitor value of 1 nF between the UDIMx pin

and GND to improve noise immunity.

200 mV

VIN

V_BG

PWM &

Dropout

Detection

PWM

Standard

PWM

+

Dropout

V5A

R_UVx2

2V_BG

10 ꢀA

D_DIM

UDIM

R_UVH

10 kΩ

R_UVx1

C_UVx

Q_DIM

Inverted

PWM

图7-4. External PWM Dimming

The brightness of LEDs can be varied by modulating the duty cycle of the signal directly connected to the UDIM

input. In addition, either an n-channel MOSFET or a Schottky diode can be used to couple an external PWM

signal when using UDIM input in conjunction with UVLO functionality. With an n-channel MOSFET, the

brightness is proportional to the negative duty cycle of the external PWM signal. With a Schottky diode, the

brightness is proportional to the positive duty cycle of the external PWM signal.

Dropout and input undervoltage protection is achieved by connecting the resistor divider network from VIN to

UDIM pin and UDIM pin to GND. Dropout protection is activated when UDIM pin voltage drops below

V_{UDIMx(DO, FALLING)}threshold but is held above V_UDIMx(EN)threshold. In dropout protection mode, the device

disables the error amplidier and disconnects the COMP pin to maintain charge on the compensation network.

The device continues switching, ensuring fast response with minimum LED current overshoot as the converter

recovers from dropout condition. The minimum input voltage, below which dropout protection is activated is

programmed using 方程式9.

+10ì10³ì R_UVx1+ R_UVx2

≈

’

÷

R

(

)

(

UVHx

∆

V

= V_INx(DO,RISE)-I_UDIMx(DO)ì R_UVx2

+

INx(DO,FALL)

∆

÷

R_UVx1

«

◊

(9)

方程式 10 shows the input voltage rising threshold. When VIN exceeds the rising threshold, the error amplifier is

enabled and COMP pin is connected to compensation network to regulate LED current.

R_UVx1+ R_UVx2

R_UVx1

V

= V_{UDIMx(DO,RISE)}ì

INx(DO,RISE)

(10)

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Additional hysteresis to internal 100 mV is programmed by connecting an extra resistor, R_UVHx, in series with

UDIM pin. This connection allows the standard resistor divider to have smaller values, minimizing PWM delays.

Input undervoltage protection is triggered when UDIM pin voltage drops below V_UDIMx(EN)threshold. The device

responds to very low VIN voltage or to the external PWM input signal by disabling the error amplifier,

disconnecting the COMP pin and tri-stating the switch node. With switching disabled, inductor current and the

LED current drop to zero and the charge on the compensation network is maintained. On rising edge of PWM or

when VIN exceeds the internal hystersis of 200 mV, the converter resumes switching operation ramping inductor

current to the previous steady-state value.

方程式11 defines the VIN UVLO rising threshold.

R_UVx1+ R_UVx2

R_UVx1

V

= V_{UDIMx(EN,RISE)}ì

INx(UVLO,RISE)

(11)

Use 方程式12 to determine the VIN UVLO falling threshold.

+10ì10³ì R_UVx1+R_UVx2

≈

’

÷

R

(

)

(

UVHx

≈

∆

«

’

÷

◊

R_UVx1+R_UVx2

R_UVx1

∆

V

= V_{UDIMx(EN,FALL)}

ì

-I_UDIMx(DO)ì R_UVx2

+

INx(UVLO,FALL)

∆

÷

R_UVx1

«

◊

(12)

7.3.9 Shunt FET Dimming or Matrix Beam Application

V_CSN

V_LED12

V_LED1

t

V_(CSP-CSN)

V_VAL

0

t

图7-5. Shunt FET Dimming Transient Response

The TPS92519-Q1 is compatible with shunt FET dimming and LED Matrix Manager devices. The fast dynamic

response and adaptive on-time control topology ensure near ideal current source behavior with minimum

inductor current overshoot or undershoot. In contrast to constant off-time control, the control loop is able to

maintain LED current regulation under shorted output condition. The off-time of the converter naturally adapts to

the inductor slope and valley command while keeping the average LED current constant. 图 7-5 shows the

shunt-FET dimming transient with all LEDs switched from on to off.

The device behavior is impacted by the falling slew-rate of CSN node, V_CSN. A large slew-rate in conjunction

with the parasitic capacitances from CSP and CSN to GND results in differential voltage forcing the converter to

burst with minimum on-time and minimum off-time. To avoid switch node bursting TI recommends a maximum

slew-rate (dv/dt) of 15 V/µs.

7.3.10 Bias Supply

The device is powered by an external 5-V supply connected to V5D and V5A pins. Operation is enabled when

V5D and V5A exceed the 4.1-V (typical) rising threshold and is disabled when either V5D or V5A drops below

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the 4-V (typical) falling threshold. The comparator provides 100 mV of hysteresis to avoid chatter during

transitions. The V5D supply powers the internal digital logic and the high-side and low-side gate driver circuits.

The V5A supply powers sensitive analog circuits. The two bias pins can be connected together on the PCB or

through a series 10-Ω resistor between V5D and V5A with 5-V external supply connected directly to the V5D

pin. TI recommends a capacitor from each pin to GND . The recommended range for the bypass capacitor from

V5D pin to ground is between 1 µF and 4.7 µF. The recommended range from the V5A pin to ground is between

100 nF and 1 µF. The bypass capacitor from V5D to GND must be 10 times larger than the bootstrap capacitor,

C_BST, to support proper operation during PWM dimming. The voltage on V5D and V5A must never exceed 5.5 V.

In device sleep state, the V5A input is internally disconnected to reduce power consumption.

7.3.11 Bootstrap Supply

The TPS92519-Q1 contains both high-side and low-side N-channel MOSFETs. The high-side gate driver works

in conjunction with an internal bootstrap diode and an external bootstrap capacitor, C_BST. During the on-time of

the low-side MOSFET, the SW pin voltage is approximately 0 V and C_BSTis charged from the V5D supply

through the internal diode. TI recommends a 0.1-µF to 1-µF capacitor connected with short traces between the

BST and SW pins. A larger capacitor is required to prevent a bootstrap undervoltage fault when operating at low

PWM dimming frequencies.

7.3.12 Faults and Diagnostics

表7-1 summarizes the device behavior under fault conditions.

表7-1. Fault Description

FAULT

DETECTION

DESCRIPTION

Each channel is protected by an individual thermal sensor located close to the

switching MOSFETs. The thermal protection is activated in the event the maximum

MOSFET temperature exceeds the typical value of 175°C. The corresponding channel

is forced into shutdown mode. This feature is designed to prevent overheating and

damage to the internal switching MOSFETs.

Thermal protection

T_J> 175°C

V_5D(RISE)< 4.1 V

V_5D(FALL)> 4 V

V_5A(RISE)< 4.1 V

V5D undervoltage

lockout

The device enters the Undervoltage Lockout (UVLO). The switching operation is

disabled, the COMP capacitor is discharged.

In sleep mode, the internal V5A node is disconnected to reduce the current

consumption. The switching operation is disabled and the COMP capacitor is

discharged.

V5A undervoltage

lockout

V_5A(FALL)> 4 V

The device disables error amplifier and disconnects the compensation network for the

corresponding channel. Error amplifier is enabled and compensation network is

internally connected when the input voltage rises above the dropout rising threshold,

VINx dropout

protection

V_UDIMx< 2.35 V

V_INx(DO,RISE)

The device disables switching operation for the corresponding channel. Switching is

enabled when the input voltage rises above the turn-on threshold, V_{INx(UVLO,RISE)}

.

VINx undervoltage

lockout

V_UDIMx< 1.02 V

.

V_BSTx(RISE)> 3.14 V

V_BSTx(FALL)< 2.95 V

The device turns off the high-side MOSFET and turns on the low-side MOSFET for the

corresponding channel. Normal switching operation is resumed after the bootstrap

voltage exceeds 3.14 V.

BSTx undervoltage

lockout

COMPx

overvoltage

The FLTx flag is set low to indicate that the COMP voltage exceeded the normal

operating range. This condition indicates output open circuit fault.

V_COMPx> 3.2 V

V_CSNx< 2.45 V

The FLTx flag is set low to indicate an output short circuit condition based on sensed

CSNx voltage.

Short CHx output

The device turns off the high-side MOSFET and discharges the COMP capacitor when

the drain current exceeds 3.5-A typical. The low-side switch is turned on to discharge

the inductor and output capacitor. The device attempts to restart after delay of 3.6 ms

High-side switch

current limit

I_HS> 3.5 A

I_LS> 2.5 A

The device turns off both high-side and low-side MOSFETs and discharges the COMP

capacitor when the drain current exceeds 2.5 A typical. The device attempts to restart

after delay of 3.6 ms.

Low-side switch

current limit

The TPS92519-Q1 triggers an auto-restart on detection of the thermal shutdown, high-side, or low-side current

limit faults. In the case of thermal shutdown fault, the restart is initiated after the MOSFET temperature

decreases by the fixed hysteresis of 10°C. A soft-start sequence is initiated and switching operation is enabled.

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For a high-side or low-side current limit fault, a fixed 3.6-ms timer is initiated on detection of the fault. A restart is

initiated by the expiration of the fault timer and switching operation is enabled.

The output open circuit and short circuit faults force the FLTx pin low when biased through an external resistor

and connected to a 5-V supply. The FLTx output can be used in conjunction with a microcontroller or system

basis chip (SBC) as an interrupt and can be used to aid in fault diagnostics.

表7-2. Faults and Diagnostic Summary

FAULT OR

DIAGNOSTIC

ENABLE FAULT

TIMER

LIST

DESCRIPTION

FLT INDICATION

Thermal protection

VIN supply dropout protection

VIN supply undervoltage lockout

BST supply undervoltage lockout

COMP overvoltage

Fault

Diagnostics

Fault

No

Yes

No

Yes

No

VINx_(DO)

VINx_(UVLO)

CHxBSTUV

CHxCOMPOV

CHxSHORT

CHxHSILIM

CHxLSILIM

V5AUV

Fault

Diagnostics

Fault

Short circuit detected

High-side current limit

Low-side current limit

Fault

V5A undervoltage

Diagnostics

7.3.13 Output Short Circuit Fault

The TPS92519-Q1 monitors the CSNx voltage to detect output short circuit faults. A short failure is indicated

when the CSNx voltage drops below 1.5 V. The corresponding is FLTx flag is set low. The device continues to

regulate current and operate without interruption in case of short circuit.

CSNx

CSPx

VINx

L_PAR

R_CS

LED+

SWx

t_SH

C_OUT

L_PAR

PGNDx

LEDÅ

图7-6. Cable Harness Parasitic Inductance

The voltage transient imposed on CSPx and CSNx inputs during short circuit is dependent on the output

capacitance and is influenced by the cable harness impedance. The inductance associated with a long cable

harness resonates with the charge stored on the output capacitor and forces CSPx and CSNx voltage to ring

below ground. The negative voltage and current are dependent on the parasitic cable harness inductance and

resistance.

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V_CSN

V_LED

0

t_SH

t

图7-7. Short Circuit Fault Transient Behavior

When using a long cable harness, TI recommends a diode to clamp the negative voltage across CSPx and

CSNx input, as shown in 图 7-8. TI recommends a low forward voltage Schottky diode or a fast recovery silicon

diode with reverse blocking voltage rating greater than the maximum output voltage. The diode is required to be

placed close to the output capacitor and must ensure that the current flowing through CSP and CSN nodes

under negative transient condition is below the absolute maximum rating of the device.

VINx

LED+

SWx

C_OUT

D_RP

PGNDx

LEDÅ

图7-8. CSP and CSN Transient Protection Using an External Diode

7.3.14 Output Open Circuit Fault

An LED open circuit fault ultimately causes the output voltage to increase and settle close to the input voltage.

When this occurs, the TPS92519-Q1 switching operation is then controlled by the fixed on-time and minimum

off-time resulting in a duty cycle close to 100%. Under this condition, COMP voltage exceeds V_COMPx(OV)

threshold forcing FLTx flag low.

The dynamic behavior of the device and buck converter is influenced by the input voltage, V_IN, and the output

capacitor, C_OUT, value. The device response to open circuit can be categorized into the following three distinct

cases.

Case 1: For a Buck converter design with a small output capacitor, the switching operation in open load

condition excites the inductor and the output capacitor resonance, forcing the output voltage to oscillate. The

frequency and amplitude of the oscillation are based on the resonant frequency and Q-factor of the tank.

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V_CSN

V_IN

t

V_COMP

t_OC

V_COMPx(OV)

t

图7-9. Open Circuit Condition With Output Voltage Oscillation

Case 2: For a buck converter design with larger output capacitor, the inductor Q-factor and resonant frequency

are much lower than the switching frequency. In this case, output voltage rises to input voltage and the converter

continues to switch with minimum off-time.

V_CSN

V_IN

t

图7-10. Open Circuit Condition With Minimum Off-time Operation

7.3.15 Parallel Operation

The adaptive on-time control technique enables parallel operation of two or more channels with independent

current sharing and regulation. Each channel operates independently and delivers current based on the

corresponding IADJx set point. To equally share current amongst channels, the IADJx for all channels must be

connected to the external reference voltage.

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V_IADJ

IADJx

COMPx

CSNx

CSPx

SWx

C_COMPx

CHx

V_EN

EN

I_LED

PWM

UDIMx

L_x

R_CSx

C_OUTx

COMPy

EN

CSNy

CSPy

SWy

C_COMPy

CHy

UDIMy

IADJy

L_y

R_CSy

C_OUTy

V_IADJ

图7-11. Parallel Channel Configuration

Startup requires all channels to be enabled simultaneously by synchronizing the rising edge of IADJx voltage

above V_IADJx(SD)rising threshold. This simultaneous enabling ensures that the soft-start ramp is synchronized

and current sharing is achieved after COMP voltage increases above the rising startup threshold, V_COMPx(ST)

.

PWM dimming is achieved by connecting the external PWM signal to UDIMx pin of all parallel channels. All

parallel channels have to be controlled by single PWM dimming reference. TI does not recommend to PWM dim

individual parallel channels.

Additional considerations are necessary to account for bootstrap capacitor tolerance and the impact of the

capacitor variation when PWM dimming multiple parallel channels. Ensure that bootstrap capacitor voltage is

above the undervoltage threshold, V_BSTx(UV)for all operating conditions. For application requiring very low PWM

duty cycle or low PWM dimming frequency, TI recommends to connect the COMPx pin of all parallel channels

using nonparallel diodes, as shown in 图 7-12. This connection allows the parallel channels to respond and

recovery from bootstrap undervoltage fault when operating at low PWM dimming duty cycles.

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V_IADJ

IADJx

COMPx

CSNx

CSPx

SWx

C_COMPx

CHx

I_LED

D

L_x

R_CSx

C_OUTx

COMPy

CSNy

CSPy

SWy

C_COMPy

CHy

L_y

R_CSy

C_OUTy

V_IADJ

IADJy

图7-12. Parallel Channel Configuration for PWM Dimming Operation

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7.4 Device Functional Modes

The device has three functional modes: Power On Reset (POR) state, run mode and sleep mode.

7.4.1 Power On Reset (POR)

The device is in POR state when V5A or V5D input is below the undervoltage lockout threshold. In POR, both

channels are turned off. The device exits POR and enters functional modes when the V5D supply exceeds 4.1 V

(typical).

7.4.2 Run Mode

The device advances to run mode EN input is set high. In this mode, all the necessary conditions for initiating the

soft-start sequence are checked. If a fault occurs in this state, the device attempts to resume operation after

waiting for the fault timer to timeout.

Transition to sleep mode is by pulling EN input low. This action causes the device to enter a low-power state.

7.4.3 Sleep Mode

In sleep mode, the following occurs:

1. The internal regulators are disconnected from the V5A pin.

2. The oscillator is disabled.

3. The channels are disabled.

4. The high side and low side MOSFETs are turned off.

In sleep mode, the output voltage rises above 3 V as all internal loads are switched off and the leakage current

associated with high-side gate drive is forced through the switch node, SWx.

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8 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

8.1 Application Information

图8-1 shows a schematic of a typical application for the TPS92519-Q1.

LED+

C_COMP2

1

2

32

COMP2

UDIM2

CSN2

C_OUT2

R_CS2

31

30

CSP2

BST2

C_UV2

3

R_UV22

R_UV21

PGND

L₂

4

GND

V_BST

C_BST2

29

28

SW2

C_IN2

5V

5

6

7

VIN2

GND

V5A

27

26

25

24

23

22

R_ADJ21

FLT2

IADJ2

FSET

EN

C_V5D

5V

Supply

8

9

V5D

R_ADJ11R_ADJ22

C_V5A

IADJ1

FLT1

10

11

12

GND

VIN1

R_ADJ12

21

20

V_BST

SW1

C_IN1

13

GND

PGND

C_BST1

L₁

14

C_UV1

15

19

18

R_UV11

BST1

CSP1

R_UV12

UDIM1

R_CS1

C_COMP1

C_OUT1

16

17

COMP1

CSN1

LED+

图8-1. Buck LED Driver

8.1.1 Duty Cycle Consideration

The switch duty cycle, D, defines the converter operation and is a function of the input and output voltages. In

steady state, the duty cycle is defined using 方程式13:

V_CSN

D =

V

IN

(13)

There is no limitation for small duty cycles, because at low duty cycles, the switching frequency is reduced as

needed to always ensure current regulation. The maximum duty cycle attainable is limited by the minimum off-

time duration and is a function of switching frequency.

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8.1.2 Switching Frequency Selection

Nominal switching frequency (t_ON> t_ON(MIN)) is set by input voltage, V_IN, output voltage, V_CSPand the FSET pin.

The switching varies slightly over operating range and temperature based on converter efficiency. 表 8-1 shows

the nominal switching frequency for channel 1 and channel 2 based on FSET pin setting.

表8-1. Frequency Setting

FSET

CHANNEL

Channel 1

Channel 2

Channel 1

Channel 2

FREQUENCY

384 kHz

V_FSET> 1.8 V

438 kHz

2.04 MHz

2.14 MHz

V_FSET< 0.8 V

8.1.3 LED Current Set Point

The LED current is set by the external resistor, R_CS, and the IADJx pin. The current sense resistor, R_CS, is

selected to meet the maximum LED current specification and 90% of the full-scale range of IADJx clamp voltage.

0.9ì V

IADJx(CLP)

R_CS

=

14ìI_LEDx(MAX)

(14)

The LED current can be varied between minimum and maximum specified limits by modulating the voltage on

IADJx pin.

8.1.4 Inductor Selection

The inductor is sized to meet the ripple specification at 50% duty cycle. TI recommends a minimum of 30%

peak-to-peak inductor ripple to ensure periodic switching operation. Use 方程式 15 to calculate the inductor

value.

V

IN(TYP)

L =

4ì Di_Lì f_SW

(15)

Use 方程式 16 and 方程式 17 to calculate the RMS and peak currents through the inductor. Make sure that the

inductor is rated to handle these currents.

2

≈

∆

’

÷

Di_L(MAX)

2

i_L(RMS)

=

I_LED(MAX)+

∆

«

÷

◊

12

(16)

(17)

Di_L(MAX)

i_L(PK)= I_LED(MAX)

+

2

8.1.5 Output Capacitor Selection

The output capacitor value depends on the total series resistance of the LED string, r_D, and the switching

frequency, f_SW. 方程式18 calculates the capacitance required for the target LED ripple current.

Di_L(MAX)

C_OUT

=

8ì f_SWìr_Dì Di_LED

(18)

For applications where the converter supports pixel beam or matrix LED loads, additional design considerations

influence the selection of output capacitor. The size of the output capacitor depends on the slew-rate control of

the LED bypass switches and must be carefully selected while considering the overshoot current created by the

dv/dt of the bypass switch.

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When choosing the output capacitors, it is important to consider the ESR and ESL characteristics because they

directly impact the LED current ripple. Ceramic capacitors are the best choice due to the following:

• Low ESR

• High ripple current rating

• Long lifetime

• Good temperature performance

With ceramic capacitor technology, it is important to consider the derating factors associated with higher

temperature and DC bias operating conditions. TI recommends an X7R dielectric with a voltage rating greater

than maximum LED stack voltage.

8.1.6 Input Capacitor Selection

The input capacitor buffers the input voltage for transient events and decouples the converter from the supply. TI

recommends a 2.2-µF input capacitor across the VIN pin and PGND placed close to the device, and connected

using wide traces. X7R-rated ceramic capacitors are the best choice due to the low ESR, high ripple current

rating, and good temperature performance. Additional capacitance can be required to further limit the input

voltage deviation during PWM dimming operation.

8.1.7 Bootstrap Capacitor Selection

The bootstrap capacitor biases the high-side gate driver during the high-side FET on-time. The required

capacitance depends on the PWM dimming frequency, PWM_FREQ, and is sized to avoid boot undervoltage and

fault during PWM dimming operation. 方程式19 calculates the bootstrap capacitance, C_BST

.

I_Q(BST)

C_BST

=

V

+ V_BST(HYS)- V_BST(UV)ìPWM

(

)

5D

FREQ

(19)

表8-2 summarizes the TI recommended bootstrap capacitor value for different PWM dimming frequencies.

表8-2. Bootstrap Capacitor Value

PWM DIMMING FREQUENCY (Hz)

BOOTSTRAP CAPACITOR (µF)

1507

1318

1055

879

0.1

0.15

0.22

0.33

0.47

1

659

439

215

108

2

8.1.8 Compensation Capacitor Selection

A simple integral compensator is recommended to achieve stable operation across the wide operating range.

The bode plot of the loop gain with different compensation capacitors is shown in 图 8-2. The buck converter

behaves as a single pole system with additional phase lag caused by the switching behavior. The gain and

phase margin is then determined by the choice of the switching frequency and is independent of other design

parameters. TI recommends a 1-nF to 10-nF capacitor to achieve bandwidth between 4 kHz and 40 kHz. The

choice of compensation capacitor impacts the transient response, the shunt FET dimming behavior and PWM

dimming performance. A larger compensation capacitor (lower bandwidth) is recommended to limit the LED

current overshoot on the rising edge of internal or external PWM signal. A smaller compensation capacitor

(higher bandwidth) is recommend to improve shunt FET dimming response.

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60

100

2.2 nF

1 nF

40

20

75

3.3 nF

4.7 nF

6.8 nF

50

10 nF

25

0

-20

-40

-60

-80

-100

0

-25

-50

-75

-100

-125

-120

1000

2000 3000 5000

10000

20000

50000 100000 200000

Frequency (Hz)

500000 1000000 2000000

5000000 1E+7

L = 68 µH, f_SW= 438 kHz

图8-2. Simulated Bode Plot of Loop Gain

8.1.9 Input Undervoltage Protection

图 8-1 shows that the undervoltage protection threshold is programmed using a resistor divider, R_UV1and R_UV2

,

from the input voltage, V_IN, to ground. Use 方程式20 and 方程式21 to calculate the resistor values.

2ì V

V

INx(DO,FALL)

INx(UVLO,RISE)

R_UVx2

=

-

-10ì10³

I_UDIMx(HYS)

(20)

(21)

V_{UDIMx(EN,RISE)}

_{INx(UVLO,RISE)}- V_{UDIM(EN,RISE)}

R_UVx1

=

ìR_UVx2

V

8.1.10 CSN Protection Diode

An external Schottky diode is selected to protect the CSP / CSN node by clamping the negative voltage during

short circuit transient. The Schottky diode must be selected based on the length of the cable harness and the

choice of output capacitor. TI recommends a Schottky diode with low forward voltage drop at room-temperature

and non-repetitive peak surge current rating of 10 A for duration of 5 µs. The diode must be located close to the

CSN pin.

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8.2 Typical Application

图8-3. Application Schematic

8.2.1 Design Requirements

表8-3. Design Parameters

PARAMETER

CONDITIONS

MIN

TYP

60

MAX

UNIT

V

V_IN

Input Voltage

58

62

V_IN(DO)

N_S

V_FLED

r_D

V_OUT

I_LED

Dropout protection threshold

Number of LEDs

Falling

55

V

1

16

3.4

LED forward voltage drop

LED string series resistance

Output voltage

2.8

0.1

2.8

100

3

V

N × r_D(LED)

Ns × V_FLED

1.6

Ω

V

54.4

1600

LED current

mA

Defined as percentage peak-to-peak at maximum

LED current. 5 % of maximum LED current.

LED current ripple

80

mA

Δi_LED

Defined as percentage peak-to-peak at maximum

LED current

Inductor current ripple

Start input voltage

30

28.5

5

%

V

Δi_L

V_{IN(UVLO,RISE)}

V_IN(UVLO,HYS)

Input voltage rising

Input voltage undervoltage lockout

hysteresis

V

f_PWM

D_PWM

V_SW

T_A

PWM frequency

439

Hz

%

PWM dimming duty cycle

Switching frequency

Ambient temperature

4

100

438

25

kHz

°C

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8.2.2 Detailed Design Procedure

8.2.2.1 Calculating Duty Cycle

Solve for duty cycle D, D_MAX, and D_MIN

:

V_OUT(MAX)

54.4

58

D_MAX

=

= 0.938

V

IN(MIN)

(22)

(23)

V_OUT(MIN)

2.8

D_MIN

=

= 0.0452

V

62

IN(MAX)

8.2.2.2 Calculating Minimum On-Time and Off-Time

Solve for minimum on-time, t_ON(DMIN)at minimum duty cycle and maximum on-time, t_ON(DMAX)at maximum duty

cycle:

V_OUT(MIN)

1

2.8

62

1

t_ON(DMIN)

=

ì

=

ì

= 103.1ì10^-9

= 2.141ì10^-6

438ì10³

V

f_SW

IN(MAX)

(24)

(25)

V_OUT(MAX)

1

54.4

58

1

t_ON(DMAX)

=

ì

=

ì

438ì10³

V

f_SW

IN(MIN)

8.2.2.3 Minimum Switching Frequency

Confirm minimum switching frequency at t_ON(DMIN), f_SW(MIN)

:

V_OUT(MIN)

2.8

103.1ì10^-9ì 62

f_SW(MIN)

=

= 438ì10³

t_ON(DMIN)ì V

IN(MAX)

(26)

(27)

(28)

For the design specification, t_ON(DMIN)> t_ON(MIN)and f_SW(MIN)= f_SW

.

8.2.2.4 LED Current Set Point

Solve for sense resistor, R_CS

:

0.9ì V

0.9ì 2.45

14ì1.6

IADJ(CLP)

R_CS

=

= 0.0984

14ìI_LED(MAX)

A standard resistor of 100 mΩwith tolerance better than 1 % and low temperature coefficient is selected.

8.2.2.5 Inductor Selection

The inductor is selected to meet the recommended 30% peak-to-peak inductor ripple specification:

V

IN(TYP)

60

4ì0.3ì1.6ì 438x10³

IN(TYP)

L =

=

= 71.3ì10^-6

4ì Di_Lì f_SW4ì 0.3ìI_LED(MAX)ì f_SW

The closest standard capacitor is 68 µH.

• Lower inductor values increase the peak-to-peak inductor current, which minimizes size and cost at the

expense of reduced efficiency and larger output capacitor.

• Higher inductance values decrease the peak-to-peak inductor current, which increases efficiency but reduces

the operating range based on minimum sense voltage ripple, ΔV_(CSP-CSN)specification.

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8.2.2.6 Output Capacitor Selection

The minimum output capacitance is selected to meet the LED current ripple specification:

Di_L(MAX)

0.48

8ì 438ì10³ì1.6 ì80 ì10^-3

C_OUT

=

= 1.07ì10^-6

8ì f_SWìr_D(MAX)ì Di_LED(MAX)

(29)

A standard 1-µF, 100-V X7R capacitor is selected.

8.2.2.7 Bootstrap Capacitor Selection

Referring to 表8-2, a standard 470-nF, 16-V X7R capacitor is selected to support PWM frequency of 439 Hz.

8.2.2.8 Compensation Capacitor Selection

A compensation capacitor of 2.2 nF is selected to achieve balanced transient response between PWM dimming

and shunt FET dimming.

60

100

2.2 nF

1 nF

3.3 nF

4.7 nF

6.8 nF

10 nF

40

75

20

50

0

25

-20

-40

-60

-80

-100

-120

0

-25

-50

-75

-100

-125

1000

2000 3000 5000

10000

20000

50000 100000 200000

Frequency (Hz)

500000 1000000 2000000

5000000 1E+7

图8-4. Simulated Buck Converter Bode Plot

8.2.2.9 PWM Dimming and Input Voltage Protection

The device channel enable function and external PWM signal is achieved by controlling UDIM input. The device

modulates the LED current based on the PWM duty cycle of the external signal.

Input undervoltage lockout function is implemented by selecting R_UV1and R_UV2resistor along with internal

hysteresis.

2ì V

V

IN(DO,FALL)

2ì28.5

55

IN(UVLO,RISE)

R_UV2

=

-

-10ì10³=

-

-10ì10³= 190ì10³

10ì10^-610ì10^-6

I_UDIM(DO)

(30)

(31)

A standard 191-kΩresistor is selected for R_UV2

.

V_{UDIM(EN,RISE)}

1.22

28.5 -1.22

R_UV1

=

ìR_UV2

=

ì191ì10³= 8.54ì10³

V_{IN(UVLO,RISE)}- V_{UDIM(EN,RISE)}

A standard 8.45-kΩresistor is selected for R_UV1

.

34

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8.2.3 Application Curves

Ch1: SW voltage (10 V/div); Ch2: Output voltage (4 V/div);

Ch3: Inductor current (200 mA/div); Time: 1 µs/div

Ch1: SW voltage (10 V/div); Ch3: Inductor current (200 mA/

div); Ch4: COMP voltage (400 mV/div); Time: 50 µs/div

图8-6. Normal Operation

图8-5. Start-up Transient

Ch1: SW voltage (10 V/div); Ch2: Output voltage (4 V/div);

Ch3: Inductor current (200 mA/div); Ch4: LED current (200

mA/div); Time: 500 µs/div

Ch1: SW voltage (10 V/div); Ch2: Output voltage (4 V/div);

Ch3: Inductor current (200 mA/div); Ch4: LED current (200

mA/div); Time: 5 µs/div

图8-7. PWM Dimming Transient

图8-8. PWM Dimming (Rising Edge)

Ch1: SW voltage (10 V/div); Ch2: Output voltage (4 V/div);

Ch4: LED current (200 mA/div); Time: 400 µs/div

Ch1: SW voltage (10 V/div); Ch2: Output voltage (4 V/div);

Ch3: Inductor current (200 mA/div); Ch4: LED current (200

mA/div); Time: 5 µs/div

图8-10. Shunt Dimming With Matrix Manager

图8-9. PWM Dimming (Falling Edge)

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Ch1: SW voltage (10 V/div); Ch2: Output voltage (4 V/div);

Ch4: LED current (200 mA/div); Time: 400 µs/div

Ch1: SW voltage (10 V/div); Ch2: Output voltage (4 V/div);

Ch4: LED current (200 mA/div); Time: 50 µs/div

图8-11. Shunt Dimming (LEDs ON-OFF Transient)

图8-12. Shunt Dimming (LEDs OFF to LEDs ON)

Ch1: SW voltage (10 V/div); Ch2: Output voltage (4 V/div);

Ch4: LED current (200 mA/div); Time: 50 µs/div

Ch1: SW voltage (10 V/div); Ch2: Output voltage (4 V/div);

Ch3: Inductor current (200 mA/div); Ch4: LED current (200

mA/div); Time: 50 µs/div

图8-13. Shunt Dimming (LEDs ON to LEDs OFF)

图8-14. Output Short Circuit Fault

Ch1: SW voltage (10 V/div); Ch2: Output voltage (4 V/div);

Ch3: Inductor current (200 mA/div); Ch4: LED current (200

mA/div); Time: 40 µs/div

Ch1: SW voltage (10 V/div); Ch2:

Output voltage (4 V/div); Ch3: Inductor

current (400 mA/div); Ch4: LED current

(200 mA/div); Time: 40 µs/div

图8-15. Output Short Circuit Fault Recovery

图8-16. Output Open Circuit Fault

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9 Power Supply Recommendations

This device is designed to operate from an input voltage supply range between 4.5 V and 65 V. The input can be

a car battery or another preregulated power supply. Additional bulk capacitance or an input filter can be required

in addition to the ceramic bypass capacitors to address converter stability, noise, and EMI concerns.

10 Layout

10.1 Layout Guidelines

The performance of any switching converter depends as much on the layout of the PCB as the component

selection. The following guidelines can help you design a PCB with the best power converter performance:

• Place ceramic high-frequency bypass capacitors as close as possible to the TPS92519-Q1 VIN and PGND

pins. Grounding for both the input and output capacitors must consist of localized top side planes that

connect to the PGND pins.

• Place bypass capacitors for V5D and V5A close to the pins and ground the capacitors to device ground.

• Differentially route the CSP and CSN pins to sense resistor. Route the traces away from noisy nodes,

preferably through a layer on the other side of a shielding or ground layer.

• Use ground plane in one of the middle layers for noise shielding.

• Make VIN and ground connection as wide as possible. This action reduces any voltage drops on the input of

the converter and maximizes efficiency.

10.1.1 Compact Layout for EMI Reduction

Radiated EMI is generated by the high di/dt from pulsing currents in switching converters. The larger the area

covered by the path of a pulsing current, the more electromagnetic emission is generated. The key to minimize

radiated EMI is to identify the pulsing current path and minimize the area of the path. In buck converters, the

pulsing current path is from the VIN side of the input capacitors through the HS switch, through the LS switch,

and then returns to the ground of the input capacitor.

High-frequency ceramic bypass capacitors at the input side provide primary path for the high di/dt components of

the pulsing current. Placing ceramic capacitors as close as possible to the VIN and PGND pins is the key to EMI

reduction.

The PCB copper connection of the SW pin to the inductor must be as short as possible and just wide enough to

carry the LED current without excessive heating. Short, thick traces or, copper pours (shapes), must be used for

high current conduction path to minimize parasitic resistance. Place the output capacitor close to the CSN pin

and grounded closely to the PGND pin.

10.1.1.1 Ground Plane

TI recommends using one of the middle layers as a solid ground plane. The ground plane provides shielding for

sensitive circuits and traces. The ground plane also provides a quiet reference potential for the control circuitry.

Connect the GND and PGND pins to the ground plane using vias right next to the bypass capacitors. PGND pins

are connected to the source of the internal LS switch. The pins must be connected directly to the grounds of the

input and output capacitors. The PGND net contains noise at the switching frequency and can bounce due to

load variations.

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10.2 Layout Example

COMP2

UDIM2

PGND

VIN2

CSN2

CSP2

BST2

SW2

1

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

2

3

4

SW2

5

VIN2

FLT2

IADJ2

FSET

EN

6

GND

7

V5A

8

V5D

9

GND

IADJ1

FLT1

SW1

10

11

12

13

14

15

16

VIN1

PGND

UDIM1

COMP1

SW1

BST1

CSP1

CSN1

图10-1. TPS92519-Q1 Layout Example

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11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation

For related documentation see the following:

Texas Instruments, TPS92519-Q1 Evaluation Module User's Guide

11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

11.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

11.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

11.5 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE MATERIALS INFORMATION

www.ti.com

12-Dec-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS92519QDAPRQ1 HTSSOP

DAP

32

2500

330.0

24.4

8.8

11.8

1.8

12.0

24.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

12-Dec-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

HTSSOP DAP 32

SPQ

Length (mm) Width (mm) Height (mm)

367.0 367.0 45.0

TPS92519QDAPRQ1

2500

Pack Materials-Page 2

GENERIC PACKAGE VIEW

DAP 32

8.1 x 11, 0.65 mm pitch

PowerPAD^TMTSSOP - 1.2 mm max height

PLASTIC SMALL OUTLINE

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4225303/A

www.ti.com

PACKAGE OUTLINE

TM

DAP0032F

PowerPAD TSSOP - 1.2 mm max height

S

C

A

L

E

1

.

5

0

PLASTIC SMALL OUTLINE

8.3

7.9

TYP

A

PIN 1 ID AREA

30X 0.65

32

1

11.1

10.9

NOTE 3

2X

9.75

16

B

17

0.30

32X

0.19

6.2

6.0

0.1 C

0.1

C A B

SEATING PLANE

(0.15) TYP

C

SEE DETAIL A

4.11

3.29

EXPOSED

THERMAL PAD

0.25

4.06

3.16

1.2 MAX

GAGE PLANE

0.75

0.50

0.15

0.05

2X (0.9)

NOTE 5

0 - 8

2X (0.15)

NOTE 5

DETAIL A

TYPICAL

4226056/A 07/2020

PowerPAD is a trademark of Texas Instruments.

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. Reference JEDEC registration MO-153.

5. Features may differ and may not be present.

www.ti.com

EXAMPLE BOARD LAYOUT

TM

DAP0032F

PowerPAD TSSOP - 1.2 mm max height

PLASTIC SMALL OUTLINE

(5.2)

NOTE 9

SOLDER MASK

DEFINED PAD

(4.11)

32X (1.5)

SYMM

SEE DETAILS

1

32

32X (0.45)

30X (0.65)

(11)

NOTE 9

SYMM

(4.06)

(1.2 TYP)

(R0.05) TYP

(

0.2) TYP

VIA

16

17

(0.65) TYP

(1.3) TYP

(7.5)

METAL COVERED

BY SOLDER MASK

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

METAL UNDER

SOLDER MASK

METAL

SOLDER MASK

OPENING

EXPOSED METAL

0.05 MIN

ALL AROUND

0.05 MAX

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4226056/A 07/2020

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).

9. Size of metal pad may vary due to creepage requirement.

www.ti.com

EXAMPLE STENCIL DESIGN

TM

DAP0032F

PowerPAD TSSOP - 1.2 mm max height

PLASTIC SMALL OUTLINE

(4.11)

BASED ON

0.125 THICK

STENCIL

32X (1.5)

1

32

32X (0.45)

30X (0.65)

(4.06)

BASED ON

SYMM

0.125 THICK

STENCIL

SEE TABLE FOR

DIFFERENT OPENINGS

FOR OTHER STENCIL

THICKNESSES

17

16

METAL COVERED

BY SOLDER MASK

SYMM

(7.5)

SOLDER PASTE EXAMPLE

EXPOSED PAD

100% PRINTED SOLDER COVERAGE BY AREA

SCALE:8X

STENCIL

THICKNESS

SOLDER STENCIL

OPENING

0.1

4.60 X 4.54

4.11 X 4.06 (SHOWN)

3.75 X 3.71

0.125

0.15

0.175

3.47 X 3.43

4226056/A 07/2020

NOTES: (continued)

10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

11. Board assembly site may have different recommendations for stencil design.

www.ti.com

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TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS92519-Q1
厂家：	TEXAS INSTRUMENTS
描述：	汽车 2A 双路同步降压 LED 驱动器驱动驱动器
文件：	总47页 (文件大小：4531K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS92519-Q1 [TI]

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