TPS92561 [TI]

用于 LED 照明的相位可调光、单级升压控制器;


型号：	TPS92561
厂家：	TEXAS INSTRUMENTS
描述：	用于 LED 照明的相位可调光、单级升压控制器控制器
文件：	总26页 (文件大小：2709K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS92561

www.ti.com.cn

ZHCSC14B –DECEMBER 2013–REVISED JANUARY 2014

TPS92561 – 针对发光二极管 (LED) 照明的相位可调光、单级升压控制器

特性

应用范围

•

简单滞后控制

•

离线 TRIAC 可调光应用

•

紧凑解决方案和简单物料清单

离线不可调光灯

自然可调光三端双向可控硅 (TRIAC) 和反相位调光

器

要求高效和尽可能低的物料清单 (BOM) 成本的灯

工业用和商用固态照明

•

执行 LED 驱动电路，此电路效率大于 90%，功率

因数大于 0.9，并且总谐波失真 (THD) 小于 20%

说明

•

可编程输出过压保护

过热关断

TPS92561 器件是一款升压控制器，此控制器用于采

用高压、低电流 LED 的 LED 照明应用。在照明应用

使用升压转换器的方法可生产出体积尽可能小的转换

器，并且可实现 90% 以上的高效率。此器件包含一个

具有固定偏移的电流感测比较器，从而实现简单滞后控

制机制，此机制没有那些通常与升压转换器相关的环路

补偿问题。集成过压保护 (OVP) 和 VCC 稳压器进一

步简化了设计过程，并且减少了外部组件数量。

VCC 欠压闭锁

带外露焊盘的 8 引脚超薄型小外形尺寸

(VSSOP)（表面贴装小外形尺寸 (MSOP)）封装

LED+

EMI

Filter

LED+

TPS92561

GATE

SRC

VCC

SEN

OVP

ADJ

GND

(opt) TRIAC

Dimmer

图 1. 典型应用电路原理图

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

English Data Sheet: SLVSCD1

TPS92561

ZHCSC14B –DECEMBER 2013–REVISED JANUARY 2014

www.ti.com.cn

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

Absolute Maximum Ratings⁽¹⁾

Over operating free-air temperature range (unless otherwise noted)

MIN

MAX

5.0

UNIT

SRC, SEN, ADJ, OVP

–0.3

Pin voltage range⁽²⁾

–1.0

45.0

12.0

VCC

–0.3

ESD rating⁽³⁾

Human body model (HBM)

Storage temperature range

Junction temperature range

1.5

°C

T_stg

T_J

–60

150

Internally Limited

(1) Stresses beyond those listed under "absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating

conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to network ground terminal.

(3) ESD testing is performed according to the respective JESD22 JEDEC standard.

Thermal Characteristics

Over operating free-air temperature range (unless otherwise noted)

TPS92561

THERMAL METRIC⁽¹⁾

UNITS

DGN (8 PINS)

65.3

θ_JA

Junction-to-ambient thermal resistance⁽²⁾

θ_JCtop

θ_JB

Junction-to-case (top) thermal resistance⁽³⁾

Junction-to-board thermal resistance⁽⁴⁾

Junction-to-top characterization parameter⁽⁵⁾

Junction-to-board characterization parameter⁽⁶⁾

Junction-to-case (bottom) thermal resistance⁽⁷⁾

64.8

44.8

°C/W

ψ_JT

3.9

ψ_JB

44.6

θ_JCbot

13.2

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specified JEDEC

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, θ_JT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, θ_JB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)

MIN

6.5

NOM

MAX

UNIT

T_J

Supply voltage

Operating junction temperature

–40

125

°C

TPS92561

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ZHCSC14B –DECEMBER 2013–REVISED JANUARY 2014

Electrical Characteristics

Over recommended operating conditions with –40°C ≤ T_J≤ 125°C. VCC = 12 V. C_VCC= 0.47 µF

PARAMETER

SUPPLY

CONDITIONS

MIN

0.5

TYP

1.0

MAX UNIT

I_IN

V_Poperating current

6.5 V < V_VP< 42 V

1.6

VCC Regulator

I_CC≤ 10 mA

7.75

8.35

8.95

C_VCC= 0.47 µF

12 V < V_VP< 42 V

I_CC= 10 mA

C_VCC= 0.47 µF

V_VP= 6.5 V

5.42

5.92

6.42

VCC

V_CCregulated voltage

I_CC= 0 mA

C_VCC= 0.47 µF

V_VP= 2 V

V_CC= 0 V

6.5 V < V_VP< 42 V

I_CC-LIM

V_CCcurrent limit

V_CC-UVLO-UPTHV_CCUVLO rising threshold

V_CC-UVLO-LOTHV_CCUVLO falling threshold

MOSFET Gate Driver

5.00

4.68

5.44

5.07

5.85

5.46

With respect to SRC

Sinking 100 mA from GATE

Force VCC = 9.5 V

8.00

8.71

180

9.41

350

V_GATE-HIGH

Gate driver output high

With respect to SRC

Sourcing 100 mA to GATE

V_GATE-LOW

Gate driver output low

t_RISE

t_FALL

V_GATErise time

V_GATEfall time

C_GATE= 1 nF across GATE and SRC

t_{RISE-PG-DELAY}V_GATElow-to-high propagation delay

t_{FALL-PG-DELAY}V_GATEhigh-to-low propagation delay

Current Source at ADJ Pin

112

I_ADJ-STARTUP

Output current of ADJ pin at start-up

V_ADJ< 90 mV

µA

Current Sense Amplifier

V_SEN-UPPER-THV_SENupper threshold over V_ADJ

V_SEN– V_ADJ

17.6

29.3

V_ADJ= 0.2 V

V_GATEat falling edge

V_SEN-LOWER-THV_SENlower threshold over V_ADJ

V_SEN– V_ADJ

V_ADJ= 0.2 V

–40.7 –29.1 –17.5

V_GATEat rising edge

V_SEN-HYS

V_SENhysteresis

(V_SEN-UPPER-TH– V_SEN-LOWER-TH

)

40.9

–4.0

60.0

–0.1

75.9

4.0

V_SEN-OFFSET

V_SENoffset with respect to V_ADJ

(V_SEN-UPPER-TH+ V_SEN-LOWER-TH) / 2

Output Overvoltage Protection (OVP)

V_OVP-UPTHOutput overvoltage detection upper

V_OVPincreasing, V_GATEat falling edge

V_OVP-UPTH– V_OVP-LOTH

1.11

1.19

1.27

threshold

V_OVP-HYS

Output overvoltage detection hysteresis

Thermal Shutdown

T_SD

Thermal shutdown temperature

T_Jrising

165

°C

T_SD-HYS

Thermal shutdown temperature hysteresis T_Jfalling

TPS92561

ZHCSC14B –DECEMBER 2013–REVISED JANUARY 2014

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DEVICE INFORMATION

8-PIN VSSOP (MSOP) PACKAGE (EXPOSED PAD)

(TOP VIEW)

TPS92561

GATE

SRC

VCC

SEN

OVP

ADJ

GND

Table 1. Terminal Functions

NAME

DESCRIPTION

APPLICATION INFORMATION

NO.

Gate driver output pin

Connect to the gate terminal of the low-side N-channel power FET. For off-line

applications, use a gate resistance of ≥ 75 Ω.

GATE

Gate driver return

Connect to the source terminal of the low-side, N-channel power FET. By connecting

SRC to the FET source, switching current spikes are not passed through the sense

resistor.

SRC

VCC

SEN

Gate driver power rail

LED current sense pin

Connect a 0.47-µF minimum decoupling cap from this pin to SRC pin.

Current sense input. For off-line applications, connect to SEN and the current sensing

resistor through an R-C filter with a time constant similar to the converter switching

frequency.

GND

ADJ

OVP

Ground

Connect to the system ground plane.

LED current adjust pin

Converter reference. Can be connected to the converter rectified AC for high power

factor, or to the LED output voltage for improved line regulation.

Overvoltage

Connect to resistor divider from VOUT (LED+) to detect overvoltage.

Power supply of the

integrated circuit (IC)

Connect to an appropriate voltage source to provide power for the IC. (VP ≤ 42 V) See

Application Circuits for example diagrams.

Solder to printed circuit board (PCB) with or without thermal vias to enhance thermal

performance. Although it can be left floating, TI recommends to connect the

PowerPAD™ to GND.

PowerPAD

TPS92561

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ZHCSC14B –DECEMBER 2013–REVISED JANUARY 2014

Block Diagram

VCC

LDO

VCC

GATE

DRIVER

GATE

VCC

VCC Under-

Voltage

Lockout

UVLO

TSD

SRC

SEN

Thermal

Shutdown

CONTROL

ADJ

GND

OVP

1.2V

Figure 2. Functional Block Diagram

TPS92561

ZHCSC14B –DECEMBER 2013–REVISED JANUARY 2014

www.ti.com.cn

Typical Characteristics

V_P= V_{P_NOM}= 12 V

V_PBIAS CURRENT (mA)

TEMPERATURE (°C)

V_CCVOLTAGE (V)

TEMPERATURE (°C)

1.00

0.99

0.98

0.97

0.96

0.95

0.94

0.93

0.92

0.91

0.90

9.0

8.9

8.8

8.7

8.6

8.5

8.4

8.3

8.2

8.1

8.0

20 35 50 65 80 95 110 125

±40 ±25 ±10

Temperature (C)

C001

C002

Figure 3. V_POperating Current

(Non-Switching)

Figure 4. V_CCRegulated Voltage

V_CCUVLO (V)

TEMPERATURE (°C)

V_SENSWITCHING THRESHOLDS (mV)

TEMPERATURE (°C)

5.75

5.65

5.55

5.45

5.35

5.25

5.15

5.05

4.95

4.85

4.75

±10

±20

±30

±40

Vsen Switching Threshold (Lower)

Vsen Switching Threshold (Upper)

Vcc UVLO Rising

Vcc UVLO Falling

20 35 50 65 80 95 110 125

±40 ±25 ±10

20 35 50 65 80 95 110 125

±40 ±25 ±10

Temperature (C)

C003

C004

Figure 5. V_CCUVLO Thresholds

Figure 6. V_SENSwitching Thresholds (mV)

TPS92561

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ZHCSC14B –DECEMBER 2013–REVISED JANUARY 2014

V_P= V_{P_NOM}= 12 V

V_SENHYSTERESIS (mV)

TEMPERATURE (°C)

OVP RISING THRESHOLD (V)

TEMPERATURE (°C)

1.200

1.198

1.196

1.194

1.192

1.190

1.188

1.186

1.184

1.182

1.180

20 35 50 65 80 95 110 125

±40 ±25 ±10

Temperature (C)

C005

C006

Figure 7. V_SENHysteresis (mV)

Figure 8. OVP Threshold Voltages

TPS92561

ZHCSC14B –DECEMBER 2013–REVISED JANUARY 2014

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APPLICATION INFORMATION

Description

The TPS92561 device is a boost controller for phase cut dimmer compatible LED lighting applications. The

device incorporates a current sense comparator with a fixed offset, allowing the construction of a hysteretic, off-

line converter suitable for driving LEDs in a wide variety of applications.

The inductor peak-to-peak current ripple follows the device reference, the ADJ pin voltage (V_ADJ), and is bounded

by the SEN pin hysteresis (V_SEN-HYS). By using a voltage divider from the rectified AC voltage, the inductor

current can be made to follow the line closely and create conversions which result in high power factor and low

THD. Boost converters also have an advantage when TRIAC dimming because of their inherent ability to draw

continuous current from the line. This eliminates the need for additional hold current circuitry as the converter

itself can draw power until the zero crossing point is reached. The continuous input current of a boost also

reduces the input EMI filter requirements.

Basics of Operation

The main switch is turned on and off when the SEN comparator reaches trip points in a window around the ADJ

reference. In cycle 1, the main switch is on until the current reaches the turn off threshold. In cycle 2, the switch

is kept off until the turn on threshold is reached. In Figure 9, V_{SEN-UPPER_TH}and V_SEN-LOWER-THare assumed to be

their typical value of 30 mV.

(V_ADJ+ 30 mV) / R_SENSE

V_ADJ/ R_SENSE

L(ave)

ꢀ V_LED

(V_ADJ± 30 mV) / R_SENSE

OFF

Time

TPS92561

GATE

SRC OVP

VCC ADJ

SEN GND

Figure 9. Basics of Hysteretic Boost Operation

TPS92561

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ZHCSC14B –DECEMBER 2013–REVISED JANUARY 2014

Sample Scope Capture

The main inductor current varies in a window around the ADJ reference voltage:

Figure 10. TPS92561 Operation Waveform (1 ms/div)

Yellow: ADJ Voltage (50 mV/div) Blue: R_SENSEVoltage (50 mV/div)

VCC Bias Supply and Start-Up

The TPS92561 device can be configured to obtain bias power in several different configurations: AUX winding

from the main inductor (see Figure 15), a linear regulator from the input rectified AC (see Figure 16), or a linear

regulator from the output LED voltage (see Figure 17). A linear regulator can be constructed from a resistor, a

Zener diode, and a N-Channel MOSFET. Each configuration has benefits and trade-offs.

Table 2. VCC Bias Power Configurations

Bias Configuration

Description

Highest efficiency bias choice

Coupled inductor bias with

linear regulator start-up

(see Figure 15)

Requires a custom magnetic, which can range in cost similar to an off-the-shelf single coil inductor

Method to start the TPS92561 device (linear) still required, however, can be undersized for start-up condition

only. VCC_UVLOhas not been engineered to support resistive start-up methods.

Lowest efficiency bias choice because output voltage is higher than input

Ensures fast output turn off due to bias draining output capacitor

Aids dimming performance under deep dimming, a stable bias is always available

Lower capacitance value required at VP pin, output capacitor is doubling as VP capacitor

Can be supplemented with charge pump bias circuit to achieve higher efficiency

Better efficiency performance than linear regulator derived from output

Higher VP capacitor value required

Linear regulator from

output

(see Figure 16)

Linear regulator from input

(see Figure 17)

TPS92561

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VCC and VP Connection

A bias voltage with a maximum of 42 V is connected to the VP pin to supply the internal 8.3 V (typical) VCC

linear regulator. This voltage is also used to drive the main FET gate. Use a FET with a gate threshold at least

750 mV below the VCC voltage. The VCC capacitor ground must be placed at the SEN pin. This ensures the

SEN voltage is free of switching spikes that occur at the edge of each switching cycle.

Bias Source

Main

Switch

TPS92561

GATE

OVP

ADJ

SRC

VCC

SEN

C_VCC

LED±

GND

R_SENSE

Figure 11. TPS92561 Bias, SRC, and C_VCCConnection

Output Current Control (ADJ, SEN)

The TPS92561 power stage design follows two rules:

1. Output current is determined by the ADJ reference voltage, the sense resistor selected, and the converter

operating points, V_INand V_LED

2. Output frequency is determined by the inductance value and the SEN pin hysteresis V_SEN. For off-line

applications, the effective hysteresis must be increased using an R-C filter on the SEN pin.

Because the TPS92561 device does not have leading edge blanking, the SEN pin filter must be used to obtain

consistent operation. The SEN pin filter is typically set using an R-C with a corner frequency close to the desired

switching frequency. Leading edge blanking was not implemented to allow high-frequency operation in other non-

off-line applications.

At start up (V_ADJ< 90 mV) a small current is supplied to the V_ADJdivider to ensure a reference is available to

begin converter switching. When the ADJ voltage is above 90 mV, the current source is shut off.

Setting the Output Current

Using the desired ADJ reference voltage, the input current can be calculated based on:

V_ADJ

I_in

R _SENSE

where V_ADJcan be DC, rectified AC derived, or other source.

(1)

If V_ADJis derived from a voltage divider from the input rectified AC, we can solve for the R9 resistor divider value

based on, for example, a V_ADJvoltage of 150 mV, an R17 value of 374 Ω, and the average value of the sine

wave:

VIN

u 0.9 u R17

ꢀ

ꢁ

ꢂ R17

RMS

V_ADJ

(2)

TPS92561

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ZHCSC14B –DECEMBER 2013–REVISED JANUARY 2014

TPS92561

Rectified

GATE

OVP

ADJ

SRC

VCC

SEN

R17

GND

Figure 12. TPS92561 ADJ Connection

To find the R_SENSEvalue, where ƞ is the converter efficiency, assume 0.9.

u V_ADJu K

INꢀRMS

R_SENSE

V_LEDu I_LED

(3)

Selecting an Inductance

The TPS92561 device is hysteretic. Therefore, switching transitions are based on the sensed current in the

inductor. There is no direct control of the switching frequency other then the relationship of the comparator

hysteresis to the inductor ripple. A typical switching frequency of an off-line converter using a rectified AC

injected reference could vary up to 50 kHz over a line cycle. This creates a spread-spectrum effect and helps

reduced conducted EMI.

A typical line injected (using a divided down rectified AC as the reference) hysteretic boost converter reaches the

peak switching frequency when V_LED= 2 × V_{RECTIFIED AC}, or when the duty cycle D = 0.5. We call this operating

point V_IN-FSW-PK. Use this voltage as the typical operating point for the design equations. Solve for the V_IN-FSW-PK

term based on:

V_LED

INꢀFSWꢀPK

1 ꢀ D

INꢀFSWꢀPK

(4)

Select the approximate highest desired frequency (for example, f_SW-PKof 65 kHz could be used), then design the

SEN pin filter with corner frequency equal to f_SW-PK. The filter and the internal hysteresis define the inductor ripple

for a given inductance. This has the effect of increasing the SEN pin hysteresis V_SEN-HYS-2to approximately 140

mV. Select a C12 value between 1000 and 4700 pF. Solve for the resistor R12 in the filter based on:

R₁₂

2S u f_SWꢀPKu C₁₂

(5)

TPS92561

GATE

OVP

ADJ

SRC

VCC

SEN

LED-

GND

R12

R_SENSE

C12

Figure 13. Current Sense

TPS92561

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With the effective hysteresis, calculate the inductor peak-to-peak, Δi_L-PPripple current using:

V_{SENꢀHYSꢀ2}

R_SENSE

'i_LꢀPP

(6)

To find the converter inductance, L, substitute into:

u D u

INꢀFSWꢀPK

'i_LꢀPP

(7)

To further aid in the converter design, see the TPS92561 design tool, TI literature number SLUC517.

Important Design Consideration: Diode in Parallel With Sense Resistance

Figure 13 shows a diode in use in parallel with the R_SENSEresistor. The diode clamps the SEN pin voltage when

the boost converter is first powered up. Because a boost converter utilizes a diode connected to the output, the

output capacitor is charged immediately when power is applied.

CAUTION

The current charging the output capacitor when V_INis applied flows through the sense

resistors, and if it is not clamped by the diode, can exceed the TPS92561 SEN pin

rating, which may damage the device.

Gate Driver Operation

An additional aid to converter operation and radiated EMI is to slow the main FET switching speed. This can be

accomplished by adding a resistor in series with the FET gate. A fast turn off diode across the resistor could also

be implemented to improve efficiency. For off-line designs, use a gate resistance value ≥ 75 Ω.

As in all power converters grounding and layout are key considerations. Give careful attention to the layout of the

sense resistors, GND pin, VCC, and SRC connections, as well as the FET Gate and Source connections. All

should follow short and low-inductance paths. For examples, see the TPS92561 EVM User's Guide, SLUUAU9.

Overcurrent Protection

The TPS92561 device inherently limits the main switch current, but cannot implement output short circuit

protection because of the converter (boost) topology. To implement LED short-circuit protection in a boost

converter requires a blocking switch or other means to open the path to the output, which adds significant cost

and complexity to the solution and is not commonly used. An input fuse should be used as output overcurrent

protection.

Overvoltage Protection (OVP)

Overvoltage protection is implemented using a resistor voltage divider to the output. Note that the output voltage

is high (> 200 V) so the resistor divider should contain a high (> 1 MΩ) value. Also use a small cap on OVP.

First pick a value for R18, for example 1.6 MΩ and select the desired overvoltage protection voltage V_OVP. Using

the V_OVP-UPTHvalue (1.19 V, typical) the trip point can then be computed using:

R18 u V_OVPꢀUPTH

V_OVPꢀ V_OVPꢀUPTH

R19

(8)

TPS92561

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ZHCSC14B –DECEMBER 2013–REVISED JANUARY 2014

LED+

TPS92561

R18

GATE

OVP

ADJ

SRC

VCC

SEN

R19

0.1 µF

GND

Figure 14. Overvoltage Protection Circuit

When the OVP trip point is reached the converter shuts off until the OVP voltage drops below the level controlled

by the OVP hysteresis, V_OVP-HYS(44 mV, typical). After OVP is reached, switching begins again when V_LEDfalls

to the restart voltage (one V_OVP-HYSterm ignored):

OVPꢀHYS

V_{OVP_RESTART} V_OVP

ꢀ

R18

R19

(9)

Output Bulk Capacitor

The required output bulk capacitor, C_BULK, stores energy during the input voltage zero crossing interval and limits

the twice the line frequency ripple component flowing through the LEDs. The following equation describes the

calculation of the output capacitor value:

C_BULK

4S u f_Lu R_LEDu V_LEDu I_LED(ripple)

where

•

R_LEDis the dynamic resistance of LED string

I_LED(ripple)is the peak-to-peak LED ripple current

f_Lis line frequency

(10)

R_LEDis found by computing the difference in LED forward voltage divided by the difference in LED current for a

given LED using the manufacturer’s V_Fversus I_Fcurve. For more details, see Application Note 1656.

In typical applications, the solution size becomes a limiting factor and dictates the maximum dimensions of the

bulk capacitor. When selecting an electrolytic capacitor, manufacturer recommended de-rating factors should be

applied based on the worst case capacitor ripple current, output voltage, and operating temperature to achieve

the desired operating lifetime.

Phase Dimming

After following the design procedure for a TPS92561 non-dimming design, the creation of a TRIAC dimmer

compatible design only requires the addition of an input snubber (R-C), as shown in Figure 17. Ideally, a

capacitor value of 3× the input filter capacitance would be implemented to ensure sufficient damping of the input

filter resonance. However, capacitance values as low as 2× tested successfully. If the input voltage is used to

provide the converter reference, dimming occurs naturally with the decreasing ADJ set point and decreased

power transfer due to shorter line-cycle conduction times.

TPS92561

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Application Circuits

Target LED lamp applications include:

•

A-15, A-19, A-21, A-23

R-20, R-25, R-27, R-30, R-40

PS-25, PS-30, PS-35

BR-30, BR-38, BR-40

PAR-20, PAR-30, PAR-30L

MR-16, GU-10

G-25, G-30, G-40

Applications also include: fluorescent replacement, recessed (canister) type lighting replacement, and new LED-

specific lighting form factors.

Coupled Inductor Bias

LED+

Linear

EMI

Filter

LED+

TPS92561

Pbias

GATE

OVP

ADJ

SRC

VCC

SEN

LED±

GND

(opt) TRIAC

Dimmer

Figure 15. Offline Boost Configuration With Auxiliary Winding and Linear Regulator for Start-Up

LED+

EMI

Filter

LED+

TPS92561

GATE

OVP

ADJ

SRC

VCC

SEN

GND

(opt) TRIAC

Dimmer

Linear Regulator

Figure 16. Offline Boost With Linear Regulator from Input Rectified AC

TPS92561

www.ti.com.cn

ZHCSC14B –DECEMBER 2013–REVISED JANUARY 2014

LED+

Linear Regulator

LED+

Peak Power Limit

TPS92561

R_THD

GATE

SRC

VCC

SEN

OVP

ADJ

GND

(opt) TRIAC

Dimmer

Input R-C Damper

Figure 17. Offline Boost With Linear Regulator from V_LED+,THD Improvement Resistor, Peak Power Limit

Circuit, EMI Filter, and Snubber for TRIAC Dimming

LED+

VCC

LED+

TPS92561

GATE

SRC

VCC

SEN

OVP

ADJ

VCC

ADJ

GND

ADJ

Electronic

Transformer

Figure 18. Closed-Loop Regulated E-Transformer Compatible, Non-TRIAC Dimmable Boost for AR111

and MR16 Lamps

TPS92561

ZHCSC14B –DECEMBER 2013–REVISED JANUARY 2014

www.ti.com.cn

修订历史记录

Changes from Original (December 2013) to Revision A

Page

•

Updated figure to add AR111 lamps for closed-loop regulated e-transformer compatible, non-TRIAC dimmable

boost for AR111 and MR16 lamps ..................................................................................................................................... 15

Changes from Revision A (December 2013) to Revision B

Page

•

已删除产品预览条 ................................................................................................................................................................. 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS92561DGN

ACTIVE

HVSSOP

DGN

RoHS & Green

NIPDAUAG

Level-2-260C-1 YEAR

-40 to 125

92561

TPS92561DGNR

2500 RoHS & Green

NIPDAUAG

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS92561DGNR

HVSSOP DGN

2500

330.0

12.4

5.3

3.4

1.4

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

*All dimensions are nominal

Device

Package Type Package Drawing Pins

HVSSOP DGN

SPQ

Length (mm) Width (mm) Height (mm)

366.0 364.0 50.0

TPS92561DGNR

2500

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

TUBE

*All dimensions are nominal

Device

Package Name Package Type

DGN HVSSOP

Pins

SPQ

L (mm)

W (mm)

T (µm)

B (mm)

TPS92561DGN

330

6.55

500

2.88

Pack Materials-Page 3

GENERIC PACKAGE VIEW

DGN 8

3 x 3, 0.65 mm pitch

PowerPAD VSSOP - 1.1 mm max height

SMALL OUTLINE PACKAGE

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4225482/A

www.ti.com

PACKAGE OUTLINE

DGN0008G

PowerPAD^TMVSSOP - 1.1 mm max height

SMALL OUTLINE PACKAGE

5.05

4.75

TYP

0.1 C

SEATING

PLANE

PIN 1 INDEX AREA

6X 0.65

3.1

2.9

1.95

NOTE 3

0.38

0.25

3.1

2.9

0.13

C A B

NOTE 4

0.23

0.13

SEE DETAIL A

EXPOSED THERMAL PAD

0.25

GAGE PLANE

2.15

1.95

1.1 MAX

0.15

0.05

0.7

0.4

0 -8

DETAIL A

TYPICAL

1.846

1.646

4225480/B 12/2022

PowerPAD is a trademark of Texas Instruments.

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-187.

www.ti.com

EXAMPLE BOARD LAYOUT

DGN0008G

PowerPAD^TMVSSOP - 1.1 mm max height

SMALL OUTLINE PACKAGE

(2)

NOTE 9

METAL COVERED

BY SOLDER MASK

(1.57)

SOLDER MASK

DEFINED PAD

SYMM

8X (1.4)

(R0.05) TYP

8X (0.45)

(3)

NOTE 9

SYMM

(1.89)

(1.22)

6X (0.65)

(

0.2) TYP

VIA

SEE DETAILS

(0.55)

(4.4)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 15X

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

OPENING

METAL

EXPOSED METAL

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

15.000

(PREFERRED)

SOLDER MASK DETAILS

4225480/B 12/2022

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

9. Size of metal pad may vary due to creepage requirement.

www.ti.com

EXAMPLE STENCIL DESIGN

DGN0008G

PowerPAD^TMVSSOP - 1.1 mm max height

SMALL OUTLINE PACKAGE

(1.57)

BASED ON

0.125 THICK

STENCIL

SYMM

(R0.05) TYP

8X (1.4)

8X (0.45)

(1.89)

SYMM

BASED ON

0.125 THICK

STENCIL

6X (0.65)

METAL COVERED

BY SOLDER MASK

SEE TABLE FOR

DIFFERENT OPENINGS

FOR OTHER STENCIL

THICKNESSES

(4.4)

SOLDER PASTE EXAMPLE

EXPOSED PAD 9:

100% PRINTED SOLDER COVERAGE BY AREA

SCALE: 15X

STENCIL

THICKNESS

SOLDER STENCIL

OPENING

0.1

1.76 X 2.11

1.57 X 1.89 (SHOWN)

1.43 X 1.73

0.125

0.15

0.175

1.33 X 1.60

4225480/B 12/2022

NOTES: (continued)

10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

11. Board assembly site may have different recommendations for stencil design.

www.ti.com

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TPS92561 [TI]

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