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TPS92601-Q1, TPS92602-Q1, TPS92601A-Q1, TPS92602A-Q1

SLUSBP5D –MARCH 2014–REVISED JANUARY 2015

TPS9260x-Q1 Single- and Dual-Channel Automotive Headlight LED Driver

1 Features

3 Description

The TPS9260x-Q1 family of devices is a single-

channel and dual-channel high-side-current LED

driver. With full protection and diagnostics, this family

of devices is dedicated for and ideally suited to

automotive front lighting. The base of each

independent driver is a peak-current-mode boost

controller. Each controller has two independent

feedback loops, a current-feedback loop with a high-

side current-sensing shunt and a voltage-feedback

loop with an external resistor-divider network. The

controller delivers a constant output voltage or a

constant output current. The connected load

determines whether the device regulates a constant

output current (if the circuit reaches the current set-

point earlier than voltage set-point) or a constant

output voltage (if the circuit reaches the voltage set-

point is reached first, for example, in an open-load

condition).

1

•

Qualified for Automotive Applications

•

AEC-Q100 Qualified With the Following Results:

–

Device Temperature Grade 1: –40°C to 125°C

Ambient Operating Temperature

–

Device HBM ESD Classification Level 2

Device CDM ESD Classification Level C4B

•

Input Voltage: 4 V–40 V (45 V Abs. Max.)

Output Voltage: 4 V–75 V (80 V Abs. Max.)

Fixed-Frequency Current-Mode Controller With

Integrated Slope Compensation

•

Two Regulation Loops, Constant-Current Output

and Constant-Voltage Output of Each Channel

High-Side Current Sense:

–

150-mV or 300-mV Sense Voltage (EEPROM

Option)

Each controller supports all typical topologies such as

boost, boost-to-battery, SEPIC, or flyback.

–

±6-mV Offset (Achieving Approx. 4% or 2%

LED Current Accuracy)

Uses of the high-side PMOS FET driver are for PWM

dimming of the LED string and for cutoff in case of an

external short circuit to GND to protect the circuit.

•

Output Voltage Sense, Internal Voltage

Reference: 2.2 V ±5%

Integrated Low-Side NMOS-FET Driver: Peak

Gate-Drive Current Typ. 0.7 A

Device Information(1)

•

Frequency Synchronization

Both PWM Dimming and Analog Dimming

Diagnostic:

SENSE-VOLTAGE

PART NUMBER

CHANNELS

RANGE

15 mV–150 mV

30 mV–300 mV

15 mV–150 mV

30 mV–300 mV

TPS92601-Q1

1

2

TPS92601A-Q1(2)

TPS92602-Q1

–

High-Side Current (LED Current) Available as

Analog Output

TPS92602A-Q1(2)

–

Open-LED and Short-to-GND Detection

Shorted Output Protection

(1) For all available packages, see the orderable addendum at

the end of the datasheet.

•

Internal Under- and Overvoltage Lockout

(2) Device is available as a preview only.

2 Applications

•

Automotive Headlight LED Driver

High-Brightness LED Applications

4 Typical Schematic

VBAT

Part of

TPS92602-Q1

RT

DIAG1

GDRV1

ISNS1

DIAG2

GDRV2

ISNS2

COMP1

COMP2

CHANNEL

2

1

ISP1

ISN1

ISP2

ISN2

ICTRL1

PWIN1

ICTRL2

PWIN2

VOUT1

PWMO1

OVFB1

PGND1

VOUT2

PWMO2

OVFB2

PGND2

VCC

Part of

TPS92602-Q1

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION

DATA.

TPS92601-Q1, TPS92602-Q1, TPS92601A-Q1, TPS92602A-Q1

SLUSBP5D –MARCH 2014–REVISED JANUARY 2015

www.ti.com

Table of Contents

8.3 Feature Description................................................. 11

8.4 Device Functional Modes........................................ 16

Application and Implementation ........................ 18

9.1 Application Information............................................ 18

9.2 Typical Applications ................................................ 18

1

2

3

4

5

6

7

Features.................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Typical Schematic.................................................. 1

Revision History..................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

7.1 Absolute Maximum Ratings ...................................... 4

7.2 ESD Ratings.............................................................. 4

7.3 Recommended Operating Conditions....................... 5

7.4 Thermal Information.................................................. 5

7.5 Electrical Characteristics........................................... 5

7.6 Typical Characteristics.............................................. 8

Detailed Description ............................................ 10

8.1 Overview ................................................................. 10

8.2 Functional Block Diagram ....................................... 10

9

10 Power Supply Recommendations ..................... 34

11 Layout................................................................... 34

11.1 Layout Guidelines ................................................. 34

11.2 Layout Example .................................................... 35

12 Device and Documentation Support ................. 36

12.1 Related Links ........................................................ 36

12.2 Trademarks........................................................... 36

12.3 Electrostatic Discharge Caution............................ 36

12.4 Glossary................................................................ 36

8

13 Mechanical, Packaging, and Orderable

Information ........................................................... 36

5 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision C (September 2014) to Revision D

Page

•

Changed the device status for the TPS92601-Q1 from Product Preview to Production Data .............................................. 1

Added single-channel in addition to the dual-channel text throughout the data sheet .......................................................... 1

Changed the Handling Ratings table to ESD Ratings and moved the storage temperature to the Absolute Maximum

Ratings table .......................................................................................................................................................................... 4

•

Updated the units of the Q(GS) equation (Equation 37) ...................................................................................................... 24

Updated the units of the Q(GS) equation (Equation 71) and the resulting values............................................................... 31

Updated the r_DS(on)values as a result of Equation 72........................................................................................................... 31

Changes from Revision B (August 2014) to Revision C

Page

•

Updated the package type for the TPS92601-Q1 and TPS92601A-Q1 ................................................................................ 3

Changes from Revision A (April 2014) to Revision B

Page

•

Added a column to the Device Comparison table ................................................................................................................. 1

Changed Device Information table ........................................................................................................................................ 1

Changed pinout diagram and combined Pin Function tables................................................................................................. 3

Changes from Original (March 2014) to Revision A

Page

•

Added all new content following the first page ....................................................................................................................... 3

2

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Product Folder Links: TPS92601-Q1 TPS92602-Q1 TPS92601A-Q1 TPS92602A-Q1

TPS92601-Q1, TPS92602-Q1, TPS92601A-Q1, TPS92602A-Q1

www.ti.com

SLUSBP5D –MARCH 2014–REVISED JANUARY 2015

6 Pin Configuration and Functions

PWP Package

28-Pin HTSSOP With PowerPAD™

TPS92602-Q1 and TPS92602A-Q1 Top View

20-Pin HTSSOP Package With PowerPAD™

TPS92601-Q1 and TPS92601A-Q1 Top View

1

2

20

19

1

2

28

27

PWMO1

VOUT1

PWMO1

VOUT1

ICTRL1

COMP1

ICTRL1

COMP1

3

4

5

6

18

17

16

15

3

4

5

6

26

25

24

23

OVFB1

RT

OVFB1

RT

ISN1

ISP1

Thermal

Pad

DIAG1

GND

PGND1

ISNS1

DIAG1

GND

PGND1

ISNS1

Thermal

Pad

7

14

13

12

11

7

22

21

20

19

18

17

16

15

PWMIN1

VIN

GDRV1

VCC

NC

PWMIN1

VIN

GDRV1

VCC

8

9

NC

PWMIN2

OVFB2

ICTRL2

COMP2

DIAG2

GDRV2

ISNS2

PGND2

ISP2

10

11

12

13

14

NC

NC – No internal connection

ISN2

PWMO2

VOUT2

NC – No internal connection

Pin Functions

TPS92601-Q1

TPS92601A-Q1 TPS92602A-Q1

TPS92602-Q1

I/O

DESCRIPTION

NAME

20 PINS

2

28 PINS

2

COMP1

COMP2

DIAG1

DIAG2

GDRV1

GDRV2

GND

O

—

I

Compensation network (channel 1)

—

5

12

5

Compensation network (channel 2)

Diagnostic pin (open, short, LED current) (channel 1)

Diagnostic pin (open, short, LED current) (channel 2)

Gate driver NMOS-FET (channel 1)

—

14

—

6

13

22

20

6

Gate driver NMOS-FET (channel 2)

Ground

ICTRL1

ICTRL2

ISN1

1

LED current-control pin, analog dimming (channel 1)

LED current control pin, analog dimming (channel 2)

Current-sense input – negative (channel 1)

Current-sense input – negative (channel 2)

Overcurrent sense input (channel 1)

—

18

—

15

—

17

—

9

11

26

16

23

19

25

17

I

ISN2

I

ISNS1

ISNS2

ISP1

I

Overcurrent sense input (channel 2)

I

Current-sense input – positive (channel 1)

Current-sense input – positive (channel 2)

ISP2

I

10

11

12

3

NC

—

No internal connection

OVFB1

OVFB2

PGND1

PGND2

PWMIN1

PWMIN2

3

10

24

18

7

I

Voltage-feedback input (channel 1)

Voltage feedback input (channel 2)

Power ground (channel 1)

—

16

—

7

—

I

Power ground (channel 2)

PWM input and channel enable or disable function (channel 1)

PWM input and channel enable or disable function (channel 2)

—

9

I

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3

Product Folder Links: TPS92601-Q1 TPS92602-Q1 TPS92601A-Q1 TPS92602A-Q1

TPS92601-Q1, TPS92602-Q1, TPS92601A-Q1, TPS92602A-Q1

SLUSBP5D –MARCH 2014–REVISED JANUARY 2015

www.ti.com

Pin Functions (continued)

TPS92601-Q1

TPS92601A-Q1 TPS92602A-Q1

TPS92602-Q1

I/O

DESCRIPTION

NAME

20 PINS

28 PINS

PWMO1

PWMO2

RT

20

—

4

28

14

4

O

I

PWM PMOS-FET driver output (channel 1)

PWM PMOS-FET driver output (channel 2)

Oscillator pin and pin for external sync. frequency

Gate-drive supply voltage (external decoupling capacitor)

Supply voltage

VCC

13

8

21

8

O

I

VIN

VOUT1

VOUT2

Thermal pad

19

—

27

15

I

Connect to boost output voltage (channel 1)

Connect to boost output voltage (channel 2)

Solder to achieve appropriate power dissipation. Connect to PGND.

I

—

7 Specifications

7.1 Absolute Maximum Ratings^(1)(2)(3)

over operating free-air temperature (unless otherwise noted)

MIN

–0.3

MAX

40

UNIT

V

Supply voltage

Output voltage

Differential voltage

Grounds

VIN, PWMINx⁽⁴⁾

VOUTx, ISPx, ISNx, PWMOx⁽⁴⁾

(VOUTx – PWMOx)⁽⁴⁾

PGNDx⁽⁴⁾

GDRVx, ISNSx⁽⁴⁾

OVFBx⁽⁴⁾

80

V

8.8

0.3

8.8

80

V

Other pins

VCC

8.8

3.6

220

150

V

ICTRLx, COMPx, RT, DIAGx⁽⁴⁾

V

VCC current

Gate-driver supply

mA

°C

Junction temperature, T_J

Storage temperature, T_stg

–40

–55

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.

(2) The algebraic convention, whereby the most-negative value is a minimum and the most-positive value is a maximum.

(3) All voltages are with respect to ground (GND pin), unless otherwise specified.

(4) ⁽⁾or the TPS9602-Q1 device, x = 1 or 2. For the TPS9601-Q1 device, x is blank.

7.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

Other pins

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per

AEC Q100-011

Corner pins (1, 14, 15, 28 for

TPS92602x-Q1; 1, 10, 11, 20 for

RPS92601x-Q1)

±750

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

4

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SLUSBP5D –MARCH 2014–REVISED JANUARY 2015

7.3 Recommended Operating Conditions

over operating free-air temperature (unless otherwise noted)

MIN

6

MAX

26

40

75

40

7

UNIT

V

VIN (first connection to battery, full functionality)

Supply voltage

VIN (battery voltage during cranking profile, full functionality)

4

V

VIN

26

4

V

Output sense

PWMIN

VOUTx, ISPx, ISNx⁽¹⁾

PWMINx: enable and disable functionality⁽¹⁾

PWMINx: PWM functionality⁽¹⁾

ISNSx, OVFBx⁽¹⁾

V

0

V

0

V

0

8

V

Other pins

VCC

3

8

V

ICTRLx, RT⁽¹⁾

0

3.3

100

125

150

V

Gate-driver supply current, VCC⁽²⁾

Ambient temperature range

Junction temperature range

mA

°C

T_A

T_J

–40

(1) For the TPS9602-Q1 device, x = 1 or 2. For the TPS9601-Q1 device, x is blank.

(2) Note available current for low-side gate drivers to drive the external BOOST FETs

7.4 Thermal Information

TPS92601-Q1

TPS92602-Q1

THERMAL METRIC⁽¹⁾

PWP (HTSSOP)

UNIT

20 PINS

37

28 PINS

37.2

19.3

16.7

0.8

R_θJA

Junction-to-ambient thermal resistance

R_θJC(top)Junction-to-case (top) thermal resistance

23.4

17.7

0.9

R_θJB

ψ_JT

Junction-to-board thermal resistance

°C/W

Junction-to-top characterization parameter

Junction-to-board characterization parameter

ψ_JB

17.5

0.9

16.5

2.6

R_θJC(bot)Junction-to-case (bottom) thermal resistance

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

T_J= –40°C to 150°C, V_VDD= 12 VDC, over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INPUT SUPPLY

V_{(VIN_norm)}

Normal mode after initial start-up, VIN rising

Normal mode after initial start-up, VIN falling

6

4

40

Input voltage range

V

V_{(VIN_crank)}

PWM1 = PWM2 = High, VIN falling,f_(PMWOx)

V_(VOUTx)– 2 V

<

V_(UVLO)

V_(UVsh)

Undervoltage lockout

Undervoltage shutdown

Overvoltage shutdown

3.72

2.8

4

V

PWM1 = PWM2 = High, VIN falling, quiescent

current < 2 µA

3.5

PWM1 = PWM2 = High, VIN falling, V_(PMWOx)

V_(VOUTx), V_(GRDVx)= 0

=

V_(OVSH)

40

40.7

SUPPLY CURRENT

VIN = 12 V, PWMIN1 and PWMIN2 = low for >

t_{(CH_OFF)}

T_A= 25°C

,

2

3

I_(stby)

Shutdown current

µA

VIN = 12 V, PWMIN1 and PWMIN2 = low for >

t_{(CH_OFF)}

,

T_A= 125°C

t_{(CH_OFF)}

t_{(CH_ON)}

I_nom

Channel OFF timer

PWMINx = low

9.5

14

8

18

1

ms

mA

Channel ON timer

PWMINx = high, V_CC= 5.5 V

VIN = 12 V, PWMINx = high

Normal-mode current in OVP loop

12

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5

Product Folder Links: TPS92601-Q1 TPS92602-Q1 TPS92601A-Q1 TPS92602A-Q1

TPS92601-Q1, TPS92602-Q1, TPS92601A-Q1, TPS92602A-Q1

SLUSBP5D –MARCH 2014–REVISED JANUARY 2015

www.ti.com

Electrical Characteristics (continued)

T_J= –40°C to 150°C, V_VDD= 12 VDC, over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

6.6

10

MAX

UNIT

GATE DRIVER SUPPLY VCC

V_(VCC)

Output voltage

VIN > 6 V

5.5

7.4

400

20

V

V_{(VCC_dr)}

C_(VCC)

Drop-out voltage

4 V < VIN < 8 V, I_(VCC)< 50 mA

VCC shorted to ground

mV

µF

VCC buffer capacitance

Output current (only for internal usage)

Current limit

2.2

I_(VCC)

80

mA

I_{(VCC_LIM)}

150

220

GATE DRIVER – LOW-SIDE BOOST NMOS-FET

Gate-source voltage to switch on boost NMOS

FET. Depends on VCC

V_GS(NMOS)

NMOS gate-source voltage

5.5

6.6

7.4

V

D_(MAX)

Maximum duty cycle

93.8%

22

t_r(NMOS)

Gate driver rising

V_CC= 6.6 V, no load

ns

Ω

t_f(NMOS)

Gate driver falling

V_CC= 6 V, no load

8.5

r_{DS(on)(Source,Nmos)}

r_{DS(on)(Sink,Nmos)}

Gate driver resistance, sourcing

Gate driver resistance, sinking

V_CC= 6.6 V, 100-mA load

2.5

4

2.5

Ω

CURRENT LIMIT – NMOS FET

Voltage limit threshold across sense-

current resistor

V_(ISNSx)

83

40

100

115

65

mV

t_(ISNSx)

I_(ISNSx)

A_(PS)

Leading edge blanking

Current on ISNSx

200

50

4

ns

µA

VC current-mode gain (ΔV_vc/ ΔV_sns

)

V/V

GATE DRIVER – HIGH-SIDE PWM PMOS-FET

I_{(PWMOx_Source)}

I_{(PWMOx_Sink)}

V_(PWMOx)

Peak source current

Peak sink current

V_(OUT)– V_(PWMOx)= 6.5 V, V_(OUT)= 40 V

V_(OUT)– V_(PWMOx)= 0 V, V_(OUT)= 40 V

150

10

mA

V

Output voltage

4

6

75

8

V_GS(PMOS)

PMOS gate-source voltage

PWMx = high, V_(OUT)= 40 V

6.9

6.6

V

Sufficient gate-source voltage to switch on the

NMOS FET; this depends on VCC.

V_GS(NMOS)

NMOS gate-source voltage

5.5

7.4

V

t_r(PMOS)

HS gate driver rising

HS gate driver falling

No load

1

3

µs

t_f(PMOS)

PWM DIMMING

f_(PWMIN)

Dimming frequency

Logic low

See PWM dimming section

0.2

2

kHz

V

V_(thLOW)

Switch off PMOS dimming FET (low below)

Switch on PMOS dimming FET (high above)

0.8

V_(thHIGH)

Logic high

2

V

R_{(PWMIN_pd)}

Pulldown resistance at PWMINx pin

PWMIN to LED turnoff time

90

120

80

150

kΩ

ns

PWMIN to LED turnon time

60

INTERNAL PLL OSCILLATOR

f_(OSC)

Oscillator range

100

–20%

100

600

kHz

RT: 20-kΩ resistor. See Equation 2 and Figure 3

for f_(OSC)vs RT

Δf_(OSC)

Oscillator accuracy

20%

f_(EXT)

Ext. synchronization

600

70

kHz

ns

V

t_(CLKpw)

V_(RTthLO)

V_(RTthHI)

t_(RTdelay)

t_(PLLlock)

Minimum clock input pulse duration

RT low voltage

0.8

RT high voltage

2

V

RT rising edge to GDRV1 rising edge

PLL lock-in time

35

ns

µs

200

6

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SLUSBP5D –MARCH 2014–REVISED JANUARY 2015

Electrical Characteristics (continued)

T_J= –40°C to 150°C, V_VDD= 12 VDC, over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

HIGH-SIDE CURRENT-SENSE ERROR AMPLIFIER VFBx < 2.1 V

V_(SPSN,Com)

Common-mode voltage ISPx, ISNx

Full-scale sense voltage ISPx – ISNx

4

74

V

4 V < V_{(SPSN_Com)}< 75 V, VFBx < 2.1 V,

TPS92601-Q1, TPS92602-Q1

150

300

mV

V_{(SPSN_Diff)}

4 V < V_{(SPSN_Com)}< 75 V, VFBx < 2.1 V,

TPS92601A-Q1, TPS92602A-Q1

mV

V_{(SPSN_AC)}

I_{(BIAS_SPSN)}

Sense-voltage accuracy

Common-mode voltage 4 V to 75 V

–6

6

mV

µA

Input bias current ISPx, ISNx

4 V < V_{(SPSN_Com)}< 75 V, V_{(SPSN_Diff)}= 150 mV

40

TPS92601-1, TPS92602-Q1, 4 V < V_{(SPSN_Com)}

75 V, V_{(SPSN_Diff)}= 150 mV

<

100

135

200

µA

I_{(offset_SPSN)}

Input offset current ISPx, ISNx

TPS92601A-Q1, TPS92602A-Q1, 4 V <

V_{(SPSN_Com)}< 75 V, V_{(SPSN_Diff)}= 300 mV

175

g_MC

Forward transconductance

HS current-sense gain

1

5

mS

V/V

TPS92601-Q1, TPS92602-Q1

TPS92601A-Q1, TPS92602A-Q1

A_(HSCS)

2.5

CURRENT CONTROL ICTRL – ANALOG DIMMING FOR ALL PARAMETERS: VFBx < 2.1 V

I_{(DIM_LIN)}

Linear analog dimming range

10%

9.7

100%

10.3

10.5

5.15

5.25

1.5

TPS92601-Q1, TPS92602-Q1, T_A= 25ºC⁽¹⁾

TPS92601-Q1, TPS92602-Q1, T_A= 125ºC⁽¹⁾

TPS92601A-Q1, TPS92602A-Q1, T_A= 25ºC⁽¹⁾

10

5

9.5

K_(DIMfactor)

Dimming factor, V_(ICTRL)/ V_(SNSPx)

4.85

4.75

0

TPS92601A-Q1, TPS92602A-Q1, T_A= 125ºC⁽¹⁾

5

V_(ICTRLx)

Adjustable voltage range

See Figure 12

V

R_(ICTRLpd)

Pulldown resistance at ICTRLx pin

0.75

1

1.2

MΩ

ERROR AMPLIFIER - REFERENCE VOLTAGE

V_(VFB)

ΔV_(VFB)

I_(BIAS)

g_(Mv)

Voltage feedback

2.2

V

Voltage FB accuracy

Input bias current

–5%

5%

VFB = 2.2 V

500

nA

Forward transconductance

1

mS

INTERNAL SOFT-START

t_(softstart)

Soft-start time, internal soft-start

COMP 0 V to 1.5 V

3.5

ms

DIAGNOSIS – DIAGx PIN

TPS92601-Q1, TPS92602-Q1

10

20

mV

V

V_(OPLED)

V_{(DIAG_OP)}

V_(SHLED)

Open LED failure

TPS92601A-Q1, TPS92602A-Q1

DIAGx pin pulled low, I_(DIAGx)= 100 µA

TPS92601-Q1, TPS92602-Q1

Low-level voltage, DIAGx pin

Shorted LED failure

0.15

225

450

mV

V

TPS92601A-Q1, TPS92602A-Q1

DIAGx pin pulled high, I_(DIAGx)= 100 µA

V_{(DIAG_SH)}

V_(ILED1)

High-level voltage, DIAGx pin

3

0.2

–12

3.47

2.85

12

Range for tracking LED current on DIAGx

Voltage range on DIAGx pin (VIN > 6 V)

V

V_(ILED2)

V_{(DIAG_AC)}

Offset of DIAG output buffer

At input of DIAG buffer

mV

Within linear analog dimming range and DIAG

tracking range. Exclusive offset V_{(DIAG_AC)}

TPS92601-Q1, TPS92602-Q1

,

12.5

6.25

K_{(DIAG_factor)}

Factor V_(DIAG)/ V_(SPSN)

Within linear analog dimming range and DIAG

tracking range. Exclusive offset V_{(DIAG_AC)}

,

TPS92601A-Q1, TPS92602A-Q1

COMPENSATION NETWORK – COMPx PIN

V_(COMPx)

Compensation-network output-pin voltage

0

3.3

V

THERMAL SHUTDOWN

T_(SD)

Thermal shutdown

Hysteresis

165

20

°C

T_(HYS)

(1) Within linear analog dimming range (10%–100%). Exclusive offset V_{(SPSN_AC)}= 6 mV

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7.6 Typical Characteristics

Load is eight LEDs per channel at 500 mA, –40ºC ≤ T_A≤ 125ºC, –40ºC ≤ T_J≤ 150ºC, C_(COMP)= 0.22 µF, unless otherwise

noted.

100

98

96

94

92

90

88

86

510

508

506

504

502

500

498

496

494

492

490

CH1

CH2

8

10

12

14

16

18

20

8

10

12

14

16

18

20

V_(VIN)Voltage (V)

C001

C002

Figure 1. Boost Efficiency vs Input Voltage

Figure 2. Line Regulation

600

500

400

300

200

100

0

700

600

500

400

300

200

100

0

CH1

CH2

0

20

40

60

80

100

0

20

40

60

80

100

120

140

Dimming Duty Cycle (%)

R_(RT)Resistance (k)

C004

C003

f_(PWM)= 200 Hz

Figure 4. I_(OUT)vs PWM Dimming Duty Cycle

Figure 3. Switching Frequency vs R_(RT)Resistance

3000

2500

2000

1500

1000

500

180

160

140

120

100

80

60

40

20

0

50

100

150

200

250

0

500

1000

1500

2000

2500

ISP t ISN (mV)

V_(ICTRLx)(mV)

C006

C005

Figure 6. V_(DIAGx)vs V_{(ISPx – ISNx)}

Figure 5. Analog Dimming: Differential Sense Voltage,

V_{(ISPx – ISNx)}vs V_(ICTRLx)

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Typical Characteristics (continued)

Load is eight LEDs per channel at 500 mA, –40ºC ≤ T_A≤ 125ºC, –40ºC ≤ T_J≤ 150ºC, C_(COMP)= 0.22 µF, unless otherwise

noted.

605

603

601

599

597

595

593

591

589

587

585

503

502

501

500

499

498

497

496

495

CH1

CH2

5

20 35 50 65 80 95 110 125

5

20 35 50 65 80 95 110 125

±40 ±25 ±10

Ambient Temperature (C)

C007

C008

R_(RT)= 20 kΩ

Figure 7. Switching Frequency vs Ambient Temperature

Figure 8. V_{(ISPx – ISNx)}vs Ambient Temperature

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8 Detailed Description

8.1 Overview

The TPS92602-Q1 device is a dual-channel LED driver. The base of each independent driver is a peak-current-

mode boost controller. The two boost controllers operate 180° out-of-phase in order to reduce ripple currents and

radiation.

Each controller is independently configurable to regulate the output current (the typical case for driving LEDs) or

to regulate the output voltage. Depending on the chosen configuration for each channel, one loop is active while

the other loop only acts in case of a failure condition. In a constant-current application, the inactive voltage loop

sets the maximum output-voltage limit (and hence becomes active in case of output overvoltage due to an open

LED). In constant-voltage applications, the inactive current loop sets the maximum output current limit (and

hence becomes active in case of output overcurrent because of an LED short to ground).

The TPS92601-Q1 device is a single-channel version of the TPS92602-Q1 device. Both devices have the same

functions.

8.2 Functional Block Diagram

V

(BAT)

TPS9260x-Q1

L

C

D

VIN

VCC

LED

VCC

LDO

Int. FET

LDO

Int. FET

VDD

C

VCC

Voltage

Monitor

T

J

ISP

Shutdown

+

UVLO

R_{LED_SNS}

Shutdown

Logic

±

ISN

VOUT

DIAG

RT

PWMO

GDRV

&

MP

CLRZ

D

QZ

Over-

current

Detect

1

Osc

or

PLL

Q

CLK

R

OSC

Slope

Compensation

ISNS

+

C

P

±

+

±

R

SNS

+

100 mV

COMP

R

OVFB_B

OVFB_A

OVFB

C

Z

R

Z

±

2.2 V

+

R

PWMIN

ICTRL

±

+

0.75 V

Soft-

start

PGND

GND

Figure 9. Block Diagram, TPS9260x-Q1 in Boost-To-Battery Configuration

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Functional Block Diagram (continued)

VBAT

VCC

BOOST-TO-BATTERY

SEPIC

FLYBACK

BOOST

BUCK-TO-BATTERY

Note: The SEPIC and flyback topologies require two extra diodes per channel for start-up, because the minimum common-mode voltage of the current-regulation amplifier is 4 V.

Figure 10. Supported Topologies per Channel

8.3 Feature Description

8.3.1 Fixed-Frequency PWM Control

Each boost controller uses an adjustable fixed-frequency peak-current-mode control. In a constant-current

application, the device senses the output current across an external shunt resistor at the ISPx and ISNx pins,

amplifies and level-shifts it to ground-reference, and compares it to the voltage applied on the ICTRLx pin by the

primary error amplifier, which drives the COMPx pin. In a constant-voltage application, the device compares the

output voltage through external resistors on the OVFBx pin to an internal 2.2-V voltage reference by a secondary

error amplifier, which drives the COMPx pin. Depending on the chosen application, only one of the error

amplifiers is active.

An internal oscillator initiates the turnon of the external boost-power NMOS switch. The device compares the

error-amplifier output to the switch current sensed on the ISNSx pin. When the power-switch current reaches the

level set by the COMPx voltage, the power NMOS switch turns off. The COMPx pin voltage increases and

decreases as the output current increases and decreases. The device implements a current limit by clamping the

COMPx pin voltage to a maximum level.

8.3.2 Slope-Compensation Output Current

Each controller adds a compensating ramp to the switch-current signal. This slope compensation prevents sub-

harmonic oscillations. The available peak inductor current remains constant over the full duty-cycle range.

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Feature Description (continued)

8.3.3 Boost-Current Limit

Each controller achieves peak-current-mode control using a comparator that monitors the current through the

external boost FET at the ISNSx pin by comparing it with the voltage on the COMPx pin. A redundant current-

limit comparator, which compares the voltage on the ISNSx pin with a typical 100-mV reference voltage, limits

the current through the external boost FET. If the voltage on the ISNSx pin exceeds this typical 100-mV

threshold, the on-cycle of the respective boost controller immediately terminates. The current-limit comparator

has a lead-edge blanking time to avoid any unwanted triggering of the current limit during switch-on of the

external boost FET. One can set the current-limit level with an external resistor, as calculated with the following

equation.

100 mV

=

I_(Lim)

R_(LIM)

(1)

8.3.4 Oscillator and PLL

The switching frequency is adjustable over a range from 100 kHz to 600 kHz by placing a resistor on the RT pin.

The RT pin voltage is typically 0.5 V and must have a resistor to ground to set the switching frequency. To

determine the timing resistance for a given switching frequency, use Equation 2 or the curve in Figure 3. To

reduce the solution size one would typically set the switching frequency as high as possible, but give

consideration to tradeoffs of the supply efficiency, maximum input voltage, and minimum controllable on-time.

12.5 MHz ´1 kW

R_RT[kW] =

f_(OSC)[MHz]

(2)

One can also use the RT pin to synchronize the controllers to an external system clock, over a range from 100

kHz to 600 kHz. Apply a square wave to the RT pin to use this synchronization feature. The square wave must

transition lower than 0.8 V and higher than 2 V on the RT pin and have an on-time greater than 70 ns and an off

time greater than 70 ns. The synchronization frequency range is 100 kHz to 600 kHz. The rising edge of GDRV1

is synchronized to the falling edge of the RT pin signal.

Leaving the RT pin open or shorted to ground with no external system clock signal is present disables both boost

controllers, and both PWM dimming FETs switch off. In order to recover from this global failure state, (for

example, after the failure condition on the RT pin has been removed) there must be one global disable-and-

enable cycle (active shutdown by pulling both PWMINx pins low for t > t_{(CH_OFF)}, and setting one or both PWMINx

pins high for t > t_{(CH_ON)}).

8.3.5 Control Loop Compensation

Modeling of the TPS9260x-Q1 control loop is like that for any current-mode controller. Using a first-order

approximation, one can model the uncompensated loop as a single pole created by the output capacitor and, in

the boost and buck-boost topologies, a right half-plane zero created by the inductor, where both have a

dependence on the dynamic resistance of the LED string. There is also in the model a high-frequency pole

which, however, is near the switching frequency and plays no part in the compensation design process.

Therefore, the loop analysis neglects this high-frequency pole. Because TI recommends ceramic capacitors for

use with LED drivers due to long lifetimes and high ripple-current rating, one can also neglect the ESR of the

output capacitor in the loop analysis. Finally, there is a dc gain of the uncompensated loop which depends on

internal controller gains and the external sensing network. A boost regulator serves as an example case. See the

Detailed Design Procedure section for compensation of all topologies.

Equation 3 gives the whole-loop gain for a boost regulator.

æ

ö

÷

ø

æ

ç

è

ö

÷

ø

s(j)

1+

´ 1-

ç

è

w_ezc

w_ezrhp

T_u= T_uo

´

æ

ç

è

ö

÷

ø

s(j)

1+

w_ep0

(3)

Equation 4 approximates the output pole (ω_ep0).

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Feature Description (continued)

2

w_ep0

=

r

_(D)´ C_o

where

•

r_(D): LED and R_{(ILED_SNS)}dynamic resistance

C_O: Output capacitor

(4)

(5)

(6)

Use Equation 5 to calculate the right half-plane zero (ω_ezrhp).

r

_(D)´D^'2

w_ezrhp

=

L1

Use Equation 6 to calculate the output capacitor and ESR zero (ω_ezc).

1

w_ezc

=

r_esr´ C_o

The EA transfer function with compensation capacitor and resistor of the system is described in Equation 7 is

shown in Equation 7.

s(j)

æ

ö

1+

ç

÷

wez1

è

ø

T_uo= Adc ´

æ

ö æ

ö

s(j)

1+

´ 1+

÷ ç

ç

÷

wep1

wep2

è

ø è

ø

where

•

Adc is the error-amplifier (EA) dc gain

(7)

(8)

Use Equation 8 to calculate the EA output with compensation capacitor pole (ω_ep1).

1

w_ep1

=

R

_(o)´ C_z

where

•

R_(o)is the EA output impendence

The EA higher frequency pole (ω_ep2to filter the high-frequency noise, which is higher than whole-loop bandwidth)

is shown in Equation 9.

1

w_ep2

=

R_z´ C_p

(9)

The EA output ESR zero (ω_ez1) is shown in Equation 10.

1

w_ez1

=

R_z´ C_z

(10)

Compensator design should give adequate phase margin (above 45°) at the crossover frequency. A simple

compensator using a single capacitor at the COMP pin adds a dominant pole to the system, which ensures

adequate phase margin if placed low enough. At high duty cycles, the RHP zero places extreme limits on the

achievable bandwidth with this type of compensation. However, because an LED driver is essentially free of

output transients (except catastrophic failures, open or short), the dominant pole approach, even with reduced

bandwidth, is usually the best approach.

8.3.6 LED Open-Circuit Detection

An open LED in any channel interrupts the current flow of that channel. If the LED current in the sensing circuit

falls below the defined threshold th_OLED, then the device pulls the DIAGx pin of the affected channel low (for

example, for use as an interrupt to a microcontroller). The output-voltage regulation is with respect to the set

point of the voltage-control loop (resistor divider network on the OVFBx pin). Removal of the failure releases the

DIAGx pin automatically.

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Feature Description (continued)

8.3.7 Output Short-Circuit and Overcurrent Detection

In case of an external short circuit of a boost output supply line to GND, the respective boost controller of the

affected channel is no longer able to limit the current through the control loop. This is because of the conductive

path from the supply voltage to the shorted output through the inductor and the boost diode.

To protect the external components from excessive currents, the controller of the affected channel interrupts the

path to its output by switching off the high-side PWM-dimming PMOS-FET. The interruption occurs as soon as

the high-side current-sense amplifier detects a common-mode voltage below 4 V, or when the voltage on the

VOUTx pin is below 4 V, or once the high-side current-sense amplifier hits the shorted-output detection threshold

V_(OPLED). The protection of each channel operates in this way, independently of the other channel (see state-

diagram in Figure 13). The device pulls the DIAGx pin of the affected channel high, and the controller of the

affected channel remains in this channel-fail state. In order to reset the controller of the affected channel (for

example, after removal of a short circuit) there must be one disable-and-enable cycle for the affected channel by

pulling the PWMINx pin low for t > t_{(CH_OFF)}, and setting it high for t > t_{(CH_ON)}

.

8.3.8 Measuring LED Current During a Non-Failure Condition

In regular operation mode, one can measure the actual output current of the controller with an external

microcontroller by sensing the voltage at the DIAGx pin. The DIAGx pin voltage between 0.2 V and 2.85 V

represents in a linear relation the output current measured by the current-sense block across the external shunt

resistor. Parameter DIAG_factorgives the scale factor of typically 12.5 (the TPS92601-Q1 or TPS92602-Q1 device

with 150-mV full-scale current-sense voltage) or 6.25 (the TPS92601A-Q1 or TPS92602A-Q1 device with 300-

mV full-scale current-sense voltage). Figure 11 gives the relation between the DIAGx pin voltage and the current-

sense voltage.

V_DIAGx

Short Circuit or

Overcurrent Detected

HIGH, 3 V < V_DIAG< 3.465 V

Default Working Point

0.2 V to 2.85 V

Normal Operation

for VIN > 6 V

LOW, 0 V < V_DIAG< 0.15 V

Open LED Detected

V_{ISPx_ISNx}

TPS92601-Q1, TPS92602-Q1: 20 mV*

150 mV*

300 mV*

225 mV*

450 mV*

TPS92601A-Q1, TPS92602A-Q1:

40 mV*

* Approximate voltages

Figure 11. DIAGx Pin Function

When the device is in global shutdown mode (when both PWMINx pins go low for t > t_{(CH_OFF)}), both DIAGx pins

are low.

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Feature Description (continued)

8.3.9 LED Dimming Options

The device offers two different approaches to regulate and control the brightness and the color of the LEDs:

analog dimming and PWM dimming.

8.3.9.1 Analog Dimming

An analog voltage applied to the ICTRLx pin allows changing the output current for each channel on the fly from

10%–100% of full-scale. Typically, this approach is used to:

•

Reduce the default current in a narrow range to adjust to different binning classes of the LEDs

Reduce the current at high temperatures (protect LEDs from overtemperature)

Reduce the current at low input voltages (for example, cranking-pulse breakdown of the supply)

Implementing this analog dimming function is possible with an analog approach (discrete resistor and NTC

network) or with a more-flexible approach by using a microcontroller. Internally clamping the maximum voltage

on the ICTRLx pin at 1.5 V simplifies the analog implementation. So applying any higher voltage has no effect on

the output current (which remains at its current set point at 100% of full scale, that is, 150 mV or 300 mV drop at

the external current shunt resistor).

V_{(ISPx_ISNx)}

TPS92601A-Q1,

TPS92602A-Q1,

TPS92601-Q1,

TPS92602-Q1,

300 mV

150 mV

Linear Analog Dimming

Region

10%–100%

30 mV

0 mV

15 mV

0 mV

V_(ICTRLx)

150 mV

Figure 12. Analog Dimming – ICTRLx Pin

1.5 V

8.3.9.2 PWM Dimming

To change the brightness of an LED string by a certain magnitude without affecting the lighting-color of the LED,

it is necessary to use PWM dimming topology. Turning the LEDs ON and OFF at a certain frequency with a

certain duty cycle reduces the brightness without changing the LED current (so not affecting the color).

The integrated high-side PMOS-FET gate driver turns the LED string ON and OFF following the supplied signal

frequency and duty cycle on the PWMIN pin. During the OFF time of the FET, the device stops the internal

control loop by disconnecting the loop internally and then stores the value of the compensation network. This

technique allows fastest recovery of the regulator with the following ON time, as the control loop restarts from the

point at which it stopped. The average LED current during ON time is almost the same as the LED current with

no PWM dimming (duty cycle 100%). For very low duty cycles, the time required by the controller to ramp up the

inductor current form 0 A becomes more significant relative to the overall ON time, leading to lower average

current. So for very low duty cycles, the relation between average current and duty cycle is no longer linear.

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Feature Description (continued)

One must maintain a minimum on-time in order for PWM dimming to operate in the linear region of its transfer

function. Because of disabling the controller during dimming, the PWM pulse must be long enough that the

energy intercepted from the input is greater than or equal to the energy being put into the LEDs. For boost and

boost-to-battery topologies, the minimum ON time (in seconds) for which the PWM dimming operates in the

linear region is:

2´I_(LED)´ V_(out)´L

t

=

(PWMON_MIN)

2

V

(IN)

(11)

To ensure that the applied dimming-pulse duration matches with the effective dimming-pulse duration, TI

recommends synchronizing the dimming pulses with the switching clock of the boost converter. Choose the

external inductor and output capacitors according to the requirements for the minimum duty cycle.

8.4 Device Functional Modes

8.4.1 Undervoltage and Overvoltage Shutdown

During normal operation (6 V < V_(VIN)< 40 V), when the supply voltage at the VIN pin drops below 4 V during

cranking, each boost controller is disabled (when previously in normal operation). As long as the battery voltage

stays above 3.5 V, both PWM dimming FETs are still controllable through the PWMINx pins, and the VCC

regulator is still active. The supply voltage recovering above 4 V re-enables each boost controller (which was

working normally before the supply voltage drop). When supply voltage at the VIN pin drops below 3.5 V, the

device enters standby due to battery undervoltage. From standby mode, re-enabling the device can only occur

when the supply voltage is above 6 V and one or both PWMINx pins are high for t > t_{(CH_ON)}). See the state

diagram in Figure 13. When the supply voltage at the VIN pin goes above 40 V during load-dump, the device

disables both boost controllers due to battery overvoltage, and switches both PWM dimming FETs off. The VCC

regulator is still active. Once the battery voltage is below 40 V, the device recovers from this global failure state

after a global disable-and-enable cycle (active shutdown by pulling both PWMINx pins low for t > t_{(CH_OFF)}, and

setting one or both PWMINx pins high for t > t_{(CH_ON)}). See the state diagram in Figure 13.

8.4.2 Overtemperature Shutdown

When the junction temperature rises above 165ºC, both boost controllers are disabled due to junction

overtemperature, and both PWM dimming FETs are switched off. Once the junction temperature is below 145ºC,

the device recovers from this global failure state or a global disable-and-enable cycle (active shutdown by pulling

both PWMINx pins low for t > t_{(CH_OFF)}, and setting one or both PWMINx pins high for t > t_{(CH_ON)}). See the state

diagram in Figure 13.

8.4.3 Device State Diagram

Figure 13 shows the state diagram of the device, with a short description of the device behavior in each state.

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Device Functional Modes (continued)

Main State Machine

VIN > 40 V OR

Missing Clock OR

V_(VIN)> 6 V AND

Wakeup

Standby

Active

Global Failure

VCC enabled

T_J> 165°C

V_(VCC)disabled

V_(VCC)enabled

Both boost controllers

disabled

Both boost controllers

disabled

One or both channels

active (see Active

Sub-State Machine)

Both PWM dimming

FETs switched off

DIAG1 and 2 pins low

Both PWM dimming

FETs switched off

Both DIAGx pins low

PowerOnReset OR

PowerDown

WakeUp =

.

(V_(PWMIN1)= 1 for t > t_{(CH_ON)}OR V_(PWMIN2)= 1 for t > t_{(CH_ON)}

)

PowerDown =

.(V_(PWMIN1)= 0 for t > t_{(CH_ON)}AND V_(PWMIN2)= 0 for t > t_{(CH_ON)}

)

Missing Clock = RT terminal open AND no sync pulse _{(CH_ON)}

PowerOnReset = V_(VIN)< 3.5 V

Active Sub-State Machine

Each channel can independently follow this State Machine.

Low-Voltage

Boost controller

disabled

PWM dimming FET

controllable through

PWMINx pin

V_(PWMINx)= 0 for t > t_{(CH_OFF)}

3.5 V < V_(VIN)< 4 V

DIAGx pin shows

measured current

Main State ≠ Active

V_(VIN)> 6 V

V_(VIN)> 6 V AND

V_(PWMINx)= 1 for t > t_{(CH_ON)}

OFF

ON

Boost controller

enabled

Boost controller

disabled

PWM dimming FET

controllable through

PWMINx terminal

DIAGx terminal shows

measured current

PWM dimming FET

switched off

DIAGx terminal low

V_(PWMINx)= 0 for t > t_{(CH_OFF)}

Channelx Failure

Detected

Channel-Fail

V_(PWMINx)= 0 for t > t_{(CH_OFF)}

Boost controller

disabled

PWM dimming FET

switched off

DIAGx terminal high

Channelx Failure Detected = (V_(VOUTx)< 4 V OR V_{(SPSNx_Com)}< 4V OR V_{(SPSNx_Diff)}> th_(SHOUT)

)

NOTE: In the case of an open LED on channel x, the DIAGx pin is low, but the boost controller and the PWM

dimming FET of channel x work normally. Hence, the behavior is as in the ON state or the low-voltage state.

Figure 13. Device State Diagram

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

This section describes the application-level considerations when designing with the TPS9260x-Q1 family of

devices. For corresponding calculations, see the following section.

9.2 Typical Applications

In an application directly connected to a battery, if the application is a passenger car, V_(VIN)is from 9 V to 16 V,

and LED forward voltage is always higher than battery, then one can select the boost topology. If the LED

forward voltage is between 9 V and 16 V, boost-to-battery or single-ended primary-inductance converter (SEPIC)

topology is appropriate.

9.2.1 Boost Regulator With Separate or Paralleled Channels

A boost application is appropriate for a situation where V_(VIN)is from 9 V to 16 V and LED forward voltage is

always higher than battery the battery voltage. One can use the boost-regulator topology with each channel

driving a separate LED string. For higher-current applications, connect both channels in parallel to drive a single

LED string. The per-channel design parameters and calculations are the same in either case.

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Typical Applications (continued)

VBAT

C_IN1

L1

Q1

R_SNS

1

D1

DIAG1

GDRV1

ISNS1

COMP1

C_O1

R_LIM1

CHANNEL

1

ISP1

ISN1

ICTRL1

PWIN1

VOUT1

PWMO1

OVFB1

PGND1

R_OV1

R_OV2

VCC

RT

VBAT

L2

C_IN2

TPS92602-Q1

Q1

R_SNS

2

D2

DIAG2

GDRV2

ISNS2

COMP2

C_O

2

R_LIM2

CHANNEL

2

ISP2

ISN2

ICTRL2

PWIN2

VOUT2

R_OV3

PWMO2

OVFB2

PGND2

R_OV4

Figure 14. Boost Regulator (V_IN< V_O) Simplified Schematic, Separate Channels

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Typical Applications (continued)

VBAT

C_IN1

L1

Q1

R_SNS

1

D1

DIAG1

GDRV1

ISNS1

COMP1

C_O1

R_LIM1

CHANNEL

1

ISP1

ISN1

ICTRL1

PWIN1

VOUT1

PWMO1

OVFB1

PGND1

R_OV1

R_OV2

VCC

RT

VBAT

L2

C_IN2

TPS92602-Q1

Q1

R_SNS

2

D2

DIAG2

GDRV2

ISNS2

COMP2

C_O

2

R_LIM2

CHANNEL

2

ISP2

ISN2

ICTRL2

PWIN2

VOUT2

R_OV3

PWMO2

OVFB2

PGND2

R_OV4

Figure 15. Boost Regulator (V_IN< V_O) Simplified Schematic, Paralleled Channels

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SLUSBP5D –MARCH 2014–REVISED JANUARY 2015

Typical Applications (continued)

D7

D8

D9

D10

LED_B1

LED_B2

J_B1

D1

1

2

1

2

1

2

1

2

VBAT1

VBAT2

R1

464k

R2

464k

White

GND

B150-13-F

0.7V

D2

MP_PMOS1

OVP1

OVP2

R3

30.0k

R4

30.0k

B150-13-F

0.7V

C1

R5

0.15

AGND

U1

AGND

C2

0.1uF

10uF

C3

0.1uF

8

LED_B1

VIN

VCC

AGND

21

C4

3.3uF/100V

R6

0.012

DIAG1

PWM1

5

2

22

23

DIAG1

GDRV1

GND

R7

510

COMP1

ISNS1

GND

D4

C5

0.22uF

C6

270pF

GND

25

26

27

28

3

MN_POWER1

ISP1

ISN1

D3

1

7

ICTRL1

10uF/50V

VOUT1

PWMO1

OVFB1

PWMIN1

AGND

100V

OVP1

GND

J_VBAT1

L_B1

VBAT1

R9

10

R8

10.0k

24

20

19

10A

22u

PGND1

GDRV2

ISNS2

C7

R10

10

DIAG2 13

12

DIAG2

L_B2

J_VBAT2

R12

510

R11

20.0k

VBAT2

COMP2

10A

22u

C8

0.22uF

C9

270pF

D5

17

16

15

14

ISP2

ISN2

D6

11

9

ICTRL2

C10

10uF/50V

VOUT2

PWMO2

OVFB2

AGND

PWM2

MN_POWER2

PWMIN2

AGND

10 OVP2

+5V

R14

0.012

GND

18

6

PGND2

R13

10.0k

R16

0.15

4

RT

GND

PAD

GND

TPS92602-Q1

LED_B2

R15

20.0k

GND

R17

20.0k

MP_PMOS2

C11

3.3u/100V

R18

0

AGND

GND

AGND

J_B2

GND

D11

D12

D13

D14

1

2

1

2

1

2

1

2

White

GND

Figure 16. Boost Regulator (V_IN< V_O) Detailed Schematic

9.2.1.1 Design Requirements

For this boost regulator example, use the following as the design parameters.

Table 1. Design Parameters

DESIGN PARAMETER

EXAMPLE VALUE

Input voltage range

Output current per channel (I_(setting)

Output voltage

Connect to battery (6 V to 16 V)

)

1 A

30 V (9 white LEDs)

400 mV

Input ripple voltage

Output ripple current

±10%

Operating frequency

600 kHz

9.2.1.2 Detailed Design Procedure

To begin the design process, one must decide on a few parameters. The designer must know the following:

•

Input voltage range

Output current per channel

Output voltage

Input ripple voltage

Output ripple current

Operating frequency

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9.2.1.2.1 Switching Frequency

The RT pin resistor sets the switching frequency of the TPS92602-Q1 device. Use Equation 2 to calculate the

required value for R17. The calculated value is 20.83 kΩ. Use the nearest standard value of 20 kΩ.

9.2.1.2.2 Maximum Output-Current Set Point

The constant output current of the TPS92602-Q1 device is adjustable by using the external current-shunt

resistor. In the application circuit of Figure 16, R5 is the channel 1 current-shunt resistor, and R16 is the channel-

2 current shunt resistor. Equation 12 and Equation 13 calculate the resistors that determine maximum output

current.

R_(sense)= V_{SPSN_Diff}/ I_(setting)

(12)

(13)

R5 = R16 = 150 mV / 1 A = 0.15 Ω

9.2.1.2.3 Output Overvoltage-Protection Set Point

The output overvoltage protection threshold of the TPS92602-Q1 device is externally adjustable using a resistor

divider network. In the application circuit of Figure 16, this divider network comprises R1 and R3 for channel1

and R2 and R4 for channel2. The following equation gives the relationship of the overvoltage-protection

threshold (V_(OVPT)) to the resistor divider.

R1 / R3 = R2 / R4 = (V_(OVPT)– V_(VFB)) / V_(VFB)

(14)

The load is nine white LEDs, the forward voltage is about 30 V. For an overvoltage protection margin of 20%,

V_(OVPT)is: V_(OVPT)= 30 × 1.2 = 36 V. So R1 / R3 = R2 / R4 = (36 – 2.2) / 2.2 = 15.36. Select R3 = R4 = 30 kΩ;

then R1 = R2 = 460 kΩ. Use the nearest standard value of 464 kΩ.

9.2.1.2.4 Duty Cycle Estimation

Estimate the duty cycle of the main switching MOSFET using Equation 15 and Equation 16.

V

- V_(IN-max)+ V_(FD)

30 V -16 V + DMIN 0.5V

30 V + 0.5V

(OUT)

D_(MIN)

»

=

= 47.5%

V

+ V_(FD)

(OUT)

where

•

D is the duty cycle in these and all following equations

(15)

(16)

V

- V_(IN-min)+ V_(FD)

30 V - 6 V + 0.5V

30 V + 0.5V

(OUT)

D_(MAX)

»

=

= 80.3%

V

+ V_(FD)

(OUT)

Using an estimated forward drop of 0.5 V for a Schottky rectifier diode, the approximate duty cycle is 47.5%

(minimum) to 80.3% (maximum).

9.2.1.2.5 Inductor Selection

The peak-to-peak ripple is limited to 30% of the maximum output current.

I_(OUT-max)

1

I_(Lrip-max)= 0.3´

= 0.3´

= 0.571 A

1- D_(MIN)

1- 0.475

(17)

(18)

Estimate the minimum inductor size using Equation 18.

V_(IN-max)

1

16 V

1

L_(MIN)>>

´D_(MIN)

´

=

f_(SW)0.571 A

´ 0.475´

= 22.1mH

I_(Lrip-max)

600 kHz

Select the nearest standard inductor value of 22 µH. Estimate the ripple current using Equation 19.

V

1

16 V

1

(IN)

I_(RIPPLE)

»

´D_(MIN)

´

=

f_(SW)22 mH

´ 0.475´

= 0.575 A

L

600 kHz

(19)

(20)

V

1

6 V

1

(IN)

I_{(RIPPLE-Vinmin)}

»

´D_(MIN)

´

=

f_(SW)22 mH

´ 0.475´

= 0.365 A

L

600 kHz

The worst-case peak-to-peak ripple current occurs at 47.5% duty cycle and is estimated as 0.575 A. Equation 21

estimates the worst-case rms current through the inductor.

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SLUSBP5D –MARCH 2014–REVISED JANUARY 2015

ö²

é

ù

æ

ö²

æ

ç

è

ö²

I_(OUT-max)

æ

1

I_(Lrms)

=

(I_(L-avg))²+

´I_(RIPPLE)

»

+

´I_{(RIPPLE-Vinmin)}

÷

ç

÷

ç

÷

ê

ú

÷

12

1- D

12

ë

û

è

ø

è

ø

^(MAX)ø

ö²

1 A

1

æ

ç

ö

÷

æ

+

´ 0.365 A = 5.08 A rms

ç

÷

1- 0.803

12

è

ø

è

ø

(21)

(22)

The worst-case rms inductor current is 5.08 A rms. Equation 22 estimates the peak inductor current.

I_(OUT-max)

1

2

1

I_(Lpeak)

»

+

´I_{(RIPPLE- Vinmin)}

=

+ 0.5´ 0.365 = 5.26 A

1- D_(MAX)

1- 0.083

Select a 22-µH inductor with a minimum rms current rating of 5.08 A and minimum saturation current rating of

5.26 A. The selection is a Wurth 74435572200 inductor (shielded-drum core, ferrite, 22 µH, 11 A, 0.0146 Ω,

SMD).

Equation 23 estimates the power dissipation of this inductor

P_(L)» (I_(Lrms))²´DCR

(23)

The Wurth 74435572200 inductor with 14.6-mΩ DCR dissipates 404 mW of power.

9.2.1.2.6 Rectifier Diode Selection

The circuit uses a low-forward-voltage-drop Schottky diode as a rectifier diode to reduce power dissipation and

improve efficiency. Use 80% derating for the diode on VOUTx to allow for for ringing on the switch node.

Equation 24 gives the rectifier-diode minimum reverse-breakdown voltage.

V_(VOPT)

V

³

= 1.25´36 V = 45 V

(BR)(R-min)

0.8

(24)

The diode must have a reverse-breakdown voltage greater than 45 V. Equation 25 and Equation 26 estimate the

rectifier diode peak and average currents.

I_(D-avg)» I_(OUT-max)= 1 A

(25)

I_(D-peak)= I_(L-peak)= 5.26 A

(26)

For this design, average current is 1 A and peak current is 5.26 A.

Equation 27 estimates the power dissipation in the diode.

P_(D-max)» V_(F)´I_(OUT-max)= 0.5 V ´1 A = 0.5 W

(27)

For this design, the maximum power dissipation is estimated as 0.5 W. After reviewing 45-V and 60-V Schottky

diodes, the selection is the 30BQ060PbF diode, Schottky, 60 V, 3 A, SMC. This diode has a forward voltage drop

of 0.5 V at 1 A, so the conduction power dissipation is approximately 500 mW, less than half its rated power

dissipation.

9.2.1.2.7 Output Capacitor Selection

Assume a maximum LED current ripple of 0.1 × I_(LED). Also, assume that the dynamic impedance of the chosen

LED is 0.2 Ω (1.8 Ω total for the nine-LED string). The total output-voltage ripple calculation is then as per

Equation 28.

V_{(VOUT-ripple)}= 0.1 A ´1.8 W = 180 mV

(28)

Assuming a ripple contribution of 95% from bulk capacitance, Equation 29 calculates the output capacitor.

I_(OUT)´D

æ

ç

è

ö

÷

ø

1

1 A ´0.803

1

C_(OUT)

=

´

=

´

= 7.83 mF

V_{(VOUT-ripple)}´ 0.95 f_(SW)

180 mV ´0.95

600 kHz

(29)

(30)

V_{(VOUT-ripple)}

9 mV

ESR =

=

= 1.71 mW

I_(L-peak)

5.26 A

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Use three 3.3-μF capacitors in parallel to achieve the minimum output capacitance of 10 μF. Ensure that the

chosen capacitors meet the minimum bulk capacitance requirement at the operating voltage.

9.2.1.2.8 Input Capacitor Selection

Because a boost converter has continuous input current, the input capacitor senses only the inductor ripple

current. Equation 31 and Equation 32 calculate the input capacitor values.

I_(L-RIPPLE)

0.575 A

C_(IN)

=

= 4 mF

4´ v_(IN-RIPPLE)´ f_(SW)4´ 60 mV ´ 600 kHz

(31)

V_(VIN-RIPPLE)

60 mV

ESR =

=

= 52 mW

I_(L-RIPPLE)

2´ 0.575 A

(32)

For this design, to meet a maximum input ripple of 60 mV requires a minimum 4-µF input capacitor with ESR

less than 52 mΩ. Select a 10-µF X7R ceramic capacitor.

9.2.1.2.9 Current Sense and Current Limit

The maximum allowable current sense resistor value is limited by R_(ISNSx). Equation 33 gives this limitation.

V

100 mV

(SNS)

R_(ISNSx)

=

1.3´I_(L-peak)1.3´5.26 A

= 14.62 mW

(33)

Select a 15-mΩ resistor.

9.2.1.2.10 Switching MOSFET Selection

The TPS92602-Q1 device drives a ground-referenced N-channel FET. The breakdown voltage is the output

voltage plus any voltage spike, with 30% added for a safety margin as shown in Equation 34.

V_(BD-MOS-min)³ V_(VOPT)´1.3 = 1.3´ 36 V = 46.8 V

(34)

Select an N-channel FET with breakdown voltage of 50 V.

Estimate the r_DS(on)and gate charge based on the desired efficiency target.

æ 1

ö

1

æ

ö

P_(DISS-total)» P_(OUT)

´

-1 = 30 V ´1 A ´

-1 = 1.578 W

ç

÷

ç

è

÷

h

è

0.95

ø

(35)

For a target of 95% efficiency with a 16-V input voltage at 1 A, maximum power dissipation is limited to 1.578 W.

The main power-dissipating devices are the MOSFET, inductor, diode, current-sense resistor and the integrated

circuit, the TPS92602-Q1 device.

P_(FET)< P_(DISS-total)- P_(L)- P_(D)- P_(RSNS)- V_(IN-max)´I_(VDD)

(36)

This assumption leaves 740 mW of power dissipation for the MOSFET. Allowing half for conduction and half for

switching losses, we can determine a target r_DS(on)and Q_(GS)for the MOSFET by Equation 37 and Equation 38.

3´P_(FET)´I_(DRIVE)

3´ 0.5 W ´0.7 A

Q_(GS)

<

=

= 29.2 nC

2´ V_(OUT)´I_(OUT)´ f_(SW)2´30 V ´1 A ´ 600 kHz

(37)

Calculate a target MOSFET gate-to-source charge of less than 29.2 nC to limit the switching losses to less than

250 mW.

P_(FET)

0.5 W

2´(5.08 A)²´0.803

r_DS(on)

<

=

= 12 mW

2

2´ I

´D

(_(RMS))

(38)

Selecting a target MOSFET r_DS(on)of 12 mΩ limits the conduction losses to less than 250 mW.

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9.2.1.2.11 Loop Compensation

The COMP pin on the TPS92602-Q1 device is for external compensation, allowing optimization of the loop

response for each application. The COMP pin is the output of the internal transconductance amplifier. External

resistor R7, along with ceramic capacitors C5 and C6 (see Figure 16 ), connect to the COMP pin to provide

poles and zero. The poles and zero, along with the inherent pole and zero in a peak-current-mode control boost

converter, determine the closed-loop frequency response. Thhis connection is important to converter stability and

transient response. The first step is to calculate the pole and the right half-plane zero of the peak-current-mode

boost converter by Equation 39 and Equation 40. To make the loop stable, the loop must have sufficient phase

margin at the crossover frequency where the loop gain is 1. To avoid the effect of the right half-plane zero on

loop stability, choose a crossover frequency less than 1/5 of f_(ZRHP)

I_(OUT)

2p´ V_(OUT)´ C_(OUT)2p´R_(OUT)´ C_(OUT)

.

1

f_(p)

=

where

•

C_(OUT)is the bulk output capacitance calculated previously

R_(OUT)is the effective output impedance

(39)

(40)

V

_(OUT)´(1- D)²

2p´L ´I_(OUT)

+ R_(SENSE)´ V

f_(ZRHP)

=

R

(

)

(LED)

R_(OUT)

=

R

(

+ R_(SENSE)´I

)

+ V_(LED)

(LED)

where

•

R_(LED)is the dynamic impedance of the LED string in ohms at the operating current

(41)

The loop compensation consists of a series resistor and capacitor (R_(COMP)and C_(COMP)) from COMP to SGND.

R_(COMP)sets the crossover frequency and C_(COMP)sets the zero frequency of the integrator. For optimum

performance, use the following equations:

g_M(COMP)= 1000

(42)

f

_(ZRHP)´R_(ISNSx)

R_(COMP)

=

5´ f_(p)´(1- D_(MAX))´R_(SENSE)´5´GM_(COMP)

(43)

1

C_(COMP)

=

2p´R_(COMP)´ 5´ f_(p)

where

•

f_(p)is the pole frequency of the power stage calculated by Equation 39

(44)

An output capacitor that is an electrolytic capacitor which has large ESR requires a capacitor to cancel the zero

of the output capacitor. Equation 45 calculates the value of this capacitor.

C

_(OUT)´R_(ESR)

C₆

=

R_(COMP)

(45)

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9.2.1.3 Application Curves

Figure 17. PWM Dimming at 200 Hz, 5% Duty Cycle

Figure 18. PWM Dimming at 200 Hz, 50% Duty Cycle

Figure 19. PWM Dimming at 200 Hz, 95% Duty Cycle

Figure 20. Switching and LED Current Ripple

When I_(OUT)= 1 A

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9.2.2 Boost-to-Battery Regulator

When the LED forward voltage is between 9 V and 16 V, an appropriate selection is boost-to-battery topology,

which can share the same layout and components as the boost topology, with just a different way to connect

load.

VBAT

C_IN

1

L1

C_O1

Q1

R_SNS

1

D1

DIAG1

GDRV1

ISNS1

COMP1

R_LIM

1

CHANNEL

1

ISP1

ISN1

ICTRL1

PWIN1

VOUT1

PWMO1

OVFB1

PGND1

R_OV

1

2

R_OV

VCC

RT

VBAT

L2

TPS92602-Q1

C_O2

C_IN

2

Q1

R_SNS

2

D2

DIAG2

GDRV2

ISNS2

COMP2

R_LIM

2

CHANNEL

2

ISP2

ISN2

ICTRL2

PWIN2

VOUT2

R_OV

3

4

PWMO2

OVFB2

PGND2

R_OV

Figure 21. Boost-to-Battery Regulator Simplified Schematic

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D7

D8

D9

D10

1

2

1

2

1

2

1

2

LED_B1

LED_B2

J_B1

White

D1

VBAT1

VBAT2

R1

464k

R2

464k

B150-13-F

0.7V

D2

MP_PMOS1

OVP1

OVP2

R3

30.0k

R4

30.0k

B150-13-F

0.7V

C1

R5

0.15

AGND

U1

AGND

C2

0.1uF

10uF

C3

0.1uF

8

LED_B1

VIN

VCC

AGND

21

C4

16.2uF/45V

R6

0.020

DIAG1

PWM1

5

2

22

23

DIAG1

GDRV1

GND

MN_POWER1

R7

510

COMP1

ISNS1

GND

D4

C5

0.22uF

C6

270pF

GND

10uF/50V

25

26

27

28

3

ISP1

ISN1

D3

1

7

ICTRL1

VOUT1

PWMO1

OVFB1

PWMIN1

AGND

100V

OVP1

GND

J_VBAT1

L_B1

VBAT1

R9

10

R8

10.0k

24

20

19

5.3A

22u

PGND1

GDRV2

ISNS2

C7

L_B2

R10

10

DIAG2 13

12

DIAG2

J_VBAT2

VBAT2

R12

510

R11

20.0k

COMP2

5.3A

22u

C8

0.22uF

C9

270pF

D5

17

16

15

14

ISP2

ISN2

D6

11

9

ICTRL2

C10

10uF/50V

VOUT2

PWMO2

OVFB2

AGND

PWM2

MN_POWER2

PWMIN2

AGND

10 OVP2

+5V

R14

0.020

GND

18

6

PGND2

R13

10.0k

R16

0.15

4

RT

GND

PAD

GND

TPS92602-Q1

LED_B2

R15

20.0k

GND

R17

20.0k

MP_PMOS2

C11

16.2u/45V

R18

0

AGND

GND

AGND

J_B2

GND

D11

D12

D13

2

D14

2

1

2

1

2

1

White

Figure 22. Boost-to-Battery Regulator Detailed Schematic

9.2.2.1 Design Requirements

For this boost-to-battery regulator example, use the following as the design parameters.

Table 2. Design Parameters

DESIGN PARAMETER

Input voltage range

EXAMPLE VALUE

Connect to battery (6 V to 16 V)

Output current per channel (I_(setting)

)

1 A

13.2 V (4 white LEDs)

400 mV

Output voltage

Input ripple voltage

Output ripple current

±10%

Operating frequency

600 kHz

9.2.2.2 Detailed Design Procedure

To begin the design process, one must decide on a few parameters. The designer must know the following:

•

Input voltage range

Output current per channel

Output voltage

Input ripple voltage

Output ripple current

Operating frequency

28

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9.2.2.2.1 Switching Frequency

The RT pin resistor sets the switching frequency of the TPS92602-Q1 device to 600 kHz. Use Equation 2 to

calculate the required value for R17. The calculated value is 20.83 kΩ. Use the nearest standard value of 20 kΩ.

9.2.2.2.2 Maximum Output-Current Set Point

The output constant of the TPS92602-Q1 device is adjustable by using the external current-shunt resistor. In the

application circuit of Figure 22, R5 is the channel 1 current-shunt resistor, and R16 is the channel-2 current shunt

resistor. Equation 46 and Equation 47 calculate the resistors that determine maximum output current.

R_(sense)= V_{SPSN_Diff}/ I_(setting)

(46)

(47)

R5 = R16 = 150 mV / 1 A = 0.15 Ω

9.2.2.2.3 Output Overvoltage-Protection Set Point

The output overvoltage protection threshold of the TPS92602-Q1 device is externally adjustable using a resistor

divider network. In the application circuit of Figure 22, this divider network comprises of R1 and R3 for channel1

and R2 and R4 for channel2. The following equation gives the relationship of the overvoltage-protection

threshold (V_(OVPT)) to the resistor divider.

R1 / R3 = R2 / R4 = (V_(OVPT)– V_(VFB)) / V_(VFB)

(48)

The load is four white LEDs, the forward voltage is about 13.2 V, maximum V_(VIN)is 16 V, so the maximum

output is 13.2 + 16 = 29.2 V, which is close to 30 V. Allowing 20% margin for overvoltage protection, V(OVPT) is:

V_(OVPT)= 30 × 1.2 = 36 V. So R1 / R3 = R2 / R4 = (36 – 2.2) / 2.2 = 15.36. Select R3 = R4 = 30 kΩ; then R1 =

R2 = 460 kΩ. Use the nearest standard value of 464 kΩ.

9.2.2.2.4 Duty Cycle Estimation

Estimate the duty cycle of the main switching MOSFET using Equation 49 and Equation 50.

V

+ V_(FD)

(LED)

=

+ V_(MAX)+ V_(FD)30 V + 16 V + 0.5V

13.2 V + 0.5V

D_(MIN)

»

= 46.1%

V

(LED)

where

•

D is the duty cycle in these and all following equations

(49)

(50)

V

+ V_(FD)

13.2 V + 0.5V

(LED)

D_(MAX)

»

=

+ V_(FD)13.2 V + 6 V + 0.5V

= 69.5%

V

+ V

(MIN)

(LED)

Using an estimated forward drop of 0.5 V for a Schottky rectifier diode, the approximate duty cycle is 46.1%

(minimum) to 69.5% (maximum).

9.2.2.2.5 Inductor Selection

The peak-to-peak ripple is limited to 30% of the maximum output current.

I_(OUT-max)

1

I_(Lrip-max)= 0.3´

= 0.3´

= 0.556 A

1- D_(MIN)

1- 0.461

(51)

(52)

Estimate the minimum inductor size using Equation 52

V_(IN-max)

1

16 V

1

L_(MIN)>>

´D_(MIN)

´

=

f_(SW)0.571 A

´ 0.475´

= 22.1mH

I_(Lrip-max)

600 kHz

Select the nearest higher standard inductor value of 22 µH. Estimate the ripple current using Equation 53.

V

1

16 V

1

(IN)

I_(RIPPLE)

»

´D_(MIN)

´

=

f_(SW)22 mH

´ 0.461´

= 0.559 A

L

600 kHz

(53)

(54)

V

1

6 V

1

(IN)

I_{(RIPPLE-Vinmin)}

»

´D_(MIN)

´

=

f_(SW)22 mH

´ 0.695´

= 0.316 A

L

600 kHz

The worst-case peak-to-peak ripple current occurs at 46.1% duty cycle and is estimated as 0.559 A. Equation 55

estimates the worst-case rms current through the inductor.

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ö²

é

ù

æ

ö²

æ

ç

è

ö²

I_(OUT-max)

æ

1

I_(Lrms)

=

(I_(L-avg))²+

´I_(RIPPLE)

»

+

´I_{(RIPPLE-Vinmin)}

÷

ç

÷

ç

÷

ê

ú

÷

12

1- D

12

ë

û

è

ø

è

ø

^(MAX)ø

ö²

´ 0.3316 A = 3.28 A rms

1 A

1

æ

ç

ö

÷

æ

+

ç

÷

1- 0.695

12

è

ø

è

ø

(55)

(56)

The worst-case rms inductor current is 3.28 A rms. Equation 56 estimates the peak inductor current.

I_(OUT-max)

1

2

1

I_(Lpeak)

»

+

´I_{(RIPPLE- Vinmin)}

=

+ 0.5´ 0.316 = 3.44 A

1- D_(MAX)

1- 0.695

Select a 22-µH inductor with a minimum rms current rating of 3.44 A and minimum saturation current rating of

3.44 A. The selection is a Wurth 7447709220 inductor (shielded-drum core, ferrite, 22 µH, 5.3 A, 0.0233 Ω,

SMD).

Equation 57 estimates the power dissipation of this inductor

P_(L)» (I_(Lrms))²´DCR

(57)

The Wurth 7447709220 inductor with 23.3-mΩ DCR dissipates 251 mW of power.

9.2.2.2.6 Rectifier Diode Selection

The circuit uses a low-forward-voltage-drop Schottky diode as a rectifier diode to reduce power dissipation and

improve efficiency. Use 80% derating for the diode on VOUTx to allow for ringing on the switch node.

Equation 58 gives the rectifier-diode minimum reverse-breakdown voltage.

V_(VOPT)

V

³

= 1.25´36 V = 45 V

(BR)(R-min)

0.8

(58)

The diode must have a reverse-breakdown voltage greater than 45 V. Equation 59 and Equation 60 estimate the

rectifier diode peak and average currents.

I_(D-avg)» I_(OUT-max)= 1 A

(59)

I_(D-peak)= I_(L-peak)= 3.44 A

(60)

For this design, average current is 1 A and peak current is 3.44 A.

Equation 61 estimates the power dissipation in the diode.

P_(D-max)» V_(F)´I_(OUT-max)= 0.5 V ´1 A = 0.5 W

(61)

For this design, the maximum power dissipation is estimated as 0.5 W. After reviewing 45-V and 60-V Schottky

diodes, the selection is the 30BQ060PbF diode, Schottky, 60 V, 3 A, SMC. This diode has a forward voltage drop

of 0.5 V at 1 A, so the conduction power dissipation is approximately 500 mW, less than half its rated power

dissipation.

9.2.2.2.7 Output Capacitor Selection

Assume a maximum LED current ripple of 0.1 × I_(LED). Also, assume that the dynamic impedance of the chosen

LED is 0.2 Ω (0.8 Ω total for the four-LED string). The total output voltage ripple calculation is then as per

Equation 62.

V_{(VOUT-ripple)}= 0.1 A ´ 0.8 W = 80 mV

(62)

Assuming a ripple contribution of 95% from bulk capacitance, Equation 64 calculates the output capacitor.

I_(OUT)´D

æ

ç

è

ö

÷

ø

1

1 A ´0.695

1

C_(OUT)

=

´

=

´

= 15.2 mF

V_{(VOUT-ripple)}´ 0.95 f_(SW)

80 mV ´0.95

600 kHz

(63)

(64)

V_{(VOUT-ripple)}

4 mV

ESR =

=

= 1.16 mW

I_(L-peak)

3.44 A

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SLUSBP5D –MARCH 2014–REVISED JANUARY 2015

Use five 3.3-μF capacitors in parallel to achieve the minimum output capacitance of 15.2 μF. Ensure that the

chosen capacitors meet the minimum bulk capacitance requirement at the operating voltage.

9.2.2.2.8 Input Capacitor Selection

Because a boost converter has continuous input current, the input capacitor senses only the inductor ripple

current. The input capacitor value can be calculated by Equation 65 and Equation 66.

I_(L-RIPPLE)

0.559 A

C_(IN)

=

= 3.89 mF

4´ v_(IN-RIPPLE)´ f_(SW)4´ 60 mV ´ 600 kHz

(65)

V_(VIN-RIPPLE)

60 mV

ESR =

=

= 53.67 mW

I_(L-RIPPLE)

2´0.559 A

(66)

For this design, to meet a maximum input ripple of 60 mV requires a minimum 4-µF input capacitor with ESR

less than 52 mΩ. Select a 10-µF X7R ceramic capacitor.

9.2.2.2.9 Current Sense and Current Limit

The maximum allowable current sense resistor value is limited by R(ISNSx). Equation 67 gives this limitation.

V

100 mV

(SNS)

R_(ISNSx)

=

1.3´I_(L-peak)1.3´3.44 A

= 22.36 mW

(67)

Select a 20-mΩ resistor.

9.2.2.2.10 Switching MOSFET Selection

The TPS92602-Q1 device drives a ground-referenced N-channel FET. The breakdown voltage is the output

voltage plus any voltage spike, with 30% added for a safety margin as shown in Equation 68.

V_(BD-MOS-min)³ V_(VOPT)´1.3 = 1.3´ 36 V = 46.8 V

(68)

Select an N-channel FET with breakdown voltage of 50 V.

Estimate the r_DS(on)and gate charge based on the desired efficiency target.

æ 1

ö

1

æ

ö

P_(DISS-total)» P_(OUT)

´

-1 = 13.2 V ´1 A ´

-1 = 1.148 W

ç

÷

ç

è

÷

h

è

0.92

ø

(69)

For a target of 92% efficiency with a 16-V input voltage at 1 A, maximum power dissipation is limited to 1.148 W.

The main power-dissipating devices are the MOSFET, inductor, diode, current-sense resistor and the integrated

circuit, the TPS92602-Q1 device.

P_(FET)< P_(DISS-total)- P_(L)- P_(D)- P_(RSNS)- V_(IN-max)´I_(VDD)

(70)

This assumption leaves 600 mW of power dissipation for the MOSFET. Allowing half for conduction and half for

switching losses, we can determine a target r_DS(on)and Q_(GS)for the MOSFET by Equation 71 and Equation 72.

3´P_(FET)´I_(DRIVE)

3´ 0.4 W ´0.7 A

Q_(GS)

<

=

= 28.3 nC

2´ V_(OUT)´I_(OUT)´ f_(SW)2´13.2 V ´1 A ´ 600 kHz

(71)

Calculate a target MOSFET gate-to-source charge of less than 28.3 nC to limit the switching losses to less than

200 mW.

P_(FET)

0.4 W

2´(3.28 A)²´0.695

r_DS(on)

<

=

= 26.7 mW

2

2´ I

´D

(_(RMS))

(72)

Selecting a target MOSFET r_DS(on)of 26.7 mΩ limits the conduction losses to less than 250 mW.

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9.2.2.2.11 Loop Compensation

The COMP pin on the TPS92602-Q1 device is for external compensation, allowing optimization of the loop

response for each application. The COMP pin is the output of the internal transconductance amplifier. The

external resistor R7, along with ceramic capacitors C5 and C6 (see Figure 22 ), connect to the COMP pin to

provide poles and zero. The poles and zero, along with the inherent pole and zero in a peak-current-mode

control boost converter, determine the closed-loop frequency response. This is important to converter stability

and transient response. The first step is to calculate the pole and the right half-plane zero of the peak-current-

mode boost converter by Equation 73 and Equation 74. To make the loop stable, the loop must have sufficient

phase margin at the crossover frequency where the loop gain is 1. To avoid the effect of the right half-plane zero

on the loop stability, choose the crossover frequency less than 1/5 of f_(ZRHP)

I_(OUT)

2p´ V_(OUT)´ C_(OUT)2p´R_(OUT)´ C_(OUT)

.

1

f_(p)

=

where

•

C_(OUT)is the bulk output capacitance previously calculated

R_(OUT)is the effective output impedance

(73)

(74)

V

_(OUT)´(1- D)²

2p´L ´I_(OUT)

+ R_(SENSE)´ V

f_(ZRHP)

=

R

(

)

(LED)

R_(OUT)

=

R

(

+ R_(SENSE)´I

)

+ V_(LED)

(LED)

where

•

R_(LED)is the dynamic impedance of the LED string in ohms at the operating current

(75)

The loop compensation consists of a series resistor and capacitor (R_(COMP)and C_(COMP)) from COMP to SGND.

R_(COMP)sets the crossover frequency and C_(COMP)sets the zero frequency of the integrator. For optimum

performance, use the following equations:

g_M(COMP)= 1000

(76)

f

_(ZRHP)´R_(ISNSx)

R_(COMP)

=

5´ f_(p)´(1- D_(MAX))´R_(SENSE)´5´GM_(COMP)

(77)

1

C_(COMP)

=

2p´R_(COMP)´ 5´ f_(p)

where

•

f_(p)is the pole frequency of the power stage calculated by Equation 73

(78)

An output capacitor that is an electrolytic capacitor which has large ESR requires a capacitor to cancel the zero

of the output capacitor. Equation 79 calculates the value of this capacitor.

C

_(OUT)´R_(ESR)

C₆

=

R_(COMP)

(79)

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SLUSBP5D –MARCH 2014–REVISED JANUARY 2015

9.2.2.3 TPS92602-Q1 Application Curves

Figure 23. PWM Dimming at 2 kHz, 5% Duty Cycle

Figure 24. PWM Dimming at 2 kHz, 50% Duty Cycle

Figure 25. PWM Dimming at 2 kHz, 95% Duty Cycle

Figure 26. Switching and LED Current Ripple

When I_(OUT)= 1 A

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10 Power Supply Recommendations

The design of the devices is for operation via direct connection to a battery, so the input-voltage supply range is

from 4 V to 40 V. This input supply should be well regulated. If the input supply is located more than a few inches

from the TPS9260x-Q1 family of devices, additional bulk capacitance may be required in addition to the ceramic

bypass capacitors.

11 Layout

11.1 Layout Guidelines

•

The performance of any switching regulator depends as much on the layout of the PCB as the component

selection. Following a few simple guidelines maximizes noise rejection and minimizes the generation of EMI

within the circuit.

•

Discontinuous currents are the most likely to generate EMI, therefore care should be taken when routing the

following paths. The main path for discontinuous current in the TPS9260x-Q1 buck regulator contains the

input capacitor (C_IN1), the recirculating diode (D1), the N-channel MOSFET (Q1), and the sense resistor

(R_LIM1). In the TPS9260x-Q1 boost regulator, the discontinuous current flows through the output capacitor

(C_O1), D1, Q1, and R_LIM1. In the buck-boost regulator, both loops are discontinuous and require careful

attention to layout. Keep these loops as small as possible and the connections between all the components

short and thick to minimize parasitic inductance. In particular, make the switch node (where L1, D1 and Q1

connect) just large enough to connect the components. To minimize excessive heating, place large copper

pours adjacent to the short current path of the switch node.

•

The RT, COMP, ISNS, ICTRL, OVFB, ISP, and ISN pins are all high-impedance inputs which couple external

noise easily; therefore, minimize the loops containing these nodes whenever possible. In some applications,

the LED or LED array can be far away (several inches or more) from the TPS9260x-Q1 family of devices, or

on a separate PCB connected by a wiring harness. When using an output capacitor where the LED array is

large or separated from the rest of the regulator, place the output capacitor close to the LEDs to reduce the

effects of parasitic inductance on the ac impedance of the capacitor.

•

AGND and PGND must be separated and connected at the input GND connector.

The TPS9260x-Q1 family of devices has two independent channels. in order to avoid crosstalk, the POWER

GND of CH1 and CH2 must be separated and connected at the input GND connector.

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11.2 Layout Example

Trace on the top

Exposed

Thermal

Pad Area

Via of Signal Loop

Via of Power Ground

Via of Signal Ground

Trace on the bottom

For high-current paths, (thick traces on the diagram) keep loops as

small as possible and the connections between all the components

short and thick to minimize parasitic inductance.

C_px

ICTRL1

PWMO1

VOUT1

ISN1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1

VBAT

COMP1

OVFB1

RT

2

R_zx

C_zx

3

4

TPS92602-Q1

TPS92602A-Q1

ISP1

DIAG1

GND

PGND1

ISNS1

GDRV1

VCC

5

Current limit resistor GND

connected to PGND1

terminal with separate trace

6

PWMIN1

VIN

7

C_VIN

Separate the PGGNDx of both channels and connect to VCC GND.

8

PWMIN2

OVFB2

ICTRL2

COMP2

DIAG2

PWMO2

GDRV2

ISNS2

PGND2

ISP2

9

VBAT

10

11

12

13

14

ISN2

VOUT2

Power Ground on Bottom Layer

Signal Ground on Bottom Layer

Figure 27. TPS92602-Q1 Board Layout

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12 Device and Documentation Support

12.1 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to sample or buy.

Table 3. Related Links

TECHNICAL

DOCUMENTS

TOOLS &

SOFTWARE

SUPPORT &

COMMUNITY

PARTS

PRODUCT FOLDER

SAMPLE & BUY

TPS92601-Q1

TPS92602-Q1

Click here

12.2 Trademarks

PowerPAD is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.3 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.4 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most-

current data available for the designated devices. This data is subject to change without notice and without

revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

36

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PACKAGE MATERIALS INFORMATION

www.ti.com

11-Dec-2014

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS92601QPWPRQ1 HTSSOP PWP

TPS92602QPWPRQ1 HTSSOP PWP

20

28

3000

2000

330.0

16.4

6.95

6.9

7.1

1.6

1.8

8.0

16.0

Q1

10.2

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

11-Dec-2014

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS92601QPWPRQ1

TPS92602QPWPRQ1

HTSSOP

PWP

20

28

3000

2000

367.0

38.0

Pack Materials-Page 2

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TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of

non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.

Products

Applications

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www.ti.com/audio

amplifier.ti.com

dataconverter.ti.com

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Communications and Telecom www.ti.com/communications

Amplifiers

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DLP® Products

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www.ti.com/computers

www.ti.com/consumer-apps

www.ti.com/energy

dsp.ti.com

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Interface

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interface.ti.com

logic.ti.com

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www.ti.com/medical

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RFID

power.ti.com

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www.ti.com/space-avionics-defense

www.ti.com/video

microcontroller.ti.com

www.ti-rfid.com

www.ti.com/omap

OMAP Applications Processors

Wireless Connectivity

TI E2E Community

e2e.ti.com

www.ti.com/wirelessconnectivity

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS92601QPWPRQ1
厂家：	TEXAS INSTRUMENTS
描述：	汽车类单通道高侧电流感应开关模式 LED 驱动器 \| PWP \| 20 \| -40 to 125 开关驱动驱动器
文件：	总45页 (文件大小：1663K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS92601QPWPRQ1 [TI]

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