TPSI3052 [TI]

具有集成式 15V 栅极电源的隔离式开关驱动器;


型号：	TPSI3052
厂家：	TEXAS INSTRUMENTS
描述：	具有集成式 15V 栅极电源的隔离式开关驱动器开关栅驱动驱动器栅极
文件：	总44页 (文件大小：3103K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPSI3052

SLVSGS3A – APRIL 2022 – REVISED APRIL 2023

TPSI3052 Isolated Switch Driver with Integrated 15-V Gate Supply

The TPSI3052 supports two modes of operation

based on the number of input pins required. In

two-wire mode, typically found in driving mechanical

relays, controlling the switch requires only two pins

and supports a wide voltage range of operation of 6.5

V to 48 V. In three-wire mode, the primary supply of

3 V to 5.5 V is supplied externally, and the switch

is controlled through a separate enable. Available

in three-wire mode only, the TPSI3052S features a

one-shot enable for the switch control. This feature is

useful for driving SCRs that typically require only one

pulse of current to trigger.

1 Features

•

No isolated secondary supply required

Drives external power transistors or SCRs

3-kV_RMSbasic isolation

15-V gate drive with 1.5/3-A peak source and sink

current

•

Up to 50-mW supply for external auxiliary circuitry

Supports AC or DC switching

Supports two-wire or three-wire modes

Seven levels of power transfer, resistor selectable

Functional Safety-Capable

– Documentation available to aid functional safety

system design

Temperature range –40 to 125°C ambient

Safety-related certifications

– Planned: 4243-V_PKbasic isolation per DIN EN

IEC 60747-17 (VDE 0884-17)

– Planned: 3-kV_RMSisolation for 1 minute per UL

1577

The secondary side provides a regulated, floating

supply rail of 15 V for driving a large variety

of power switches with no need for a secondary

bias supply. The application can drive single power

switches for DC applications or dual back-to-back

power switches for AC applications, as well as various

types of SCR. The TPSI3052 integrated isolation

protection is extremely robust with much higher

reliability, lower power consumption, and increased

temperature ranges than traditional mechanical relays

and optocouplers.

•

2 Applications

•

Solid State Relays (SSR)

Building automation

Factory automation and control

The power transfer of the TPSI3052 can be adjusted

by selecting one of seven power level settings using

an external resistor from the PXFR pin to VSSP. This

action allows for tradeoffs in power dissipation versus

power provided on the secondary depending on the

needs of the application.

3 Description

The TPSI3052 is a fully integrated, isolated switch

driver, which when combined with an external power

switch, forms a complete isolated Solid State Relay

(SSR). With a nominal gate drive voltage of 15 V

with 1.5/3.0-A peak source and sink current, a large

variety of external power switches can be chosen to

meet a wide range of applications. The TPSI3052

generates its own secondary bias supply from the

power received from its primary side, so no isolated

secondary supply bias is required. Additionally, the

TPSI3052 can optionally supply power to external

supporting circuitry for various application needs.

Device Information

PART NUMBER

TPSI3052

PACKAGE⁽¹⁾

SOIC 8-pin (DWZ)

BODY SIZE (NOM)

7.50 mm × 5.85 mm

TPSI3052S

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

DC Link Pre-charge

DC Link

Cap

3–5.5 V

VDRV

VDDH

Micro

PWR

SIGNAL

PXFR

VDDP

3–5.5 V

VDDM

VSSS

VSSP

TPSI3052 Simplified Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPSI3052

SLVSGS3A – APRIL 2022 – REVISED APRIL 2023

www.ti.com

Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................4

6.4 Thermal Information....................................................5

6.5 Power Ratings.............................................................5

6.6 Insulation Specifications............................................. 5

6.7 Safety-Related Certifications...................................... 6

6.8 Safety Limiting Values.................................................7

6.9 Electrical Characteristics.............................................7

6.10 Switching Characteristics........................................10

6.11 Insulation Characteristic Curves............................. 12

6.12 Typical Characteristics............................................13

7 Parameter Measurement Information..........................15

8 Detailed Description......................................................17

8.1 Overview...................................................................17

8.2 Functional Block Diagram.........................................17

8.3 Feature Description...................................................17

8.4 Device Functional Modes..........................................24

9 Application and Implementation..................................25

9.1 Application Information............................................. 25

9.2 Typical Application.................................................... 25

9.3 Power Supply Recommendations.............................32

9.4 Layout....................................................................... 32

10 Device and Documentation Support..........................36

10.1 Related Links.......................................................... 36

10.2 Receiving Notification of Documentation Updates..36

10.3 Support Resources................................................. 36

10.4 Trademarks.............................................................36

10.5 Electrostatic Discharge Caution..............................36

10.6 Glossary..................................................................36

11 Mechanical, Packaging, and Orderable

Information.................................................................... 36

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision * (April 2022) to Revision A (April 2023)

Page

•

Changed device status from Advance Information to Production Data .............................................................1

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5 Pin Configuration and Functions

VDRV

PXFR

VDDP

VSSP

VDDH

VDDM

VSSS

Figure 5-1. TPSI3052, TPSI3052S 8-Pin SOIC Top View

Table 5-1. Pin Functions

I/O

TYPE⁽¹⁾

DESCRIPTION

NO.

NAME

—

Active high driver enable

Power transfer can be adjusted by selecting one of seven power level settings

using an external resistor from the PXFR pin to VSSP. In three-wire mode, a

given resistor setting sets the duty cycle of the power converter (see Table 8-1)

and hence the amount of power transferred. In two-wire mode, a given resistor

setting adjusts the current limit of the EN pin (see Table 8-2) and hence the

amount of power transferred.

PXFR

—

VDDP

VSSP

VSSS

VDDM

VDDH

VDRV

—

GND

Power supply for primary side

Ground supply for primary side

Ground supply for secondary side

Generated mid supply

Generated high supply

—

Active high driver output

(1) P = power, GND = ground, NC = no connect

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

PARAMETER⁽¹⁾

MIN

MAX

UNIT

Primary Side

VDDP

–0.3

Supply⁽²⁾

Primary Side

–0.3

Supply⁽²⁾

Primary Side

PXFR

Supply⁽²⁾

Secondary

VDRV

Side Supply⁽³⁾

Secondary

VDDH

Side Supply⁽³⁾

Secondary

VDDM

Side Supply⁽³⁾

Secondary

VDDH-VDDM

Side Supply⁽³⁾

Junction

temperature, Junction temperature, T_J

T_J

–40

–65

150

°C

Storage temperature, T_stg

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.

If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) All voltage values are with respect to VSSP.

(3) All voltage values are with respect to VSSS.

6.2 ESD Ratings

VALUE

±2000

±750

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽⁽²⁾⁾

V_(ESD)

Electrostatic discharge

Corner pins (1, 4, 5, and 8)

Other pins

Charged device model (CDM), per ANSI/

ESDA/JEDEC JS-002⁽⁽³⁾⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

Manufacturing with less than 500-V HBM is possible if necessary precautions are taken.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

Manufacturing with less than 250-V CDM is possible if necessary precautions are taken.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

3.0

NOM

MAX

5.5

48.0

5.5

330

UNIT

VDDP

Primary side supply voltage in three-wire mode⁽⁽¹⁾⁾

Enable in two-wire mode⁽¹⁾

Enable in three-wire mode⁽¹⁾

PXFR

C_VDDP

Power transfer control⁽⁽¹⁾⁾

Decoupling capacitance on VDDP and VSSP, two-wire mode⁽³⁾

Decoupling capacitance on VDDP and VSSP, three-wire mode⁽³⁾

Decoupling capacitance across VDDH and VDDM⁽³⁾

Decoupling capacitances across VDDM and VSSS⁽³⁾

Ambient operating temperature

220

0.22

0.004

0.012

–40

µF

°C

(2)

C_DIV1

C_DIV2

T_A

(2)

125

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6.3 Recommended Operating Conditions (continued)

over operating free-air temperature range (unless otherwise noted)

MIN

–40

NOM

MAX

UNIT

°C

T_J

Operating junction temperature

150

|ΔV_EN/Δt|

EN rise and fall rates, two-wire mode.

V/ms

(1) All voltage values are with respect to VSSP.

(2) C_DIV1and C_DIV2should be of same type and tolerance. C_DIV2capacitance value should be at least three times the capacitance value of

C_DIV1i.e. C_DIV2≥ 3 x C_DIV1

(3) All capacitance values are absolute. Derating should be applied where necessary.

6.4 Thermal Information

DEVICE

DWZ(SOIC)

8 PINS

89.3

THERMAL METRIC^{(1) (2)}

UNIT

R_ϴJA

R_ϴJC(top)

R_ΘJB

ψ_JT

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

40.3

45.2

Junction-to-top characterization parameter

Junction-to-board characterization parameter

10.3

Ψ_JB

44.4

(1) Estimate only.

(2) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Power Ratings

PARAMETER

TEST CONDITIONS

V_VDDP= 5 V,

MIN

TYP

MAX

UNIT

R_PXFR= 20 kΩ, three-wire mode,

C_VDRV= 100 pF,

C_DIV1= 33 nF, C_DIV2= 100 nF

f_EN= 1-kHz square wave, V_EN= 5 V peak

to peak.

Maximum power dissipation, VDDP.

250

P_D

R_PXFR= 20 kΩ, two-wire mode,

C_VDRV= 100 pF,

Maximum power dissipation, EN.

C_DIV1= 33 nF, C_DIV2= 100 nF

f_EN= 1-kHz square wave, V_EN= 48 V

peak to peak.k.

350

6.6 Insulation Specifications

SPECIFIC

ATION

PARAMETER

TEST CONDITIONS

UNIT

CREEPAGE AND TRACKING

CLR

CPG

External clearance⁽¹⁾

Shortest terminal-to-terminal distance through air ≥ 8.5

Shortest terminal-to-terminal distance across the

External Creepage⁽¹⁾

≥ 8.5

package surface

DTI

CTI

Distance through the insulation

Comparative tracking index

Material Group

Minimum internal gap (internal clearance)

DIN EN 60112 (VDE 0303-11); IEC 60112

According to IEC 60664-1

≥ 120

≥ 600

µm

Rated mains voltage ≤ 600 V_RMS

Rated mains voltage ≤ 1000 V_RMS

I-IV

I-III

Overvoltage category per IEC 60664-1

DIN EN IEC 60747-17 (VDE 0884-17)

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UNIT

SLVSGS3A – APRIL 2022 – REVISED APRIL 2023

6.6 Insulation Specifications (continued)

SPECIFIC

ATION

PARAMETER

TEST CONDITIONS

AC voltage (bipolar)

V_IORM

V_IOWM

Maximum repetitive peak isolation voltage

Maximum isolation working voltage

1414

1000

1414

4243

V_PK

V_RMS

V_DC

AC voltage (sine wave)

DC voltage

V_TEST= V_IOTM; t = 60 s (qualification test)

V_PK

V_IOTM

Maximum transient isolation voltage

V_TEST= 1.2 × V_IOTM; t = 1 s (100% production

test)

5091

4500

5850

V_PK

Tested in air;

1.2/50-µs waveform per IEC 62638-1

V_IMP

Maximum impulse voltage⁽⁽³⁾⁾

Tested in oil (qualification test);

1.2/50-µs waveform per IEC 62638-1

V_IOSM

Maximum surge isolation voltage⁽⁽³⁾⁾

Method a: After input-output safety test subgroup

2/3,

V_ini= V_IOTM, t_ini= 60 s;

≤ 5

V_pd(m)= 1.2 × V_IORM, t_m= 10 s.

Method a: After environmental tests subgroup 1,

V_ini= V_IOTM, t_ini= 60 s;

V_pd(m)= 1.3 × V_IORM, t_m= 10 s.

q_pd

Apparent charge⁽⁽⁴⁾⁾

Method b1: At routine test (100% production test)

and preconditioning (type test), V_ini= V_IOTM, t_ini

1 s;

V_pd(m)= 1.5 × V_IORM, t_m= 1 s.

C_IO

R_IO

Barrier capacitance, input to output⁽⁵⁾

Insulation resistance, input to output⁽⁵⁾

V_IO= 0.4 × sin (2πft), f = 1 MHz

V_IO= 500 V, T_A= 25°C

> 10¹²

> 10¹¹

> 10⁹

V_IO= 500 V, 100°C ≤ T_A≤ 125°C

V_IO= 500 V at T_S= 150°C

Pollution degree

Climatic category

40/125/21

UL 1577

(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.

Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the

isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal

in certain cases. Techniques such as inserting grooves, ribs, or both on a printed-circuit board are used to help increase these

specifications.

(2) Testing is carried out in air to determine the intrinsic surge immunity of the package.

(3) Testing is carried out in oil to determine the intrinsic surge immunity of the isolation barrier.

(4) Apparent charge is electrical discharge caused by a partial discharge (pd).

(5) All pins on each side of the barrier tied together creating a two-pin device.

6.7 Safety-Related Certifications

VDE

Plan to certify according to DIN EN IEC 60747-17 (VDE 0884-17)

Plan to certify under UL 1577 Component Recognition Program

Basic insulation; Maximum transient isolation voltage, 4243 V_PK

;

Maximum repetitive peak isolation voltage, 1414 V_PK; Maximum

surge isolation voltage, 5850 V_PK

Single protection, 3000 V_RMS

Certificate planned

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6.8 Safety Limiting Values

PARAMETER^{(1) (2)}

TEST CONDITIONS

MIN

TYP

MAX

UNIT

R_θJA= 89.3°C/W, V_VDDP= 5.5 V,

T_J= 150°C, T_A= 25°C,

three-wire mode.

254

R_θJA= 89.3°C/W, V_EN= 24 V,

T_J= 150°C, T_A= 25°C,

two-wire mode.

I_S

Safety input, output, or supply current

R_θJA= 89.3°C/W, V_EN= 48 V,

T_J= 150°C, T_A= 25°C,

two-wire mode.

R_θJA= 89.3°C/W,

T_J= 150°C, T_A= 25°C.

P_S

T_S

Safety input, output, or total power

Maximum safety temperature

1.4

150

°C

(1) Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the

I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and

damage the isolation barrier, potentially leading to secondary system failures.

(2) The safety-limiting constraint is the maximum junction temperature specified in the data sheet. The power dissipation and junction-

to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed

junction-to-air thermal resistance in the Thermal Information table is that of a device installed on a high-K test board for leaded

surface-mount packages. The power is the recommended maximum input voltage times the current. The junction temperature is then

the ambient temperature plus the power times the junction-to-air thermal resistance.

6.9 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted). Typicals at T_A= 25℃. C_VDDP= 220 nF (two-wire mode),

C_VDDP= 1 µF (three-wire mode) , C_DIV1= 5.1 nF, C_DIV2= 15 nF, C_VDRV= 100 pF, R_PXFR= 7.32 kΩ ±1%

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

COMMON

VDDP under-voltage threshold

rising

V_{VDDP_UV_R}

VDDP rising

2.50

2.35

2.70

2.55

2.90

2.75

VDDP under-voltage threshold

falling

V_{VDDP_UV_F}

V_{VDDP_UV_HYS}

V_{VDDH_UV_R}

VDDP falling

VDDP under-voltage threshold

hysteresis

VDDH under-voltage threshold

rising

VDDH rising.

VDDH falling.

12.5

9.9

13.4

10.9

VDDH under-voltage threshold

falling.

V_{VDDH_UV_F}

10.4

VDDH under-voltage threshold

hysteresis.

V_{VDDH_UV_HYS}

V_{VDDM_UV_R}

V_{VDDM_UV_F}

V_{VDDM_UV_HYS}

I_{Q_VDDH}

2.5

3.3

VDDM under-voltage threshold

rising

VDDM rising.

VDDM falling.

2.8

2.6

3.7

3.5

VDDM under-voltage threshold

falling

VDDM under-voltage threshold

hysteresis.

0.3

Internal quiescent current of VDDH

supply.

µA

Ω

Force V_VDDH= 15 V,

sink I_VDRV= 50 mA.

Driver on resistance in low state.

Driver on resistance in high state.

1.7

2.5

R_{DSON_VDRV}

Force V_VDDH= 15 V,

source I_VDRV= 50 mA.

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6.9 Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted). Typicals at T_A= 25℃. C_VDDP= 220 nF (two-wire mode),

C_VDDP= 1 µF (three-wire mode) , C_DIV1= 5.1 nF, C_DIV2= 15 nF, C_VDRV= 100 pF, R_PXFR= 7.32 kΩ ±1%

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

VDRV peak output current during

rise

V_VDDHin steady state, transition EN

low to high, measure peak current.

1.5

I_{VDRV_PEAK}

VDRV peak output current during

fall

V_VDDHin steady state, transition EN

high to low, measure peak current.

TSD

Temperature shutdown

173

℃

TSDH

Temperature shutdown hysteresis

CMTI

Common-mode transient immunity |V_CM| = 1000 V

100

6.5

V/ns

TWO-WIRE MODE

Minimum voltage on EN to be

detected as a valid logic high.

V_{IH_EN}

Maximum voltage on EN to be

detected as a valid logic low.

V_{IL_EN}

2.0

I_{EN_START}

Enable current at startup

EN = 0 V → 6.5 V

EN = 6.5 V,

R_PXFR= 7.32 kΩ,

R_PXFR≥100 kΩ or R_PXFR≤1 kΩ,

V_VDDHin steady state.

1.9

I_EN

Enable current steady state

EN = 6.5 V,

R_PXFR= 20 kΩ,

V_VDDHin steady state.

6.8

EN = 6.5 V,

V_{VDDP_AVG}

VDDP average voltage.

VDDH output voltage

V_VDDHin steady state,

measure average VDDP voltage.

4.5

EN = 6.5 V,

V_VDDHin steady state.

V_VDDH

13.9

16.2

EN = 6.5 V,

V_VDDHin steady state,

no DC loading.

V_{VDRV_H}

VDRV output voltage driven high

EN = 6.5 V → 0 V,

V_VDDHin steady state,

sink 10 mA load.

V_{VDRV_L}

VDRV output voltage driven low

0.1

5.5

EN = 6.5 V, steady state.

R_PXFR= 7.32 kΩ,

R_PXFR≥ 100 kΩ or R_PXFR≤ 1 kΩ,

C_DIV1= 75 nF, C_DIV2= 220 nF,

source 0.20 mA from VDDM,

measure VDDM voltage.

Average VDDM voltage when

sourcing external current.

4.6

V_{VDDM_IAUX}

EN = 6.5 V, steady state.

R_PXFR= 20 kΩ,

C_DIV1= 75 nF, C_DIV2= 220 nF,

source 1.2 mA from VDDM,

measure VDDM voltage.

Average VDDM voltage when

sourcing external current.

5.5

THREE-WIRE MODE

Minimum voltage on EN to

be detected as a valid logic

high. V_IH(min)= 0.7 x V_VDDP

V_VDDP= 3 V

2.1

V_{IH_EN}

V_VDDP= 5.5 V

3.85

V_VDDP= 3 V

0.9

Maximum voltage on EN to be

detected as a valid logic low.

V_{IL_EN}

V_VDDP= 5.5 V

1.65

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6.9 Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted). Typicals at T_A= 25℃. C_VDDP= 220 nF (two-wire mode),

C_VDDP= 1 µF (three-wire mode) , C_DIV1= 5.1 nF, C_DIV2= 15 nF, C_VDRV= 100 pF, R_PXFR= 7.32 kΩ ±1%

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

EN = 3.3 V,

V_VDDP= 3.3 V,

R_PXFR= 7.32 kΩ,

R_PXFR≥ 100 kΩ or R_PXFR≤ 1 kΩ,

C_VDDP= 10 µF,

3.1

V_VDDHin steady state,

measure I_VDDP

EN = 3.3 V,

V_VDDP= 3.3 V,

R_PXFR= 20 kΩ,

C_VDDP= 10 µF,

V_VDDHin steady state,

4.8

measure I_VDDP

VDDP average current in steady

state

I_VDDP

EN = 5 V,

V_VDDP= 5 V,

R_PXFR= 7.32 kΩ,

R_PXFR≥ 100 kΩ or R_PXFR≤ 1 kΩ,

C_VDDP= 10 µF,

V_VDDHin steady state,

measure I_VDDP

EN = 5 V,

V_VDDP= 5 V,

R_PXFR= 20 kΩ,

C_VDDP= 10 µF,

V_VDDHin steady state,

measure I_VDDP

V_VDDP= 3.3 V, EN = 0.0 V, steady

state.

R_PXFR= 7.32 kΩ,

Average VDDM voltage when

sourcing external current.

C_DIV1= 75 nF,

C_DIV2= 220 nF,

Source 0.35 mA from VDDM

measure V_VDDM

V_{VDDM_IAUX}

4.6

5.5

V_VDDP= 5.0 V, EN = 0.0 V, steady

state.

R_PXFR= 7.32 kΩ,

C_DIV1= 75 nF,

C_DIV2= 220 nF,

Average VDDM voltage when

sourcing external current.

Source 0.50 mA from VDDM

measure V_VDDM

V_VDDP= 3.3 V, EN = 0.0 V, steady

state.

R_PXFR= 20 kΩ

C_DIV1= 75 nF,

C_DIV2= 220 nF,

Average VDDM voltage when

sourcing external current.

Source 3.0 mA from VDDM

measure V_VDDM

V_VDDP= 5.0 V, EN = 0.0 V, steady

state.

R_PXFR= 20 kΩ

C_DIV1= 75 nF

C_DIV2= 220 nF

Average VDDM voltage when

sourcing external current.

Source 5.0 mA from VDDM

measure V_VDDM

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6.9 Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted). Typicals at T_A= 25℃. C_VDDP= 220 nF (two-wire mode),

C_VDDP= 1 µF (three-wire mode) , C_DIV1= 5.1 nF, C_DIV2= 15 nF, C_VDRV= 100 pF, R_PXFR= 7.32 kΩ ±1%

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_VDDP= 3.0 V,

V_VDDH

VDDH output voltage

EN = 3.0 V,

V_VDDHin steady state.

13.9

16.2

V_VDDP= 3.0 V,

EN = 3.0 V,

V_VDDHin steady state,

no DC loading.

V_{VDRV_H}

VDRV output voltage driven high

VDRV output voltage driven low

13.9

V_VDDP= 3.0 V,

EN = 0 V,

V_VDDHin steady state,

VDRV sinking 10 mA.

V_{VDRV_L}

0.1

6.10 Switching Characteristics

over operating free-air temperature range (unless otherwise noted). Typicals at T_A= 25℃. C_VDDP= 220 nF (two-wire mode),

C_VDDP= 1 µF (three-wire mode) , C_DIV1= 5.1 nF, C_DIV2= 15 nF, C_VDRV= 100 pF, R_PXFR= 7.32 kΩ ±1%

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

TWO-WIRE MODE

t_{LO_EN}

Low time of EN.

µs

Propagation delay time from EN

rising to VDDH at 50% level.

EN = 0 V → 6.5 V,

V_VDDH= 7.5 V.

t_{LH_VDDH}

t_{LH_VDRV}

t_{HL_VDRV}

t_{R_VDRV}

165

185

2.4

Propagation delay time from EN

rising to VDRV at 90% level.

EN = 0 V → 6.5 V,

V_VDRV= 13.5 V.

µs

Propagation delay time from EN

falling to VDRV at 10% level.

EN = 6.5 V → 0 V,

V_VDRV= 1.5 V.

µs

VDRV rise time from EN rising to

VDRV from 15% to 85% level.

EN = 0 V → 6.5 V,

V_VDRV= 2.25 V to 12.75 V.

VDRV fall time from EN falling to

VDRV from 85% to 15% level.

EN = 6.5 V → 0 V,

V_VDRV= 12.75 V to 2.25 V.

t_{F_VDRV}

THREE-WIRE MODE

t_{LO_EN}

V_VDDP= 3.3 V, V_VDDH= steady

state.

Low time of EN.

High time of EN.

µs

V_VDDP= 3.3 V, V_VDDH= steady

state.

t_{HI_EN}

High time of VDRV in one-shot

enable mode.

t_{HI_VDRV}

TPSI3052S only.

One-shot enable only available in

three-wire mode.

V_VDDP= 3.3 V, steady state.

EN = 0 V,

2.5

µs

Propagation delay time from VDDP V_VDDP= 0 V → 3.3 V at 1 V/µs,

t_{LH_VDDH}

t_{LH_VDRV}

t_{HL_VDRV}

µs

rising to VDDH at 50% level.

V_VDDH= 7.5 V.

C_DIV1= 3.3 nF, C_DIV2= 220 nF.

V_VDDP= 3.3 V,

Propagation delay time from EN

rising to VDRV at 90% level

V_VDDHsteady state,

EN = 0 V → 3.3 V,

V_VDRV= 13.5 V.

4.5

V_VDDP= 3.3 V,

Propagation delay time from EN

falling to VDRV at 10% level

V_VDDHsteady state,

EN = 3.3 V → 0 V,

V_VDRV= 1.5 V.

2.5

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6.10 Switching Characteristics (continued)

over operating free-air temperature range (unless otherwise noted). Typicals at T_A= 25℃. C_VDDP= 220 nF (two-wire mode),

C_VDDP= 1 µF (three-wire mode) , C_DIV1= 5.1 nF, C_DIV2= 15 nF, C_VDRV= 100 pF, R_PXFR= 7.32 kΩ ±1%

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Propagation delay time from VDDP

falling to VDRV at 10% level.

Timeout mechanism due to loss of

power on primary supply.

EN = 3.3 V,

V_VDDP= 3.3 V → 0 V at -1 V/µs,

V_VDRV= 1.5 V.

t_{HL_VDRV_PD}

300

µs

V_VDDP= 3.3 V,

VDRV rise time from EN rising to

VDRV from 15% to 85% level

V_VDDHsteady state,

EN = 0 V → 3.3 V,

V_VDRV= 2.25 V to 12.75 V.

t_{R_VDRV}

V_VDDP= 3.3 V,

VDRV fall time from EN falling to

VDRV from 85% to 15% level

V_VDDHsteady state,

EN = 3.3 V → 0 V,

V_VDRV= 12.75 V to 2.25 V.

t_{F_VDRV}

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6.11 Insulation Characteristic Curves

300

280

260

240

220

200

180

160

140

120

100

V_EN= 24 V

V_EN= 48 V

100

125

150

100

125

150

T_A(C)

Figure 6-1. Thermal Derating Curve for Limiting

Current per VDE and IEC, Three-Wire Mode

Figure 6-2. Thermal Derating Curve for Limiting

Current per VDE and IEC, Two-Wire Mode

1500

1400

1300

1200

1100

1000

900

800

700

600

500

400

300

200

100

125

150

T_A(C)

Figure 6-3. Thermal Derating Curve for Limiting Power per VDE and IEC

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6.12 Typical Characteristics

V_EN

V_VDDM

V_VDDH

V_VDRV

V_VDDM

V_VDDH

V_VDRV

-1

Time (s)

Three-wire mode

C_DIV1= 5.1 nF

C_DIV2=15 nF

VDDP = 5.0 V

C_VDRV= 100 pF

C_VDDP= 1 μF

R_PXFR= 7.32 kΩ

T_A= 25°C

Three-wire mode

VDDP = 5.0 V

C_VDRV= 100 pF

C_VDDP= 1 μF

R_PXFR= 7.32 kΩ

T_A= 25°C

C_DIV1= 5.1 nF

C_DIV2=15 nF

I_AUX= 0 mA

Figure 6-4. t_{LH_VDRV}, Three-Wire Mode

Figure 6-5. t_{HL_VDRV}, Three-Wire Mode

4.8

4.6

4.4

4.2

4.9

4.8

4.7

4.6

4.5

4.4

4.3

4.2

4.1

T_A= 25C

T_A= 125C

T_A= 25C

T_A= 125C

3.8

3.6

3.4

3.2

100

C_VDRV(nF)

Three-wire mode

C_DIV1= 2.2 μF

VDDP = 3.3 V

C_DIV2= 2.2 μF

R_PXFR= 7.32 kΩ

Three-wire mode

C_DIV1= 2.2 μF

VDDP = 3.3 V

C_DIV2= 2.2 μF

R_PXFR= 7.32 kΩ

Figure 6-6. t_{LH_VDRV}versus C_VDRV

Figure 6-7. t_{HL_VDRV}versus C_VDRV

V_EN

V_VDDM

V_VDDH

V_VDRV

V_VDDM

V_VDDH

V_VDRV

-1

-0.3

0.3

0.6

0.9

1.2

1.5

1.8

2.1

2.4

2.7

-100 -50

50 100 150 200 250 300 350 400 450 500 550 600

Time (ms)

Two-wire mode

EN = 12 V

R_PXFR= 7.32 kΩ

T_A= 25°C

Two-wire mode

EN = 12 V

R_PXFR= 7.32 kΩ

T_A= 25°C

C_DIV1= 33 nF

C_DIV2=100 nF

C_VDRV= 100 pF

C_VDDP= 220 nF

C_DIV1= 33 nF

C_DIV2=100 nF

C_VDRV= 100 pF

C_VDDP= 220 nF

I_AUX= 0 mA

Figure 6-8. t_{LH_VDRV}, Two-Wire Mode

Figure 6-9. t_{HL_VDRV}, Two-Wire Mode

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6.12 Typical Characteristics (continued)

22.5

R_PXFR= 7.32 k

R_PXFR= 9.09 k

R_PXFR= 11 k

R_PXFR= 12.7 k

R_PXFR= 14.7 k

R_PXFR= 16.5 k

R_PXFR= 20 k

R_PXFR= 9.09 k

R_PXFR= 11 k

R_PXFR= 12.7 k

R_PXFR= 14.7 k

R_PXFR= 16.5 k

R_PXFR= 20 k

17.5

12.5

7.5

2.5

100

150

200

250

300

350

400

450

500

100

150

200

250

300

350

400

450

500

C_DIV1(nF), (C_DIV2= 3 x C_DIV1

)

C_DIV1(nF), (C_DIV2= 3 x C_DIV1)

t_STARTrepresents the time from VDDP rising to VDDM and

VDDH fully discharged rails reaching > 95% of their final levels.

t_STARTrepresents the time from VDDP rising to VDDM and

VDDH fully discharged rails reaching > 95% of their final levels.

Three-wire mode

I_AUX= 0 mA

VDDP = 5.0 V

T_A= 25°C

Three-wire mode

I_AUX= 0 mA

VDDP = 3.3 V

T_A= 25°C

Figure 6-10. t_STARTversus C_DIV1, C_DIV2

Figure 6-11. t_STARTversus C_DIV1, C_DIV2

100

R_PXFR= 7.32 k

R_PXFR= 9.09 k

R_PXFR= 11 k

R_PXFR= 12.7 k

R_PXFR= 14.7 k

R_PXFR= 16.5 k

R_PXFR= 20 k

0.01

0.03

0.05

0.07

0.09

0.11

0.13

0.15

0.17

0.19

1/Q_LOAD(nC)^-1

Three-wire mode

I_AUX= 0 mA

VDDP = 5.0 V

T_A= 25°C

Three-wire mode

I_AUX= 0 mA

VDDP = 5.0 V

T_A= 25°C

Figure 6-13. Max. f_ENversus Q_LOAD= 100 nC to 1000 nC

Figure 6-12. Max. f_ENversus Q_LOAD= 10 nC to 100 nC

V_VDDP= 3.3 V

V_VDDP= 5 V

V_VDDP= 3.3 V

V_VDDP= 5 V

5.5

5.75

5.5

5.25

4.75

4.5

4.25

4.75

4.5

4.25

3.75

3.5

3.25

3.75

3.5

3.25

2.75

2.5

2.25

2.75

2.5

2.25

1.75

1.5

1.75

1.5

10 11 12 13 14 15 16 17 18

0.5

1.5

2.5

3.5

4.5

5.5

6.5

I_AUX(mA)

Three-wire mode

C_DIV1= 150 nF

R_PXFR= 20 kΩ

C_DIV2= 470 nF

T_A= 25°C

Three-wire mode

C_DIV1= 150 nF

R_PXFR= 11 kΩ

C_DIV2= 470 nF

T_A= 25°C

C_VDDP= 1 μF

Figure 6-14. V_VDDMversus I_AUX

Figure 6-15. V_VDDMversus I_AUX

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7 Parameter Measurement Information

50%

t_{LH_VDDH}

50%

VDDH

t_{LH_VDRV}

90%

85%

t_{F_VDRV}

15%

10%

VDRV

t_{R_VDRV}

t_{HL_VDRV}

Figure 7-1. Two-Wire Mode Timing, Standard Enable (TPSI3052 Only)

50%

t_{LH_VDDH}

VDDP

50%

VDDH

t_{HI_EN}

t_{LO_EN}

50%

t_{HL_VDRV_PD}

t_{LH_VDRV}

90%

t_{F_VDRV}

85%

15%

10%

15%

t_{R_VDRV}

10%

VDRV

t_{HL_VDRV}

Figure 7-2. Three-Wire Mode Timing, Standard Enable (TPSI3052 Only)

50%

VDDP

t_{LH_VDDH}

50%

VDDH

t_{HI_EN}

t_{LO_EN}

50%

t_{LH_VDRV}

50%

t_{HL_VDRV_PD}

t_{F_VDRV}

90%

85%

50%

15%

85%

50%

15%

10%

VDRV

t_{R_VDRV}

t_{HI_VDRV}

Figure 7-3. Three-Wire Mode Timing, One-Shot Enable (TPSI3052S Only)

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Pass/Fail criteria: Output

must remain stable.

PXFR

VDRV

VDDH

V_VDRV

VDDP

C_DIV1

C_VDRV

C_VDDP

R_PXFR

VSSP

VDDM

VSSS

Modulator

C_DIV2

GNDO

GNDI

+ V_CM

Figure 7-4. Common-Mode Transient Immunity Test Circuit

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8 Detailed Description

8.1 Overview

The TPSI3052 is a fully integrated, isolated power switch driver, which when combined with an external power

switch, forms a complete isolated Solid State Relay (SSR). With a nominal gate drive voltage of 15 V and

1.5/3.0-A peak source and sink current, a large variety of external power switches can be chosen to meet a

wide range of applications. The TPSI3052 generates its own secondary supply from the power received from its

primary side, so no isolated secondary bias supply is required.

The Functional Block Diagram shows the primary side that includes a transmitter that drives an alternating

current into the primary winding of an integrated transformer at a rate determined by the setting of the PXFR pin

and the logic state of the EN pin. The transmitter operates at high frequency to optimally drive the transformer

to its peak efficiency. In addition, the transmitter uses spread spectrum techniques to greatly improve EMI

performance, allowing many applications to achieve CISPR 25 - Class 5. During transmission, data information

transfers to the secondary side alongside with the power. On the secondary side, the voltage induced on the

secondary winding of the transformer is rectified, and the shunt regulator regulates the output voltage level of

VDDH. Lastly, the demodulator decodes the received data information and drives VDRV high or low based on

the logic state of the EN pin.

8.2 Functional Block Diagram

VDRV

PXFR

VDDP

VDDH

VDDM

Modulator

VSSP

VSSS

8.3 Feature Description

8.3.1 Transmission of the Enable State

The TPSI3052 and TPSI3052S use a modulation scheme to transmit the switch enable state information across

the isolation barrier. The transmitter modulates the EN signal with an internally generated, high frequency carrier

(89-MHz typical), and differentially drives the primary winding of the isolation transformer. The receiver on the

secondary side demodulates the received signal and asserts VDRV high or low based on the data received.

8.3.2 Power Transmission

The TPSI3052 and TPSI3052S do not use an isolated supply for their power. The secondary side power is

obtained by the transferring of the primary side input power across the isolation transformer. The modulation

scheme uses spread spectrum of the high frequency carrier (89-MHz typical) to improve EMI performance

assisting applications in meeting the CISPR 25 Class 5 standards.

8.3.3 Gate Driver

The TPSI3052 and TPSI3052S have an integrated gate driver that provides a nominal 15-V gate voltage

with 1.5/3.0-A peak source and sink current sufficient for driving many power transistors or Silicon-Controlled

Rectifiers (SCR). When driving external power transistors, TI recommends bypass capacitors (C_DIV2= 3 * C_DIV1

)

from VDDH to VDDM and VDDM to VSSS of 20 times the equivalent gate capacitance.

The gate driver also includes an active clamp keep off circuit. This feature helps to keep the driver output, VDRV,

low should power be lost on the secondary supply rails e.g. power loss on the VDDP supply prevents power

transfer. Should power be lost, the active clamp keep off circuit will attempt to clamp the voltage of VDRV to

under 2 V relative to VSSS.

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8.3.4 Modes Overview

The TPSI3052 and TPSI3052S have two modes of operation: two-wire mode and three-wire mode.

In two-wire mode, the power on the primary side is provided directly by the EN pin. Setting EN high causes

power transfer to the secondary side. As power transfers, the secondary rails, VDDM and VDDH, begin to rise.

After sufficient power is available on the secondary side, VDRV is asserted high. Setting EN low causes VDRV

to assert low and halts power transfer to the secondary side.

In three-wire mode, the power on the primary side is provided by a dedicated, low output impedance supply

connected to VDDP. In this case, power transfer is independent from the enable state. If VDDP power is present,

power is transferred from the primary side to the secondary side regardless of the EN state. In steady state

conditions, when sufficient power is available on the secondary side, setting EN high causes VDRV to assert

high. Setting EN low causes VDRV to assert low.

In standard enable, available only on the TPSI3052, VDRV follows the state of the EN pin and is used in most

load switch applications. In one-shot enable mode, available only on the TPSI3052S in three-wire mode, when a

rising transition occurs on EN, VDRV is asserted high momentarily and then automatically asserted low, forming

a one-shot pulse on VDRV. This event is useful for driving SCR devices that require only one burst of power to

trigger. To re-trigger VDRV, EN must first transition low, followed by another rising transition.

8.3.5 Three-Wire Mode

Three-wire mode is used for applications that require higher levels of power transfer or the shortest propagation

delay TPSI3052 can offer. VDDP is supplied independently from the EN pin by a low output impedance external

supply that can deliver the required power. In this mode, power from the primary side to the secondary side

always occurs regardless of the state of the EN pin. Setting the EN pin logic high or low asserts or de-asserts

VDRV, thereby enabling or disabling the external switch, respectively. Figure 8-1 shows the basic setup required

for three-wire mode operation which requires EN, VDDP, and VSSP signals. EN can be driven up to 5.5 V

which is normally driven from the circuitry residing on the same rail as VDDP. In this example, the TPSI3052

is being used to drive back-to-back MOSFETs in a common-source configuration. C_VDDPprovides the required

decoupling capacitance for the VDDP supply rail of the device. C_DIV1and C_DIV2provide the required decoupling

capacitances of the VDDH and VDDM supply rails that provide the peak current to drive the external MOSFETs.

Figure 8-2 and Figure 8-3 show the basic operation from start-up to steady-state conditions. Figure 8-2 shows

operation using standard enable of the TPSI3052. After power up, the TPSI3052 begins to transfer power from

VDDP to the secondary side for a fixed time period (25-μs typical) at a duty cycle rate determined by R_PXFR

which begins to charge up the VDDH (and VDDM) secondary side rails. Power transfer continues as long as

VDDP is present. The time required to fully charge VDDH depends on several factors including the values of

VDDP, C_DIV1, C_DIV2, R_PXFR, and the overall power transfer efficiency. When the application drives the EN pin

to a logic high, the TPSI3052 signals information from the primary side to the secondary side to assert VDRV

and drive it high. Similarly, setting EN pin to a logic low causes VDRV to be driven low. Figure 8-3 shows

operation using one-shot enable of the TPSI3052S. The start-up behavior is identical. In one-shot enable, when

the application drives the EN pin to a logic high, VDRV is asserted high (t_{HI_VDRV}), then is automatically asserted

low by the TPSI3052S. To assert VDRV high again, the EN pin must transition low first, followed by a transition

high.

3–5.5 V

Micro

VDRV

PWR

R_PXFR

SIGNAL

PXFR

VDDP

VDDH

VDDM

VSSS

C_DIV1

3–5.5 V

C_VDDP

C_DIV2

VSSP

Figure 8-1. Three-Wire Mode Simplified Schematic

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VDDP

V_VDDH

VDDH

V_{VDRV_H}

VDRV

Figure 8-2. Three-Wire Mode with TPSI3052 (Standard Enable)

VDDP

V_VDDH

VDDH

V_{VDRV_H}

VDRV

Figure 8-3. Three-Wire Mode with TPSI3052S (One-shot Enable)

To reduce average power, the TPSI3052 transfers power from the primary side to the secondary side in a

burst fashion. The period of the burst is fixed while the burst on time is programmable by selecting one of

seven appropriate resistor values, R_PXFR, from the PXFR to VSSP pins, thereby changing the duty cycle of the

power converter. This action provides flexibility in the application, allowing tradeoffs in power consumed versus

power delivered. Higher power converter settings increase the burst on time which, in turn, increases average

power consumed from the VDDP supply and increases the amount of power transferred to the secondary side

VDDH and VDDM supplies. Similarly, lower power converter settings decrease the burst on time which, in turn,

decreases average power consumed from the VDDP supply and decreases the amount of power transferred to

the secondary side.

Table 8-1 summarizes the three-wire mode power transfer selection.

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Table 8-1. Three-Wire Mode Power Transfer Selection

Power Converter Duty Cycle

(Three-Wire Mode, Nominal)

(1) (2)

R_PXFR

Description

7.32 kΩ

13.3%

26.7%

40.0%

53.3%

66.7%

80.0%

93.3%

The device supports seven, fixed power transfer settings, by selection of a

corresponding R_PXFRvalue . Selecting a given power transfer setting adjusts the

duty cycle of the power converter and hence the amount of power transferred.

Higher power transfer settings leads to an increased duty cycle of the power

converter leading to increased power transfer and consumption. During power

up, the power transfer setting is determined and remains fixed at that setting until

VDDP power cycles.

9.09 kΩ

11 kΩ

12.7 kΩ

14.7 kΩ

16.5 kΩ

20 kΩ

(1) Standard resistor (EIA E96), 1% tolerance, nominal value.

(2) R_PXFR≥ 100 kΩ or R_PXFR≤ 1 kΩ sets the duty cycle of the power converter to 13.3%.

8.3.6 Two-Wire Mode

Figure 8-4 shows the basic setup required for two-wire mode operation, which requires the EN signal and VSSP

ground signal. EN can be driven up to 48 V. No current limiting resistor is required on EN because the TPSI3052

limits the input current based on the values set by the R_PXFRresistor (see Table 8-2). In this example, the

TPSI3052 is being used to drive back-to-back MOSFETs in a common-source configuration. C_VDDPprovides the

required decoupling capacitance for the VDDP supply rail of the device. C_DIV1and C_DIV2provide the required

decoupling capacitance of the VDDH and VDDM supply rails that provide the peak current to drive the external

MOSFETs.

Figure 8-5 shows the typical operation in two-wire mode configured for standard enable. The application drives

EN to a logic high and the TPSI3052 begins its power-up sequence. During power up, the current provided

by the EN pin, I_EN, begins to charge up the external capacitance, C_VDDP, and the voltage on VDDP begins

to rise until it reaches V_{VDDP_H}. After VDDP reaches its peak, V_{VDDP_H}, the TPSI3052 transfers stored energy

on C_VDDPto the secondary side for a fixed time (3.3-μs typical) which begins to charge up the VDDH (and

VDDM) secondary side rails thereby discharging the voltage on VDDP. In steady state, this results in an average

voltage on VDDP, V_{VDDP_AVG}. This cycle repeats until the VDDH (and VDDM) secondary side rails are fully

charged. The time required to fully charge VDDH depends on several factors including the values of C_VDDP

C_DIV1, C_DIV2, R_PXFR, and the overall power transfer efficiency. After VDDH is fully charged, VDRV is asserted

high and remains high while the EN pin remains at a logic high. When the application drives the EN pin to a logic

low, the charge on VDDP begins to discharge. Prior to VDDP reaching its UVLO falling threshold, TPSI3052

signals information from the primary side to the secondary side to de-assert VDRV and drive it low. Because

power is no longer being transferred, all rails begin to fully discharge.

6.5–48 V

VDRV

PWR

R_PXFR

SIGNAL

PXFR

VDDP

VDDH

VDDM

VSSS

C_DIV1

C_VDDP

C_DIV2

VSSP

Figure 8-4. Two-Wire Mode Simplified Schematic

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V_{VDDP_H}

90%

t_{LH_VDDP_H}

VDDP

V_VDDH

V_{VDDH_UV_R}

VDDH

50%

V_{VDRV_H}

VDRV

Figure 8-5. Two-Wire Mode with Standard Enable (TPSI3052 Only)

In two-wire mode, power is supplied directly by the EN pin. When EN is asserted high, the TPSI3052 transfers

power to the secondary side for a fixed time (3.3-μs nominal) while the time period varies. The period varies

due to the hysteretic control of the power transfer that ensures the average current supplied through the EN pin

is maintained. The amount of average current, and hence the amount of power transferred, is programmable

by selecting one of seven appropriate resistor values, R_PXFR, from the PXFR to VSSP pins. Higher settings of

R_PXFRincrease I_ENwhich increases the average power consumed from the EN pin and increases the amount

of power transferred to the secondary side VDDH supply. Similarly, lower settings of R_PXFRdecrease I_EN, which

decreases the average power consumed from the EN pin and decreases the amount of power transferred to the

secondary side.

Table 8-2 summarizes the two-wire mode power selection.

Table 8-2. Two-Wire Mode Power Selection

(1) (2)

R_PXFR

I_EN(Two-Wire Mode, Nominal)

Description

7.32 kΩ

1.9 mA

2.8 mA

3.7 mA

4.5 mA

5.2 mA

6.0 mA

6.7 mA

9.09 kΩ

11 kΩ

The device supports seven, fixed EN input current limit options selected by

the corresponding R_PXFRspecified value. Higher current limit selections lead to

increased power transfer and consumption. During power up, the EN input current

limit is determined and remains fixed at that setting until VDDP power cycles.

12.7 kΩ

14.7 kΩ

16.5 kΩ

20 kΩ

(1) Standard resistor (EIA E96), 1% tolerance, nominal value.

(2) R_PXFR≥ 100 kΩ or R_PXFR≤ 1 kΩ sets the I_ENto 1.9 mA.

8.3.7 VDDP, VDDH, and VDDM Undervoltage Lockout (UVLO)

TPSI3052 and TPSI3052S implement an internal UVLO protection feature for both input and output power

supplies, VDDP, VDDH, and VDDM. When VDDP is lower than the UVLO threshold voltage, power ceases to

be transferred to the VDDM and VDDH rails. Over time the VDDH and VDDM rails will begin to discharge.

If enough charge is available on VDDP, the device will attempt to signal VDRV to assert low. If not enough

charge is available on VDDP, a timeout mechanism will ensure VDRV asserts low after the timeout has been

reached. When either VDDH or VDDM are lower than their respective UVLO thresholds, VDRV will be asserted

low regardless of the EN state. The UVLO protection blocks feature hysteresis, which helps to improve the

noise immunity of the power supply. During turn-on and turn-off, the driver sources and sinks a peak transient

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current, which can result in voltage drop of the VDDH, VDDM power supplies. The internal UVLO protection

block ignores the associated noise during these normal switching transients.

8.3.8 Power Supply and EN Sequencing

During power up, the device will automatically determine if two-wire or three-wire mode is to be entered. Once

two-wire or three-wire mode is determined, the mode is maintained until another power cycle is performed.

Therefore, it is important to understand different scenarios that may affect the device operation.

In two-wire mode, the device is supplied power from a single external voltage source via EN, which charges the

C_VDDPcapacitance on VDDP. The voltage supply is required to meet the power supply needs at the selected

PXFR setting, as well as, meet the recommended minimum ramp time, |ΔV_EN/Δt|. To ensure two-wire mode is

entered properly, V_ENmust reach V_{IH_EN}prior to V_VDDPreaching V_{VDDP_UV_R}. This is summarized in Figure 8-6.

Similarly, it is recommend that V_ENmeet the minimum recommended ramp down time to V_{IL_EN}. Too slow a ramp

down time may cause insufficient power to be transferred while slowly transitioning between V_{IH_EN}and V_{IL_EN}

leading to intermittent de-assertions and assertions of VDRV. This may continue until the power transfer reduces

sufficiently to maintain VDRV low.

V_{IH_EN}

V_EN

V_{IL_EN}

V_EN

V_{VDDP_UV_R}

Two-wire mode

V_VDDP

Figure 8-6. Two-wire Mode Entry

In most three-wire mode applications, EN and VDDP are supplied by the same voltage rail and source. It

is recommended that V_ENremain below V_{IL_EN}until V_VDDPreaches V_{VDDP_UV_R}. It is also possible in some

applications to connect EN directly to the VDDP supply. These two scenarios are shown in Figure 8-7.

V_{VDDP_UV_R}

V_VDDP

V_EN= V_VDDP

V_{IL_EN}

V_EN

Figure 8-7. Three-wire Mode Power Sequences

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In three-wire mode applications with separate voltage sources supplying EN and VDDP, it is recommended

that V_ENremain below V_{IL_EN}until V_VDDPreaches V_{VDDP_UV_R}. If V_ENreaches V_{IH_EN}prior to V_VDDPreaching

V_{VDDP_UV_R}, current from the supply that sources EN will attempt to power VDDP. Depending on the other

supply's impedance residing on VDDP and the amount of power available from the EN pin, V_VDDPmay begin to

rise and eventually exceed V_{VDDP_UV_R}. At that point, the device will begin to transfer power to the secondary

and start charging the VDDM and VDDH rails. If VDDP remains above V_{VDDP_UV_R}, the device will continue to

transfer power to the secondary eventually charging the VDDM and VDDH rails and VDRV may assert high.

8.3.9 Thermal Shutdown

The device contains an integrated temperature sensor to monitor its local temperature. When the sensor

reaches its threshold, it automatically ceases power transfer from the primary side to the secondary side. In

addition, if power is still present on VDDP, the driver is automatically asserted low. The power transfer is disabled

until the local temperature reduces enough to re-engage.

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8.4 Device Functional Modes

Table 8-3 summarizes the functional modes for the TPSI3052 and TPSI3052S.

Table 8-3. TPSI3052, TPSI3052S Device Functional Modes

VDDP⁽⁶⁾

VDDH

EN⁽⁶⁾

VDRV

COMMENTS

TPSI3052 normal operation:

VDRV output state assumes logic state of EN logic

state.

Powered up⁽²⁾

Powered up⁽⁴⁾

TPSI3052S normal operation (three-wire mode

only):

rising edge of EN causes VDRV to be singly pulsed

high. EN must be asserted low first to assert

another pulse.

L → H

L → H → L

Disabled operation:

VDRV output disabled, keep off circuitry applied.

Powered down⁽³⁾

Powered up⁽²⁾

Powered down⁽⁵⁾

X⁽¹⁾

Disabled operation:

VDRV output disabled, keep off circuitry applied.

Disabled operation:

when VDDP is powered down, output driver

is disabled automatically after timeout, keep off

circuitry applied.

Powered down⁽³⁾

Powered up⁽⁴⁾

X⁽¹⁾

(1) X: do not care.

(2) V_VDDP≥ VDDP undervoltage lockout rising threshold, V_{VDDP_UV_R}

(3) V_VDDP< VDDP undervoltage lockout falling threshold, V_{VDDP_UV_F}

(4) V_VDDH≥ VDDH undervoltage lockout rising threshold, V_{VDDH_UV_R}

(5) V_VDDH< VDDH undervoltage lockout falling threshold, V_{VDDH_UV_F}

(6) Refer to Power Supply and EN Sequencing for additional information.

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9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

The TPSI3052 is a fully integrated, isolated switch driver with integrated bias, which when combined with an

external power switch, forms a complete isolated solid state relay solution. With a nominal gate drive voltage

of 15 V with 1.5/3.0-A peak source and sink current, a large variety of external power switches such as

MOSFETs, IGBTs, or SCRs can be chosen to meet a wide range of applications. The TPSI3052 generates its

own secondary bias supply from the power received from its primary side, so no isolated secondary supply bias

is required.

The TPSI3052 supports two modes of operation based on the number of input pins required. In two-wire

mode, typically found in driving mechanical relays, controlling the switch requires only two pins and supports

a wide voltage range of operation of 6.5 V to 48 V. In three-wire mode, the primary supply of 3 V to 5.5 V is

supplied externally, and the switch is controlled through a separate enable. Available in three-wire mode only, the

TPSI3052S features a one-shot enable for the switch control. This feature is useful for driving SCRs that typically

require only one pulse of current to trigger.

The secondary side provides a regulated, floating supply rail of 15 V for driving a large variety of power

switches with no need for a secondary bias supply. The TPSI3052 can support driving single power switch, dual

back-to-back, parallel power switches for a variety of AC or DC applications. The TPSI3052 integrated isolation

protection is extremely robust with much higher reliability, lower power consumption, and increased temperature

ranges than those found using traditional mechanical relays and optocouplers.

The power dissipation of the TPSI3052 can be adjusted by an external resistor from the PXFR pin to VSSP.

This feature allows for tradeoffs in power dissipation versus power provided on the secondary depending on the

needs of the application.

9.2 Typical Application

The circuits in Figure 9-1 and Figure 9-2 show a typical application for driving silicon based MOSFETs in

three-wire mode and two-wire mode, respectively.

R_GSRC

R_GSNK

VDRV

VSSP

PWR

R_PXFR

SIGNAL

PXFR

VDDP

VDDH

VDDM

VSSS

C_DIV1

C_VDDP

–

C_DIV2

VSSP

Figure 9-1. TPSI3052 Three-Wire Mode Driving MOSFETs

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R_GSRC

R_GSNK

6.5–48 V

VDRV

PWR

R_PXFR

SIGNAL

PXFR

VDDH

VDDM

VSSS

C_DIV1

VDDP

VSSP

C_VDDP

C_DIV2

Figure 9-2. TPSI3052 Two-Wire Mode Driving MOSFETs

9.2.1 Design Requirements

Table 9-1 lists the design requirements of the TPSI3052 gate driver.

Table 9-1. TPSI3052 Design Requirements

DESIGN PARAMETERS

Total gate capacitance

FET turn-on time

100 nC

1 µs

Propagation delay

< 4 µs

Switching frequency

Supply voltage (VDDP)

10 kHz

5 V ± 5%

9.2.2 Detailed Design Procedure

9.2.2.1 Two-Wire or Three-Wire Mode Selection

The first design decision is to determine if two-wire or three-wire mode can be used in the application. For this

design, note that the overall propagation delay is less than 4 µs and only three-wire mode is able to meet this

requirement. In this case, two-wire mode is not applicable. Two-wire mode, due to its limited power transfer, is

typically limited to very low frequency applications of less than a few kHz or when enable times are not critical.

9.2.2.2 Standard Enable, One-Shot Enable

Next, based on the application a decision must be if standard enable or one-shot enable mode is required. In this

design, assume that after the switch is enabled, it is desired that the switch remain enabled until commanded

to be disabled. Therefore, standard enable mode is assumed. In most applications that involve driving FETs,

standard enable is appropriate. If driving SCRs or TRIACS, one-shot mode can be beneficial.

9.2.2.3 C_DIV1, C_DIV2Capacitance

The C_DIV1and C_DIV2capacitances required depends on the amount of drop that can be tolerated on the VDDH

rail during switching of the external load. The charge stored on the CDIV1 and CDIV2 capacitances is used to

provide the current to the load during switching. During switching, charge sharing occurs and the voltage on

VDDH drops. At a minimum, TI recommends that the total capacitance formed by the series combination of

C_DIV1and C_DIV2be sized to be at least 30 times the total gate capacitance to be switched. This sizing results in

an approximate 0.5-V drop of the VDDH supply rail that is used to supply power to the VDRV signal. Equation 1

and Equation 2 can be to used to calculate the amount of capacitance required for a specified voltage drop.

C_DIV1and C_DIV2must be of the same type and tolerance.

n + 1

LOAD

, n ≥ 3.0

∆ V

(1)

(2)

DIV1

DIV2

= n × C

, n ≥ 3.0

DIV1

where

•

n is a real number greater than or equal to 3.0.

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•

C_DIV1is the external capacitance from VDDH to VDDM.

C_DIV2is the external capacitance from VDDM to VSSS.

Q_LOADis the total charge of the load from VDRV to VSSS.

ΔV is the voltage drop on VDDH when switching the load.

Note

C_DIV1and C_DIV2represent absolute capacitances and components selected must be adjusted for

tolerances and any derating necessary to achieve the required capacitances.

Larger values of ΔV can be used in the application, but excessive droop can cause the VDDH undervoltage

lockout falling threshold (V_{VDDH_UVLO_F}) to be reached and cause VDRV to be asserted low. Note that as the

series combination of C_DIV1and C_DIV2capacitances increases relative to Q_LOAD, the VDDH supply voltage drop

decreases, but the initial charging of the VDDH supply voltage during power up increases.

For this design, assuming n = 3 and ΔV≅ 0.5 V, then

3 + 1

120 nC

= 320 nF

0.5 V

(3)

(4)

DIV1

= 3 × 320 nF = 960 nF

DIV2

For this design, C_DIV1= 330 nF and C_DIV2= 1 μF standard capacitor values were selected.

9.2.2.4 R_PXFRSelection

The selection of R_PXFRallows for a tradeoff between power consumed and power delivered, as described in the

Three-wire Mode section. For this design, one must choose an appropriate R_PXFRselection that ensures enough

power is transferred to support the amount of load being driven at the specified switching frequency.

During switching of the load, Q_LOADof charge on VDDH is transferred to the load and VDDH supply voltage

droops. After each switching cycle, this charge must be replenished before the next switching cycle occurs. This

action ensures that the charge residing on VDDH does not deplete over time due to subsequent switching cycles

of the load. The time it takes to recover this charge, t_RECOVER, can be estimated as follows:

LOAD

≅

(5)

RECOVER

OUT

MAX

where

•

Q_LOADis the load charge in Coulombs.

I_OUTis the average current available from VDDH supply in Amperes (A).

f_MAXis maximum switching frequency in Hertz (Hz).

For this design, Q_LOAD= 100 nC and f_MAX= 10 kHz are known, so I_OUTrequired can be estimated as

≅ 100 nC × 10 kHz = 1.0 mA

(6)

OUT

I_OUTrepresents the minimum average current required to meet the design requirements. Using the TPSI3052

calculator tool, one can easily find the R_PXFRnecessary by referring to the I_OUTor f_MAXcolumns directly. Table

9-2 shows the results from the tool, assuming VDDP = 4.75 V, to account for the supply tolerance specified in

the design requirements. The TPSI3052 Calculator tool can be found at Design Calculator.

Table 9-2. Results from the TPSI3052 Calculator Tool, T_A= 25°C, Three-Wire Mode

Power

Converter

Duty Cycle, %

f_{EN_MAX}

kHz

I_{AUX_MAX}

R_PXFR, kΩ

7.32

I_VDDP, mA

P_IN, mW

P_OUT, mW

I_OUT, mA

t_START, µs

t_RECOVER, µs

13.3

21.1

40.0

53.3

5.3

25.0

5.9

0.35

N/A

2.3

4.1

9.09

8.3

15.8

21.1

39.6

75.1

10.0

26.8

36.1

0.62

1.74

2.35

N/A

2076

1581

N/A

56.3

41.8

17.8

23.9

12.7

100.1

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Table 9-2. Results from the TPSI3052 Calculator Tool, T_A= 25°C, Three-Wire Mode (continued)

Power

Converter

Duty Cycle, %

f_{EN_MAX}

kHz

I_{AUX_MAX}

R_PXFR, kΩ

I_VDDP, mA

P_IN, mW

P_OUT, mW

I_OUT, mA

t_START, µs

t_RECOVER, µs

14.7

66.7

80.0

93.3

26.4

125.2

45.5

58.8

68.8

2.98

1287

33.2

30.2

39.0

45.6

6.0

8.6

16.5

31.6

36.9

150.2

175.2

3.86

4.52

1032

905

25.7

21.9

10.0

Table 9-3 summarizes the various output parameters of the calculator tool.

Table 9-3. TPSI3052 Calculator Tool Parameter Descriptions

Parameter

Description

External resistor setting that controls the amount of power transferred to the load by adjusting the duty

cycle. Higher R_PXFRsettings lead to increased power transfer and power consumption.

R_PXFR

Nominal duty cycle of the power converter. Higher R_PXFRsettings leads to higher duty cycles of the power

converter and higher power transfer.

Power Converter Duty Cycle

I_VDDP

P_IN

P_OUT

I_OUT

Average current consumed from the VDDP supply

Average power consumed from the VDDP supply

Average power delivered to the VDDH supply

Average current delivered to the VDDH supply

Start-up time from VDDP rising until VDDH supply rail is fully charged. This parameter assumes VDDH and

VDDM supply rails are fully discharged initially.

t_START

t_RECOVER

f_MAX

Represents the time for the VDDH rail to recover after switching the load present on VDRV

Maximum switching frequency possible for a given R_PXFRsetting for the applied loading conditions

Maximum auxiliary current available at current user input settings. There is an inverse relationship between

I_{AUX_MAX}

f_MAXand I_{AUX_MAX}

For this design example, R_PXFRmust be configured to the 9.09-kΩ setting or higher to transfer enough power to

support switching the specified load at the required 10-kHz frequency.

9.2.2.5 C_VDDPCapacitance

For two-wire mode, the recommended capacitance C_VDDPfrom VDDP to VSSP is 220 nF.

For this design, three-wire mode is required to meet the design requirements. For three-wire mode, increasing

the amount of capacitance, C_VDDP, improves the ripple on the VDDP supply. For this design, 1 μF in parallel with

100 nF is used.

9.2.2.6 Gate Driver Output Resistor

The optional external gate driver resistors, R_GSRCand R_GSNK, along with the diode are used to:

1. Limit ringing caused by parasitic inductances and capacitances

2. Limit ringing caused by high voltage switching dv/dt, high current switching di/dt, and body-diode reverse

recovery

3. Fine-tune gate drive strength for sourcing and sinking

4. Reduce electromagnetic interference (EMI)

The TPSI3052 has a pullup structure with a P-channel MOSFET with a peak source current of 1.5 A. Therefore,

the peak source current can be predicted with:

VDDH

≅ min 1.5 A,

(7)

O +

+ R

GSRC

+ R

GFET_INT

DSON_VDRV

where

•

R_GSRC: external turn-on resistance.

R_{DSON_VDRV}: TPSI3052 driver on resistance in high state. See Electrical Characteristics.

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•

V_VDDH: VDDH voltage. Assumed 15.1 V in this example.

R_{GFET_INT}: external power transistor internal gate resistance, found in the power transistor data sheet.

Assume 0 Ω for this example.

•

I_O+: peak source current. The minimum value between 1.5 A, the gate driver peak source current, and the

calculated value based on the gate drive loop resistance.

For this example, R_{DSON_VDRV}= 2.5Ω, R_GSRC= 10 Ω, and R_{GFET_INT}= 0 Ω results in:

15.1 V

≅ min 1.5 A,

= 1.21 A

2.5 Ω + 10 Ω + 0 Ω

(8)

O +

Similarly, the TPSI3052 has a pulldown structure with an N-channel MOSFET with a peak sink current of 3.0 A.

Therefore, assuming R_{GFET_INT}= 0 Ω, the peak sink current can be predicted with:

≅ min 3.0 A, V

× R

+ R

− R

× V

(9)

O −

VDDH

GSRC

GSNK

GSRC

× R

GSNK

+ R

DSON_VDRV

× R

GSRC

+ R

GSNK

GSRC

where

•

R_GSRC: external turn-on resistance.

R_GSNK: external turn-off resistance.

R_{DSON_VDRV}: TPSI3052 driver on resistance in low state. See Electrical Characteristics.

V_VDDH: VDDH voltage. Assumed 15.1 V in this example.

V_F: diode forward voltage drop. Assumed 0.7 V in this example.

I_O-: peak sink current. The minimum value between 3.0 A, the gate driver peak sink current, and the

calculated value based on the gate drive loop resistance.

For this example, assuming R_{DSON_VDRV}= 1.7 Ω, R_GSRC= 10 Ω, R_GSNK= 5.0 Ω, and R_{GFET_INT}= 0 Ω, results in:

≅ min 3.0 A, 15.1 V × 10 Ω + 5 Ω − 10Ω × 0.7 V ×

= 2.91 A

(10)

O −

10 Ω × 5 Ω + 1.7 Ω × 10Ω + 5 Ω

Importantly, the estimated peak current is also influenced by PCB layout and load capacitance. Parasitic

inductance in the gate driver loop can slow down the peak gate drive current and introduce overshoot and

undershoot. Therefore, TI strongly recommends to minimize the gate driver loop.

9.2.2.7 Start-up Time and Recovery Time

As described in the C_DIV1, C_DIV2Capacitance section, the start-up time of the fully discharged VDDH rail

depends on the amount of capacitance present on the VDDH supply. The rate at which this capacitance is

charged depends on the amount of power transferred from the primary side to the secondary side. The amount

of power transferred can be adjusted by choosing R_PXFR. Increasing the resistor settings for R_PXFRtransfers

more power from the primary supply (VDDP) to the secondary supply (VDDH), thereby reducing the overall

start-up and recovery times.

9.2.2.8 Supplying Auxiliary Current, I_AUXFrom VDDM

The TPSI3052 is capable of providing power from VDDM to support external auxiliary circuitry as shown in

Figure 9-3. In this case, the required transfer power must include the additional power consumed by the auxiliary

circuitry on the VDDM rail. The R_PXFRvalue must be set to meet the overall power requirements.

R_GSRC

R_GSNK

VDRV

VSSP

PWR

R_PXFR

SIGNAL

PXFR

VDDP

VDDH

VDDM

VSSS

C_DIV1

I_AUX

C_VDDP

Auxiliary

Circuit

–

C_DIV2

VSSP

Figure 9-3. Supplying Auxiliary Power From VDDM

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As an example, assume that the auxiliary circuitry requires an average current of 4 mA. Table 9-4 summarizes

the results from the TPSI3052 calculator tool. The Calculator tool can be found at Design Calculator.

Table 9-4. Results from the TPSI3052 Calculator Tool, T_A= 25°C, Three-Wire Mode with I_AUX= 4 mA

Power

Converter

Duty Cycle, %

f_{EN_MAX}

kHz

I_{AUX_MAX}

R_PXFR, kΩ

I_VDDP, mA

P_IN, mW

P_OUT, mW

I_OUT, mA

t_START, µs

t_RECOVER, µs

7.32

13.3

21.1

40.0

53.3

66.7

80.0

93.3

5.3

25.0

5.9

0.35

N/A

4.1

9.09

8.3

15.8

21.1

26.4

31.6

36.9

39.6

75.1

10.0

26.8

36.1

45.5

58.8

68.8

0.62

1.74

2.35

2.98

3.86

4.52

N/A

12.7

14.7

16.5

100.1

125.2

150.2

175.2

3557

2285

1549

1262

96.0

60.1

39.3

31.2

10.4

16.6

25.5

32.1

6.0

8.6

10.0

Based on the results in Table 9-4, several observations can be made:

•

With R_PXFR= 7.32 kΩ , R_PXFR= 9.09 kΩ, and R_PXFR= 11 kΩ, insufficient power is available to meet the

application power needs specified in the design requirements in Table 9-1.

With R_PXFR= 12.7 kΩ and higher, sufficient power is transferred to meet the specified design requirements,

however, for this design, R_PXFR= 14.7 kΩ was selected for additional margin.

For a given R_PXFR, because a significant amount of the transferred power is being provided to the auxiliary

circuitry, t_STARTis longer, and f_MAXreduced when compared to the results shown in Table 9-2 with I_AUX= 0

mA.

9.2.2.9 VDDM Ripple Voltage

Note that when supplying power from VDDM, that is when I_AUX> 0 mA, additional voltage ripple is present on

the VDDM rail. For a given R_PXFRsetting, this ripple can be reduced by applying additional capacitance from

VDDM to VSSS or increasing the R_PXFRsetting for more power tranfser. For this design example, the ripple on

VDDM, VDDM_ripple, computed in the calculator tool is 35 mV.

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9.2.3 Application Curves

Three-wire mode

C_DIV1= 330 nF

I_AUX= 0 mA

VDDP = 5.0 V

R_PXFR= 11 kΩ

T_A= 25°C

Three-wire mode

C_DIV1= 330 nF

I_AUX= 0 mA

VDDP = 5.0 V

C_DIV2= 1 μF

R_PXFR= 11 kΩ

T_A= 25°C

C_DIV2= 1 μF

C_VDRV= 6.8 nF

Figure 9-4. Power Up, V_EN= V_VDDP, Three-Wire Mode, TPSI3052

Figure 9-5. t_{LH_VDRV}, Three-Wire Mode, TPSI3052

Three-wire mode

C_DIV1= 330 nF

I_AUX= 0 mA

VDDP = 5.0 V

C_DIV2= 1 μF

R_PXFR= 11 kΩ

T_A= 25°C

Three-wire mode

C_DIV1= 330 nF

I_AUX= 0 mA

VDDP = 5.0 V

C_DIV2= 1 μF

R_PXFR= 11 kΩ

T_A= 25°C

C_VDRV= 6.8 nF

Figure 9-6. t_{HL_VDRV}, Three-Wire Mode, TPSI3052

Figure 9-7. Three-Wire Mode, f_EN= 10 kHz, TPSI3052

Three-wire mode

C_DIV1= 330 nF

I_AUX= 4 mA

VDDP = 5.0 V

C_DIV2= 1 μF

R_PXFR= 14.7 kΩ

T_A= 25°C

Three-wire mode

C_DIV1= 330 nF

I_AUX= 4 mA

VDDP = 5.0 V

C_DIV2= 1 μF

R_PXFR= 14.7 kΩ

T_A= 25°C

C_VDRV= 6.8 nF

Figure 9-8. Power Up, V_EN= V_VDDP, Three-Wire Mode,

TPSI3052

Figure 9-9. t_{LH_VDRV}, Three-Wire Mode, TPSI3052

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9.2.3 Application Curves (continued)

Three-wire mode

C_DIV1= 330 nF

I_AUX= 4 mA

VDDP = 5.0 V

C_DIV2= 1 μF

R_PXFR= 14.7 kΩ

T_A= 25°C

Three-wire mode

C_DIV1= 330 nF

I_AUX= 4 mA

VDDP = 5.0 V

C_DIV2= 1 μF

R_PXFR= 14.7 kΩ

T_A= 25°C

C_VDRV= 6.8 nF

Figure 9-10. t_{HL_VDRV}, Three-Wire Mode, TPSI3052

Figure 9-11. Three-Wire Mode, f_EN= 10 kHz, TPSI3052

9.3 Power Supply Recommendations

In three-wire mode, to help ensure a reliable supply voltage, TI recommends that the C_VDDPcapacitance from

VDDP to VSSP consists of a 0.1-μF bypass capacitor for high frequency decoupling in parallel with a 1 μF for

low frequency decoupling.

In two-wire mode, TI recommends that the C_VDDPcapacitance placed from VDDP to VSSP consists of a

220-nF capacitor connected close to the device between the VDDP and VSSP pins. The recommended absolute

capacitance must be 220 nF, so if derating is required, a higher component value can be needed.

Low-ESR and low-ESL capacitors must be connected close to the device between the VDDP and VSSP pins.

9.4 Layout

9.4.1 Layout Guidelines

Designers must pay close attention to PCB layout to achieve optimum performance for the TPSI3052. Some key

guidelines are:

•

Component placement:

– Place the driver as close as possible to the power semiconductor to reduce the parasitic inductance of the

gate loop on the PCB traces.

– Connect low-ESR and low-ESL capacitors close to the device between the VDDH and VDDM pins and the

VDDM and VSSS pins to bypass noise and to support high peak currents when turning on the external

power transistor.

– Connect low-ESR and low-ESL capacitors close to the device between the VDDP and VSSP pins.

– Minimize parasitic capacitances on the R_PXFRpin.

•

Grounding considerations:

– Limit the high peak currents that charge and discharge the transistor gates to a minimal physical area.

This limitation decreases the loop inductance and minimizes noise on the gate terminals of the transistors.

Place the gate driver as close as possible to the transistors.

– Connect the driver VSSS to the Kelvin connection of MOSFET source or IGBT emitter. If the power device

does not have a split Kelvin source or emitter, connect the VSSS pin as close as possible to the source

or emitter terminal of the power device package to separate the gate loop from the high power switching

loop.

•

High-voltage considerations:

– To ensure isolation performance between the primary and secondary side, avoid placing any PCB traces

or copper below the driver device. TI recommends a PCB cutout or groove to prevent contamination that

can compromise the isolation performance.

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•

Thermal considerations:

– Proper PCB layout can help dissipate heat from the device to the PCB and minimize junction-to-board

thermal impedance (θ_JB).

– If the system has multiple layers, TI also recommends connecting the VDDH and VSSS pins to internal

ground or power planes through multiple vias of adequate size. These vias must be located close to the IC

pins to maximize thermal conductivity. However, keep in mind that no traces or coppers from different high

voltage planes are overlapping.

9.4.2 Layout Example

Figure 9-12 shows a PCB layout example with the signals and key components labeled.

Figure 9-12. 3-D PCB View

Figure 9-13 and Figure 9-14 show the top and bottom layer traces and copper.

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Figure 9-13. Top Layer

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TPSI3052

SLVSGS3A – APRIL 2022 – REVISED APRIL 2023

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Figure 9-14. Bottom Layer

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SLVSGS3A – APRIL 2022 – REVISED APRIL 2023

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10 Device and Documentation Support

10.1 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to order now.

Table 10-1. Related Links

TECHNICAL

DOCUMENTS

TOOLS &

SOFTWARE

SUPPORT &

COMMUNITY

PARTS

PRODUCT FOLDER

ORDER NOW

TPSI3052

Click here

TPSI3052S

10.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

10.3 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

10.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

10.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

10.6 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

www.ti.com

18-Apr-2023

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPSI3052DWZR

TPSI3052SDWZR

ACTIVE

SO-MOD

DWZ

1000 RoHS & Green

NIPDAU

Level-3-260C-168 HR

-40 to 125

I3052

I3052S

Samples

NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

18-Apr-2023

OTHER QUALIFIED VERSIONS OF TPSI3052 :

Automotive : TPSI3052-Q1

•

NOTE: Qualified Version Definitions:

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

•

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

17-Apr-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPSI3052DWZR

TPSI3052SDWZR

SO-MOD DWZ

1000

330.0

16.4

12.05 6.15

3.3

16.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

17-Apr-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPSI3052DWZR

TPSI3052SDWZR

SO-MOD

DWZ

1000

350.0

43.0

Pack Materials-Page 2

PACKAGE OUTLINE

DWZ0008A

SOIC - 2.8 mm max height

SMALL OUTLINE PACKAGE

SEATING PLANE

11.75

11.25

TYP

PIN 1 ID

AREA

0.1 C

6X 1.27

5.95

5.75

NOTE3

3.81

0.51

0.31

7.6

7.4

NOTE4

0.25

C A

2.8 MAX

0.33

0.13

TYP

SEE DETAIL A

(2.286)

0.25

GAGE PLANE

0.46

0.36

0 -8

0.5

DETAIL A

TYPICAL

2.1

(

)

1.9

4226306/A 09/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Ref. JEDEC registration MS-013

www.ti.com

EXAMPLE BOARD LAYOUT

DWZ0008A

SOIC - 2.8 mm max height

SMALL OUTLINE PACKAGE

8X (1.8)

SEE DETAILS

SYMM

8X (0.6)

6X (1.27)

(10.9)

LAND PATTERN EXAMPLE

9.1 mm NOMINAL CLEARANCE/CREEPAGE

SCALE: 6X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4226306/A 09/2020

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DWZ0008A

SOIC - 2.8 mm max height

SMALL OUTLINE PACKAGE

SYMM

8X (1.8)

8X (0.6)

SYMM

6X (1.27)

(10.9)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 6X

4226306/A 09/2020

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

8. Board assembly site may have different recommendations for stencil design.

www.ti.com

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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

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These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

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TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TPSI3052 [TI]

相关型号：

TPSI3052-Q1

TPSI3052DWZR

TPSI3052QDWZRQ1

TPSI3052SDWZR

TPSI3052SQDWZRQ1

TPSKA4M50B00-R3

TPSKA4M50B00-R3_17

TPSKA5M50B00-R3

TPSKA5M50B00-R3_17

TPSKA6M00B00-R3

TPSKA6M00B00-R3_17

TPSKA6M50B00-R3