TPSM13604H [TI]
SIMPLE SWITCHER 6V 至 36V、4A 峰值高输出电压电源模块;
| 型号： | TPSM13604H |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SIMPLE SWITCHER 6V 至 36V、4A 峰值高输出电压电源模块 电源电路 |
| 文件： | 总26页 (文件大小：1508K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPSM13604H
ZHCSNM7 –MARCH 2021
TPSM13604H 5V 至36V、4A 高输出电压电源模块
1 特性
3 说明
• 集成屏蔽式电感器
• 简单的PCB 布局
• 采用外部软启动和精密使能端实现灵活启动排序
• 防止浪涌电流
• 输入UVLO 和输出短路保护
• -40°C 至125°C 的结温范围
• 便于装配和制造的单个外露焊盘和标准引脚分配
• 低输出电压纹波
TPSM13604H SIMPLE SWITCHER 电源模块是一款
易于使用的降压直流/直流解决方案，能以低开关频率
驱动高达 4A 的负载，并具有出色的电源转换效率、线
路和负载调节以及输出精度。TPSM13604H 采用创新
型封装，可提高热性能并支持手工或机器焊接。
TPSM13604H 支持 5V 至 36V 的输入电压轨范围，可
提供低至 3V 的高精度可调节输出电压。
TPSM13604H 仅需三个外部电阻和四个外部电容器即
可完善电源解决方案。TPSM13604H 的设计可靠而稳
健，并且具有以下保护特性：热关断、输入欠压锁定、
输出过压保护、短路保护、输出限流以及预偏置输出的
启动功能。单个电阻最高可将开关频率调节至
700kHz。
• 引脚对引脚兼容系列：
– LMZ14203/LMZ14202/LMZ14201（最大42V，
3A、2A、1A)
– LMZ12003/LMZ12002/LMZ12001 （最大
20V，3A、2A、1A)
• 电气规范
– 输出电流高达4A
(1)器件信息
– 输入电压范围：5V 至36V
– 输出电压范围：3V 至16V
– 效率高达97%
封装尺寸（标称值）
器件型号
封装
TPSM13604H
TO-PMOD (7)
10.16mm × 9.85mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 性能优势
– 高效率有效降低系统产生的热量
– 低辐射EMI（经EN 55022 B 类标准测试）
– 无需补偿
– 低封装热阻
• EN 55022:2006，+A1:2007，FCC 部分15
子部分B: 2007
2 应用
• 测试和测量
• 工厂自动化和控制
• 航天和国防
• 通用电源
100
95
90
85
80
VIN = 18V
VIN = 24V
VIN = 36V
75
70
0
0.5
1
1.5
2
2.5
Output Current (A)
3
3.5
4
效率VOUT = 9.0V, TA = 25°C, FSW = 300kHz
简化版应用原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNVSBT8
TPSM13604H
ZHCSNM7 –MARCH 2021
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Table of Contents
8 Application and Implementation.................................. 11
8.1 Application Information..............................................11
8.2 Typical Application.................................................... 11
9 Power Supply Recommendations................................16
10 Layout...........................................................................17
10.1 Layout Guidelines................................................... 17
10.2 Layout Example...................................................... 18
11 Device and Documentation Support..........................21
11.1 Device Support........................................................21
11.2 Documentation Support.......................................... 21
11.3 接收文档更新通知................................................... 21
11.4 支持资源..................................................................21
11.5 Trademarks............................................................. 21
11.6 术语表..................................................................... 21
11.7 静电放电警告...........................................................21
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics................................................6
7 Detailed Description........................................................9
7.1 Overview.....................................................................9
7.2 Functional Block Diagram...........................................9
7.3 Feature Description.....................................................9
7.4 Device Functional Modes..........................................10
Information.................................................................... 21
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
March 2021
*
Initial release.
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5 Pin Configuration and Functions
VOUT
FB
SS
GND
EN
7
6
Exposed Pad
Connect to GND
5
4
3
2
1
RON
VIN
图5-1. 7-Pin TO-PMOD NDW Package (Top View)
表5-1. Pin Functions
PIN
NAME
TYPE
DESCRIPTION
NO.
Supply input —Additional external input capacitance is required between this pin and the exposed pad
(EP).
1
VIN
Power
Analog
on-time resistor —An external resistor from VIN to this pin sets the on-time and frequency of the application.
Typical values range from 100 k to 700 k Ω. Recommended frequency for a 4-A load is 300 kHz.
2
RON
3
4
5
EN
GND
SS
Analog
Ground
Analog
Enable —Input to the precision enable comparator. Rising threshold is 1.18 V.
Ground —Reference point for all stated voltages. Must be externally connected to EP.
Soft Start —An internal 8-µA current source charges an external capacitor to produce the soft-start function.
Feedback —Internally connected to the regulation, overvoltage, and short-circuit comparators. The
regulation reference point is 0.8 V at this input pin. Connect the feedback resistor divider between the output
and ground to set the output voltage.
6
FB
Analog
Output Voltage —Output from the internal inductor. Connect the output capacitor between this pin and the
exposed pad (EP).
7
VOUT
EP
Power
Exposed Pad —Internally connected to pin 4. Used to dissipate heat from the package during operation.
Must be electrically connected to pin 4 external to the package.
Ground
—
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6 Specifications
6.1 Absolute Maximum Ratings
MIN(1)(2)(3)
–0.3
MAX
42
UNIT
V
VIN, RON to GND
EN, FB, SS to GND
7
V
–0.3
Junction Temperature
Peak Reflow Case Temperature (30 s)
Storage Temperature
150
245
150
°C
°C
°C
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) For soldering specifications, see the application note Absolute Maximum Ratings for Soldering (SNOA549)
6.2 ESD Ratings
VALUE
UNIT
V(ESD)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
5
MAX
UNIT
VIN
36
6.5
V
V
EN
0
Operation Junction Temperature
125
°C
−40
6.4 Thermal Information
TPSM13604
THERMAL METRIC(1)
NDW (TO-PMOD)
7 PINS
UNIT
4 layer printed-circuit-board, 7.62 cm x 7.62 cm
(3 in x 3 in) area, 1-oz copper, no air flow
16
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
4 layer printed-circuit-board, 6.35 cm x 6.35 cm
(2.5 in x 2.5 in) area, 1-oz copper, no air flow
18.4
1.9
RθJC(top) Junction-to-case (top) thermal resistance
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
Minimum and Maximum limits are ensured through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following
conditions apply: VIN = 24 V, VOUT = 12 V, RON = 249 kΩ
PARAMETER
SYSTEM PARAMETERS
ENABLE CONTROL
TEST CONDITIONS
VEN rising, TJ = –40°C to 125°C
VSS = 0 V, TJ = –40°C to 125°C
DC average, TJ = –40°C to 125°C
MIN(1)
1.10
8
TYP(2)
MAX(1) UNIT
VEN
EN threshold trip point
1.18
90
1.25
15
V
VEN-HYS
SOFT-START
ISS
EN threshold hysteresis
mV
SS source current
10
µA
µA
ISS-DIS
SS discharge current
–200
CURRENT LIMIT
ICL
Current limit threshold
Current limit threshold
3.2
4.7
4.5
5.5
A
A
DC average, TJ = 25°C to 125°C, VIN = 12 V,
VOUT = 9.0 V, RON = 374 kΩ
ICL
4.05
VIN UVLO
VINUVLO
Input UVLO
Hysteresis
EN pin floating, VIN rising
EN pin floating, VIN falling
3.75
130
V
VINUVLO-HYST
ON/OFF TIMER
tON-MIN
mV
ON timer minimum pulse
width
150
260
ns
ns
tOFF
OFF timer pulse width
REGULATION AND OVERVOLTAGE COMPARATOR
VIN = 24 V, VOUT = 12 V, VSS >+ 0.8 V
0.782
0.786
0.803
0.803
0.92
0.822
0.818
TJ = –40°C to 125°C
In-regulation feedback
voltage
VFB
V
V
VIN = 24 V, VOUT = 12 V, VSS >+ 0.8 V
TJ = 25°C
Feedback overvoltage
protection threshold
VFB-OVP
IFB
IQ
Feedback input bias current
Nonswitching input current
5
1
nA
mA
μA
VFB= 0.86 V
ISD
Shutdown quiescent current VEN= 0 V
25
THERMAL CHARACTERISTICS
TSD
Thermal shutdown (rising)
Thermal shutdown hysteresis
165
15
°C
°C
TSD-HYST
PERFORMANCE PARAMETERS
VOUT = 9.0 V, CO = 100-µF 6.3-V X7R,
RON = 374 kΩ
Output voltage ripple
20
mVPP
mV/A
ΔVOUT
Line regulation
Load regulation
0.01%
1.5
ΔVOUT/ΔVIN
ΔVOUT/ΔIOUT
VIN = 12 V to 24 V, IOUT= 4 A, RON = 374 kΩ
VIN = 12 V, IOUT = 0 A to 4 A, RON = 374 kΩ
VIN = 12 V, VOUT = 9.0 V, IOUT = 1 A,
RON = 374 kΩ
Efficiency
Efficiency
96%
88%
η
η
VIN = 12 V, VOUT = 9.0 V, IOUT = 4 A,
RON = 374 kΩ
(1) Minimum and Maximum limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through
correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level
(AOQL).
(2) Typical numbers are at 25°C and represent the most likely parametric norm.
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6.6 Typical Characteristics
FSW = 300 kHz; Cin = 10-μF, X7R ceramic; CO = 47 µF; TA = 25°C (unless otherwise specified)
100
95
90
85
80
75
70
5
4
3
2
1
0
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 12V
VIN = 24V
VIN = 36V
0
0.5
1
1.5
Output Current (A)
2
2.5
3
3.5
4
4
4
0
0.5
1
1.5
Output Current (A)
2
2.5
3
3.5
4
4
4
图6-1. Efficiency VOUT = 3.3 V, TA = 25°C
图6-2. Power Dissipation VOUT = 3.3 V,
TA = 25°C
100
95
90
85
80
5
4
3
2
1
0
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 12V
VIN = 24V
VIN = 36V
75
70
0
0.5
1
1.5
Output Current (A)
2
2.5
3
3.5
0
0.5
1
1.5
Output Current (A)
2
2.5
3
3.5
图6-3. Efficiency VOUT = 5.0 V, TA = 25°C
图6-4. Power Dissipation VOUT = 5.0 V,
TA = 25°C
100
95
90
85
80
6
5
4
3
2
1
0
VIN = 18V
VIN = 24V
VIN = 36V
VIN = 18V
VIN = 24V
VIN = 36V
75
70
0
0.5
1
1.5
Output Current (A)
2
2.5
3
3.5
0
0.5
1
1.5
Output Current (A)
2
2.5
3
3.5
图6-5. Efficiency VOUT = 9.0 V, TA = 25°C
图6-6. Power Dissipation VOUT = 9.0 V,
TA = 25°C
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100
6
5
4
3
2
1
0
95
90
85
80
75
VIN = 18V
VIN = 24V
VIN = 36V
VIN = 18V
VIN = 24V
VIN = 36V
70
0
0.5
1
1.5
Output Current (A)
2
2.5
3
3.5
4
0
0.5
1
1.5
Output Current (A)
2
2.5
3
3.5
4
图6-7. Efficiency VOUT = 12 V, TA = 25°C
图6-8. Power Dissipation VOUT = 12 V,
TA = 25°C
100
95
90
85
80
75
70
6
5
4
3
2
1
0
VIN = 18V
VIN = 24V
VIN = 36V
VIN = 18V
VIN = 24V
VIN = 36V
0
0.5
1
1.5
2
2.5
Output Current (A)
3
3.5
4
0
0.5
1
1.5
2
2.5
Output Current (A)
3
3.5
4
图6-10. Power Dissipation VOUT = 16 V,
图6-9. Efficiency VOUT = 16 V, TA = 25°C
TA = 25°C
40
0LFM (0m/s) air
225LFM (1.14m/s) air
500LFM (2.54m/s) air
35
Evaluation Board Area
30
25
20
15
10
5
0
0
10
20
30
40
50
60
2
BOARD AREA (cm )
图6-12. Package Thermal Resistance RθJA
图6-11. Line and Load Regulation VOUT = 9.5 V, TA
4-Layer PCB with 1-oz Copper
= 25°C
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图6-13. Output Ripple VIN = 12 V, VOUT = 9.0 V, IOUT
图6-14. Load Transient Response VIN = 12 V, VOUT
= 4 A, Ceramic COUT, BW = 200 MHz
= 9.0 V Load Step From 0% to 100%
图6-15. Load Transient Response VIN = 12 V, VOUT 图6-16. Load Transient Response VIN = 12 V, VOUT
= 9.0 V Load Step From 25% to 100%
= 9.0 V Load Step From 50% to 100%
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7 Detailed Description
7.1 Overview
7.1.1 COT Control Circuit Overview
Constant on-time control is based on a comparator and an on-time one-shot, with the output voltage feedback
compared to an internal 0.8-V reference. If the feedback voltage is below the reference, the high-side MOSFET
is turned on for a fixed on-time determined by a programming resistor RON. RON is connected to VIN such that
on-time is reduced with increasing input supply voltage. Following this on-time, the high-side MOSFET remains
off for a minimum of 260 ns. If the voltage on the feedback pin falls below the reference level again, the on-time
cycle is repeated. Regulation is achieved in this manner.
7.2 Functional Block Diagram
Vin
R
ENT
ENB
1
VIN
3
5
EN
SS
Linear reg
R
C
IN
Cvcc
Css
0.47 éF
VOUT
R
ON
7
2
6
RON
FB
V
O
Timer
C
10 éH
FF
Co
R
FBT
Internal
Passives
Regulator IC
R
FBB
GND
4
7.3 Feature Description
7.3.1 Output Overvoltage Comparator
The voltage at FB is compared to a 0.92-V internal reference. If FB rises above 0.92 V, the on-time is
immediately terminated. This condition is known as overvoltage protection (OVP). It can occur if the input voltage
is increased very suddenly or if the output load is decreased very suddenly. Once OVP is activated, the top
MOSFET on-times are inhibited until the condition clears. Additionally, the synchronous MOSFET remains on
until inductor current falls to zero.
7.3.2 Current Limit
Current limit detection is carried out during the off-time by monitoring the current in the synchronous MOSFET.
Referring to the Functional Block Diagram, when the top MOSFET is turned off, the inductor current flows
through the load, the PGND pin, and the internal synchronous MOSFET. If this current exceeds 4.2 A (typical),
the current limit comparator disables the start of the next on-time period. The next switching cycle only occurs if
the FB input is less than 0.8 V and the valley of the inductor current has decreased below 4.2 A. Inductor current
is monitored during the period of time the synchronous MOSFET is conducting. So long as inductor current
exceeds 4.2 A, further on-time intervals for the top MOSFET do not occur. Switching frequency is lower during
current limit due to the longer off-time.
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Note
The DC current limit varies with duty cycle, switching frequency, and temperature.
7.3.3 Thermal Protection
The junction temperature of the TPSM13604 must not be allowed to exceed its maximum ratings. Thermal
protection is implemented by an internal Thermal Shutdown circuit which activates at 165°C (typical), causing
the device to enter a low-power standby state. In this state, the main MOSFET remains off, causing VO to fall,
and additionally, the CSS capacitor is discharged to ground. Thermal protection helps prevent catastrophic
failures for accidental device overheating. When the junction temperature falls back below 145°C (typical Hyst =
20°C), the SS pin is released, VO rises smoothly, and normal operation resumes.
7.3.4 Zero Coil Current Detection
The current of the lower (synchronous) MOSFET is monitored by a zero coil current detection circuit which
inhibits the synchronous MOSFET when its current reaches zero until the next on-time. This circuit enables DCM
operating mode, which improves efficiency at light loads.
7.3.5 Prebiased Start-up
The TPSM13604 properly starts up into a prebiased output. This start-up situation is common in multiple rail
logic applications where current paths can exist between different power rails during the start-up sequence. The
prebias level of the output voltage must be less than the input UVLO set point. This prevents the output pre-bias
from enabling the regulator through the high-side MOSFET body diode.
7.4 Device Functional Modes
7.4.1 Discontinuous Conduction and Continuous Conduction Modes
At light-load, the regulator operates in discontinuous conduction mode (DCM). With load currents above the
critical conduction point, the regulator operates in continuous conduction mode (CCM). When operating in DCM,
the switching cycle begins at zero amps inductor current, increases up to a peak value, and then recedes back
to zero before the end of the off-time. During the period of time that inductor current is zero, all load current is
supplied by the output capacitor. The next on-time period starts when the voltage on the FB pin falls below the
internal reference. The switching frequency is lower in DCM and varies more with load current as compared to
CCM. Conversion efficiency in DCM is maintained since conduction and switching losses are reduced with the
smaller load and lower switching frequency.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The TPSM13604H is a step down DC-to-DC power module. It is typically used to convert a higher DC voltage to
a lower DC voltage with a maximum peak output current of 4 A. The following design procedure can be used to
select components for the TPSM13604H.
8.2 Typical Application
TPSM13604H
VIN
VOUT
CFF
0.022 µ F
RON
CSS
4700 pF
RENT
VIN
CIN
10 µ F
RFBT
COUT
RENB
RFBB
GND
图8-1. Simplified Application Schematic
8.2.1 Design Requirements
For this example, the following application parameters exist:
• VIN range = up to 36 V
• VOUT = 9 V
• IOUT = 4 A
• Refer to 方程式1 to calculate RENT and RENB
Refer to 图8-1 for more information.
8.2.2 Detailed Design Procedure
8.2.2.1 Design Steps for the TPSM13604 Application
The following list of steps can be used to manually design the TPSM13604 application:
1. Select minimum operating VIN with enable divider resistors.
2. Program VO with divider resistor selection.
3. Program turn-on time with soft-start capacitor selection.
4. Select CO.
5. Select CIN.
6. Set operating frequency with RON
.
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7. Determine module dissipation.
8. Lay out PCB for required thermal performance.
8.2.2.1.1 Enable Divider, RENT, and RENB Selection
The enable input provides a precise 1.18-V reference threshold to allow direct logic drive or connection to a
voltage divider from a higher enable voltage such as VIN. The enable input also incorporates 90 mV (typical) of
hysteresis, resulting in a falling threshold of 1.09 V. The maximum recommended voltage into the EN pin is 6.5
V. For applications where the midpoint of the enable divider exceeds 6.5 V, a small Zener diode can be added to
limit this voltage.
The function of the RENT and RENB dividers is to allow the designer to choose an input voltage below which the
circuit will be disabled. This implements the feature of programmable undervoltage lockout. This is often used in
battery-powered systems to prevent deep discharge of the system battery. It is also useful in system designs for
sequencing of output rails or to prevent early turnon of the supply as the main input voltage rail rises at power
up. Applying the enable divider to the main input rail is often done in the case of higher input voltage systems
such as 24-V AC/DC systems where a lower boundary of operation should be established. In the case of
sequencing supplies, the divider is connected to a rail that becomes active earlier in the power-up cycle than the
TPSM13604 output rail. The two resistors should be chosen based on the following ratio:
RENT / RENB = (VIN-ENABLE / 1.18 V) –1
(1)
The EN pin is internally pulled up to VIN and can be left floating for always-on operation. However, it is good
practice to use the enable divider and turn on the regulator when VIN is close to reaching its nominal value. This
ensures smooth start-up and prevents overloading the input supply.
8.2.2.1.2 Output Voltage Selection
Output voltage is determined by a divider of two resistors connected between VO and ground. The midpoint of
the divider is connected to the FB input. The voltage at FB is compared to a 0.8-V internal reference. In normal
operation, an on-time cycle is initiated when the voltage on the FB pin falls below 0.8 V. The high-side MOSFET
on-time cycle causes the output voltage to rise and the voltage at the FB to exceed 0.8 V. As long as the voltage
at FB is above 0.8 V, on-time cycles do not occur.
The regulated output voltage determined by the external divider resistors RFBT and RFBB is:
VO = 0.8 V × (1 + RFBT / RFBB
)
(2)
(3)
Rearranging terms; the ratio of the feedback resistors for a desired output voltage is:
RFBT / RFBB = (VO / 0.8 V) - 1
These resistors should be chosen from values in the range of 1 kΩ to 50 kΩ.
A feedforward capacitor is placed in parallel with RFBT to improve load step transient response. Its value is
usually determined experimentally by load stepping between DCM and CCM conduction modes and adjusting for
best transient response and minimum output ripple.
A table of values for RFBT, RFBB, and RON is included in the simplified applications schematic (see 图8-1).
8.2.2.1.3 Soft-Start Capacitor, CSS, Selection
Programmable soft start permits the regulator to slowly ramp to its steady-state operating point after being
enabled, thereby reducing current inrush from the input supply and slowing the output voltage rise-time to
prevent overshoot.
Upon turn-on, after all UVLO conditions have been passed, an internal 8-µA current source begins charging the
external soft-start capacitor. The soft-start time duration to reach steady-state operation is given by the formula:
tSS = VREF × CSS / Iss = 0.8 V × CSS / 8 µA
(4)
方程式4 can be rearranged as follows:
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CSS = tSS × 8 μA / 0.8 V
(5)
Use of a 4700-pF capacitor results in 0.5-ms soft-start duration. This is a recommended value. Note high values
of CSS capacitance causes more output voltage droop when a load transient goes across the DCM-CCM
boundary. Use 方程式 22 to find the DCM-CCM boundary load current for the specific operating condition. If a
fast load transient response is desired for steps between DCM and CCM mode, the soft-start capacitor value
must be less than 0.018 µF.
Note the following conditions reset the soft-start capacitor by discharging the SS input to ground with an internal
200-μA current sink:
• The enable input being pulled low
• Thermal shutdown condition
• Overcurrent fault
• Internal VINUVLO
8.2.2.1.4 Output Capacitor, CO, Selection
None of the required output capacitance is contained within the module. At a minimum, the output capacitor
must meet the worst-case RMS current rating of 0.5 × ILR P-P, as calculated in 方程式 23. Beyond that, additional
capacitance reduces output ripple so long as the ESR is low enough to permit it. A minimum value of 10 μF is
generally required. Experimentation is required if the user is attempting to operate with a minimum value. Low-
ESR capacitors, such as ceramic and polymer electrolytic capacitors, are recommended.
8.2.2.1.4.1 Capacitance
方程式6 provides a good first pass approximation of CO for load transient requirements:
CO ≥ISTEP × VFB × L × VIN / (4 × VO × (VIN —VO) × VOUT-TRAN
)
(6)
As an example, for 4-A load step, VIN = 12 V, VOUT = 9 V, VOUT-TRAN = 50 mV:
CO ≥4 A × 0.8 V × 10 μH × 12 V / (4 x 9V ( 12 V –9 V) × 50 mV)
(7)
(8)
CO ≥71 μF
8.2.2.1.4.2 ESR
The ESR of the output capacitor affects the output voltage ripple. High ESR results in larger VOUT peak-to-peak
ripple voltage. Furthermore, high output voltage ripple caused by excessive ESR can trigger the overvoltage
protection monitored at the FB pin. The ESR must be chosen to satisfy the maximum desired VOUT peak-to-peak
ripple voltage and to avoid overvoltage protection during normal operation. The following equations can be used:
ESRMAX-RIPPLE ≤VOUT-RIPPLE / ILR P-P
(9)
where
• ILR P-P is calculated using 方程式23
ESRMAX-OVP < (VFB-OVP - VFB) / (ILR P-P × AFB
where
)
(10)
• AFB is the gain of the feedback network from VOUT to VFB at the switching frequency
As worst-case, assume the gain of AFB with the CFF capacitor at the switching frequency is 1.
The selected capacitor should have sufficient voltage and RMS current rating. The RMS current through the
output capacitor is:
I(COUT(RMS)) = ILR P-P / √12
(11)
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8.2.2.1.5 Input Capacitor, CIN, Selection
The TPSM13604 module contains an internal 0.47-µF input ceramic capacitor. Additional input capacitance is
required externally to the module to handle the input ripple current of the application. This input capacitance
must be as close as possible to the module. Input capacitor selection is generally directed to satisfy the input
ripple current requirements rather than by capacitance value.
Worst-case input ripple current rating is dictated by 方程式12.
I(CIN(RMS)) ≊ 1 / 2 × IO × √(D / 1-D)
(12)
where
• D ≊ VO / VIN
As a point of reference, the worst-case ripple current occurs when the module is presented with full load current
and when VIN = 2 × VO.
Recommended minimum input capacitance is 10-µF X7R ceramic with a voltage rating at least 25% higher than
the maximum applied input voltage for the application. TI also recommends to pay attention to the voltage and
temperature deratings of the capacitor selected. Note that ripple current rating of ceramic capacitors can be
missing from the capacitor data sheet and you may have to contact the capacitor manufacturer for this rating.
If the system design requires a certain maximum value of input ripple voltage ΔVIN to be maintained, then 方程
式13 can be used.
CIN ≥IO × D × (1–D) / fSW-CCM × ΔVIN
(13)
If ΔVIN is 2% of VIN for a 12-V input to a 9-V output application this equals 120 mV and fSW = 300 kHz.
CIN ≥4 A × 9 V / 12 V × (1–9 V/12 V) / (300000 × 0.240 V)
CIN ≥10 μF
(14)
(15)
Additional bulk capacitance with higher ESR can be required to damp any resonant effects of the input
capacitance and parasitic inductance of the incoming supply lines.
8.2.2.1.6 ON-Time, RON, Resistor Selection
Many designs begin with a desired switching frequency in mind. For 4-A applications, 300 kHz is recommended.
方程式16 can be used to calculate the RON value.
fSW(CCM) ≊ VO / (1.3 × 10-10 × RON
This can be rearranged as:
)
(16)
(17)
RON ≊ VO / (1.3 × 10-10 × fSW(CCM)
The selection of RON and fSW(CCM) must be confined by limitations in the on-time and off-time for 节7.1.1.
The on-time of the TPSM13604 timer is determined by the resistor RON and the input voltage VIN. It is calculated
as follows:
tON = (1.3 × 10-10 x RON) / VIN
(18)
The inverse relationship of tON and VIN gives a nearly constant switching frequency as VIN is varied. RON must
be selected such that the on-time at maximum VIN is greater than 150 ns. The on-timer has a limiter to ensure a
minimum of 150 ns for tON. This limits the maximum operating frequency, which is governed by 方程式19.
fSW(MAX) = VO / (VIN(MAX) × 150 ns)
(19)
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This equation can be used to select RON if a certain operating frequency is desired so long as the minimum on-
time of 150 ns is observed. The limit for RON can be calculated as follows:
RON ≥VIN(MAX) × 150 nsec / (1.3 × 10-10
)
(20)
If RON calculated in 方程式17 is less than the minimum value determined in 方程式20, a lower frequency should
be selected. Alternatively, VIN(MAX) can also be limited to keep the frequency unchanged.
Additionally, the minimum off-time of 260 ns (typical) limits the maximum duty ratio. Larger RON (lower FSW) must
be selected in any application requiring large duty ratio.
8.2.2.1.6.1 Discontinuous Conduction and Continuous Conduction Mode Selection
Operating frequency in DCM can be calculated as follows:
2
fSW(DCM) ≊ VO × (VIN - 1) × 10 μH × 1.18 × 1020 × IO / (VIN –VO) × RON
(21)
In CCM, current flows through the inductor through the entire switching cycle and never falls to zero during the
off-time. The switching frequency remains relatively constant with load current and line voltage variations. The
CCM operating frequency can be calculated using 方程式16.
The approximate formula for determining the DCM/CCM boundary is as follows:
IDCB ≊ VO × (VIN –VO) / ( 2 × 10 μH × fSW(CCM) × VIN)
(22)
The inductor internal to the module is 10 μH. This value was chosen as a good balance between low and high
input voltage applications. The main parameter affected by the inductor is the amplitude of the inductor ripple
current (ILR). ILR can be calculated with:
ILR P-P = VO × (VIN- VO) / (10 µH × fSW × VIN)
(23)
where
• VIN is the maximum input voltage and fSW is determined from 方程式16
If the output current, IO, is determined by assuming that IO = IL, the higher and lower peak of ILR can be
determined. Be aware that the lower peak of ILR must be positive if CCM operation is required.
8.2.3 Application Curve
100
95
90
85
80
VIN = 18V
VIN = 24V
VIN = 36V
75
70
0
0.5
1
1.5
2
2.5
Output Current (A)
3
3.5
4
图8-2. Efficiency VOUT = 9.0 V, TA = 25°C
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9 Power Supply Recommendations
The TPSM13604 device is designed to operate from an input voltage supply range between 5 V and 36 V. This
input supply must be well-regulated and able to withstand maximum input current and maintain a stable voltage.
The resistance of the input supply rail must be low enough that an input current transient does not cause a high
enough drop at the TPSM13604 supply voltage that can cause a false UVLO fault triggering and system reset. If
the input supply is more than a few inches from the TPSM13604, additional bulk capacitance can be required in
addition to the ceramic bypass capacitors. The amount of bulk capacitance is not critical, but a 47-μF or 100-
μF electrolytic capacitor is a typical choice.
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10 Layout
10.1 Layout Guidelines
PCB layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a
DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage drop in
the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability.
Good layout can be implemented by following a few simple design rules.
1. Minimize the area of switched current loops.
From an EMI reduction standpoint, it is imperative to minimize the high di/dt paths during PCB layout. The
high current loops that do not overlap have high di/dt content that cause observable high frequency noise on
the output pin if the input capacitor (Cin1) is placed at a distance away from the TPSM13604. Therefore,
place CIN1 as close as possible to the TPSM13604 VIN and GND exposed pad. This minimizes the high di/dt
area and reduce radiated EMI. Additionally, grounding for both the input and output capacitor must consist of
a localized top-side plane that connects to the GND exposed pad (EP).
2. Have a single point ground.
The ground connections for the feedback, soft start, and enable components should be routed to the GND
pin of the device. This prevents any switched or load currents from flowing in the analog ground traces. If not
properly handled, poor grounding can result in degraded load regulation or erratic output voltage ripple
behavior. Provide the single point ground connection from pin 4 to EP.
3. Minimize trace length to the FB pin.
Both feedback resistors, RFBT and RFBB, and the feedforward capacitor, CFF, must be close to the FB pin.
Since the FB node is high impedance, maintain the copper area as small as possible. The trace are from
RFBT, RFBB, and CFF must be routed away from the body of the TPSM13604 to minimize noise.
4. Make input and output bus connections as wide as possible.
This reduces any voltage drops on the input or output of the converter and maximizes efficiency. To optimize
voltage accuracy at the load, ensure that a separate feedback voltage sense trace is made to the load.
Doing so corrects for voltage drops and provide optimum output accuracy.
5. Provide adequate device heat-sinking.
Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer.
If the PCB has a plurality of copper layers, these thermal vias can also be employed to make connection to
inner layer heat-spreading ground planes. For best results use a 6 × 6 via array with minimum via diameter
of 8 mils thermal vias spaced 59 mils (1.5 mm). Ensure enough copper area is used for heat-sinking to keep
the junction temperature below 125°C.
10.1.1 Power Module SMT Guidelines
The following recommendations are for a standard module surface mount assembly:
• Land Pattern –Follow the PCB land pattern with either soldermask defined or non-soldermask defined pads.
• Stencil Aperture
– For the exposed die attach pad (DAP), adjust the stencil for approximately 80% coverage of the PCB land
pattern.
– For all other I/O pads, use a 1:1 ratio between the aperture and the land pattern recommendation.
• Solder Paste –Use a standard SAC Alloy such as SAC 305, type 3 or higher.
• Stencil Thickness –0.125 mm to 0.15 mm
• Reflow - Refer to solder paste supplier recommendation and optimized per board size and density.
• Refer to AN Design Summary LMZ1xxx and LMZ2xxx Power Modules Family for reflow information.
• Maximum number of reflows allowed is one.
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图10-1. Sample Reflow Profile
表10-1. Sample Reflow Profile Table
MAX TEMP
REACHED TIME ABOVE REACHED TIME ABOVE REACHED TIME ABOVE REACHED
PROBE
(°C)
242.5
242.5
241
MAX TEMP
235°C
235°C
245°C
245°C
260°C
260°C
1
2
3
6.58
0.49
6.39
0
0
0
0
0
0
–
–
7.1
0.55
6.31
7.1
–
7.09
0.42
6.44
–
–
10.2 Layout Example
图10-2. Minimize Area of Current Loops in Buck Module
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Top View
Thermal Vias
GND
GND
EPAD
CIN
COUT
1
2
3
4
5
6
7
VOUT
VIN
RON
RFBT
RENT
CFF
CSS
RENB
RFBB
GND Plane
图10-3. PCB Layout Guide
10.2.1 Power Dissipation and Board Thermal Requirements
For a design case of VIN = 12 V, VOUT = 9.5 V, IOUT = 4 A, TA (MAX) = 50°C , TJUNCTION = 125°C, and continuous
operation, the device must see a maximum junction-to-ambient thermal resistance of:
RθJA-MAX < (TJ-MAX - TA(MAX)) / PD
(24)
This RθJA-MAX ensures that the junction temperature of the regulator under continuous operation does not
exceed TJ-MAX in the particular application ambient temperature.
To calculate the required RθJA-MAX, you need to get an estimate for the power losses in the IC. 图 10-4 is taken
form the Typical Characteristics and shows the power dissipation of the TPSM13604 for VOUT = 9.5 V.
图10-4. Power Dissipation VOUT = 9.5 V
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Using the 50°C TA power dissipation data as a conservative starting point, the power dissipation PD for VIN = 12
V and VOUT = 9.5 V is estimated to be 4.85 W under continuous operation. The necessary RθJA-MAX can now be
calculated.
R
θJA-MAX < (125°C - 50°C) / 4.85W
θJA-MAX < 15.5°C/W
(25)
(26)
R
To achieve this thermal resistance, the PCB is required to dissipate the heat effectively. The area of the PCB has
a direct effect on the overall junction-to-ambient thermal resistance. To estimate the necessary copper area,
refer to 图 10-5. This graph is taken from the 节 6.6 (图 6-12) and shows how the RθJA varies with the PCB
area.
40
0LFM (0m/s) air
225LFM (1.14m/s) air
500LFM (2.54m/s) air
35
Evaluation Board Area
30
25
20
15
10
5
0
0
10
20
30
40
50
60
2
BOARD AREA (cm )
图10-5. Package Thermal Resistance RθJA 4-Layer PCB with 1-oz Copper
For RθJA-MAX < 15.5°C/W and only natural convection (that is, no air flow), the PCB area must be at least 52
cm2. This corresponds to a square board with 7.25-cm × 7.25-cm (2.85 in x 2.85 in) copper area, four layers, and
1-oz copper thickness. Higher copper thickness further improves the overall thermal performance. As a
reference, the evaluation board has 2-oz copper on the top and bottom layers, achieving RθJA of 14.9°C/W for
the same board area. Note thermal vias must be placed under the IC package to easily transfer heat from the
top layer of the PCB to the inner layers and the bottom layer. For more guidelines and insight on PCB copper
area, thermal vias placement, and general thermal design practices, see the application note AN-2020 Thermal
Design By Insight, Not Hindsight.
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11 Device and Documentation Support
11.1 Device Support
11.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
11.2 Documentation Support
11.2.1 Related Documentation
• AN-2027 Inverting Application for the LMZ14203 SIMPLE SWITCHER Power Module, SNVA425
• Evaluation Board Application Note AN-2024, SNVA422
• AN-2026 Effect of PCB Design on Thermal Performance of SIMPLE SWITCHER Power Modules, SNVA424
• AN-2020 Thermal Design By Insight, Not Hindsight, SNVA419
• AN Design Summary LMZ1xxx and LMZ2xxx Power Modules Family, SNAA214
11.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
11.7 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPSM13604HNDWR
ACTIVE
TO-PMOD
NDW
7
500
RoHS & Green
SN
Level-3-245C-168 HR
-40 to 125
TPSM13604
HNDW
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
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TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPSM13604HNDWR
TO-
NDW
7
500
330.0
24.4
10.6 14.22
5.0
16.0
24.0
Q2
PMOD
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
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TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TO-PMOD NDW
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 45.0
TPSM13604HNDWR
7
500
Pack Materials-Page 2
MECHANICAL DATA
NDW0007A
BOTTOM SIDE OF PACKAGE
TOP SIDE OF PACKAGE
TZA07A (Rev D)
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