TPSM265R1V3SILR [TI]
采用 2.8mm x 3.7mm 封装的 3V 至 65V 输入、100mA 降压电源模块
| SIL | 10 | -40 to 125;
| 型号： | TPSM265R1V3SILR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 2.8mm x 3.7mm 封装的 3V 至 65V 输入、100mA 降压电源模块 | SIL | 10 | -40 to 125 电源电路 |
| 文件： | 总35页 (文件大小：2204K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ZHCSK64B – OCTOBER 2019 – REVISED DECEMBER 2020
TPSM265R1
具有超低 IQ 的 TPSM265R1 65V 输入、100mA 电源模块
1 特性
3 说明
• 3V 至 65V 的宽输入电压范围
TPSM265R1 是一款紧凑、易用的模块，其运行时具有
宽输入电压范围，最大连续输入电压高达 65V。该模
块完全集成了一个控制器、多个 MOSFET 和一个输出
电感器。该模块设计用于在小型 PCB 封装中快速、简
便地实施电源设计。此模块具有 3.3V 和 5V 两种固定
输出电压选项，和一个 1.223V 至 15V 的可调节输出
电压选项。每种选项的负载电流额定值均为 100mA。
TPSM265R1 在脉冲频率调制 (PFM) 模式下运行，从
而提高了轻载条件下的效率。其控制方案无需环路补
偿，并可提供出色的线路和负载瞬态响应。
•
输出电压选项：
– 可调节电压：1.223V 至 15V
– 固定电压：3.3V 或 5V
• 100mA 输出电流
• 10.5µA 静态电流
• ±1% 内部电压基准
• PFM 运行模式
•
•
•
•
•
•
•
–40°C 至 125°C 的环境温度范围
可实现低 EMI 的有效压摆率控制
符合 CISPR11 (EN55011) EMI 标准
单调启动至预偏置输出
虽然 TPSM265R1 采用简易的小尺寸设计，但其可提
供多种功能。精密使能端、可调 UVLO 和迟滞功能可
满足特定的上电和断电要求。可选/可调的启动时序选
项包括最短延迟（无软启动）、内部固定值 (900µs) 以
及可使用电容器进行外部编程的软启动。可以使用开漏
PGOOD 指示器进行排序和输出电压监控。其超小型
2.8mm × 3.7mm × 1.9mm 封装非常适合空间受限型应
用。
电源正常状态标志
具有迟滞功能的精密使能和输入 UVLO
具有迟滞功能的热关断保护
• 2.8mm x 3.7mm x 1.9mm 封装
•
使用 WEBENCH® Power Designer 并借助
TPSM265R1 创建定制稳压器设计
器件信息
器件型号(1)
输出
1.223V 至 15V
3.3V
封装
2 应用
TPSM265R1
TPSM265R1V3
TPSM265R1V5
•
•
现场发送器和过程传感器
位置 和 接近传感器
uSiP
5V
• PLC、DCS 和 PAC
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
•
•
伺服驱动器电源模块
负输出应用
100
90
80
70
60
50
40
TPSM265R1V5
VIN
VIN
PGOOD
VOUT
EN
VOUT
CIN
HYS
SS
SENSE+
30
20
10
0
VIN
24 V
36 V
48 V
60 V
COUT
GND
0
10
20
30
40
50
60
Output Current (mA)
70
80
90 100
15VO
典型效率 (VOUT = 15V)
典型原理图（固定输出）
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNVSBF6
TPSM265R1
ZHCSK64B – OCTOBER 2019 – REVISED DECEMBER 2020
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Table of Contents
7.3 Feature Description...................................................13
7.4 Device Functional Modes..........................................17
8 Applications and Implementation................................18
8.1 Application Information............................................. 18
8.2 Typical Applications.................................................. 18
9 Power Supply Recommendations................................21
10 Layout...........................................................................22
10.1 Layout Guidelines................................................... 22
10.2 Layout Example...................................................... 22
11 Device and Documentation Support..........................26
11.1 Device Support........................................................26
11.2 Documentation Support.......................................... 26
11.3 Receiving Notification of Documentation Updates..26
11.4 Support Resources................................................. 26
11.5 Trademarks............................................................. 27
11.6 Electrostatic Discharge Caution..............................27
11.7 Glossary..................................................................27
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics (VIN = 5 V)............................. 7
6.7 Typical Characteristics (VIN = 12 V)........................... 8
6.8 Typical Characteristics (VIN = 24 V)........................... 9
6.9 Typical Characteristics (VIN = 48 V)......................... 10
6.10 Typical Characteristics (VIN = 65 V)....................... 11
7 Detailed Description......................................................12
7.1 Overview...................................................................12
7.2 Functional Block Diagram.........................................12
Information.................................................................... 27
4 Revision History
Changes from Revision A (November 2019) to Revision B (December 2020)
Page
更新了整个文档的表、图和交叉参考的编号格式。.............................................................................................1
将器件状态从“预告信息”更改为“量产数据”................................................................................................ 1
•
•
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5 Pin Configuration and Functions
1
2
3
4
5
10
VOUT
PGOOD
9
8
7
6
SS
EN
SENSE+
/ FB
11
GND
GND
VIN
HYS
VIN
GND
图 5-1. 10-Pin uSiP Exposed Thermal Pad SIL-10C Package (Top View)
表 5-1. Pin Functions
PIN
NAME
TYPE(1)
DESCRIPTION
NO.
Output voltage pin. The VOUT pin is connected to the internal output inductor. Connect the VOUT pin
to an external output capacitor and the output load. The output capacitor connections must be made
as close as possible to the VOUT and GND pin 11 of the module. See 节 10.2.
1
VOUT
O
Soft-start programming pin. If the SS pin is floating, the output voltage ramp up time is approximately
1 ms after the device is enabled by the EN pin. If a 100-kΩ resistor is placed from the SS pin to GND,
the internal soft start is disabled and the output voltage ramps up immediately after the device is
enabled with the EN pin. Other output voltage ramp up times can be obtained by connecting an
appropriate capacitance from the SS pin to GND.
2
SS
I
Ground pins. Connect all GND pins to the system ground plane. Pin 3 is not connected to GND
internal to the module. Connect pin 3 directly to pin 11 on the host PCB. See 节 10.2.
3, 6, 11
4, 5
GND
VIN
G
I
Input supply pins. The VIN pins are connected to the internal controller and power MOSFETs. Connect
the VIN pins to an external input capacitor and the input power source. The input capacitor
connections must be made as close as possible to the VIN pins and GND pin 6 of the module. See 节
10.2.
Enable hysteresis pin. The open-drain HYS pin can be used along with external resistors to program
the hysteresis of a user-defined UVLO using the EN pin. HYS is internally pulled to GND when EN is
below its turnon threshold and HYS goes open drain when EN is above its turnon threshold.
7
HYS
O
Output voltage feedback pin. For fixed output voltage options, the SENSE+ pin must be externally
connected to VOUT. For the adjustable output voltage option, the FB pin must be connected to an
external resistor divider that is connected between VOUT and GND.
8
9
SENSE+/FB
EN
I
I
Enable pin. The module is enabled when the EN pin is pulled high and disabled when the EN pin is
pulled low. An external resistor divider can be connected to the EN pin to act as an external UVLO.
Power Good pin. The open-drain PGOOD pin is pulled low when the SENSE+ or FB pin is below the
VOUT regulation target. An external 10-kΩ to 100-kΩ pullup resistor can be used to pull the PGOOD
pin high when VOUT meets the regulation target.
10
PGOOD
O
(1) G = Ground, I = Input, O = Output
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating junction temperature range (unless otherwise noted) (1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–40
–55
MAX
68
UNIT
V
VIN, EN
SENSE+, PGOOD
Input voltage
HYS
16
V
7
V
FB, SS
3.6
16
V
Output voltage
VOUT
V
Operating junction temperature, TJ
Storage temperature, Tstg
125
150
260
3
°C
°C
°C
Peak reflow case temperature
Maximum number of reflows allowed
Mechanical shock
Mil-STD-883D, Method 2002.3, 1 msec, 1/2 sine, mounted
Mil-STD-883D, Method 2007.2, 20 to 2000 Hz
1500
20
G
G
Mechanical vibration
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
±2500
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over operating ambient temperature range (unless otherwise noted)
MIN
NOM
MAX
65
12
5
UNIT
V
VIN
3(1)
Input voltage
PGOOD
HYS
V
V
Adjustable option
Fixed 5 V option
Fixed 3.3 V option
1.223
15
V
Output voltage
VOUT
5
V
3.3
V
Output current
Iout
100
125
mA
°C
µF
µF
TA
Operating ambient temperature
Input capacitance
Output capacitance
–40
1(2)
CIN
Ceramic
Ceramic
COUT
10(3)
(1) The minimum input voltage is 3.0 V or (VOUT + 1 V), whichever is greater.
(2) See 节 8.2.2.3 of the data sheet for more information.
(3) See 节 7.3.3 of the data sheet for more information.
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6.4 Thermal Information
TPSM265R1
THERMAL METRIC(1)
SIL-10C
10 PINS
49.7
UNIT
RθJA
ψJT
Junction-to-ambient thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
°C/W
°C/W
°C/W
2.3
28.7
ψJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics Application
Report.
6.5 Electrical Characteristics
Limits apply over TA = –40°C to +125°C, VIN = 12 V, VOUT = 5 V, (unless otherwise noted); CIN1 = 1 µF, 100-V, 1206
ceramic, CIN2 = 33 µF, 100-V, electrolytic (optional), and COUT = 47 µF, 16-V, 1210 ceramic. Minimum and maximum limits
are specified through production test or by design. Typical values represent the most likely parametric norm and are provided
for reference only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY VOLTAGE
VIN
Input supply voltage range
VIN UVLO rising threshold
VIN UVLO falling threshold
Over IOUT range
VIN rising
3(1)
2.60
2.35
65
2.95
2.60
V
V
V
2.75
2.45
UVLO
VIN falling
VIN operating non-switching supply
current
IQ(VIN)
VFB = 1.5 V, TA = 25°C
VEN = 0 V, TA = 25°C
10.5
4.6
15
µA
µA
ISD(VIN)
ENABLE
VEN(rise)
VEN(fall)
VEN(hyst)
VEN(sd)
VIN shutdown supply current
6.0
EN voltage rising threshold
EN voltage falling threshold
EN voltage hysteresis
EN voltage rising
EN voltage falling
1.163
1.109
1.212
1.144
68
1.262
1.178
V
V
mV
V
EN shutdown threshold
HYS on-resistance
EN voltage falling
VEN = 1 V
0.3
0.6
RHYS
80
200
100
Ω
IHYS(LKG)
HYS off-state leakage current
VEN = 1.5 V, VHYS = 5.5 V
10
nA
FEEDBACK (Adjustable option)
Lower regulation threshold
Upper regulation threshold
Hysteresis
1.205
1.220
1.223
1.233
10
1.241
1.246
V
V
Feedback voltage(2) (4)
mV
VFB
Line regulation
Over VIN range, TA = 25°C, IOUT = 0 A
Over IOUT range, TA = 25°C
-40°C ≤ TA = TJ ≤ 125°C, IOUT = 0 A
VFB = 1 V
0.3%
0.3%
0.5%
Load regulation
Temperature variation
IFB
Input bias current into FB pin
100
5.1
nA
V
OUTPUT VOLTAGE (Fixed 5 V option)
Output voltage set-point
SENSE+ connected to VOUT
4.9
5.0
0.3%
0.3%
0.5%
6.7
Line regulation
VOUT
Over VIN range, TA = 25°C, IOUT = 0 A
Over IOUT range, TA = 25°C
Load regulation
Temperature variation
-40°C ≤ TA = TJ ≤ 125°C, IOUT = 0 A
ISENSE+
eff
SENSE+ input current
Efficiency
µA
V
VOUT = 5.0 V, IOUT = 50 mA
83.0%
OUTPUT VOLTAGE (Fixed 3.3 V option)
Output voltage set-point
SENSE+ connected to VOUT
3.23
3.3
0.3%
0.3%
0.5%
3.9
3.37
Line regulation
VOUT
Over VIN range, TA = 25°C, IOUT = 0 A
Over IOUT range, TA = 25°C
Load regulation
Temperature variation
-40°C ≤ TA = TJ ≤ 125°C, IOUT = 0 A
ISENSE+
SENSE+ input current
µA
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6.5 Electrical Characteristics (continued)
Limits apply over TA = –40°C to +125°C, VIN = 12 V, VOUT = 5 V, (unless otherwise noted); CIN1 = 1 µF, 100-V, 1206
ceramic, CIN2 = 33 µF, 100-V, electrolytic (optional), and COUT = 47 µF, 16-V, 1210 ceramic. Minimum and maximum limits
are specified through production test or by design. Typical values represent the most likely parametric norm and are provided
for reference only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
eff
Efficiency
VOUT = 3.3 V, IOUT = 50 mA
77.2%
CURRENT
IOUT
Output current
See SOA curves for any thermal derating
VOUT foldback
0
100
mA
mA
IOCL
Overcurrent limit threshold
130
SOFT-START
ISS
Soft-start charge current
Soft-start rise time
VSS = 1 V
10
µA
µs
TSS
SS pin open
900
POWER GOOD
PGOOD
PGOOD
PGOOD threshold
PGOOD threshold
PGOOD high, VOUT rising
PGOOD low, VOUT falling
VPGOOD = 5.5 V, PGOOD high
PGOOD low
94%
87%
10
IPGOOD(LKG) PGOOD leakage current
100
200
nA
RPGOOD
PGOOD ON-resistance
80
Ω
Min VIN for valid PGOOD output
IPGOOD = 0.1 mA, VPGOOD < 0.5 V
1.2
1.65
V
THERMAL SHUTDOWN
TSDN
Thermal shutdown threshold (3)
Thermal shutdown hysteresis (3)
Temperature rising
170
10
°C
°C
THYST
(1) The recommended minimum input voltage is 3.0 V or (VOUT + 1 V), whichever is greater.
(2) The FB pin has both lower and upper thresholds associated with the hysteretic control scheme of the module.
(3) Specified by design. Not production tested.
(4) The overall output voltage tolerance will be affected by the tolerance of the external RFBT and RFBB resistors.
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6.6 Typical Characteristics (VIN = 5 V)
Refer to 节 8.2 for circuit designs. TA = 25°C unless otherwise noted.
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VOUT
3.3 V
2.5 V
1.2 V
VOUT
3.3 V
2.5 V
1.2 V
0.1
1
10
100
0
10
20
30
40
50
60
Output Current (mA)
70
80
90 100
Output Current (mA)
D002
D001
图 6-2. Efficiency Log Scale
图 6-1. Efficiency
160
120
80
40
0
120
100
80
60
40
20
0
VOUT
VOUT
3.3 V
2.5 V
1.2 V
3.3 V
2.5 V
1.2 V
0
10
20
30
40
Output Current (mA)
50
60
70
80
90 100
0
10
20
30
40
Output Current (mA)
50
60
70
80
90 100
D003
D004
COUT = 47 µF, 16-V, ceramic
图 6-3. Power Dissipation
图 6-4. Output Voltage Ripple
135
125
115
105
95
85
75
VOUT
3.3 V
2.5 V
1.2 V
65
55
0
10
20
30
40
50
60
Output Current (mA)
70
80
90 100
D005
Applies to a device soldered to a 50-mm × 75-mm, 4-layer PCB
图 6-5. Safe Operating Area
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6.7 Typical Characteristics (VIN = 12 V)
Refer to 节 8.2 for circuit designs. TA = 25°C unless otherwise noted.
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VOUT
5.0 V
3.3 V
2.5 V
1.2 V
VOUT
5.0 V
3.3 V
2.5 V
1.2 V
0
10
20
30
40
50
60
Output Current (mA)
70
80
90 100
0.1
1
10
100
Output Current (mA)
D007
D008
图 6-6. Efficiency
图 6-7. Efficiency Log Scale
200
150
100
50
140
120
100
80
VOUT
5.0 V
3.3 V
2.5 V
1.2 V
VOUT
5.0 V
3.3 V
2.5 V
1.2 V
60
40
20
0
0
0
10
20
30
40
Output Current (mA)
50
60
70
80
90 100
0
10
20
30
40
Output Current (mA)
50
60
70
80
90 100
D009
D010
COUT = 47 µF, 16-V, ceramic
图 6-8. Power Dissipation
图 6-9. Output Voltage Ripple
135
125
115
105
95
85
VOUT
5 V
75
3.3 V
2.5 V
1.2 V
65
55
0
10
20
30
40
50
60
Output Current (mA)
70
80
90 100
D011
Applies to a device soldered to a 50-mm × 75-mm, 4-layer PCB
图 6-10. Safe Operating Area
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6.8 Typical Characteristics (VIN = 24 V)
Refer to the 节 8.2 for circuit designs. TA = 25°C unless otherwise noted.
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VOUT
15 V
12 V
5 V
3.3 V
2.5 V
VOUT
15 V
12 V
5 V
3.3 V
2.5 V
0
10
20
30
40
50
60
Output Current (mA)
70
80
90 100
0.1
1
10
100
Output Current (mA)
D013
D014
图 6-11. Efficiency
图 6-12. Efficiency Log Scale
200
160
120
80
280
240
200
160
120
80
VOUT
VOUT
15 V
12 V
5 V
3.3 V
2.5 V
15 V
12 V
5 V
3.3 V
2.5 V
40
40
0
0
0
10
20
30
40
Output Current (mA)
50
60
70
80
90 100
0
10
20
30
40
Output Current (mA)
50
60
70
80
90 100
D015
D016
COUT = 47 µF, 16-V, ceramic
图 6-13. Power Dissipation
图 6-14. Output Voltage Ripple
135
125
115
105
95
85
VOUT
15 V
12 V
5 V
75
65
3.3 V
2.5 V
55
0
10
20
30
40
50
60
Output Current (mA)
70
80
90 100
D017
Applies to a device soldered to a 50 mm × 75 mm, 4-layer PCB
图 6-15. Safe Operating Area
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6.9 Typical Characteristics (VIN = 48 V)
Refer to 节 8.2 for circuit designs. TA = 25°C unless otherwise noted.
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VOUT
15 V
12 V
5 V
3.3 V
VOUT
15 V
12 V
5 V
3.3 V
0
10
20
30
40
50
60
Output Current (mA)
70
80
90 100
0.1
1
10
100
Output Current (mA)
D019
D020
图 6-16. Efficiency
图 6-17. Efficiency Log Scale
350
300
250
200
150
100
50
300
250
200
150
100
50
VOUT
15 V
12 V
5 V
3.3 V
VOUT
15 V
12 V
5 V
3.3 V
0
0
0
10
20
30
40
50
60
Output Current (mA)
70
80
90 100
0
10
20
30
40
50
60
Output Current (mA)
70
80
90 100
D022
D021
COUT = 47 µF, 16-V, ceramic
图 6-19. Output Voltage Ripple
图 6-18. Power Dissipation
135
125
115
105
95
85
VOUT
15 V
12 V
5 V
75
65
3.3 V
55
0
10
20
30
40
50
60
Output Current (mA)
70
80
90 100
D023
Applies to a device soldered to a 50-mm × 75-mm, 4-layer PCB
图 6-20. Safe Operating Area
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6.10 Typical Characteristics (VIN = 65 V)
Refer to 节 8.2 for circuit designs. TA = 25°C unless otherwise noted.
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VOUT
15 V
12 V
5 V
VOUT
15 V
12 V
5 V
0
10
20
30
40
50
60
Output Current (mA)
70
80
90 100
0.1
1
10
100
Output Current (mA)
D025
D026
图 6-21. Efficiency
图 6-22. Efficiency Log Scale
350
300
250
200
150
100
50
300
250
200
150
100
50
VOUT
VOUT
15 V
12 V
5 V
15 V
12 V
5 V
0
0
0
10
20
30
40
Output Current (mA)
50
60
70
80
90 100
0
10
20
30
40
Output Current (mA)
50
60
70
80
90 100
D027
D028
COUT = 47 µF, 16-V, ceramic
图 6-23. Power Dissipation
图 6-24. Output Voltage Ripple
135
125
115
105
95
85
75
VOUT
15 V
12 V
5 V
65
55
0
10
20
30
40
50
60
Output Current (mA)
70
80
90 100
D029
Applies to a device soldered to a 50-mm × 75-mm, 4-layer PCB
图 6-25. Safe Operating Area
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7 Detailed Description
7.1 Overview
The TPSM265R1 converter is an easy-to-use, synchronous buck, DC-DC power module that operates from a 3-
V to 65-V supply voltage. The device is intended for step-down conversions from 3.3-V, 5-V, 12-V, 24-V, and 48-
V unregulated, semi-regulated, or fully-regulated supply rails. With integrated power controller, inductor, and
MOSFETs, the TPSM265R1 delivers up to 100-mA DC load current, with high efficiency and ultra-low input
quiescent current, in a very small solution size. Although designed for simple implementation, this device offers
flexibility to optimize its usage according to the target application. Operation in pulse frequency modulation
(PFM) mode achieves exceptional light-load efficiency performance. Control-loop compensation is not required,
reducing design time and external component count.
The TPSM265R1 incorporates several features for comprehensive system requirements, including an open-
drain Power Good circuit for power-rail sequencing and fault reporting, internally-fixed, or externally-adjustable
soft start, monotonic start-up into prebiased loads, precision enable with customizable hysteresis for
programmable line undervoltage lockout (UVLO), and thermal shutdown with automatic recovery. These features
enable a flexible and easy-to-use platform for a wide range of applications. The pin arrangement is designed for
simple layout, requiring as few as two external components.
7.2 Functional Block Diagram
Thermal
Shutdown
EN
1.212V
1.144V
UVLO
LDO
HYS
VIN
ENABLE
CURRENT
LIMIT
47 µH
VOUT
Control
Logic
ZERO CROSS
DETECT
+
ZC
SENSE+/FB
HYSTERETIC
MODE
R1(1)
+
+
R2(1)
Vref
1.223V
UV
SOFT-
START
PGOOD
SS
Note:
(1) R1, R2 are implemented in the fixed output voltage versions only.
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7.3 Feature Description
7.3.1 Adjustable Output Voltage (FB)
The TPSM265R1 has three voltage feedback options: fixed 3.3 V, fixed 5 V, and adjustable 1.223 V to 15 V. The
fixed 3.3-V and 5-V versions include internal feedback resistors that sense the output directly through the
SENSE+ pin; the adjustable voltage option senses the output through an external resistor divider connected
from the output to the FB pin.
Setting the output voltage of the adjustable option requires two resistors: RFBT and RFBB (see 图 7-1). Connect
RFBT between VOUT, at the regulation point, and the FB pin. Connect RFBB between the FB pin and GND (pin 6).
A resistor divider programs the ratio from output voltage VOUT to FB. The recommended value of RFBT is 100
kΩ. The value for RFBB can be calculated using 方程式 1.
1.223
RFBB
=
× RFBT
1.223
VOUT
(1)
VOUT
RFBT
100 kꢀ
FB
RFBB
GND
图 7-1. FB Resistor Divider
表 7-1. Standard RFBB Values
RFBB (kΩ) (1)
RFBB (kΩ) (1)
59.0
VOUT (V)
1.223
1.5
VOUT (V)
open
442
3.3
5.0
7.5
10
32.4
1.8
210
19.6
2.0
158
14.0
2.5
95.3
68.1
12
11.3
3.0
15
8.87
(1) RFBT = 100 kΩ
Selecting an RFBT value of 100 kΩ is recommended for most applications. A larger RFBT consumes less DC
current, which is mandatory if light-load efficiency, is critical. However, RFBT larger than 1 MΩ is not
recommended as the feedback path becomes more susceptible to noise. High feedback resistance generally
requires more careful layout of the feedback path. It is important to keep the feedback trace as short as possible
while keeping the feedback trace away from the noisy area of the PCB. For more layout recommendations, see
节 10.
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7.3.2 Input Capacitor Selection
The TPSM265R1 requires a minimum of 1 µF of ceramic type input capacitance. Use only high-quality ceramic
type X5R or X7R capacitors with sufficient voltage rating. TI recommends adding additional capacitance for
applications with transient load requirements. The voltage rating of input capacitors must be greater than the
maximum input voltage. To compensate for the derating of ceramic capacitors, TI recommends a voltage rating
of twice the maximum input voltage or placing multiple capacitors in parallel. 表 7-2 includes a preferred list of
capacitors by vendor.
表 7-2. Recommended Input Capacitors
CAPACITOR CHARACTERISTICS
TEMPERATURE
VENDOR(1)
PART NUMBER
CASE SIZE
CAPACITANCE (2)
(µF)
COEFFICIENT(3)
WORKING VOLTAGE (V)
Murata
TDK
X7R
X7R
X7S
X7S
X7S
X7S
X7R
X7R
GCJ21BR71H105KA01L
0805
0805
0805
0805
1206
1206
1206
1206
50
50
1
1
CGA4J3X7R1H105K125AB
GRJ21BC72A105KE11L
CGA4J3X7S2A105K125AB
GCM31CC72A225KE02L
C3216X7S2A225K160AB
CGA5L3X7R1H475K160AE
GRM31CR71H475KA12L
Murata
TDK
100
100
100
100
50
1
1
Murata
TDK
2.2
2.2
4.7
4.7
TDK
Murata
50
(1) Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process
requirements for any capacitors identified in this table.
(2) Specified capacitance values
(3) Maximum ESR at 100 kHz, 25°C
7.3.3 Output Capacitor Selection
The minimum amount of required output capacitance for the TPSM265R1 is 10 µF of ceramic type. TI
recommends adding additional capacitance for applications with transient load requirements. See 表 7-3 for a
preferred list of output capacitors by vendor.
表 7-3. Recommended Output Capacitors
CAPACITOR CHARACTERISTICS
TEMPERATURE
COEFFICIENT
VENDOR(1)
TDK
PART NUMBER
CASE SIZE
VOLTAGE (V)
CAPACITANCE (µF)(2)
X7R
X7R
X7R
X7S
X5R
X5R
X5R
X6S
X7R
X5R
X5R
CGA5L1X7R1C106K160AC
1206
1206
1206
1206
1210
1210
1206
1206
1210
1210
1210
16
16
25
25
16
16
25
25
25
10
16
10
10
10
10
22
22
22
22
22
47
47
Murata
TDK
GCM31CR71C106KA64L
C3216X7R1E106K160AB
GCJ31CC71E106KA15L
C3225X5R1C226M
Murata
TDK
Murata
TDK
GRM32ER61C226K
C3216X5R1E226M160AB
GRM31CC81E226K
GRM32ER71E226M
C3225X5R1A476M
Murata
Murata
TDK
Murata
GRM32ER61C476K
(1) Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process
requirements for any capacitors identified in 表 7-3.
(2) Specified capacitance values
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7.3.4 Precision Enable (EN), Undervoltage Lockout (UVLO), and Hysteresis (HYS)
The EN pin provides precision ON and OFF control for the TPSM265R1. Once the EN pin voltage exceeds the
threshold voltage, the device starts operation. The simplest way to enable the TPSM265R1 is to connect EN
directly to VIN. This allows the TPSM265R1 to start up when VIN is within its valid operating range. An external
logic signal can also be used to drive the EN input to toggle the output on and off and for system sequencing or
protection.
The TPSM265R1 implements internal undervoltage lockout (UVLO) circuitry on the VIN pin. The device is
disabled when the VIN pin voltage is below the internal VIN UVLO threshold. The internal VIN UVLO rising
threshold is 2.95 V (max) with a typical hysteresis of 300 mV.
If an application requires a higher UVLO threshold, the EN input supports adjustable UVLO by connecting a
resistor divider from VIN to the EN pin. The EN pin connects to an internal comparator referenced to a 1.212-V
bandgap voltage with 68-mV hysteresis. However, applications requiring specific power-up and power-down
requirements can program the hysteresis voltage independently using the HYS pin. 图 7-2 shows the resistor
divider connection to establish a precision UVLO level with fixed internal hysteresis. 图 7-3 shows the resistor
divider connection used to set the precision UVLO level as well as the adjustable hysteresis.
VIN
VIN
VIN
EN
VIN
EN
RUV1
RUV1
Enable
Comparator
Enable
Comparator
RUV2
1.212V
1.144V
RUV2
1.212V
1.144V
HYS
RHYS
80Ω
图 7-2. Programmable VIN UVLO with Fixed
Hysteresis
图 7-3. Programmable VIN UVLO with Adjustable
Hysteresis
Use 方程式 2 and 方程式 3 to calculate the input UVLO voltages turnon and turnoff voltages, respectively.
≈
’
÷
◊
RUV1
RUV2
V
= 1.212V ∂ 1+
∆
IN(on)
«
(2)
(3)
≈
’
÷
◊
RUV1
V
= 1.144V ∂ 1+
∆
IN(off)
RUV2 + RHYS
«
There is also a low IQ shutdown mode when EN is pulled below 0.6 V (typ). If EN is below this shutdown
threshold, the internal LDO regulator powers off, shutting down the bias currents of the TPSM265R1. The
TPSM265R1 operates in standby mode when the EN voltage is between the shutdown and precision enable
thresholds.
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7.3.5 PFM Operation
The TPSM265R1 operates in Pulse Frequency Modulation (PFM) mode. The TPSM265R1 behaves as a
hysteretic voltage regulator operating within upper and lower feedback regulation thresholds with typical 10 mV
of hysteresis. 图 7-4 is a representation of the relevant voltage waveforms and inductor current waveform. The
TPSM265R1 provides the required switching pulses to recharge the output capacitance, followed by a sleep
period where most of the internal circuits are shut off. The load current is supported by the output capacitor
during this time, and the TPSM265R1 current consumption approaches the sleep quiescent current of 10.5 μA
(typ). The sleep period duration depends on load current and output capacitance.
VIN
SW
Voltage
(internal)
VOUT
VREF = 1.233V
10mV
FB
Voltage
(internal)
ILIM
Inductor
Current
IOUT2
t
IOUT1
ACTIVE
SLEEP
ACTIVE SLEEP
ACTIVE SLEEP ACTIVE
图 7-4. PFM Mode SW Node Voltage, Feedback Voltage, and Inductor Current Waveforms
7.3.6 Power Good (PGOOD)
The TPSM265R1 provides a PGOOD signal to indicate when the output voltage is within regulation. Use the
PGOOD signal for output monitoring, fault protection, or start-up sequencing of downstream converters. PGOOD
is an open-drain output that requires a pullup resistor to a DC supply not greater than 12 V. Typical range of
pullup resistance is 10 kΩ to 100 kΩ. If necessary, use a resistor divider to decrease the voltage from a higher
voltage pullup rail.
When the output voltage exceeds 94% of the setpoint, the internal PGOOD switch turns off and PGOOD can be
pulled high by the external pullup. If the FB voltage falls below 87% of the setpoint, the internal PGOOD switch
turns on, and PGOOD is pulled low to indicate that the output voltage is out of regulation. The rising edge of
PGOOD has a built-in deglitch delay of 5 µs.
7.3.7 Configurable Soft Start (SS)
The TPSM265R1 has a flexible and easy-to-use soft-start control pin, SS. The soft-start feature prevents inrush
current when power is first applied. Soft start is achieved by slowly ramping up the target regulation voltage
when the device is powered up or enabled. Selectable and adjustable start-up timing options include minimum
delay (no soft start), 900-µs internally fixed soft start, and an externally programmable soft start.
Leaving the SS pin open enables the internal soft-start control ramp with a soft-start interval of 900 µs. The soft-
start time can be increased by connecting an external capacitor, CSS, from SS to GND. Applications with a large
amount of output capacitance or higher output voltage can benefit from increasing the soft-start time. Longer
soft-start time reduces the supply current needed to charge the output capacitors and supply any output loading.
An internal current source, ISS, of 10 µA charges CSS and generates a ramp to control the ramp rate of the
output voltage. Use 方程式 4 to calculate the CSS capacitance for a desired soft-start time, tSS
.
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CSS nF = 8.1∂t
ms
»
»
ÿ
ÿ
⁄
SS
⁄
(4)
CSS is discharged by an internal FET when VOUT is shut down by EN, UVLO, or thermal shutdown.
It is desirable in some applications for the output voltage to reach its nominal setpoint in the shortest possible
time. Connecting a 100-kΩ resistor from SS to GND disables the soft-start circuit, and the TPSM265R1
operates in current limit during start-up to rapidly charge the output capacitance.
7.3.7.1 Prebiased Start-up
To prevent discharge of a prebiased output voltage, the TPSM265R1 is capable of start-up into prebiased output
conditions. When a prebiased voltage is present at start-up, the TPSM265R1 waits until the soft-start ramp
voltage is above the prebiased voltage before it begins switching and then follows the soft-start ramp to the
regulation setpoint.
7.3.8 Overcurrent Protection (OCP)
The TPSM265R1 is protected from overcurrent conditions using cycle-by-cycle current limiting of the peak
inductor current. The current is compared every switching cycle to the current limit threshold. During an
overcurrent condition, the output voltage decreases.
7.3.9 Thermal Shutdown
Thermal shutdown is an integrated self-protection used to limit junction temperature and prevent damage related
to overheating. Thermal shutdown turns off the device when the junction temperature exceeds 170°C (typ) to
prevent further power dissipation and temperature rise. Junction temperature decreases after shutdown, and the
TPSM265R1 restarts when the junction temperature falls to 160°C (typ).
7.4 Device Functional Modes
7.4.1 Shutdown Mode
The EN pin provides ON and OFF control for the TPSM265R1. When VEN is below approximately 0.6 V, the
device is in shutdown mode. Both the internal LDO and the switching regulator are off. The quiescent current in
shutdown mode drops to 4.6 µA at VIN = 12 V. The TPSM265R1 also employs internal bias rail undervoltage
protection. If the internal bias supply voltage is below its UV threshold, the regulator remains off.
7.4.2 Standby Mode
The internal bias rail LDO has a lower enable threshold than the regulator itself. When VEN is above 0.6 V and
below the precision enable threshold (1.212 V typically), the internal LDO is on and regulating. The precision
enable circuitry is turned on once the internal VCC is above its UV threshold. The switching action and voltage
regulation are not enabled until VEN rises above the precision enable threshold.
7.4.3 Active Mode
The TPSM265R1 is in active mode when VEN and the internal bias rail are above their relevant thresholds, FB
has fallen below the lower hysteresis level, and boundary conduction mode is recharging the output capacitor to
the upper hysteresis level. There is a 4-µs wake-up delay from sleep to active states.
7.4.4 Sleep Mode
The TPSM265R1 is in sleep mode when VEN and the internal bias rail are above the relevant threshold levels,
VFB has exceeded the upper hysteresis level, and the output capacitor is sourcing the load current. In sleep
mode, the TPSM265R1 operates with very low quiescent current.
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8 Applications and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The TPSM265R1 only requires a few external components to convert from a wide range of supply voltages to a
fixed output voltage. To expedite and streamline the process of designing of a TPSM265R1, WEBENCH® online
software is available to generate complete designs, leveraging iterative design procedures and access to
comprehensive component databases. The following section describes the design procedure to configure the
TPSM265R1 power module.
As mentioned previously, the TPSM265R1 also integrates several optional features to meet system design
requirements, including precision enable, UVLO, programmable soft start, and PGOOD indicator. The application
circuit detailed below shows TPSM265R1 configuration options suitable for several application use cases. Refer
to the TPSM265R1EVM User's Guide for more detail.
8.2 Typical Applications
图 8-1 shows the schematic diagram of a 5-V, 100-mA converter.
PGOOD
VIN
VIN
RUV1
100kQ
VOUT
CIN
1µF
50V
VOUT
COUT
10µF
TPSM265R1
RFBT
100kQ
EN
16V
RUV2
21.0kQ
HYS
SS
FB
RFBB
32.4kQ
GND
图 8-1. TPSM265R1 Typical Schematic
8.2.1 Design Requirements
For this design example, use the parameters listed in 表 8-1 as the input parameters and follow the design
procedures in the 节 8.2.2.
表 8-1. Design Example Parameters
DESIGN PARAMETER
VALUE
24 V typical
5 V
Input voltage VIN
Output voltage VOUT
Output current rating
100 mA (50 Ω)
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8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPSM265R1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance.
• Run thermal simulations to understand board thermal performance.
• Export customized schematic and layout into popular CAD formats.
• Print PDF reports for the design, and share the design with colleagues.
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Output Voltage Setpoint
The output voltage of the TPSM265R1 device is externally adjustable using a resistor divider. The recommended
value of RFBT is 100 kΩ. The value for RFBB can be selected from 表 7-1 or calculated using 方程式 5:
1.223
RFBB
=
× RFBT
1.223
VOUT
(5)
For the desired output voltage of 5 V, the formula yields a value of 32.38 kΩ. Choose the closest available
standard value of 32.4 kΩ for RFBB
.
8.2.2.3 Input Capacitors
The TPSM265R1 requires a minimum input capacitance of 1-µF ceramic type. High-quality ceramic type X5R or
X7R capacitors with sufficient voltage rating are recommended. The voltage rating of input capacitors must be
greater than the maximum input voltage.
For this design, a single, 1-µF, 50-V ceramic capacitor is selected.
8.2.2.4 Output Capacitor Selection
The TPSM265R1 requires a minimum of 10 µF of ceramic output capacitance for proper operation. Additional
output capacitance can be added to reduce ripple voltage or for applications with transient load requirements.
For this design example, a single 10-µF, 16-V, ceramic capacitor is used.
8.2.2.5 UVLO Programming
Applications requiring a higher UVLO threshold can benefit from applying a resistor divider on the EN pin. The
values for the resistors can be calculated using 方程式 6 and 方程式 7.
≈
’
÷
◊
RUV1
RUV2
V
= 1.212V ∂ 1+
∆
IN(on)
«
(6)
(7)
≈
’
÷
◊
RUV1
V
= 1.144V ∂ 1+
∆
IN(off)
RUV2 + RHYS
«
For this application, the UVLO was raised to 7 V (RUV1 = 100 kΩ, RUV2 = 21.0 kΩ, and RHYS = 0 (not used)).
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8.2.2.6 Soft-Start Capacitor – CSS
In this application, the SS pin was left open, resulting in a 900 µs soft-start rise time. Applications requiring a
longer soft-start time can calculate the soft-start capacitor value using 方程式 8:
CSS nF = 8.1∂t
ms
»
»
ÿ
ÿ
⁄
SS
⁄
(8)
8.2.3 Application Curves
VIN = 24 V
VOUT = 5 V
RUV2 = 21.0 kΩ
RLOAD = 50 Ω
VIN = 24 V
VOUT = 5 V
COUT = 10 µF
RUV1 = 100
RLOAD = 50 Ω
kΩ
图 8-3. Output Voltage Ripple
图 8-2. Start-up Waveforms
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9 Power Supply Recommendations
The TPSM265R1 is designed to operate from an input voltage supply range between 3 V and 65 V. This input
supply must be able to provide the maximum input current and maintain a voltage above the set UVLO voltage.
Ensure that the resistance of the input supply rail is low enough that an input current transient does not cause a
high enough drop at the TPSM265R1 supply rail to cause a false UVLO fault triggering and system reset. If the
input supply is located more than a few inches from the TPSM265R1, additional bulk capacitance can be
required in addition to the ceramic input capacitance. A 4.7-μF electrolytic capacitor is a typical choice for this
function, whereby the capacitor ESR provides a level of damping against input filter resonances. A typical ESR
of 0.5 Ω provides enough damping for most input circuit configurations.
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10 Layout
The performance of any switching power supply depends as much upon the layout of the PCB as the component
selection. Use the following guidelines to design a PCB with the best power conversion performance, optimal
thermal performance, and minimal generation of unwanted EMI.
10.1 Layout Guidelines
To achieve optimal electrical and thermal performance, an optimized PCB layout is required. 图 10-1 and 图 10-2
show a typical PCB layout. Some considerations for an optimized layout are:
• Use large copper areas for power planes (VIN, VOUT, and GND) to minimize conduction loss and thermal
stress.
• Connect all GND pins together using copper plane or thick copper traces.
• Place ceramic input and output capacitors close to the device pins to minimize high frequency noise.
• Locate additional output capacitors between the ceramic capacitor and the load.
• Place RFBT and RFBB as close as possible to their respective pins.
• Use multiple vias to connect the power planes to internal layers.
10.2 Layout Example
图 10-1. Typical Top-Layer Layout
图 10-2. Typical Bottom-Layer Layout
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10.2.1 Theta JA versus PCB Area
The amount of PCB copper affects the thermal performance of the device. 图 10-3 shows the effects of copper
area on the junction-to-ambient thermal resistance (RθJA) of the TPSM265R1. The junction-to-ambient thermal
resistance is plotted for a 4-layer PCB with an area from 0.5 cm2 to 39 cm2.
To determine the required copper area for an application:
1. Determine the maximum power dissipation of the device in the application by referencing the power
dissipation graphs in 节 6.6 to 节 6.10.
2. Calculate the maximum θJA using 方程式 9 and the maximum ambient temperature of the application.
(125˘C œ TA(max)
)
ꢀJA
=
(˘C/W)
PD(max)
(9)
3. Reference 图 10-3 to determine the minimum required PCB area for the application conditions.
64
60
56
52
48
44
40
0
5
10
15
20
25
30
35
40
PCB Area (cm2)
D030
图 10-3. θJA versus PCB Area
10.2.2 Package Specifications
表 10-1. Package Specifications Table
TPSM265R1
VALUE
UNIT
Weight
37.7
mg
Flammability
Meets UL 94 V-O
MTBF Calculated Reliability
Per Bellcore TR-332, 50% stress, TA = 40°C, ground benign
139
MHrs
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10.2.3 EMI
The TPSM265R1 is compliant with EN55011 radiated emissions. 图 10-4, 图 10-5, and 图 10-6 show typical
examples of radiated emission plots for the TPSM265R1. The graphs include the plots of the antenna in the
horizontal and vertical positions.
EMI plots were measured using the standard TPSM265R1EVM with no input filter.
图 10-4. Radiated Emissions 12-V Input, 5-V Output, 100-mA Load
图 10-5. Radiated Emissions 24-V Input, 5-V Output, 100-mA Load
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图 10-6. Radiated Emissions 24-V Input, 12-V Output, 100-mA Load
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 Development Support
For development support, see the following:
• For TI's reference design library, visit TI reference designs.
• For TI's WEBENCH Design Environment, visit the WEBENCH® Design Center.
• To view a related device of this product, see the LM5166.
11.1.3 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPSM265R1 device with WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance.
• Run thermal simulations to understand board thermal performance.
• Export customized schematic and layout into popular CAD formats.
• Print PDF reports for the design, and share the design with colleagues.
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, TPSM265R1EVM User's Guide
• Texas Instruments, Using the TPSM265R1 in an Inverting Buck-Boost Topology Application Report
• Texas Instruments, Using New Thermal Metrics Application Report
• Texas Instruments, Semiconductor and IC Package Thermal Metrics Application Report
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
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11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
WEBENCH® are registered trademarks of Texas Instruments.
is a registered trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this datasheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
SIL0010C
uSIPTM - 1.9 mm max height
S
C
A
L
E
4
.
0
0
0
MICRO SYSTEM IN PACKAGE
2.9
2.7
A
B
PIN 1 INDEX
AREA
PICK AREA
NOTE 3
3.8
3.6
(3.5)
(1.8)
POSSIBLE LASER
MARKING AREA
2X
2X (0.075)
2X (0.2)
1.9
1.7
C
SEATING PLANE
0.08 C
2.2
SYMM
(0.1) TYP
(0.05) TYP
6
5
SYMM
2X
11
3.62
3.58
3.2
8X 0.8
10
1
0.32
0.28
PIN 1 ID
(OPTIONAL)
10X
0.42
0.38
0.1
C A B
0.52
0.48
10X
0.05
C
4223804/B 06/2019
MicroSiP is a trademark of Texas Instruments
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Pick and place nozzle 1.3 mm or smaller recommended.
4. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
SIL0010C
uSIPTM - 1.9 mm max height
MICRO SYSTEM IN PACKAGE
SYMM
(1.65) TYP
(0.45) TYP
COPPER
KEEP-OUT AREA
TYP
2X (0.3)
11
(
0.2) VIA TYP
10
1
(R0.05) TYP
(0.05) TYP
2X (4.2)
(4.1)
SYMM
2X (3.2)
7X (0.3)
8X (0.8)
2X (1)
10X (0.3)
5
6
10X (0.75)
(0.4)
10X (1.225)
LAND PATTERN EXAMPLE
SOLDER MASK DEFINED
EXPOSED METAL SHOWN
SCALE:20X
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
EXPOSED METAL
(R0.05) TYP
METAL UNDER
SOLDER MASK
SOLDER MASK DETAILS
NOT TO SCALE
4223804/B 06/2019
NOTES: (continued)
5. This package is designed to be soldered to thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
6. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
SIL0010C
uSIPTM - 1.9 mm max height
MICRO SYSTEM IN PACKAGE
SYMM
SOLDER MASK EDGE
TYP
10X (0.75)
10
1
11
10X (0.3)
2X
(1.5)
8X (0.8)
2X
(0.5)
SYMM
EXPOSED METAL
TYP
(R0.05) TYP
4X
(0.8)
5
6
4X (0.4)
(1.225)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
78% SOLDER COVERAGE BY PRINTED
AREA ON CENTER THERMAL PAD
SCALE:20X
4223804/B 06/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPSM265R1SILR
TPSM265R1V3SILR
TPSM265R1V5SILR
ACTIVE
ACTIVE
ACTIVE
uSiP
uSiP
uSiP
SIL
SIL
SIL
10
10
10
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
ENEPIG
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-40 to 125
TPSM265R1
Samples
Samples
Samples
ENEPIG
ENEPIG
TPSM265R1V3
TPSM265R1V5
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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18-Jan-2023
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Sep-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPSM265R1SILR
TPSM265R1V3SILR
TPSM265R1V5SILR
uSiP
uSiP
uSiP
SIL
SIL
SIL
10
10
10
3000
3000
3000
330.0
330.0
330.0
12.4
12.4
12.4
3.15
3.15
3.15
4.05
4.05
4.05
2.15
2.15
2.15
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Sep-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPSM265R1SILR
TPSM265R1V3SILR
TPSM265R1V5SILR
uSiP
uSiP
uSiP
SIL
SIL
SIL
10
10
10
3000
3000
3000
383.0
383.0
383.0
353.0
353.0
353.0
58.0
58.0
58.0
Pack Materials-Page 2
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