TPSM365R6FRDNR_技术文档

TPSM365R3, TPSM365R6

ZHCSPW5B –SEPTEMBER 2022 –REVISED FEBRUARY 2023

TPSM365R6、TPSM365R3 采用HotRod™ QFN 封装的3V 至65V 输入、600mA/

300mA、4μA 空载I_Q同步降压转换器电源模块

1 特性

2 应用

• 功能安全型

• 工厂自动化和控制

• 楼宇自动化

• 测试设备

– 有助于进行功能安全系统设计的文档

• 多功能同步降压直流/直流模块：

• 电器

– 集成MOSFET、电感器和控制器

– 宽输入电压范围：3V 至65V

– 高达70V 的输入瞬态

3 说明

TPSM365R6 或 TPSM365R3 是一款 600mA 或

300mA、65V 输入同步降压直流/直流电源模块，它在

紧凑且易于使用的 3.5mm × 4.5mm × 2mm 11 引脚

QFN 封装中整合了功率 MOSFET、集成电感器和启动

电容器。小型 HotRod^™QFN 封装技术可提高热性能

并降低EMI。该器件在空载时具有4μA 的超低运行I_Q

（24V 至 3.3V V_OUT）。TPSM365Rx 提供两个支持

3.3V 和5V 的固定输出电压选项，以及一个支持 1V 至

13V 范围的可调节输出电压选项。该模块仅需四个外

部元件即可实现 3.3V 和 5V 固定输出解决方案。

TPSM365Rx 针对出色的 EMI 性能和空间受限型应用

进行了优化。

– 结温范围为–40°C 至+125°C

– 4.5mm × 3.5mm × 2mm 超模压塑料封装

– 使用RT 引脚或外部SYNC 信号可在200kHz 至

2.2MHz 范围内调节频率

• 在整个负载范围内具有超高效率：

– 在12V_IN、3.3V_OUT下效率高于85%

– 在24V_IN、5V_OUT下效率高于85%

– 空载时工作静态电流很低：V_IN= 24V 至3.3V

V

_OUT下为4µA

• 针对超低EMI 要求进行了优化：

– 假随机展频可降低峰值发射

– 在轻负载下通过MODE/SYNC 引脚使用引脚可

选FPWM 模式可提供恒定频率

– FSW 与MODE/SYNC 引脚同步

– 符合CISPR11 B 类要求

封装信息

封装⁽¹⁾

器件型号

封装尺寸（标称值）

TPSM365R6

TPSM365R3

3.50mm × 4.50mm ×

2.00mm

RDN (QFN-HR,11)

• 输出电压和电流选项：

– 3.3V 或5V V_OUT的固定输出型号

– 可调输出电压范围为1V 至13V

– 与TPSM33625 引脚兼容

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

– 输出电流为600mA (TPSM365R6)

– 输出电流为300mA (TPSM365R3)

• 固有保护特性，可实现稳健设计

– 精密使能输入和漏极开路PGOOD 指示器（用

于时序、控制和V_INUVLO）

– 过流和热关断保护

• 使用TPSM365Rx 并借助WEBENCH® Power

Designer 创建定制设计方案

100

V_IN= 12V

V_IN= 24V

V_IN= 36V

V_IN= 48V

V_IN

C_IN

VIN

SW

90

80

BOOT

EN

V_IN= 54V

70

60

50

40

30

20

10

0

TPSM365Rx

VOUT

V_OUT

C_OUT

R_FBT

FB

VCC

RT

C_VCC

R_FBB

PGOOD

GND

1E-5

0.0001

0.001

0.01

0.1 0.2 0.5 1

Load Current (A)

效率与输出电流间的关系V_OUT= 5V，F_SW= 1MHz

典型电路原理图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNVSC83

TPSM365R3, TPSM365R6

ZHCSPW5B –SEPTEMBER 2022 –REVISED FEBRUARY 2023

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Table of Contents

9.1 Overview...................................................................16

9.2 Functional Block Diagram.........................................17

9.3 Feature Description...................................................17

9.4 Device Functional Modes..........................................28

10 Application and Implementation................................33

10.1 Application Information........................................... 33

10.2 Typical Application.................................................. 33

10.3 Power Supply Recommendations...........................42

10.4 Layout..................................................................... 42

11 Device and Documentation Support..........................45

11.1 Device Support........................................................45

11.2 Documentation Support.......................................... 45

11.3 Receiving Notification of Documentation Updates..46

11.4 支持资源..................................................................46

11.5 Trademarks............................................................. 46

11.6 静电放电警告...........................................................46

11.7 术语表..................................................................... 46

12 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Description (continued).................................................. 2

6 Device Comparison Table...............................................3

7 Pin Configuration and Functions...................................4

8 Specifications.................................................................. 5

8.1 Absolute Maximum Ratings........................................ 5

8.2 ESD Ratings............................................................... 5

8.3 Recommended Operating Conditions.........................6

8.4 Thermal Information....................................................6

8.5 Electrical Characteristics.............................................7

8.6 System Characteristics............................................. 10

8.7 Typical Characteristics..............................................12

8.8 Typical Characteristics: V_IN= 12 V........................... 13

8.9 Typical Characteristics: V_IN= 24 V........................... 14

8.10 Typical Characteristics: V_IN= 48 V......................... 15

9 Detailed Description......................................................16

Information.................................................................... 47

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision A (November 2022) to Revision B (February 2023)

Page

• 向数据表添加了TPSM365R3.............................................................................................................................1

Changes from Revision * (September 2022) to Revision A (November 2022)

Page

• 将状态从“预告信息”更改为“量产数据”....................................................................................................... 1

5 Description (continued)

The TPSM365Rx uses a peak current mode control scheme with internal compensation to maintain stable

operation with minimal output capacitance. The precision EN feature allows precise control of the device during

start-up and shutdown. An open-drain PGOOD output provides a true indication of the output voltage status. The

TPSM365Rx includes prebias start up, overcurrent, and temperature protections, making the TPSM365Rx an

excellent device for powering a wide range of industrial applications. In the fixed option variants, the MODE/

SYNC pin enables seamless transition from FPWM to PFM with a no-load standby quiescent current of less than

4 μA, ensuring high efficiency and superior transient response for the entire load-current range.

2

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6 Device Comparison Table

ORDERABLE PART

OUTPUT

VOLTAGE

DEVICE

F_SW

EXTERNAL SYNC

SPREAD SPECTRUM

NUMBER ⁽¹⁾

Adjustable

with RT resistor

Adjustable

(1 V to 13 V)

No

TPSM365R6

TPSM365R6FRDNR

TPSM365R6V3RDNR

Yes

(FPWM only)

Yes

(PFM/PWM

Selectable)

Fixed

1 MHz

TPSM365R6V3

3.3-V Fixed

5-V Fixed

Yes

(PFM/PWM

Selectable)

Fixed

1 MHz

TPSM365R6V5

TPSM365R6V5RDNR

No

Adjustable

with RT resistor

Adjustable

(1 V to 13 V)

TPSM365R6

TPSM365R3

TPSM365R6RDNR

TPSM365R3FRDNR

TPSM365R3RDNR

(Default PFM

at light load)

Yes

Adjustable

with RT resistor

Adjustable

(1 V to 13 V)

No

(FPWM only)

No

Adjustable

with RT resistor

Adjustable

(1 V to 13 V)

(Default PFM

at light load)

(1) For more information on device orderable part numbers, see Device Nomenclature.

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7 Pin Configuration and Functions

MODE/SYNC^(A)FB

RT^(B)GND BIAS

PGOOD

VCC

1

8

11

10

9

BOOT

SW

EN

2

3

7

6

VIN

SW

VOUT

4

5

A. Pin 11 factory-set for fixed switching frequency MODE/SYNC variants only.

B. See Device Comparison Table for more details. Pin 11 trimmed and factory-set for externally adjustable switching frequency RT variants

only.

图7-1. RDN Package, 11-Pin QFN-HR, Top View (All Variants)

表7-1. Pin Functions

I/O

DESCRIPTION

NO.

NAME

Power-good monitor. Open-drain output that asserts low if the feedback voltage is not within the specified window thresholds. A

10-kΩto 100-kΩpullup resistor is required to a suitable pullup voltage. If not used, this pin can be left open or connected to

GND.

1

PGOOD

A

High = power OK, Low = power bad. PGOOD pin goes low when EN = Low.

Precision enable input pin. High = ON, Low = OFF. Can be connected to VIN. Precision enable allows the pin to be used as an

adjustable UVLO. Can be connected directly to VIN. The module can be turned off by using an open-drain or collector device to

connect this pin to GND. An external voltage divider can be placed between this pin, GND, and VIN to create an external

UVLO.Do not float this pin.

2

EN

A

Input supply voltage. Connect the input supply to these pins. Connect a high-quality bypass capacitor or capacitors directly to

this pin and GND in close proximity to the module. Refer to 节10.4.2 for input capacitor placement example.

3

4

VIN

P

Output voltage. The pin is connected to the internal output inductor. Connect the pin to the output load and connect external

output capacitors between the pin and GND.

VOUT

Fixed output options are available. For fixed output variants, connect the FB pin to VOUT. Check 节6 for more details.

Power module switch node. Do not place any external component on this pin or connect to any signal. The amount of copper

placed on these pins must be kept to a minimum to prevent issues with noise and EMI.

5, 6

7

SW

BOOT

VCC

P

Bootstrap pin for internal high-side driver circuitry. A 100-nF bootstrap capacitor is internally connected from this pin to SW within

the module to provide the bootstrap voltage.

Internal LDO output. Used as supply to internal control circuits. Do not connect to external loads. Can be used as logic supply for

power-good flag. Connect a high-quality 1-µF capacitor from this pin to GND.

8

Feedback input. For the adjustable output version, connect the mid-point of the feedback resistor divider to this pin. Connect the

upper resistor (R_FBT) of the feedback divider to VOUT at the desired point of regulation. Connect the lower resistor (R_FBB) of the

feedback divider to GND. When connecting with feedback resistor divider, keep this FB trace short and as small as possible to

avoid noise coupling. See 节10.4.2 for a feedback resistor placement.

FB

or

BIAS

9

A

G

A

For a fixed output version, connect BIAS directly to VOUT pin. Do not leave open or connect to ground.

10

11

GND

Power ground terminal. Connect to system ground. Connect to C_INwith short, wide traces.

When the part is trimmed as the RT pin variant, the switching frequency in the part can be adjusted from 200 kHz to 2.2 MHz

based on the resistor value connected between RT and GND.

When the pin is trimmed as the MODE/SYNC variant, the part can operate in user-selectable PFM/FPWM operation. In FPWM,

the part can be synchronized to an external clock. Clock triggers on rising edge of applied external clock.

Do not float this pin..

RT

or

MODE/SYNC

A = Analog, P = Power, G = Ground

4

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8 Specifications

8.1 Absolute Maximum Ratings

Over the recommended operating junction temperature range (unless otherwise noted) ⁽¹⁾

PARAMETER

MIN

–0.3

0

MAX

70

UNIT

V

Voltage

VIN to GND

EN to GND

70

V

SW to GND

70.3

5.5

13

V

MODE/SYNC to GND (MODE/SYNC variant)

RT to GND (RT variant)

BIAS to GND (Fixed V_OUTvariant)

FB to GND (Adjustable V_OUTvariant)

PGOOD to GND

V

13

V

20

V

BOOT to SW

5.5

125

150

V

–0.3

–40

–55

VCC to GND

V

(2)

T_J

Junction temperature

Storage temperature

°C

T_stg

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) The ambient temperature is the air temperature of the surrounding environment. The junction temperature is the temperature of the

internal power IC when the device is powered. Operating below the maximum ambient temperature, as shown in the safe operating

area (SOA) curves in the Typical Applications sections, ensures that the maximum junction temperature of any component inside the

module is never exceeded.

8.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/

JEDEC JS-001⁽¹⁾

±2000

V

V_(ESD)

Electrostatic discharge

Charged-device model (CDM), per ANSI/ESDA/

JEDEC JS-002⁽²⁾

±1000

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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8.3 Recommended Operating Conditions

Over the recommended operating junction temperature range of –40°C to 125°C (unless otherwise noted) ^{(1) (2)}

MIN

3.6

1

TYP

MAX

UNIT

Input voltage Input voltage, V_IN(Input voltage range after startup)

Output voltage Output Adjustment Range for adjustable output versions, V_OUT

Output current (TPSM365R3X) Load current range ⁽³⁾

65

13

V

A

0

0.3

0.6

Output current (TPSM365R6X) Load current range ⁽³⁾

0

Frequency

Selectable Frequency Range with RT (RT variant)

setting

0.2

2.2

MHz

Frequency

External Sync CLK (with MODE/SYNC variant)

setting

0.2

2.2

MHz

°C

Temperature

T_Jjunction temperature

125

–40

(1) Recommended operating conditions indicate conditions for which the device is intended to be functional, but do not ensure specific

performance limits. For ensured specifications, see Electrical Characteristics table.

(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125℃

(3) Maximum continuous DC current may be derated when operating with high switching frequency or high ambient temperature. See

Application section for details.

8.4 Thermal Information

TPSM365R6 / TPSM365R3

THERMAL METRIC ⁽¹⁾

RDN

11 Pins

56.3

UNIT

R_θJA

R_θJC(top)

R_θJB

Ψ_JT

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

53.9

17.3

Junction-to-top characterization parameter

Junction-to-board characterization parameter

10.7

17.2

Ψ_JB

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report. The value of R_ΘJAgiven in this table is only valid for comparison with other packages and can not be used for design

purposes. This value was calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board. It does not represent

the performance obtained in an actual application.

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8.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature (T_J) range of –40°C to +125°C, unless otherwise stated.

Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most

likely parametric norm at T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated, the following

(1)

conditions apply: V_IN= 24 V_.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

SUPPLY VOLTAGE (VIN PIN)

Minimum operating Input Voltage

(Rising)

V_{IN_R}

Rising Threshold

3.4

3.0

3.6

V

Minimum operating Input Voltage

(Falling)

V_{IN_F}

Once Operating; Falling Threshold

2.45

V

Non-switching input current;

measured at V_INpin ⁽²⁾

V_IN= V_EN= 13.5 V; V_BIAS= 5.25 V, V_MODE/SYNC

= 0 V; Fixed Output Option

I_{Q_13p5_Fixed}

I_{Q_13p5_Adj}

I_{Q_24p0_Fixed}

I_{Q_24p0_Adj}

I_{B_13p5}

0.25 0.672

1.05

24

µA

Non-switching input current;

measured at V_INpin ⁽²⁾

V_IN= V_EN= 13.5 V; V_FB= 1.5 V, V_RT= 0 V;

Adjustable Output Option

11

0.8

11

17

1.2

18

17

18

0.5

1

Non-switching input current;

measured at V_INpin ⁽²⁾

V_IN= V_EN= 24 V; V_BIAS= 5.25 V, V_MODE/SYNC

0 V; Fixed Output Option

=

1.7

24

Non-switching input current;

measured at V_INpin ⁽²⁾

V_IN= V_EN= 24 V; V_FB= 1.5 V, V_RT= 0 V;

Adjustable Output Option

Current into BIAS pin (not switching) V_IN= V_EN= 13.5 V, V_BIAS= 5.25 V, V_MODE/SYNC

14

22

(2)

= 0 V; Fixed Output Option

Current into BIAS pin (not switching) V_IN= V_EN= 24 V, V_BIAS= 5.25 V, V_MODE/SYNC

=

I_{B_24p0}

22

(2)

0 V; Fixed Output Option

Shutdown quiescent current;

V_EN= 0 V; V_IN= 13.5 V

measured at V_INpin ⁽²⁾

I_{SD_13p5}

I_{SD_24p0}

1.3

1.8

Shutdown quiescent current;

V_EN= 0 V; V_IN= 24 V

measured at V_INpin ⁽²⁾

ENABLE (EN PIN)

V_EN-WAKEEnable wake-up threshold

V_EN-VOUT

0.4

V

Precision enable high level for V_OUT

1.16 1.263

1.36

0.4

10

Enable threshold hysteresis below

V_EN-VOUT

V_EN-HYST

0.3

0.35

0.3

V

I_LKG-EN

Enable input leakage current

V_EN= 3.3 V

nA

INTERNAL LDO

V_CC

Internal VCC voltage

Adjustable or Fixed Output Option; Auto mode

3.125

3.15

65

3.22

V

I_CC

Bias regulator current limit

Internal VCC undervoltage lockout

240 mA

V_CC-UVLO

VCC rising under voltage threshold

Hysteresis below V_CC-UVLO

3

3.3

3.65

1.2

V

Internal VCC under voltage lock-out

hysteresis

V_CC-UVLO-HYST

0.4

0.8

CURRENT LIMITS

I_SC-0p3

Short circuit high side current limit ⁽²⁾0.3 A version (TPSM365R3)

0.42

0.27

0.5 0.575

A

I_LS-LIMIT-0p3

Low side current limit ⁽²⁾

0.3 A version (TPSM365R3)

0.35

0.42

Auto operation, 0.3 A version; Duty Cycle =

0%; (TPSM365R3)

I_PEAK-MIN-0p3

Minimum Peak Inductor Current ⁽²⁾

0.065

0.09 0.113

A

I_SC-0p6

Short circuit high side current limit ⁽²⁾0.6 A version (TPSM365R6)

0.87

0.6

1

1.11

0.8

A

I_LS-LIMIT-0p6

Low side current limit ⁽²⁾

0.6 A version (TPSM365R6)

0.7

Auto operation, 0.6 A version; Duty Cycle =

0%; (TPSM365R6)

I_PEAK-MIN-0p6

I_ZC

Minimum Peak Inductor Current ⁽²⁾

0.127

0.19 0.227

0.01 0.025

–0.7 –0.6

A

Auto mode operation; (TPSM365R3) and

(TPSM365R6)

Zero Cross Current ⁽²⁾

Negative current limit ⁽²⁾

FPWM operation; (TPSM365R3) and

(TPSM365R6)

I_L-NEG

–0.8

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8.5 Electrical Characteristics (continued)

Limits apply over the recommended operating junction temperature (T_J) range of –40°C to +125°C, unless otherwise stated.

Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most

likely parametric norm at T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated, the following

(1)

conditions apply: V_IN= 24 V_.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

POWER GOOD

V_PG-OV

PGOOD upper threshold - Rising

PGOOD lower threshold - Falling

PGOOD hysteresis

% of BIAS or FB (adjustable or fixed output)

106

93

107

94

110

96.5

2.3

%

V_PG-UV

V_PG-HYS

1.3

1.8

Minimum input voltage for proper

PGOOD function

V_PG-VALID

0.72

1

2

V

R_PG-EN5p0

R_DS(ON)PGOOD output

V_EN= 5 V, 1 mA pull-up current

V_EN= 0 V, 1 mA pull-up current

20

10

15

40

18

25

70

31

Ω

R_PG-EN0

R_DS(ON)PGOOD output

t_{RESET_FILTER}

t_{PGOOD_ACT}

SOFT START

PGOOD deglitch delay at falling edge

Delay time to PGOOD high signal

40

µs

ms

1.7 1.956

2.16

Time from first SW pulse to V_OUT/FB

at 90% of set point

t_SS

1.95

2.58

3.2

ms

OSCILLATOR (MODE/SYNC)

SYNC input and mode high level

threshold

V_SYNC-H

1.8

V

SYNC input and mode low level

threshold

V_SYNC-L

0.8

V_SYNC-HYS

t_{PULSE_H}

t_{PULSE_L}

SYNC input hysteresis

230

100

300

380 mV

ns

High duration needed to be

recognized as a pulse

Low duration needed to be

recognized as a pulse

100

6

ns

High/Low signal duration to be

recognized as a valid synchronization

signal

t_SYNC

9

12

µs

Time at one level needed to indicate

FPWM or Auto Mode

t_MODE

18

OSCILLATOR (RT)

f_{OSC_2p2MHz}

f_{OSC_1p0MHz}

f_{ADJ_400kHz}

Internal oscillator frequency

RT = GND

2.1

0.93

0.34

2.2

1

2.3 MHz

1.05 MHz

0.46 MHz

RT = VCC

0.4

RT = 39.2 kΩ(with RT variant only)

SWITCH NODE (SW)

t_ON-MIN

Minimum switch on-time

V_IN= 24 V, I_OUT= 0.6 A

40

57

58

9

86

77

ns

µs

t_OFF-MIN

Minimum switch off-time

Maximum switch on-time

t_ON-MAX

High-side timeout in dropout

7.6

9.8

MOSFETS

R_DSON-HS

R_DSON-LS

V_BOOT-UVLO

High-side MOSFET on-resistance

Low-side MOSFET on-resistance

BOOT - SW UVLO threshold ⁽³⁾

Load = 0.3 A

560

280

2.3

920

480

mΩ

V

2.14

2.42

8

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8.5 Electrical Characteristics (continued)

Limits apply over the recommended operating junction temperature (T_J) range of –40°C to +125°C, unless otherwise stated.

Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most

likely parametric norm at T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated, the following

(1)

conditions apply: V_IN= 24 V_.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

VOLTAGE REFERENCE

V_{OUT_Fixed3p3}

V_{OUT_Fixed5p0}

V_FB

Initial V_OUTvoltage accuracy for 3.3-V 3.3-V V_OUT;V_IN= 3.6 V to 65 V; FPWM Mode

3.25

4.93

3.3

5

3.34

5.07

1.01

115

V

Initial V_OUTvoltage accuracy for 5-V

Internal reference voltage accuracy

FB input current

5-V V_OUT;V_IN= 5.5 V to 65 V; FPWM Mode

V_IN= 3.6 V to 65 V; FPWM Mode

Adjsutable output, FB = 1 V

0.985

1

V

I_FB

85

nA

(1) MIN and MAX limits are 100% production tested at 25ºC. Limits over the operating temperature range verified through correlation

using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).

(2) This is the current used by the device open loop. It does not represent the total input current of the system when in regulation.

(3) When the voltage across the C_BOOTcapacitor falls below this voltage, the low side MOSFET is turn to recharge the boot capacitor

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8.6 System Characteristics

The following specifications apply only to the typical applications circuit, with nominal component values. Specifications in the

typical (TYP) column apply to T_J= 25°C only. Specifications in the minimum (MIN) and maximum (MAX) columns apply to the

case of typical components over the temperature range of T_J= –40°C to 125°C. These specifications are not ensured by

production testing.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

SUPPLY VOLTAGE (VIN)

Input supply current when in

regulation

V_IN= 13.5 V, V_BIAS= 3.3-V V_OUT, I_OUT= 0 A, PFM

mode (fixed output voltage)

I_SUPPLY

6.5

µA

Input supply current when in

regulation

V_IN= 24 V, V_BIAS= 3.3-V V_OUT, I_OUT= 0 A, FPWM

mode (fixed output voltage)

I_SUPPLY

D_MAX

4

µA

%

Maximum switch duty cycle ⁽¹⁾

98

VOLTAGE REFERENCE (FB or BIAS)

V_OUT= 5 V, V_IN= 5.5 V to 65 V,

V_{OUT_5p0V_ACC}

V_{OUT_3p3V_ACC}

FPWM mode

Auto mode

1.5

2.5

1.5

2.5

%

–1.5

I_OUT= 0 A to full load ⁽²⁾

V_OUT= 5 V, V_IN= 5.5 V to 65 V,

I_OUT= 0 A to full load ⁽²⁾

V_OUT= 3.3 V, V_IN= 3.6 V to 65 V,

I_OUT= 0 A to full load ⁽²⁾

FPWM mode

Auto mode

V_OUT= 3.3 V, V_IN= 3.6 V to 65 V,

I_OUT= 0 A to full load ⁽²⁾

SPREAD SPECTRUM

Frequency span of spread

f_SSS

spectrum operation - largest

Spread spectrum active

±2

%

deviation from center frequency ⁽³⁾

Spread spectrum pseudo random

pattern frequency ⁽³⁾

f_PSS

0.98

1.5

Hz

EFFICIENCY

V_IN= 12 V, V_OUT= 3.3 V, I_OUT= 0.6 A, F_SW= 1

MHz

Efficiency

82.7

80.2

%

η

V_IN= 24 V, V_OUT= 3.3 V, I_OUT= 0.6 A, F_SW= 1

MHz

η

Efficiency

V_IN= 24 V, V_OUT= 5 V, I_OUT= 0.6 A, F_SW= 1 MHz

V_IN= 36 V, V_OUT= 5 V, I_OUT= 0.6 A, F_SW= 1 MHz

84.7

82.3

%

η

V_IN= 24 V, V_OUT= 12 V, I_OUT= 0.4 A, F_SW= 2.2

MHz

Efficiency

88.4

78.5

%

η

V_IN= 48 V, V_OUT= 12 V, I_OUT= 0.4 A, F_SW= 2.2

MHz

10

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8.6 System Characteristics (continued)

The following specifications apply only to the typical applications circuit, with nominal component values. Specifications in the

typical (TYP) column apply to T_J= 25°C only. Specifications in the minimum (MIN) and maximum (MAX) columns apply to the

case of typical components over the temperature range of T_J= –40°C to 125°C. These specifications are not ensured by

production testing.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

THERMAL SHUTDOWN

T_SD-R

Thermal shutdown rising

Thermal shutdown falling

Thermal shutdown hysteresis

Shutdown threshold

Recovery threshold

158

150

8

168

158

10

180

165

15

°C

T_SD-F

T_SD-HYS

(1) In dropout the switching frequency drops to increase the effective duty cycle. The lowest frequency is clamped at approximately: f_MIN

1 / (t_ON-MAX+ T_OFF-MIN). D_MAX= t_ON-MAX/(t_ON-MAX+ t_OFF-MIN).

=

(2) Deviation is with respect to V_IN= 13.5 V

(3) Specified by design. Not production tested.

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8.7 Typical Characteristics

Unless otherwise specified, the following conditions apply: T_A= 25°C, V_IN= 24 V

1.01

1.005

1

Shutdown Current

4

3.6

3.2

2.8

2.4

2

T_J= -40C

T_J= 125C

T_J= 25C

0.995

1.6

1.2

0.8

0.4

0

0.99

-50

-25

0

25

50

75

100

125

Junction Temperature (°C)

图8-2. Feedback Voltage

0

5

10 15 20 25 30 35 40 45 50 55 60 65 70

V_IN(V)

图8-1. Shutdown Supply Current

800

700

600

500

400

300

200

100

1.4

1.2

1

0.8

0.6

0.4

0.2

0

V_ENRising

V_ENFalling

V_{EN_WAKE}Rising

V_{EN_WAKE}Falling

High-side MOSFET

Low-side MOSFET

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Junction Temperature (°C)

图8-3. High-Side and Low-Side MOSFET R_DS(on)

图8-4. Enable Thresholds

115

110

105

100

95

90

OV Tripping

OV Recovery

UV Recovery

UV Tripping

85

80

-50

-25

0

25

50

75

100

125

Junction Temperature (°C)

图8-5. Power-Good (PG) Thresholds

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8.8 Typical Characteristics: V_IN= 12 V

Unless otherwise specified, the following condition apply: T_A= 25°C

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

V_OUT= 3.3V

V_OUT= 5V

V_OUT= 3.3V

V_OUT= 5.0V

1E-5

0.0001

0.001

0.01

0.1 0.2 0.5 1

1E-5

0.0001

0.001

0.01

0.1 0.2 0.5 1

Load Current (A)

图8-6. Efficiency in Auto Mode

图8-7. Efficiency in FPWM Mode

110

105

100

95

1.8V 400kHz

90

85

2.5V 400kHz

3.3V 800kHz

5.0V 1MHz

0

0.1

0.2

0.3

0.4

0.5

0.6

Output Current (A)

图8-8. Safe Operating Area (Standard EVM Layout and Board Size)

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8.9 Typical Characteristics: V_IN= 24 V

Unless otherwise specified, the following condition apply: T_A= 25°C

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

V_OUT= 3.3V

V_OUT= 5.0V

V_OUT= 12V

V_OUT= 3.3V

V_OUT= 5.0V

V_OUT= 12V

1E-5

0.0001

0.001

0.01

0.1 0.2 0.5 1

1E-5

0.0001

0.001

0.01

0.1 0.2 0.5 1

Load Current (A)

图8-9. Efficiency in Auto Mode

图8-10. Efficiency in FPWM Mode

110

105

100

95

90

85

1.8V 400kHz

80

75

70

2.5V 400kHz

3.3V 800kHz

5.0V 1MHz

12V 2.2MHz

0

0.1

0.2

0.3

0.4

0.5

0.6

Output Current (A)

图8-11. Safe Operating Area (Standard EVM Layout and Board Size)

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8.10 Typical Characteristics: V_IN= 48 V

Unless otherwise specified, the following condition apply: T_A= 25°C

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

V_OUT= 3.3V

V_OUT= 5.0V

V_OUT= 12V

V_OUT= 3.3V

V_OUT= 5.0V

V_OUT= 12V

1E-5

0.0001

0.001

0.01

0.1 0.2 0.5 1

1E-5

0.0001

0.001

0.01

0.1 0.2 0.5 1

Load Current (A)

图8-12. Efficiency in Auto Mode

图8-13. Efficiency in FPWM Mode

110

105

100

95

90

85

80

75

70

1.8V 400kHz

65

60

55

50

2.5V 400kHz

3.3V 800kHz

5.0V 1MHz

12V 2.2MHz

0

0.1

0.2

0.3

0.4

0.5

0.6

Output Current (A)

图8-14. Safe Operating Area (Standard EVM Layout and Board Size)

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9 Detailed Description

9.1 Overview

The TPSM365R6 or TPSM365R3 is an easy-to-use, synchronous buck, DC-DC power module that operates

from a 3-V to 65-V supply voltage. The device is intended for step-down conversions from 5-V, 12-V, 24-V, and

48-V supply rails. With an integrated power controller, inductor, and MOSFETs, the TPSM365R6 or TPSM365R3

delivers up to 600-mA or 300-mA DC load current with high efficiency and ultra-low input quiescent current in a

very small solution size. Although designed for simple implementation, this device offers flexibility to optimize its

usage according to the target application. Control-loop compensation is not required, reducing design time and

external component count.

The TPSM365Rx can operate over a wide range of switching frequencies and duty ratios. If the minimum ON-

time or OFF-time cannot support the desired duty ratio, the switching frequency gets reduced automatically,

maintaining the output voltage regulation. With the right internal loop compensation the system design time with

the TPSM365Rx reduces significantly with minimal external components. In addition, the PGOOD output feature

with built-in delayed release allows the elimination of the reset supervisor in many applications.

With a programmable switching frequency from 200 kHz to 2.2 MHz using its RT pin or an external clock signal,

the TPSM365Rx incorporates specific features to improve EMI performance in noise-sensitive applications:

• An optimized package that incorporates flip chip on lead (FCOL) technology and pinout design enables a

shielded switch-node layout that mitigates radiated EMI.

• Pseudo-Random Spread Spectrum (PRSS) modulation reduces peak emissions.

• Clock synchronization and FPWM mode enable constant switching frequency across the load current range.

Together, these features eliminate the need for any common-mode choke, shielding, and input filter inductor,

greatly reducing the complexities and cost of the EMI/EMC mitigation measures.

The TPSM365Rx module also includes inherent protection features for robust system requirements:

• An open-drain PGOOD indicator for power-rail sequencing and fault reporting

• Precision enable input with hysteresis, providing:

– Programmable line undervoltage lockout (UVLO)

– Remote ON and OFF capability

• Internally fixed output-voltage soft start with monotonic start-up into prebiased loads

• Hiccup-mode overcurrent protection with cycle-by-cycle peak and valley current limits

• Thermal shutdown with automatic recovery

These features enable a flexible and easy-to-use platform for a wide range of applications. The pin arrangement

is designed for a simple layout, requiring few external components. See 节10.4 for a layout example.

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9.2 Functional Block Diagram

VCC

MODE/SYNC VARIANTS

ONLY

FIXED OUTPUT

VOLTAGE

VARIANTS

MODE

/SYNC

CLOCK

BIAS

OSCILLATOR

ONLY

SLOPE

COMPENSATION

RT

LDO

VCC UVLO

TSD

RT VARIANTS ONLY

VIN

THERMAL

SHUTDOWN

F_SWFOLDBACK

SYS ENABLE

BOOT

ENABLE

EN

0.1 μF

HS CURRENT SENSE

VIN

ADJ. OUTPUT

VOLTAGE

VARIANTS ONLY

ERROR

AMPLIFIER

–

+

–

FB /

BIAS

COMP

MAX

TSD

+

CLOCK

SW

and

MIN

LIMITS

+

HS CURRENT

LIMIT

10 μH

FIXED OUTPUT

VOLTAGE

VARIANTS

ONLY

–

VOUT

SYS ENABLE

CONTROL

LOGIC and

DRIVER

SOFT-

START

and

TSD

GND

VREF

BANDGAP

VCC UVLO

LS CURRENT

LIMIT

–

+

FIXED OUTPUT

ADJ. OUTPUT

VOLTAGE

VARIANTS ONLY

VOLTAGE

VARIANTS

ONLY

–

+

MIN

LS CURRENT

LIMIT

FB

BIAS

GND

PGOOD

VOUT UV/OV

FPWM or AUTO

VOUT UV/OV

LS CURRENT SENSE

PGOOD

LOGIC

9.3 Feature Description

9.3.1 Input Voltage Range

With a steady-state input voltage range from 3 V to 65 V, the TPSM365Rx module is intended for step-down

conversions from typical 12-V to 48-V input supply rails. The schematic circuit in 图 9-1 shows all the necessary

components to implement a TPSM365Rx-based buck regulator using a single input supply.

VIN

EN

SW

V_IN= 3 V to 65 V

C_IN

BOOT

TPSM365Rx

V_OUT= 1 V to 13 V

I_OUT(max)= 600 mA/

VOUT

C_OUT

300 mA

R_FBT

FB

VCC

RT

C_VCC

VCC

R_PGOOD

R_FBB

PGOOD

GND

PGOOD

indicator

R_RT

图9-1. TPSM365Rx Schematic Diagram with Input Voltage Operating Range of 3 V to 65 V

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Take extra care to ensure that the voltage at the VIN pin does not exceed the absolute maximum voltage rating

of 70 V during line or load transient events. Voltage ringing at the VIN pins that exceeds the absolute maximum

ratings can damage the IC.

9.3.2 Output Voltage Selection

Adjustable Output Voltage Variants

For adjustable output voltage variants, the TPSM365Rx has an adjustable output voltage range from 1.0 V to 13

V. Setting the output voltage requires two resistors, R_FBTand R_FBB(see 图9-2). Connect R_FBTbetween VOUT at

the regulation point and the FB pin. Connect R_FBBbetween the FB pin and AGND. The variants with adjustable

output voltage option in the TPSM365Rx family are designed with a 1-V internal reference voltage. The value for

R_FBTcan be calculated using 方程式1.

V

OUT

1 V

R

kΩ = R

kΩ ×

− 1

(1)

FBT

FBB

For adjustable output options, an addition feedforward capacitor, C_FF, in parallel with the R_FBTcan be needed to

optimize the transient response. See 节 10.2.1.2.7 for additional information. No additional resistor divider or

feedforward capacitor, C_FF, is needed in case of fixed-output variants.

VOUT

R_FBT

FB /

BIAS

R_FBB

AGND

图9-2. Setting Output Voltage for Adjustable Output Variant

表9-1. Standard R_FBTValues, Recommended F_SWand Minimum C_OUT

RECOMMENED

F_SW(kHz)

C_OUT(MIN)(µF)

(EFFECTIVE)

RECOMMENED

F_SW(kHz)

C_OUT(MIN)(µF)

(EFFECTIVE)

R_FBT(kΩ) ⁽¹⁾

V_OUT(V)

1.0

1.2

1.5

1.8

2.0

2.5

3.0

Short

2

400

500

600

750

300

200

160

120

100

65

3.3

5.0

7.5

10

23.2

40.2

64.9

90.9

110

800

40

25

20

15

5

1000

1300

1500

2000

2200

4.99

8.06

10

12

15

13

120

5

20

50

(1) R_FBB= 10 kΩ

Select an R_FBBvalue of 10 kΩ for most applications. A larger R_FBTvalue consumes less DC current, which is

mandatory if light-load efficiency is critical. However, TI does not recommend R_FBTlarger than 1 MΩ because

the feedback path becomes more susceptible to noise. High feedback resistance generally requires more careful

layout of the feedback path. Keep the feedback trace as short as possible while keeping the feedback trace

away from the noisy area of the PCB. For more layout recommendations, see 节10.4.

Fixed Output Voltage Variants

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When using the TPSM365Rx as fixed-output options (no external resistors), simply connect the FB/BIAS to the

output (VOUT). The 3.3-V or 5-V fixed output options are factory trimmed and are unique to a specific device.

See 节6 for more details about the fixed-output variants.

9.3.3 Input Capacitors

Input capacitors are required to limit the input ripple voltage to the module due to switching-frequency AC

currents. TI recommends using ceramic capacitors to provide low impedance and high RMS current rating over a

wide temperature range. 方程式 2 gives the input capacitor RMS current. The highest input capacitor RMS

current occurs at D = 0.5, at which point, the RMS current rating of the capacitors must be greater than half the

output current.

2

∆ I

2

out

L

I

=

D × I

× 1 − D +

(2)

CIN, rms

12

where

• D = V_OUT/ V_INis the module duty cycle.

Ideally, the DC and AC components of the input current to the buck stage are provided by the input voltage

source and the input capacitors, respectively. Neglecting inductor ripple current, the input capacitors source

current of amplitude (I_OUT– I_IN) during the D interval and sink I_INduring the 1 – D interval. Thus, the input

capacitors conduct a square-wave current of peak-to-peak amplitude equal to the output current. The resulting

capacitive component of the AC ripple voltage is a triangular waveform. Together with the ESR-related ripple

component, 方程式3 gives the peak-to-peak ripple voltage amplitude.

I

× D × 1 − D

× C

OUT

F

∆ V

=

+ I

× R

ESR

(3)

IN

OUT

SW

IN

方程式4 gives the input capacitance required for a particular load current.

D × 1 − D × I

OUT

× I

OUT

C

≥

(4)

IN

F

×

∆ V − R

IN ESR

SW

where

• ΔV_INis the input voltage ripple specification.

The TPSM365Rx requires a minimum of a 2.2-µF ceramic type input capacitance. Only use high-quality ceramic

type capacitors with sufficient voltage and temperature rating. The ceramic input capacitors provide a low

impedance source to the power module in addition to supplying the ripple current and isolating switching noise

from other circuits. Additional capacitance can be required for applications with transient load requirements. The

voltage rating of the input capacitors must be greater than the maximum input voltage. To compensate for the

derating of ceramic capacitors, TI recommends a voltage rating of twice the maximum input voltage or placing

multiple capacitors in parallel. 表9-2 includes a preferred list of capacitors by vendor.

表9-2. Recommended Input Capacitors

CAPACITOR CHARACTERISTICS

VENDOR ⁽¹⁾

DIELECTRIC

PART NUMBER

CASE SIZE

VOLTAGE RATING (V)

CAPACITANCE (µF) ⁽²⁾

TDK

Kemet

X7R

C3225X7R2A225K230AM

C1210C225K1RAC

12061C225KAT4A

1210

1206

100

2.2

Kyocera / AVX

Sansung

Electro-

Mechanics

X7R

CL32B225KCJSNNE

1210

100

2.2

Taiyo Yuden

MSASH32MSB7225KPNA01

(1) Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process

requirements for any capacitors identified in this table. See the Third-Party Products Disclaimer.

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(2) Nameplate capacitance values (the effective values are lower based on the applied DC voltage and temperature).

9.3.4 Output Capacitors

表 9-1 lists the TPSM365Rx minimum amount of required output capacitance. The effects of DC bias and

temperature variation must be considered when using ceramic capacitance. For ceramic capacitors, the package

size, voltage rating, and dielectric material contribute to differences between the standard rated value and the

actual effective value of the capacitance.

When adding additional capacitance above C_OUT(MIN), the capacitance can be ceramic type, low-ESR polymer

type, or a combination of the two. See 表9-3 for a preferred list of output capacitors by vendor.

表9-3. Recommended Output Capacitors

CAPACITOR CHARACTERISTICS

TEMPERATURE

COEFFICIENT

VENDOR ⁽¹⁾

PART NUMBER

CASE SIZE

VOLTAGE (V)

CAPACITANCE (µF) ⁽²⁾

TDK

Murata

TDK

X7R

CGA5L1X7R1C106K160AC

GCM31CR71C106KA64L

C3216X7R1E106K160AB

GRM32ER71E226M

1206

1210

16

25

10

22

Murata

TDK

C3225X7R1E226M250AB

(1) Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process

requirements for any capacitors identified in this table. See the Third-Party Products Disclaimer.

(2) Nameplate capacitance values (the effective values are lower based on the applied DC voltage and temperature).

9.3.5 Enable, Start-Up, and Shutdown

Voltage at the EN pin controls the start-up or remote shutdown of the TPSM365Rx. The part stays shut down as

long as the EN pin voltage is less than V_EN-WAKE= 0.4 V. During the shutdown, the input current drawn by the

device typically drops down to 0.5 µA (V_IN= 13.5 V). With the voltage at the EN pin greater than V_EN-WAKE, the

device enters device standby mode and the internal LDO powers up to generate VCC. As the EN voltage

increases further, approaching V_EN-VOUT, the device finally starts to switch, entering start-up mode with a soft

start. During the device shutdown process, when the EN input voltage measures less than (V_EN-VOUT

–

V_EN-HYST), the regulator stops switching and re-enters device standby mode. Any further decrease in the EN pin

voltage, below V_EN-WAKE, and the device is then firmly shut down. The high-voltage compliant EN input pin can

be connected directly to the VIN input pin if remote precision control is not needed. The EN input pin must not be

allowed to float.

The various EN threshold parameters and their values are listed in the 节8.5. 图9-3 shows the precision enable

behavior and 图 9-4 shows a typical remote EN start-up waveform in an application. After EN goes high, after a

delay of about 1 ms, the output voltage begins to rise with a soft start and reaches close to the final value in

about 2.58 ms (t_ss). After a delay of about 1.956 ms (t_{PGOOD_ACT}), the PG flag goes high. During start-up, the

device is not allowed to enter FPWM mode until the soft-start time has elapsed. This time is measured from the

rising edge of EN.

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EN

V_EN-VOUT

V_EN-HYST

V_EN-WAKE

VCC

3.15V

0

VOUT

V_OUT

0

图9-3. Precision Enable Behavior

EN (5 V/DIV)

VOUT (5 V/DIV)

PGOOD (5 V/DIV)

IOUT (500 mA/DIV)

2 ms/DIV

图9-4. Enable Start-Up V_IN= 24 V, V_OUT= 5 V, I_OUT= 0.5 A

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External UVLO via EN pin

In some cases, an input UVLO level different than that provided internal to the device is needed. This can be

accomplished by using the circuit shown in 图 9-5. The input voltage at which the device turns on is designated

as V_ONwhile the turn-off voltage is V_OFF. First, a value for R_ENBis chosen in the range of 10 kΩto 100 kΩ, then

方程式5 and 方程式6 are used to calculate R_ENTand V_OFF, respectively.

V_IN

R_ENT

EN

R_ENB

AGND

图9-5. Setup for External UVLO Application

V

ON

R

V

=

− 1 × R

(5)

(6)

ENT

ENB

V

EN − VOUT

V

EN − HYST

= V × 1 −

OFF

ON

EN − VOUT

where

• V_ONis the V_INturn-on voltage.

• V_OFFis the V_INturn-off voltage.

9.3.6 External CLK SYNC (with MODE/SYNC)

It is often desirable to synchronize the operation of multiple regulators in a single system, resulting in a well-

defined system level performance. The select variants in the TPSM365Rx with the MODE/SYNC pin allow the

power designer to synchronize the device to a common external clock. An in-phase locking scheme where the

rising edge of the clock signal, provided to the MODE/SYNC pin, corresponds to the turning on of the high-side

device. The external clock synchronization is implemented using a phase locked loop (PLL) eliminating any large

glitches. The external clock fed into the TPSM365Rx replaces the internal free-running clock, but does not affect

any frequency foldback operation. Output voltage continues to be well-regulated. The device remains in FPWM

mode and operates in CCM for light loads when synchronization input is provided.

The MODE/SYNC input pin in the TPSM365Rx can operate in one of three selectable modes:

• Auto Mode: Pulse frequency modulation (PFM) operation is enabled during light load and diode emulation

prevents reverse current through the inductor.

• FPWM Mode: In FPWM mode, diode emulation is disabled, allowing current to flow backwards through the

inductor. This allows operation at full frequency even without load current.

• SYNC Mode: The internal clock locks to an external signal applied to the MODE/SYNC pin. As long as output

voltage can be regulated at full frequency and is not limited by minimum off-time or minimum on-time, clock

frequency is matched to the frequency of the signal applied to the MODE/SYNC pin. While the device is in

SYNC mode, it operates as though in FPWM mode: diode emulation is disabled allowing the frequency

applied to the MODE/SYNC pin to be matched without a load.

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9.3.6.1 Pulse-Dependent MODE/SYNC Pin Control

Most systems that require more than a single mode of operation from the device are controlled by digital circuitry

such as a microprocessor. These systems can generate dynamic signals easily but have difficulty generating

multi-level signals. Pulse-dependent MODE/SYNC pin control is useful with these systems. To initiate pulse-

dependent MODE/SYNC pin control, a valid sync signal must be applied. 表 9-4 shows a summary of the pulse

dependent mode selection settings.

表9-4. Pulse-Dependent Mode Selection Settings

MODE/SYNC INPUT

MODE

> V_{MODE_H}

FPWM with spread spectrum factory setting

Auto mode with spread spectrum factory setting

SYNC mode

< V_{MODE_L}

Synchronization Clock

图 9-6 shows the transition between auto mode and FPWM mode while in pulse-dependent MODE/SYNC

control. The device transitions to a new mode of operation after the time, t_MODE. 图 9-6 and 图 9-7 show the

details.

Transition to new mode of operation

starts, spread spectrum turns on

> t_MODE

FPWM Mode

V_{MODE_H}

V_{MODE_L}

Auto Mode

图9-6. Transition from Auto Mode and FPWM Mode

If MODE/SYNC voltage remains constant longer than t_MODE, the device enters either auto mode or FPWM mode

with spread spectrum turned on (if factory setting is enabled) and MODE/SYNC continues to operate in pulse-

dependent scheme.

t_MODE

Now Auto Mode, Spread Spectrum on

V_{MODE_H}

V_{MODE_L}

> t_{PULSE_H}

< t_SYNC

> t_{PULSE_L}

图9-7. Transition from SYNC Mode to Auto Mode

t_MODE

< t_SYNC

Now FPWM Mode, Spread Spectrum on

V_{MODE_H}

V_{MODE_L}

> t_{PULSE_H}

< t_SYNC

> t_{PULSE_L}

图9-8. Transition from SYNC Mode to FPWM Mode

9.3.7 Switching Frequency (RT)

The select variants in the TPSM365Rx family with the RT pin allows the power designers to set any desired

operating frequency between 200 kHz and 2.2 MHz in their applications. See 图 9-9 to determine the resistor

value needed for the desired switching frequency or simply select from 表9-6. The RT pin and the

MODE/SYNC pin variants share the same pin location. The power supply designer can either use the RT pin

variant and adjust the switching frequency of operation as warranted by the application or use the MODE/SYNC

variant and synchronize to an external clock signal. See 表9-5 for selection on programming the RT pin.

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表9-5. RT Pin Setting

RT INPUT

VCC

SWITCHING FREQUENCY

1 MHz

GND

2.2 MHz

RT to GND

Adjustable according to 图9-9

No switching

Float (not recommended)

18286

RT =

Fsw^1.021

(7)

where

• RT is the frequency setting resistor value (kΩ).

• F_SWis the switching frequency (kHz).

80

70

60

50

40

30

20

10

0

200 400 600 800 1000 1200 1400 1600 1800 2000 2200

Switching Frequency (kHz)

图9-9. RT Values vs Frequency

The switching frequency must be selected based on the output voltage setting of the device. See 表 9-6 for R_RT

resistor values and the allowable output voltage range for a given switching frequency for common input

voltages.

表9-6. Switching Frequency Versus Output Voltage (I_OUT= 600 mA)

V_IN= 5 V

V_IN= 12 V

V_IN= 24 V

V_IN= 36 V

V_IN= 48 V

R_RT

(kΩ)

F_SW

(kHz)

V_OUTRANGE (V)

MIN

1

MAX

1

MIN

-

MAX

-

MIN

-

MAX

-

MIN

-

MAX

-

MIN

-

MAX

-

200

400

81.6

40.2

26.7

19.8

15.8

13.2

11.3

9.76

8.66

7.77

7.06

1

2.4

2.7

3.1

3.5

3.9

4

1

2

1

1.9

3

1.1

1.6

2.1

2.6

3.1

3.6

4.1

4.6

5.1

5.6

1.8

2.8

3.9

5.1

6.4

7.9

9.7

11.9

13

1.4

2.1

2.7

3.4

4.1

4.8

5.4

6.1

6.8

7.4

1.8

2.8

3.8

4.9

6

600

1

4

1.1

1.4

1.7

2.1

2.4

2.7

3.1

3.4

3.7

800

1

6

4.4

5.8

8

1000

1200

1400

1600

1800

2000

2200

1

6

1

1.1

1.2

1.4

1.6

1.7

1.9

6

1

6.4

7

12

7.3

8.6

10.1

11.7

13

1

4

1

4

7.4

7.8

8.2

1

4

1

4

13

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9.3.8 Power-Good Output Operation

The power-good feature using the PGOOD pin of the TPSM365Rx can be used to reset a system

microprocessor whenever the output voltage is out of regulation. This open-drain output remains low under

device fault conditions, such as current limit and thermal shutdown, as well as during normal start-up. A glitch

filter prevents false flag operation for any short duration excursions in the output voltage, such as during line and

load transients. Output voltage excursions lasting less than t_{RESET_FILTER}do not trip the power-good flag. Power-

good operation can best be understood in reference to 图 9-10. 表 9-7 gives a more detailed breakdown of the

PGOOD operation. Here, V_PGis defined as the PG_UVscaled version of V_OUT(target regulated output voltage)

UV

and V_PG

as the PG_HYSscaled version of V_OUT, where both PG_UVand PG_HYSare listed in 节 8.5. During the

HYS

initial power up, a total delay of 5 ms (typical) is encountered from the time V_EN-VOUTis triggered to the time that

the power-good is flagged high. This delay only occurs during the device start-up and is not encountered during

any other normal operation of the power-good function. When EN is pulled low, the power-good flag output is

also forced low. With EN low, power-good remains valid as long as the input voltage (V_PGD-VALIDis ≥ 1 V

(typical)).

The power-good output scheme consists of an open-drain n-channel MOSFET, which requires an external pullup

resistor connected to a suitable logic supply. It can also be pulled up to either V_CCor V_OUTthrough an

appropriate resistor, as desired. If this function is not needed, the PGOOD pin can be open or grounded. Limit

the current into this pin to ≤4 mA.

Output

Input

Voltage

Input Voltage

t_{RESET_FILTER}

t_{PGOOD_ACT}

t_{RESET_FILTER}

V_PG-HYS

t_{RESET_FILTER}

V_PG-UV(falling)

V_{IN_R}(rising)

V_{IN_F}(falling)

V_PG-VALID

GND

VOUT

PGOOD

Small glitches

do not cause

reset to signal

a fault

PG may not

be valid if

input is below

V_PG-VALID

Small glitches do not

reset t_{PGOOD_ACT}timer

PG may not be

valid if input is

below V_PG-VALID

Startup

delay

图9-10. Power-Good Operation (OV Events Not Included)

表9-7. Fault Conditions for PGOOD (Pull Low)

FAULT CONDITION ENDS (AFTER WHICH t_{PGOOD_ACT}MUST PASS

BEFORE PGOOD OUTPUT IS RELEASED)

FAULT CONDITION INITIATED

Output voltage in regulation:

V_OUT< V

AND t > t_{RESET_FILTER}

PG_UV

V

+ V

< V_OUT< V

- V

PG_UV

PG_HYS

PG_OVPG_HYS

V_OUT> V_PGAND t > t_{RESET_FILTER}

Output voltage in regulation

OV

T_J> T_SD-R

T_J< T_SD-R-T_SD-HYSAND output voltage in regulation

EN > V_EN-VOUTAND output voltage in regulation

V_CC> V_CC-UVLOAND output voltage in regulation

EN < V_EN-VOUT- V_EN-HYST

V_CC< V_CC-UVLO- V_CC-UVLO-HYST

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9.3.9 Internal LDO, VCC UVLO, and BIAS Input

The TPSM365Rx uses the internal LDO output and the VCC pin for all internal power supply. The VCC pin

draws power either from the VIN (in adjustable output variants) or the BIAS (in fixed-output variants). In the fixed

output variants, after the TPSM365Rx is active but has yet to regulate, the VCC rail continues to draw power

from the input voltage, VIN, until the BIAS voltage reaches > 3.15 V (or when the device has reached steady-

state regulation post the soft start). The VCC rail typically measures 3.15 V in both adjustable and fixed output

variants. To prevent unsafe operation, VCC has an undervoltage lockout, which prevents switching if the internal

voltage is too low. See V_VCC-UVLOand V_{VCC-UVLO-HYST}in 节 8.5. During start-up, VCC momentarily exceeds the

normal operating voltage until V_VCC-UVLOis exceeded, then drops to the normal operating voltage. Note that

these undervoltage lockout values, when combined with the LDO dropout, drives the minimum input voltage

rising and falling thresholds.

9.3.10 Bootstrap Voltage and V_BOOT-UVLO(BOOT Terminal)

The high-side switch driver circuit requires a bias voltage higher than VIN to ensure the HS switch is turned ON.

There is an internal 0.1-μF capacitor connected between BOOT and SW that operates as a charge pump to

boost the voltage on the BOOT terminal to (SW + VCC). The boot diode is integrated on the TPSM365Rx die to

minimize physical solution size. The BOOT rail has an UVLO setting. This UVLO has a threshold of V_BOOT-UVLO

and is typically set at 2.3 V. If the BOOT capacitor is not charged above this voltage with respect to the SW pin,

then the part initiates a charging sequence, turning on the low-side switch before attempting to turn on the high-

side device.

9.3.11 Spread Spectrum

The purpose of spread spectrum is to eliminate peak emissions at specific frequencies by spreading these peaks

across a wider range of frequencies than a part with fixed-frequency operation. In most systems containing the

TPSM365Rx, low-frequency conducted emissions from the first few harmonics of the switching frequency can be

easily filtered. A more difficult design criterion is reduction of emissions at higher harmonics, which fall in the FM

band. These harmonics often couple to the environment through electric fields around the switch node and

inductor. The TPSM365Rx uses a ±2% spread of frequencies which can spread energy smoothly across the FM

and TV bands, but is small enough to limit subharmonic emissions below the switching frequency of the part.

Peak emissions at the switching frequency of the part are only reduced slightly, by less than 1 dB, while peaks in

the FM band are typically reduced by more than 6 dB.

The TPSM365Rx uses a cycle-to-cycle frequency hopping method based on a linear feedback shift register

(LFSR). This intelligent pseudo-random generator limits cycle-to-cycle frequency changes to limit output ripple.

The pseudo-random pattern repeats at less than 1.5 Hz, which is below the audio band.

The spread spectrum is only available while the clock of the TPSM365Rx device is free running at its natural

frequency. Any of the following conditions overrides spread spectrum, turning it off:

• The clock is slowed due to operation at low-input voltage –this is operation in dropout.

• The clock is slowed under light load in auto mode. Note that if you are operating in FPWM mode, spread

spectrum can be active, even if there is no load.

• The clock is slowed due to high input to output voltage ratio. This mode of operation is expected if on-time

reaches minimum on-time. See Electrical Characteristics.

• The clock is synchronized with an external clock.

9.3.12 Soft Start and Recovery from Dropout

When designing with the TPSM365Rx, slow rise in output voltage due to recovery from dropout and soft start

must be considered as a two separate operating conditions, as shown in 图 9-11 and 图 9-12. Soft start is

triggered by any of the following conditions:

• Power is applied to the VIN pin of the device, releasing undervoltage lockout.

• EN is used to turn on the device.

• Recovery from shutdown due to overtemperature protection.

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After soft start is triggered, the power module takes the following actions:

• The reference used by the power module to regulate the output voltage is slowly ramped up. The net result is

that output voltage, if previously 0 V, takes t_SSto reach 90% of the desired value.

• Operating mode is set to auto mode of operation, activating the diode emulation mode for the low-side

MOSFET. This allows start-up without pulling the output low. This is true even when there is a voltage already

present at the output during a pre-bias start-up.

If selected, FPWM

is enabled only

after completion of

t_SS

If selected, FPWM

is enabled only

after completion of

t_SS

Triggering event

t_EN

t_SS

t_EN

t_SS

V

V_EN

V_OUTSet

Point

V_OUTSet

Point

V_OUT

90% of

V_OUTSet

Point

90% of

V_OUTSet

Point

t

0 V

Time

图9-11. Soft Start with and without Prebias Voltage

9.3.12.1 Recovery from Dropout

Any time the output voltage falls more than a few percent, output voltage ramps up slowly. This condition, called

graceful recovery from dropout in this document, differs from soft start in two important ways:

• The reference voltage is set to approximately 1% above what is needed to achieve the existing output

voltage.

• If the device is set to FPWM, it continues to operate in that mode during its recovery from dropout. If output

voltage were to suddenly be pulled up by an external supply, the TPSM365Rx can pull down on the output.

Note that all protections that are present during normal operation are in place, preventing any catastrophic

failure if output is shorted to a high voltage or ground.

V

Load

current

V_OUTSet

Point

and max

output

Slope

V_OUT

the same

as during

soft start

current

t

Time

图9-12. Recovery from Dropout

Whether the output voltage falls due to high load or low input voltage, after the condition that causes the output

to fall below its set point is removed, the output climbs at the same speed as during start-up. 图 9-12 shows an

example of this behavior.

9.3.13 Overcurrent Protection (OCP)

The TPSM365Rx is protected from overcurrent conditions by using cycle-by-cycle current limiting circuitry on

both the high-side and low-side MOSFETs. The current is compared every switching cycle to the current limit

threshold. During an overcurrent condition, the output voltage decreases.

High-side MOSFET overcurrent protection is implemented by the typical peak-current mode control scheme. The

HS switch current is sensed when the HS is turned on after a short blanking time. The HS switch current is

compared to either the minimum of a fixed current set point or the output of the internal error amplifier loop

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minus the slope compensation every switching cycle. Because the output of the internal error amplifier loop has

a maximum value and slope compensation increases with duty cycle, HS current limit decreases with increased

duty factor if duty factor is typically above 35%.

When the LS switch is turned on, the current going through it is also sensed and monitored. Like the high-side

device, the low-side device has a turnoff commanded by the internal error amplifier loop. In the case of the

lowside device, turn-off is prevented if the current exceeds this value, even if the oscillator normally starts a new

switching cycle. Also like the high-side device, there is a limit on how high the turn-off current is allowed to be.

This is called the low-side current limit. If the LS current limit is exceeded, the LS MOSFET stays on and the HS

switch is not to be turned on. The LS switch is turned off after the LS current falls below this limit and the HS

switch is turned on again as long as at least one clock period has passed since the last time the HS device has

turned on.

9.3.14 Thermal Shutdown

Thermal shutdown limits total power dissipation by turning off the internal switches when the device junction

temperature exceeds 168°C (typical). Thermal shutdown does not trigger below 158°C (minimum). After thermal

shutdown occurs, hysteresis prevents the part from switching until the junction temperature drops to

approximately 158°C (typical). When the junction temperature falls below 158°C (typical), the TPSM365Rx

attempts another soft start.

While the TPSM365Rx is shut down due to high junction temperature, power continues to be provided to VCC.

To prevent overheating due to a short circuit applied to VCC, the LDO that provides power for VCC has reduced

current limit while the part is disabled due to high junction temperature. The LDO only provides a few

milliamperes during thermal shutdown.

9.4 Device Functional Modes

9.4.1 Shutdown Mode

The EN pin provides electrical ON and OFF control of the device. When the EN pin voltage is below 0.4 V, the

power module does not have any output voltage and the device is in shutdown mode. In shutdown mode, the

quiescent current drops to typically 0.5 µA.

9.4.2 Standby Mode

The internal LDO has a lower EN threshold than the output of the power module. When the EN pin voltage is

above V_EN-WAKEand below the precision enable threshold for the output voltage, the internal LDO regulates the

VCC voltage at 3.15 V typical. The precision enable circuitry is ON after VCC is above its UVLO. The internal

power MOSFETs of the SW node remain off unless the voltage on EN pin goes above its precision enable

threshold. The TPSM365Rx also employs UVLO protection. If the VCC voltage is below its UVLO level, the

output of the module is turned off.

9.4.3 Active Mode

The TPSM365Rx is in active mode whenever the EN pin is above V_EN-VOUT, V_INis high enough to satisfy V_{IN_R}

and no other fault conditions are present. The simplest way to enable the operation is to connect the EN pin to

V_IN, which allows self start-up when the applied input voltage exceeds the minimum V_{IN_R}

,

.

In active mode, depending on the load current, input voltage, and output voltage, the TPSM365Rx is in one of

five modes:

• Continuous conduction mode (CCM) with fixed switching frequency when the load current is above half of the

inductor current ripple.

• Auto Mode - Light Load Operation: PFM when switching frequency is decreased at very light load.

• FPWM Mode - Light Load Operation: Discontinuous conduction mode (DCM) when the load current is lower

than half of the inductor current ripple.

• Minimum on-time: At high input voltage and low output voltages, the switching frequency is reduced to

maintain regulation.

• Dropout mode: When switching frequency is reduced to minimize voltage dropout.

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9.4.3.1 CCM Mode

The following operating description of the TPSM365Rx refers to 节 9.2. In CCM, the TPSM365Rx supplies a

regulated output voltage by turning on the internal high-side (HS) and low-side (LS) switches with varying duty

cycle (D). During the HS switch on-time, the SW pin voltage, V_SW, swings up to approximately V_IN, and the

inductor current increases with a linear slope. The HS switch is turned off by the control logic. During the HS

switch off-time, t_OFF, the LS switch is turned on. Inductor current discharges through the LS switch, which forces

the V_SWto swing below ground by the voltage drop across the LS switch. The buck module converter loop

adjusts the duty cycle to maintain a constant output voltage. D is defined by the on-time of the HS switch over

the switching period:

D = T_ON/ T_SW

(8)

In an ideal buck module converter where losses are ignored, D is proportional to the output voltage and inversely

proportional to the input voltage:

D = V_OUT/ V_IN

(9)

9.4.3.2 AUTO Mode - Light Load Operation

The TPSM365Rx can have two behaviors while lightly loaded. One behavior, called auto mode operation, allows

for seamless transition between normal current mode operation while heavily loaded and highly efficient light

load operation. The other behavior, called FPWM Mode, maintains full frequency even when unloaded. Which

mode the TPSM365Rx operates in depends on which variant from this family is selected. Note that all parts

operate in FPWM mode when synchronizing frequency to an external signal.

The light load operation is employed in the TPSM365Rx only in the auto mode. The light load operation employs

two techniques to improve efficiency:

• Diode emulation, which allows DCM operation (See 图9-13)

• Frequency reduction (See 图9-14)

Note that while these two features operate together to improve light load efficiency, they operate independent of

each other.

9.4.3.2.1 Diode Emulation

Diode emulation prevents reverse current through the inductor which requires a lower frequency needed to

regulate given a fixed peak inductor current. Diode emulation also limits ripple current as frequency is reduced.

With a fixed peak current, as output current is reduced to zero, frequency must be reduced to near zero to

maintain regulation.

t_ON

t_SW

V_OUT

V_IN

V_SW

D =

<

V_IN

t_OFF

t_ON

t_HIGHZ

0

t

t_SW

i_L

I_PEAK

I_OUT

0

t

In auto mode, the low-side device is turned off after SW node current is near zero. As a result, after output current is less than half of

what inductor ripple can be in CCM, the part operates in DCM which is equivalent to the statement that diode emulation is active.

图9-13. PFM Operation

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The TPSM365Rx has a minimum peak inductor current setting (see I_PEAK-MINin 节8.5) while in auto mode. After

current is reduced to a low value with fixed input voltage, on-time is constant. Regulation is then achieved by

adjusting frequency. This mode of operation is called PFM mode regulation.

9.4.3.2.2 Frequency Reduction

The TPSM365Rx reduces frequency whenever output voltage is high. This function is enabled whenever the

internal error amplifier compensation output, COMP, an internal signal, is low and there is an offset between the

regulation set point of FB/BIAS and the voltage applied to FB/BIAS. The net effect is that there is larger output

impedance while lightly loaded in auto mode than in normal operation. Output voltage must be approximately 1%

high when the part is completely unloaded.

V_OUT

Current

Limit

1% Above

Set point

V_OUTSet

Point

I_OUT

Output Current

0

In auto mode, after output current drops below approximately 1/10th the rated current of the part, output resistance increases so that

output voltage is 1% high while the buck is completely unloaded.

图9-14. Steady State Output Voltage versus Output Current in Auto Mode

In PFM operation, a small DC positive offset is required on the output voltage to activate the PFM detector. The

lower the frequency in PFM, the more DC offset is needed on VOUT. If the DC offset on VOUT is not acceptable,

a dummy load at VOUT or FPWM Mode can be used to reduce or eliminate this offset.

9.4.3.3 FPWM Mode - Light Load Operation

In FPWM Mode, frequency is maintained while the output is lightly loaded. To maintain frequency, a limited

reverse current is allowed to flow through the inductor. Reverse current is limited by reverse current limit circuitry,

see 节8.5 for reverse current limit values.

t_ON

t_SW

V_SW

V_OUT

V_IN

D =

≈

V_IN

t_OFF

t_ON

0

t

t_SW

i_L

I_PEAK

I_OUT

0

I_ripple

t

In FPWM mode, Continuous Conduction (CCM) is possible even if I_OUTis less than half of I_ripple

.

图9-15. FPWM Mode Operation

For all devices, in FPWM mode, frequency reduction is still available if output voltage is high enough to

command minimum on-time even while lightly loaded, allowing good behavior during faults which involve output

being pulled up.

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9.4.3.4 Minimum On-time (High Input Voltage) Operation

The TPSM365Rx continues to regulate output voltage even if the input-to-output voltage ratio requires an on-

time less than the minimum on-time of the chip with a given clock setting. This is accomplished using valley

current control. At all times, the compensation circuit dictates both a maximum peak inductor current and a

maximum valley inductor current. If for any reason, valley current is exceeded, the clock cycle is extended until

valley current falls below that determined by the compensation circuit. If the power module is not operating in

current limit, the maximum valley current is set above the peak inductor current, preventing valley control from

being used unless there is a failure to regulate using peak current only. If the input-to-output voltage ratio is too

high, such that the inductor current peak value exceeds the peak command dictated by compensation, the high-

side device cannot be turned off quickly enough to regulate output voltage. As a result, the compensation circuit

reduces both peak and valley current. After a low enough current is selected by the compensation circuit, valley

current matches that being commanded by the compensation circuit. Under these conditions, the low-side device

is kept on and the next clock cycle is prevented from starting until inductor current drops below the desired valley

current. Because on-time is fixed at its minimum value, this type of operation resembles that of a device using a

Constant On-Time (COT) control scheme; see 图9-16.

t_ON

V_OUT

V_IN

V_SW

D =

≈

t_SW

t_ON= t_{ON_MIN}

V_IN

t_OFF

0

- I_OUTR_DSON-LS

t

t_SW> Clock setting

i_L

I_OUT

I_VAL

I_ripple

t

0

In valley control mode, minimum inductor current is regulated, not peak inductor current.

图9-16. Valley Current Mode Operation

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9.4.4 Dropout

Dropout operation is defined as any input-to-output voltage ratio that requires frequency to drop to achieve the

required duty cycle. At a given clock frequency, duty cycle is limited by the minimum off-time. After this limit is

reached as shown in 图 9-18 if clock frequency was to be maintained, the output voltage can fall. Instead of

allowing the output voltage to drop, the TPSM365Rx extends the high side switch on-time past the end of the

clock cycle until the needed peak inductor current is achieved. The clock is allowed to start a new cycle after

peak inductor current is achieved or after a pre-determined maximum on-time, t_ON-MAX, of approximately 9 µs

passes. As a result, after the needed duty cycle cannot be achieved at the selected clock frequency due to the

existence of a minimum off-time, frequency drops to maintain regulation. As shown in 图 9-17 if input voltage is

low enough so that output voltage cannot be regulated even with an on-time of t_ON-MAX, output voltage drops to

slightly below the input voltage by V_DROP. For additional information on recovery from dropout, refer back to 节

9.3.12.1.

Input

Voltage

V_OUT

V_DROP

Output

Setting

Voltage

V_IN

0

Input Voltage

F_SW

F_SW-NOM

≅ 110 kHz

V_IN

0

Input Voltage

Output voltage and frequency versus input voltage: If there is little difference between input voltage and output voltage setting, the IC

reduces frequency to maintain regulation. If input voltage is too low to provide the desired output voltage at approximately 110 kHz,

input voltage tracks output voltage.

图9-17. Frequency and Output Voltage in Dropout

t_ON

t_SW

V_OUT

V_IN

V_SW

D =

V_IN

t_OFF= t_{OFF_MIN}

t_ON< t_{ON_MAX}

0

- I_OUTR_DSON-LS

t

t_SW> Clock setting

i_L

I_PEAK

I_OUT

I_ripple

t

0

Switching waveforms while in dropout. Inductor current takes longer than a normal clock to reach the desired peak value. As a result,

frequency drops. This frequency drop is limited by t_ON-MAX

.

图9-18. Dropout Waveforms

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10 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

10.1 Application Information

The TPSM365Rx only requires a few external components to convert from a wide range of supply voltages to a

fixed output voltage. To expedite and streamline the process of designing of a TPSM365Rx, WEBENCH® online

software is available to generate complete designs, leveraging iterative design procedures and access to

comprehensive component databases. The following section describes the design procedure to configure the

TPSM365Rx power module.

As mentioned previously, the TPSM365Rx also integrates several optional features to meet system design

requirements, including precision enable, UVLO, and PGOOD indicator. The application circuit detailed below

shows TPSM365Rx configuration options suitable for several application use cases. Refer to the

TPSM365R6EVM User's Guide for more detail.

备注

All of the capacitance values given in the following application information refer to effective values

unless otherwise stated. The effective value is defined as the actual capacitance under DC bias and

temperature, not the rated or nameplate values. Use high-quality, low-ESR, ceramic capacitors with

an X7R or better dielectric throughout. All high value ceramic capacitors have a large voltage

coefficient in addition to normal tolerances and temperature effects. Under DC bias the capacitance

drops considerably. Large case sizes and higher voltage ratings are better in this regard. To help

mitigate these effects, multiple capacitors can be used in parallel to bring the minimum effective

capacitance up to the required value. This can also ease the RMS current requirements on a single

capacitor. A careful study of bias and temperature variation of any capacitor bank must be made to

ensure that the minimum value of effective capacitance is provided.

10.2 Typical Application

The following design is a sample typical application and design procedure to implement the TPSM365Rx.

10.2.1 600-mA and 300-mA Synchronous Buck Regulator for Industrial Applications

图 10-1 and 图 10-2 shows respectively the TPSM365R6 and TPSM365R3 setup in a typical application with an

output voltage of 5-V with a switching frequency of 1 MHz. The nominal input voltage is 24 V. The RT pin is tied

to VCC which sets the free-running switching frequency at 1 MHz.

VIN

EN

SW

V_IN= 24 V

2.2

100 V

F

0.1

100 V

F

BOOT

TPSM365R6

V_OUT= 5 V

I_OUT(max)= 600 mA

VOUT

R_FBT

40.2 K

2 X 22

F

FB

VCC

RT

R_FBB

10 K

100 K

PGOOD

GND

PGOOD

indicator

1

F

图10-1. Example Application Circuit

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VIN

EN

SW

V_IN= 24 V

2.2

100 V

F

0.1

100 V

F

BOOT

TPSM365R3

V_OUT= 5 V

I_OUT(max)= 300 mA

VOUT

R_FBT

40.2 K

2 X 22

F

FB

VCC

RT

R_FBB

10 K

100 K

PGOOD

GND

PGOOD

indicator

1

F

图10-2. Example Application Circuit

10.2.1.1 Design Requirements

For this design example, use the parameters listed in 表 10-1 as the input parameters and follow the design

procedures in Detailed Design Procedure.

表10-1. Design Example Parameters

DESIGN PARAMETER

VALUE

Input voltage

24 V

Output voltage

5 V

Output current

0 A to 600 mA

1 MHz

Switching frequency

表 10-2 gives the selected buck module power-stage components with availability from multiple vendors. This

design uses an all-ceramic output capacitor implementation.

表10-2. List of Materials for Application Circuit 1

REFERENCE

DESIGNATOR

QTY

SPECIFICATION

MANUFACTURER ⁽¹⁾

PART NUMBER

1

2

1

2.2 µF, 100 V, X7R, 1210, ceramic

100 nF, 100 V, X7R, 0603, ceramic

TDK

Murata

C3225X7R2A225K230AB

GRM188R72A104KA35J

C3225X7R1E226M250AB

C1608X7R1C105K080AC

TPSM365R6FRDNR

C_IN

C_OUT

C_VCC

U₁

22 µF, 25 V, X7R, 1210, ceramic

TDK

1 µF, 16 V, X7R, 0603, ceramic

TDK

TPSM365R6 65-V, 600-mA synchronous buck module

Texas Instruments

(1) See the Third-Party Products Disclaimer

More generally, the TPSM365Rx module is designed to operate with a wide range of external components and

system parameters. However, the integrated loop compensation is optimized for a certain range of output

capacitance.

10.2.1.2 Detailed Design Procedure

10.2.1.2.1 Custom Design With WEBENCH® Tools

To create a custom design using the TPSM365Rx device with the WEBENCH Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

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• Run electrical simulations to see important waveforms and circuit performance.

• Run thermal simulations to understand board thermal performance.

• Export customized schematic and layout into popular CAD formats.

• Print PDF reports for the design, and share the design with colleagues.

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

10.2.1.2.2 Output Voltage Setpoint

The output voltage of the TPSM365Rx device is externally adjustable using a resistor divider. The recommended

value of R_FBBis 10 kΩ. The value for R_FBTcan be selected from 表9-1 or calculated using 方程式10:

V

OUT

1 V

R

kΩ = R

kΩ ×

− 1

(10)

FBT

FBB

For the desired output voltage of 5 V, the formula yields a value of 40.2 kΩ. Choose the closest available

standard value of 40.2 kΩ for R_FBT. Alternatively, if a fixed 3.3-V or 5-V output voltage power module variant is

used, the user can connect the FB/BIAS pin directly to the output capacitor.

10.2.1.2.3 Switching Frequency Selection

The recommended switching frequency for standard output voltages can be found in 表 9-1. For a 5-V output,

the recommended switching frequency is 1 MHz. To set the switching frequency to 1 MHz, connect the RT pin to

VCC.

10.2.1.2.4 Input Capacitor Selection

The TPSM365Rx requires a minimum input capacitance of 1 × 2.2-µF and 1 × 0.1-µF ceramic type. High-quality

ceramic type capacitors with sufficient voltage and temperature rating are required. The voltage rating of input

capacitors must be greater than the maximum input voltage.

For this design, select a 2.2-µF, 100-V, 1210 case size, and a 0.1-µF, 100-V, 0603 case size ceramic capacitors.

10.2.1.2.5 Output Capacitor Selection

For a 5-V output, the TPSM365Rx requires a minimum of 25 µF of effective output capacitance for proper

operation (see 表 9-1). High-quality ceramic type capacitors with sufficient voltage and temperature rating are

required. Additional output capacitance can be added to reduce ripple voltage or for applications with transient

load requirements.

For this design example, select 2 × 22-µF, 25-V, 1210 case size, ceramic capacitors, which have a total effective

capacitance of approximately 42 µF at 5 V.

10.2.1.2.6 VCC

The VCC pin is the output of the internal LDO used to supply the control circuits of the regulator. This output

requires a 1-µF, 16-V ceramic capacitor connected from VCC to GND for proper operation. In general, this

output must not be loaded with any external circuitry. However, this output can be used to supply the pullup for

the power-good function (see 节 9.3.8). A value in the range of 10 kΩ to 100 kΩ is a good choice in this case.

The nominal output voltage on VCC is 3.15 V; see 节8.5 for limits.

10.2.1.2.7 C_FFSelection

In some cases, a feedforward capacitor can be used across R_FBTto improve the load transient response or

improve the loop-phase margin. This is especially true when values of R_FBT> 100 kΩ are used. Large values of

R_FBT, in combination with the parasitic capacitance at the FB pin, can create a small signal pole that interferes

with the loop stability. A C_FFcan help mitigate this effect. Use 方程式 11 to estimate the value of C_FF. The value

found with 方程式 11 is a starting point; use lower values to determine if any advantage is gained by the use of a

C_FFcapacitor. The Optimizing Transient Response of Internally Compensated DC-DC Converters with Feed

forward Capacitor application report is helpful when experimenting with a feedforward capacitor.

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V

× C

OUT

V

C

<

(11)

FF

REF

OUT

120 × R

×

FBT

V

10.2.1.2.8 Power-Good Signal

Applications requiring a power good signal to indicate that the output voltage is present and in regulation must

use a pullup resistor between the PGOOD pin and a valid voltage source.

For this design, a 100-kΩ resistor is placed between the PGOOD pin and the VCC pin (the internal 3.15-V LDO

output).

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10.2.1.2.9 Maximum Ambient Temperature

As with any power conversion module, the TPSM365Rx dissipates internal power while operating. The effect of

this power dissipation is to raise the internal temperature of the power module above ambient. The internal die

and inductor temperature (T_J) is a function of the ambient temperature, the power loss, and the effective thermal

resistance, R_θJA, of the module and PCB combination. The maximum junction temperature for the TPSM365Rx

must be limited to 125°C. This establishes a limit on the maximum module power dissipation and, therefore, the

load current. 方程式 12 shows the relationships between the important parameters. It is easy to see that larger

ambient temperatures (T_A) and larger values of R_θJAreduce the maximum available output current. The power

module efficiency can be estimated by using the curves provided in this data sheet. If the desired operating

conditions cannot be found in one of the curves, interpolation can be used to estimate the efficiency.

Alternatively, the EVM can be adjusted to match the desired application requirements and the efficiency can be

measured directly. The correct value of R_θJAis more difficult to estimate. As stated in the Semiconductor and IC

Package Thermal Metrics application report the values given in Thermal Information section are not valid for

design purposes and must not be used to estimate the thermal performance of the application. The values

reported in that table were measured under a specific set of conditions that are rarely obtained in an actual

application.

T − T

η

J

A

1

I

=

×

(12)

OUT MAX

R

1 − η

V

θJA

OUT

where

• ηis the efficiency.

The effective R_θJAis a critical parameter and depends on many factors such as the following:

• Power dissipation

• Air temperature/flow

• PCB area

• Copper heat-sink area

• Number of thermal vias under the package

• Adjacent component placement

As a reference, the effective R_θJAon the EVM for typical 24-V V_IN5-V V_OUTfull-load condition is around 30

°C/W. Use the following resources as guides to optimal thermal PCB design and estimating R_θJAfor a given

application environment:

• Thermal Design by Insight not Hindsight Application Report

• A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages Application Report

• Semiconductor and IC Package Thermal Metrics Application Report

• Thermal Design Made Simple with LM43603 and LM43602 Application Report

• PowerPAD^™Thermally Enhanced Package Application Report

• PowerPAD^™Made Easy Application Report

• Using New Thermal Metrics Application Report

• PCB Thermal Calculator

10.2.1.2.10 Other Connections

• The RT pin can be connected to AGND for a switching frequency of 2.2 MHz or tied to VCC for a switching

frequency of 1 MHz. A resistor connected between the RT pin and GND can be used to set the desired

operating frequency between 200 kHz and 2.2 MHz.

• For the MODE/SYNC pin variant, connecting this pin to an external clock forces the device into SYNC

operation. Connecting the MODE/SYNC pin low allows the device to operate in PFM mode at light load.

Connecting the MODE/SYNC pin high puts the device into FPWM mode and allows full frequency operation

independent of load current.

• A resistor divider network on the EN pin can be added for a precision input undervoltage lockout (UVLO)

• For fixed output voltage variants, connect FB/BIAS pin to VOUT.

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• Place a 1-µF capacitor between the VCC pin and PGND, located near to the device.

• A pullup resistor between the PGOOD pin and a valid voltage source to generate a power-good signal.

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10.2.1.3 Application Curves

Unless otherwise indicated, V_IN= 24 V, V_OUT= 5 V, I_OUT= 0.5 A, and F_SW= 1 MHz

EN (5 V/DIV)

VOUT (5 V/DIV)

PGOOD (5 V/DIV)

IOUT (500 mA/DIV)

V_OUT= 5 V

EN (5 V/DIV)

VOUT (5 V/DIV)

PGOOD (5 V/DIV)

IOUT (500 mA/DIV)

2 ms/DIV

V_IN= 24 V

V_OUT= 5 V

V_IN= 24 V

图10-3. Start-Up Waveforms

图10-4. Shutdown Waveforms

VOUT (50 mV/DIV)

VOUT (100 mV/DIV)

300 mA

Load Current (0.5 A/DIV)

Load Current (200 mA/DIV)

400 s/DIV

V_OUT= 3.3 V

400 s/DIV

V_OUT= 3.3 V

V_IN= 24 V

F_SW= 1 MHz

C_OUT= 2 × 22 µF

V_IN= 24 V

F_SW= 1 MHz

C_OUT= 2 × 22 µF

图10-5. Load Transient, 0 A to 0.6 A, 1 A/µs

图10-6. Load Transient, 0.3 A to 0.6 A, 1 A/µs

VOUT (50 mV/DIV)

VOUT (100 mV/DIV)

Load Current (200 mA/DIV)

300 mA

Load Current (0.5 A/DIV)

400 s/DIV

V_OUT= 5 V

400 s/DIV

V_IN= 24 V

V_OUT= 5 V

F _SW= 1 MHz

V_IN= 24 V

F_SW= 1 MHz

C_OUT= 2 × 22 µF

图10-8. Load Transient, 0.3 A to 0.6 A, 1 A/µs

图10-7. Load Transient, 0 A to 0.6 A, 1 A/µs

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图10-9. Thermal Image, V_IN= 24 V, V_OUT= 12 V, F_SW图10-10. Thermal Image, V_IN= 24 V, V_OUT= 5 V, F_SW

= 2.2 MHz, I_OUT= 0.6 A (Standard EVM and BOM)

= 1 MHz, I_OUT= 0.6 A (Standard EVM and BOM)

CISPR 11 Class B Conducted Emmissions

130

Class B QPk Limit

Class B Average Limit

Class B QPk Limit

Class B Average Limit

120

110

100

90

80

70

60

50

40

30

20

10

110

100

90

80

70

60

50

40

30

20

10

Qpk Amplitude

Average Amplitude

Qpk Amplitude

Average Amplitude

0.15

0.3 0.5 0.7

1

2

3

4 5 6 78 10

20 30

0.15

0.3 0.5 0.7

1

2

3

4 5 6 78 10

20 30

Frequency (MHz)

V_IN= 24 V

V_OUT= 5 V

f_SW= 1 MHz

Load = 500 mA

V_IN= 24 V

V_OUT= 5 V

f_SW= 1 MHz

Load = 500 mA

图10-11. Typical CISPR 11 Class B Conducted EMI 图10-12. Typical CISPR 11 Class B Conducted EMI

150 kHz - 30 MHz with EMI Filter (Standard EVM

Layout and BOM)

150 kHz - 30 MHz without EMI Filter (Standard EVM

Layout and BOM)

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CISPR 11 Class B QPk Radiated Emissions 3-Meter

60

55

50

45

40

35

30

25

20

15

10

5

Class B QPk Limit

Horizontal Amplitude

Vertical Amplitude

30 40 50 6070 100

200 300 400500 700 1000

Frequency (MHz)

V_IN= 24 V

V_OUT= 5 V

f_SW= 1 MHz

Load = 500 mA

图10-13. Typical CISPR 11 Class B Radiated EMI 30 kHz - 1000 MHz (Standard EVM Layout and BOM,

Input Filter Removed)

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10.3 Power Supply Recommendations

The TPSM365Rx buck module is designed to operate over a wide input voltage range of 3 V to 65 V. The

characteristics of the input supply must be compatible with the Absolute Maximum Ratings and Recommended

Operating Conditions in this data sheet. In addition, the input supply must be capable of delivering the required

input current to the loaded regulator circuit. Estimate the average input current with 方程式13.

V

× I

OUT

V

I

=

(13)

IN

× η

IN

where

• ηis the efficiency

If the module is connected to an input supply through long wires or PCB traces with a large impedance, take

special care to achieve stable performance. The parasitic inductance and resistance of the input cables can

have an adverse affect on module operation. More specifically, the parasitic inductance in combination with the

low-ESR ceramic input capacitors form an underdamped resonant circuit, possibly resulting in instability, voltage

transients, or both, each time the input supply is cycled ON and OFF. The parasitic resistance causes the input

voltage to dip during a load transient. If the module is operating close to the minimum input voltage, this dip can

cause false UVLO triggering and a system reset.

The best way to solve such issues is to reduce the distance from the input supply to the module and use an

electrolytic input capacitor in parallel with the ceramics. The moderate ESR of the electrolytic capacitor helps

damp the input resonant circuit and reduce any overshoot or undershoot at the input. A capacitance in the range

of 47 μF to 100 μF is usually sufficient to provide input parallel damping and helps hold the input voltage

steady during large load transients. A typical ESR of 0.1 Ω to 0.4 Ω provides enough damping for most input

circuit configurations.

10.4 Layout

The performance of any switching power supply depends as much upon the layout of the PCB as the component

selection. Use the following guidelines to design a PCB with the best power conversion performance, optimal

thermal performance, and minimal generation of unwanted EMI.

10.4.1 Layout Guidelines

The PCB layout of any DC/DC module is critical to the optimal performance of the design. Poor PCB layout can

disrupt the operation of an otherwise good schematic design. Even if the module regulates correctly, bad PCB

layout can mean the difference between a robust design and one that cannot be mass produced. Furthermore,

to a great extent, the EMI performance of the regulator is dependent on the PCB layout. In a buck converter

module, the most critical PCB feature is the loop formed by the input capacitor or capacitors and power ground,

as shown in 图 10-14. This loop carries large transient currents that can cause large transient voltages when

reacting with the trace inductance. These unwanted transient voltages disrupt the proper operation of the power

module. Because of this, the traces in this loop must be wide and short, and the loop area as small as possible

to reduce the parasitic inductance. 图 10-15 shows a recommended layout for the critical components of the

TPSM365Rx.

1. Place the input capacitors as close as possible to the VIN and GND terminals. VIN and GND pins are

adjacent, simplifying the input capacitor placement.

2. Place bypass capacitor for VCC close to the VCC pin. This capacitor must be placed close to the device and

routed with short, wide traces to the VCC and GND pins.

3. Place the feedback divider as close as possible to the FB pin of the device. Place R_FBB, R_FBT, and C_FF, if

used, physically close to the device. The connections to FB and GND must be short and close to those pins

on the device. The connection to V_OUTcan be somewhat longer. However, the latter trace must not be

routed near any noise source (such as the SW node) that can capacitively couple into the feedback path of

the regulator.

4. Use at least one ground plane in one of the middle layers. This plane acts as a noise shield and as a heat

dissipation path.

42

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5. Provide wide paths for VIN, VOUT, and GND. Making these paths as wide and direct as possible reduces

any voltage drops on the input or output paths of the power module and maximizes efficiency.

6. Provide enough PCB area for proper heat-sinking. Sufficient amount of copper area must be used to ensure

a low R_θJA, commensurate with the maximum load current and ambient temperature. The top and bottom

PCB layers must be made with two ounce copper and no less than one ounce. If the PCB design uses

multiple copper layers (recommended), these thermal vias can also be connected to the inner layer heat-

spreading ground planes.

7. Use multiple vias to connect the power planes to internal layers.

See the following PCB layout resources for additional important guidelines:

• Layout Guidelines for Switching Power Supplies Application Report

• Simple Switcher PCB Layout Guidelines Application Report

• Construction Your Power Supply- Layout Considerations Seminar

• Low Radiated EMI Layout Made Simple with LM4360x and LM4600x Application Report

VIN

C_IN

SW

GND

图10-14. Current Loops with Fast Edges

10.4.1.1 Ground and Thermal Considerations

As previously mentioned, TI recommends using one of the middle layers as a solid ground plane. A ground

plane provides shielding for sensitive circuits and traces as well as a quiet reference potential for the control

circuitry. Connect the GND pin to the ground planes using vias next to the bypass capacitors. The GND trace, as

well as the VIN and SW traces, must be constrained to one side of the ground planes. The other side of the

ground plane contains much less noise; use for sensitive routes.

TI recommends providing adequate device heat-sinking by having enough copper near the GND pin. See

图 10-15 for example layout. Use as much copper as possible, for system ground plane, on the top and bottom

layers for the best heat dissipation. Use a four-layer board with the copper thickness for the four layers, starting

from the top as: 2 oz / 1 oz / 1 oz / 2 oz. A four-layer board with enough copper thickness, and proper layout,

provides low current conduction impedance, proper shielding and lower thermal resistance.

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10.4.2 Layout Example

CVCC

RFBT

CFF

RFBB

GND

COUT

RT

VOUT

RPG

CIN

RENB

GND

RENT

CIN

VIN

图10-15. Example Layout

44

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11 Device and Documentation Support

11.1 Device Support

11.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.1.2 Device Nomenclature

图 11-1 shows the device naming nomenclature of the TPSM365Rx. See 节 6 for the availability of each variant.

Contact TI sales representatives or on TI's E2E forum for detail and availability of other options; minimum order

quantities apply.

TPSM365R X X X X RDNR

OUTPUT CURRENT MAX

3: 300 mA

F

_SWMODE OPTION

V

_OUTOPTION

SWITCHING METHOD

F: FPWM

PACKAGE

RDNR = QFN 11-pin large reel

V: MODE/SYNC Trim *: Adjustable

6: 600 mA

(Fixed Frequency

_SW= 1MHz)

3: 3.3-V Fixed

5: 5-V Fixed

F

* No alpha character * No numerical digit * No alpha character

means F_SWis set by

the RT pin

means adjustable

output

means FPWM is o

图11-1. Device Naming Nomenclature

11.1.3 Development Support

11.1.3.1 Custom Design With WEBENCH® Tools

To create a custom design using the TPSM365R3 device with the WEBENCH Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance.

• Run thermal simulations to understand board thermal performance.

• Export customized schematic and layout into popular CAD formats.

• Print PDF reports for the design, and share the design with colleagues.

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

11.2 Documentation Support

11.2.1 Related Documentation

For related documentation, see the following:

• Texas Instruments, Innovative DC/DC Power Modules selection guide

• Texas Instruments, Enabling Small, Cool and Quiet Power Modules with Enhanced HotRod™ QFN Package

Technology white paper

• Texas Instruments, Benefits and Trade-offs of Various Power-Module Package Options white paper

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• Texas Instruments, Simplify Low EMI Design with Power Modules white paper

• Texas Instruments, Power Modules for Lab Instrumentation white paper

• Texas Instruments, An Engineer's Guide To EMI In DC/DC Regulators e-book

• Texas Instruments, Soldering Considerations for Power Modules application report

• Texas Instruments, Practical Thermal Design With DC/DC Power Modules application report

• Texas Instruments, Using New Thermal Metrics application report

• Texas Instruments, Thermal Design by Insight not Hindsight application report

• Texas Instruments, A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages

application report

• Texas Instruments, Semiconductor and IC Package Thermal Metrics application report

• Texas Instruments, Thermal Design Made Simple with LM43603 and LM43602 application report

• Texas Instruments, PowerPAD^™Thermally Enhanced Package application report

• Texas Instruments, PowerPAD^™Made Easy application report

• Texas Instruments, Using New Thermal Metrics application report

• Texas Instruments, PCB Thermal Calculator

• Texas Instruments, Layout Guidelines for Switching Power Supplies application report

• Texas Instruments, Simple Switcher PCB Layout Guidelines application report

• Texas Instruments, Construction Your Power Supply- Layout Considerations Seminar

• Texas Instruments, Low Radiated EMI Layout Made Simple with LM4360x and LM4600x application report

• Texas Instruments, TPSM365R6EVM User's Guide

• Texas Instruments, AN-2020 Thermal Design By Insight, Not Hindsight application report

• Optimizing Transient Response of Internally Compensated DC-DC Converters with Feed forward Capacitor

application report

11.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

11.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

11.5 Trademarks

HotRod^™, PowerPAD^™, and TI E2E^™are trademarks of Texas Instruments.

所有商标均为其各自所有者的财产。

11.6 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

11.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

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12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OUTLINE

QFN-FCMOD - 2.1 mm max height

PLASTIC QUAD FLAT PACK- NO LEAD

RDN0011A

3.6

3.4

B

A

4.6

4.4

PIN 1 INDEX AREA

2.1

1.9

C

SEATING PLANE

0.05

0

0.08

C

SYMM

(0.2) TYP

(0.2)

8X (0.25)

1.15

1.05

2X

6X 0.5

2X 0.3

2.1

2

4

5

2X

PKG

0.35

6X

3

1

0.15

0.1

6

8

2X 0.65

2X 1.15

C

A B

0.05

C

1.4

1.3

2X 1.9

11

9

0.425

0.325

0.1

0.65

0.55

2X

1

0.8

0.4

0.2

4X

C A B

0.1

C

A

B

0.05

C

1.025

0.825

2X

0.05

C

2X 0.5

4226623/B 04/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

QFN-FCMOD - 2.1 mm max height

PLASTIC QUAD FLAT PACK- NO LEAD

RDN0011A

2X (1.125)

2X (0.5)

(0.3)

9

1

(2.23)

2X

(0.8)

2X (2.06)

11

2X

(0.37)

2X (1.96)

8

(1.69)

(1.48)

(1.52)

(1.23)

2X (1.15)

4X(0.65)

3

6

2X (0.2)

6X (0.25)

4X (1.1)

(0.23)

0.000 PKG

2X (0.3)

6X

(0.5)

2X (0.55)

2X (0.59)

(0.77)

2X

(2.05)

2X

(1.75)

4

5

2X (1.05)

8X

(0.25)

2X (1.41)

2X (1.55)

(1.77)

(Ø0.2)

TYP

(R0.05) TYP

(0.56)

(0.9)

2X (1.1)

(0.385) TYP

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 20X

0.05 MIN

ALL AROUND

0.05 MAX

ALL AROUND

METAL

SOLDER MASK

OPENING

EXPOSED METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

EXPOSED

METAL

NON- SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4226623/B 04/2022

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

QFN-FCMOD - 2.1 mm max height

PLASTIC QUAD FLAT PACK- NO LEAD

RDN0011A

2X (1.125)

2X (0.5)

(0.3)

11

9

8

1

2X

(0.8)

2X (2.06)

2X

(0.37)

2X (1.96)

(1.69)

(1.52)

4X (1.1)

2X (1.15)

(0.65)

6X (0.25)

2X (0.2)

4

5

0.000 PKG

2X (0.23)

2X (0.3)

8X

(0.25)

2X (2.05)

2X

(0.62)

2X (1)

2X (1.75)

6X (0.5)

4X

(0.51)

2X (1.77)

(R0.05) TYP

6X (0.93)

8X (0.375)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

PIN 4 & 5:

72% SOLDER COVERAGE BY AREA

SCALE: 20X

4226623/B 04/2022

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

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TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPSM365R6FRDNR
厂家：	TEXAS INSTRUMENTS
描述：	3-65V 输入 1-13V 输出 0.6A 同步降压转换器电源模块 \| RDN \| 11 \| -40 to 125 电源电路转换器
文件：	总55页 (文件大小：3831K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPSM365R6FRDNR [TI]

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