TPSM53603 [TI]

采用小型 5.5mm x 5mm x 4mm Enhanced HotRod™ QFN 封装、具有小尺寸的 36V、3A 降压电源模块;


型号：	TPSM53603
厂家：	TEXAS INSTRUMENTS
描述：	采用小型 5.5mm x 5mm x 4mm Enhanced HotRod™ QFN 封装、具有小尺寸的 36V、3A 降压电源模块电源电路
文件：	总35页 (文件大小：2394K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPSM53603

ZHCSKO1B –DECEMBER 2019 –REVISED SEPTEMBER 2021

TPSM53603 采用Enhanced HotRod™ QFN 封装的36V 输入、3A 电源模块

1 特性

3 说明

• 提供功能安全

TPSM53603 电源模块是一款高度集成的 3A 电源解决

方案，在热增强型 QFN 封装内整合了一个带有功率

MOSFET 的 36V 输入降压直流/直流转换器、一个屏

蔽式电感器和多个无源器件。此 5mm × 5.5mm ×

4mm、15 引脚封装采用增强型HotRod QFN 技术来实

现增强的热性能、小尺寸和低 EMI。该封装尺寸的所

有引脚均分布在外围，具有单个大散热垫，实现简单的

布局和制造中的轻松处理。

– 可帮助进行功能安全系统设计的文档

• 5mm × 5.5mm × 4mm 增强型HotRod^™QFN 封装

– 业界超小型36V、3A 外形尺寸：

85mm²解决方案尺寸（单面）

– 低EMI：符合CISPR11 辐射发射标准

– 优异的热性能：

在85°C 且无气流的情况下具有高达18W 的输

出功率

– 标准封装尺寸：单个大型散热焊盘和所有引脚均

分布在封装外围

总体解决方案仅需四个外部组件，并且省去了设计流程

中的环路补偿和磁性元件选择过程。TPSM53603 具有

全套功能集，包括正常电源状态指示、可编程UVLO、

预偏置启动、过流和过热保护，因此是为各种应用供电

的出色器件。

• 输入电压范围：3.8V 至36V

• 输出电压范围：1 V 至7 V

• 效率高达95%

• 电源正常状态标志

器件信息

器件型号⁽¹⁾

TPSM53603

封装尺寸（标称值）

封装

• 精密使能端

• 内置断续模式短路保护、过热保护、启动至预偏置

输出、软启动和UVLO

• IC 工作结温范围：–40°C 至+125°C

• 工作环境温度范围：-40°C 至+105°C

• 通过了Mil-STD-883D 冲击和振动测试

• 与以下器件引脚兼容：4A TPSM53604

和2A TPSM53602

B3QFN (15)

5.0mm × 5.5mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

• 下载EVM 设计文件以快速进行电路板设计

• 使用TPSM53603 并借助WEBENCH^®Power

Designer 创建定制设计方案

2 应用

增强型HotRod QFN 和典型布局

• 通用宽输入电压电源

• 工厂自动化和控制

• 测试和测量

• 航天和国防

• 负输出电压应用

100

PGOOD

V_IN

VIN

C_IN

V_OUT

VOUT

TPSM53603

C_OUT

R_FBT

V_OUT= 5 V

V5V

V_IN

12 V

24 V

R_FBB

PGND

AGND

0.5

1.5

Output Current (A)

2.5

EFF2

GND

5V_OUT效率

简化版原理图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNVSB77

TPSM53603

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ZHCSKO1B –DECEMBER 2019 –REVISED SEPTEMBER 2021

Table of Contents

8 Application and Implementation..................................20

8.1 Application Information............................................. 20

8.2 Typical Application.................................................... 20

9 Power Supply Recommendations................................22

10 Layout...........................................................................23

10.1 Layout Guidelines................................................... 23

10.2 Layout Examples.................................................... 23

10.3 Theta JA versus PCB Area.....................................24

10.4 Package Specifications...........................................25

10.5 EMI..........................................................................25

11 Device and Documentation Support..........................27

11.1 Device Support........................................................27

11.2 Documentation Support.......................................... 27

11.3 接收文档更新通知................................................... 27

11.4 支持资源..................................................................27

11.5 Trademarks............................................................. 27

11.6 静电放电警告...........................................................27

11.7 术语表..................................................................... 28

12 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................4

6.4 Thermal Information....................................................5

6.5 Electrical Characteristics.............................................5

6.6 Typical Characteristics (V_IN= 5 V)..............................7

6.7 Typical Characteristics (V_IN= 12 V)............................8

6.8 Typical Characteristics (V_IN= 24 V)............................9

6.9 Typical Characteristics (V_IN= 36 V)..........................10

7 Detailed Description......................................................11

7.1 Overview................................................................... 11

7.2 Functional Block Diagram......................................... 11

7.3 Feature Description...................................................12

7.4 Device Functional Modes..........................................19

Information.................................................................... 28

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision A (July 2020) to Revision B (September 2021)

Page

• 添加了功能安全项目符号.................................................................................................................................... 1

Changes from Revision * (December 2019) to Revision A (July 2020)

Page

• 将封装信息更新为正确的封装类型......................................................................................................................1

• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1

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5 Pin Configuration and Functions

VIN

V5V

AGND

DNC

PGND

DNC

PGOOD

VOUT

图5-1. 15-Pin QFN RDA Package (Top View)

表5-1. Pin Functions

TYPE

DESCRIPTION

NO.

NAME

Analog ground. Zero voltage reference for internal references and logic. All electrical parameters are

measured with respect to this pin. This pin must be connected to PGND at a single point. See 节10

for a recommended layout.

AGND

Do not connect. Do not connect these pins to ground, to another DNC pin, or to any other voltage. These

pins are connected to internal circuitry. Each pin must be soldered to an isolated pad.

4, 5

DNC

—

Enable pin. This pin turns the converter on when pulled high and turns off the converter when pulled low.

This pin can be connected directly to VIN. Do not float. This pin can be used to set the input under

voltage lockout with two resistors. See 节7.3.6.

Feedback input. Connect the mid-point of the feedback resistor divider to this pin. Connect the upper

resistor (R_FBT) of the feedback divider to V_OUTat the desired point of regulation. Connect the lower

resistor (R_FBB) of the feedback divider to AGND.

3, 10, 11

Not connected. These pins are not connected to any circuitry within the module. It is recommended that

these pins be connected to the PGND plane on the application board to enhance shielding and thermal

performance.

—

Power ground. This is the return current path for the power stage of the device. Connect this pad to the

input supply return, the load return, and the capacitors associated with the VIN and VOUT pins. See 节

10 for a recommended layout.

PGND

Power-good pin. Open-drain output that asserts low if the feedback voltage is not within the specified

window thresholds. A 10-kΩto 100-kΩpullup resistor is required and can be tied to the V5V pin or other

DC voltage less than 22 V. If not used, this pin can be left open or connected to PGND.

PGOOD

Input supply voltage. Connect the input supply to these pins. Connect input capacitors between these

pins and PGND in close proximity to the device.

1, 14

7, 8

VIN

VOUT

V5V

Output voltage. These pins are connected to the internal output inductor. Connect these pins to the

output load and connect external output capacitors between these pins and PGND.

Internal 5-V LDO output. Supplies internal control circuits. Do not connect to external loads. This pin can

be used as logic supply for PGOOD pin.

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6 Specifications

6.1 Absolute Maximum Ratings

Over the recommended operating junction temperature range⁽¹⁾

PARAMETER

MIN

–0.3

-0.3

MAX

UNIT

VIN to PGND

V_IN+ 0.3

EN to AGND⁽²⁾

Input voltage

PGOOD to AGND⁽²⁾

FB to AGND

5.5

AGND to PGND

VOUT to PGND⁽²⁾

0.3

V_IN+ 0.3

5.5

Output voltage

V5V to AGND

(3)

Operating IC junction temperature, T_J

Storage temperature, T_stg

150

°C

–40

–55

150

Peak reflow case temperature

Maximum number or reflows allowed

245

Mechanical vibration

Mechanical shock

Mil-STD-883D, Method 2007.2, 20 to 2000 Hz

Mil-STD-883D, Method 2002.3, 1 msec, 1/2 sine, mounted

500

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) The voltage on this pin must not exceed the voltage on the VIN pin by more than 0.3 V.

(3) The ambient temperature is the air temperature of the surrounding environment. The junction temperature is the temperature of the

internal power IC when the device is powered. Operating below the maximum ambient temperature, as shown in the safe operating

area (SOA) curves in the typical characteristics sections, ensures that the maximum junction temperature of any component inside the

module is never exceeded.

6.2 ESD Ratings

VALUE

±2500

±1000

UNIT

Human-body model (HBM)⁽¹⁾

V_(ESD)

Electrostatic discharge

Charged-device model (CDM)⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Over operating ambient temperature range (unless otherwise noted) ⁽¹⁾

MIN

MAX

UNIT

Input voltage, V_IN

3.8 ⁽³⁾

7 ⁽⁴⁾

Output voltage, V_OUT

Output current, I_OUT

(2)

EN voltage, V_EN

V_IN

(2)

PGOOD pullup voltage, V_PGOOD

PGOOD sink current

°C

µF

Operating ambient temperature, T_A

105

–40

(5)

Input capacitance, C_IN

Output capacitance, C_OUT

min ⁽⁶⁾

1000

(1) Recommended operating conditions indicate conditions for which the device is intended to be functional, but do not ensure specific

performance limits. For ensured specifications, see 节6.5.

(2) The voltage on this pin must not exceed the voltage on the VIN pin by more than 0.3 V.

(3) The recommended minimum V_INis 3.8 V or (VOUT + 1 V), whichever is greater. See the 节7.3.9 section for more information.

(4) The recommended maximum output voltage varies depending input voltage. See the 节7.3.9 section for more information.

(5) Minimum C_INof 20 µF must be ceramic type.

(6) The minimum amount of required output capacitance varies depending on the output voltage. See 表7-1.

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6.4 Thermal Information

TPSM53603

THERMAL METRIC⁽¹⁾

RDA (QFN)

15 PINS

19.5

UNIT

R_θJA

ψ_JT

Junction-to-ambient thermal resistance ⁽²⁾

°C/W

°C

Junction-to-top characterization parameter ⁽³⁾

Junction-to-board characterization parameter ⁽⁴⁾

Thermal shutdown temperature

1.0

5.5

ψ_JB

165

T_SHDN

Recovery temperaure

148

°C

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) The junction-to-ambient thermal resistance, R_θJA, applies to devices soldered directly to a 75-mm x 75-mm four-layer PCB with 2 oz.

copper and natural convection cooling. Additional airflow and PCB copper area reduces R_θJA. For more information see the 节10.3

section.

(3) The junction-to-top board characterization parameter, ψ_JT, estimates the junction temperature, T_J, of a device in a real system, using a

procedure described in JESD51-2A (section 6 and 7). T_J= ψ_JT× Pdis + T_T; where Pdis is the power dissipated in the device and T_Tis

the temperature of the top of the device.

(4) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature, T_J, of a device in a real system, using a

procedure described in JESD51-2A (sections 6 and 7). T_J= ψ_JB× Pdis + T_B; where Pdis is the power dissipated in the device and T_B

is the temperature of the board 1mm from the device.

6.5 Electrical Characteristics

Limits apply over T_A= –40°C to +105°C, V_IN= 12 V, V_OUT= 3.3 V, I_OUT= I_OUTmaximum, (unless otherwise noted); C_IN1

2x10 µF, 50-V, 1206 ceramic; C_IN2= 100 nF, 50-V, 0603 ceramic; C_OUT= 3x22 µF, 25-V, 1210 ceramic. Minimum and

maximum limits are specified through production test or by design. Typical values represent the most likely parametric norm

and are provided for reference only.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INPUT VOLTAGE (V_IN

)

Input voltage range

V_INturn on

Over I_OUTrange

3.8 ⁽¹⁾

V_IN

V_INincreasing, I_OUT= 0 A

V_INdecreasing, I_OUT= 0 A

Non-switching, V_FB= 1.2 V

V_EN= 0 V, I_OUT= 0 A

3.55

3.05

V_INturn off

I_Q

Quiescient current

Shutdown supply current

µA

I_SHDN

5.25

INTERNAL LDO (V5V)

Internal LDO output voltage appearing

at the V5V pin

V5V

4.75

6 V ≤V_IN≤36 V

FEEDBACK

Feedback voltage⁽²⁾

Load regulation

0.985

0.06

0.15

0.2

1.015

–40°C ≤T_J≤+125°C, I_OUT= 0.75 A

T_A= +25°C, 0.5 A ≤I_OUT≤3 A

T_A= +25°C, I_OUT= 0.75 A, Over V_INrange

FB = 1 V

V_FB

Line regulation

I_FB

Current into FB pin

CURRENT

I_OUT

Output current

T_A= 25°C

I_OUT

Over-current threshold

4.5

0.4

FB pin voltage required to trip short-

circuit hiccup mode

V_HC

t_HC

Time between current-limit hiccup burst

ENABLE (EN PIN)

EN input level required to turn on

internal LDO

V_EN-VCC-H

V_EN-VCC-L

Rising threshold

Falling threshold

EN input level required to turn off

internal LDO

0.3

1.2

V_EN-H

EN input level required to start switching Rising threshold

1.23

100

1.26

V_EN-HYS

Hysteresis below V_EN-H

Falling

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Limits apply over T_A= –40°C to +105°C, V_IN= 12 V, V_OUT= 3.3 V, I_OUT= I_OUTmaximum, (unless otherwise noted); C_IN1

2x10 µF, 50-V, 1206 ceramic; C_IN2= 100 nF, 50-V, 0603 ceramic; C_OUT= 3x22 µF, 25-V, 1210 ceramic. Minimum and

maximum limits are specified through production test or by design. Typical values represent the most likely parametric norm

and are provided for reference only.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I_LKG-EN

Enable input leakage current

V_EN= 3.3 V

0.2

POWER GOOD (PGOOD PIN)

V_PG-HIGH-UP

V_PG-HIGH-DN

V_PG-LOW-UP

V_PG-LOW-DN

R_PG

V_OUTrising (fault)

V_OUTfalling (good)

V_OUTrising (good)

V_OUTfalling (fault)

Power-good flag R_DSON

% of FB voltage

V_EN= 0 V

107

105

Ω

Minimum input voltage for proper

PGOOD function

V_IN-PG

V_PG

50-µA, EN = 0 V

PGOOD logic low output

50-µA, EN = 0 V, V_IN= 2 V

0.2

PERFORMANCE

Efficiency

I_OUT= 2 A, T_A= 25°C

SOFT START

t_SS

Internal soft-start time

SWITCHING FREQUENCY

Max switching frequency

I_OUT= 2 A, T_A= 25°C

1.4⁽³⁾

MHz

ƒ_SW-MAX

(1) The recommended minimum V_INis 3.8 V or (VOUT + 1 V), whichever is greater. See Voltage Dropout for more information.

(2) The overall output voltage tolerance will be affected by the tolerance of the external R_FBTand R_FBBresistors.

(3) The typical switching frequency of this device will change based on operating conditions. See the 节7.4.2 section for more information.

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6.6 Typical Characteristics (V_IN= 5 V)

The typical characteristic data has been developed from actual products tested at T_A= 25°C. This data is

considered typical for the device.

100

V_OUT

3.3 V

2.5 V

1.8 V

1.0 V

V_OUT

3.3 V

2.5 V

1.8 V

1.0 V

0.5

1.5

Output Current (A)

2.5

0.001

0.01

0.1

Output Current (A)

D001

D002

V_IN= 5 V

Linear Scale

V_IN= 5 V

Log Scale

图6-1. Efficiency versus Output Current

图6-2. Efficiency versus Output Current

1.5

V_OUT

3.3 V

2.5 V

1.8 V

1.0 V

V_OUT

3.3 V

2.5 V

1.8 V

1.0 V

1.2

0.9

0.6

0.3

0.0

0.5

1.5

Output Current (A)

2.5

0.5

1.5

Output Current (A)

2.5

D003

D004

V_IN= 5 V

C_OUT= 4x 47µF

图6-3. Power Dissipation versus Output Current

图6-4. Voltage Ripple versus Output Current

115

105

115

105

Airflow

200LFM

100LFM

Nat conv

Airflow

Nat conv

0.5

1.5

Output Current (A)

2.5

0.5

1.5

Output Current (A)

2.5

D005

D006

V_IN= 5 V

V_OUT= 3.3 V

_OUT≤2.5 V

PCB = 85 mm × 65 mm, 4-layer, 2 oz. copper

图6-6. Safe Operating Area

图6-5. Safe Operating Area

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6.7 Typical Characteristics (V_IN= 12 V)

The typical characteristic data has been developed from actual products tested at T_A= 25°C. This data is

considered typical for the device.

100

V_OUT

7.0 V

V_OUT

7.0 V

5.0 V

3.3 V

2.5 V

1.8 V

1.0 V

5.0 V

3.3 V

2.5 V

1.8 V

1.0 V

0.5

1.5

Output Current (A)

2.5

0.001

0.01

0.1

Output Current (A)

D007

D008

V_IN= 12 V

Linear Scale

V_IN= 12 V

Log Scale

图6-7. Efficiency versus Output Current

图6-8. Efficiency versus Output Current

1.8

V_OUT

7.0 V

5.0 V

3.3 V

2.5 V

1.8 V

V_OUT

7.0 V

5.0 V

3.3 V

2.5 V

1.8 V

1.0 V

1.5

1.2

1.0 V

0.9

0.6

0.3

0.0

0.5

1.5

Output Current (A)

2.5

0.5

1.5

Output Current (A)

2.5

D009

D010

V_IN= 12 V

C_OUT= 4x 47µF

图6-9. Power Dissipation versus Output Current

图6-10. Voltage Ripple versus Output Current

115

105

115

105

Airflow

400LFM

200LFM

Airflow

Nat conv

100LFM

Nat conv

0.5

1.5

Output Current (A)

2.5

0.5

1.5

Output Current (A)

2.5

D011

D012

V_IN= 12 V

V_OUT= 1.8 V

V_IN= 12 V

V_OUT= 5 V

PCB = 85 mm × 65 mm, 4-layer, 2 oz. copper

图6-11. Safe Operating Area

图6-12. Safe Operating Area

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6.8 Typical Characteristics (V_IN= 24 V)

The typical characteristic data has been developed from actual products tested at T_A= 25°C. This data is

considered typical for the device.

100

V_OUT

7.0 V

5.0 V

3.3 V

2.5 V

1.8 V

V_OUT

7.0 V

5.0 V

3.3 V

2.5 V

1.8 V

0.5

1.5

Output Current (A)

2.5

0.001

0.01

0.1

Output Current (A)

D013

D014

V_IN= 24 V

图6-13. Efficiency versus Output Current

图6-14. Efficiency versus Output Current

2.4

V_OUT

7.0 V

5.0 V

3.3 V

2.5 V

1.8 V

7.0 V

5.0 V

3.3 V

2.5 V

1.8 V

2.1

1.8

1.5

1.2

0.9

0.6

0.3

0.0

0.5

1.5

Output Current (A)

2.5

0.5

1.5

Output Current (A)

2.5

D015

D016

V_IN= 24 V

C_OUT= 4x 47µF

图6-15. Power Dissipation versus Output Current

图6-16. Voltage Ripple versus Output Current

115

105

115

105

Airflow

400LFM

200LFM

400LFM

200LFM

100LFM

Nat conv

100LFM

Nat conv

0.5

1.5

Output Current (A)

2.5

0.5

1.5

Output Current (A)

2.5

D017

D018

V_IN= 24 V

V_OUT= 1.8 V

V_IN= 24 V

V_OUT= 5 V

PCB = 85 mm × 65 mm, 4-layer, 2 oz. copper

图6-17. Safe Operating Area

图6-18. Safe Operating Area

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6.9 Typical Characteristics (V_IN= 36 V)

The typical characteristic data has been developed from actual products tested at T_A= 25°C. This data is

considered typical for the device.

100

V_OUT

7.0 V

5.0 V

3.3 V

2.5 V

V_OUT

7.0 V

5.0 V

3.3 V

2.5 V

0.5

1.5

Output Current (A)

2.5

0.001

0.01

0.1

Output Current (A)

D019

D020

V_IN= 36 V

图6-19. Efficiency versus Output Current

图6-20. Efficiency versus Output Current

3.2

V_OUT

7.0 V

5.0 V

3.3 V

2.5 V

7.0 V

2.8

2.4

2.0

1.6

1.2

0.8

0.4

0.0

5.0 V

3.3 V

2.5 V

0.5

1.5

Output Current (A)

2.5

0.5

1.5

Output Current (A)

2.5

D021

D022

V_IN= 36 V

C_OUT= 4x 47µF

图6-21. Power Dissipation versus Output Current

图6-22. Voltage Ripple versus Output Current

115

105

115

105

Airflow

400LFM

200LFM

400LFM

200LFM

100LFM

Nat conv

100LFM

Nat conv

0.5

1.5

Output Current (A)

2.5

0.5

1.5

Output Current (A)

2.5

D023

D024

V_IN= 36 V

V_OUT= 1.8 V

V_IN= 36 V

V_OUT= 5 V

PCB = 85 mm × 65 mm, 4-layer, 2 oz. copper

图6-23. Safe Operating Area

图6-24. Safe Operating Area

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7 Detailed Description

7.1 Overview

The TPSM53603 is a full-featured, 36-V input, 3-A, synchronous step-down converter with PWM, MOSFETs,

shielded inductor, and control circuitry integrated into a low-profile, over-molded package. The device integration

enables small designs while providing the ability to adjust key parameters to meet specific design requirements.

The TPSM53603 provides an output voltage range of 1 V to 7 V. An external resistor divider is used to adjust the

output voltage to the desired value. The device provides accurate voltage regulation over a wide load range by

using a precision internal voltage reference. Input undervoltage lockout is internally set at 3.55 V (typical), but

can be adjusted upward using a resistor divider on the EN pin of the device. The EN pin can also be pulled low

to put the device into standby mode to reduce input current draw. A power-good signal is provided to indicate

when the output is within its nominal voltage range. Thermal shutdown and current limit features protect the

device during an overload condition. A 15-pin, QFN package that includes exposed bottom pads provides a

thermally enhanced solution for space-constrained applications.

7.2 Functional Block Diagram

Thermal

Shutdown

UVLO

LDO

V5V

VIN

Shutdown

Logic

Enable

Logic

OCP

PGOOD

Logic

Power

Stage

and

2.2 µH

Oscillator

VOUT

Control

Logic

Soft Start

Comp

VREF

AGND

PGND

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7.3 Feature Description

7.3.1 Adjusting the Output Voltage

A resistor divider connected to the FB pin (pin 9) sets the output voltage of the TPSM53603. The output voltage

adjustment range is from 1 V to 7 V. 图 7-1 shows the feedback resistor connections for setting the output

voltage. The recommended value of R_FBTis 10 kΩ. The value for R_FBBcan be calculated using 方程式 1. 表7-1

lists the standard resistor values for several output voltages. The minimum required output capacitance for each

output voltage is also included in 表 7-1. The capacitance values listed represent the effective capacitance,

taking into account the effects of DC bias and temperature variation.

(kꢀ)

R_FBB

(V_OUTœ 1)

(1)

VOUT

R_FBT

10kꢀ

R_FBB

AGND

图7-1. Setting the Output Voltage

表7-1. Setting the Output Voltage

C_OUT(MIN)(µF)

(EFFECTIVE)

C_OUT(MIN)(µF)

(EFFECTIVE)

R_FBB(kΩ)⁽¹⁾

V_OUT(V)

1.0

1.1

1.2

1.3

1.4

1.5

1.8

2.0

2.5

open

100

150

140

128

117

108

101

3.0

3.3

4.0

4.5

5.0

5.5

6.0

6.5

7.0

4.99

4.32

3.32

2.87

2.49

2.21

2.00

1.82

1.65

49.9

33.2

24.9

20.0

12.4

10.0

6.65

(1) R_FBT= 10.0 kΩ

7.3.2 Switching Frequency

The switching frequency of the TPSM53603 is set to 1.4 MHz, internal to the device. The switching frequency

cannot be adjusted. When the load current is high enough and the device is operating in PWM mode, the device

operates at a fixed frequency. As the load current drops and the device switches to PFM mode, the switching

frequency is reduced, resulting in reduced power dissipation. See 节 7.4.2 for typical information on when the

device switches from PWM mode to PFM mode.

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7.3.3 Input Capacitors

The TPSM53603 requires a minimum input capacitance of 20 μF (2 × 10 μF) of ceramic type. High-quality,

ceramic-type X5R or X7R capacitors with sufficient voltage rating are recommended. TI recommends an

additional 47 µF of non-ceramic capacitance for applications with transient load requirements. The voltage rating

of input capacitors must be greater than the maximum input voltage.

表7-2. Recommended Input Capacitors

CAPACITOR CHARACTERISTICS

VENDOR⁽¹⁾

SERIES

SIZE

PART NUMBER

VOLTAGE RATING

(V)

CAPACITANCE ⁽³⁾

(µF)

Murata

X5R

X7R

1206

1210

GRT31CR61H106ME01L

CGA5L3X5R1H106M160AB

CGA5L1X7R1H106K160AC

GRM32ER71H106KA12L

C3225X7R1H106M250AC

TDK

Murata

TDK

(1) Capacitor Supplier Verification, RoHS, Lead-free, and Material Details

Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process

requirements for any capacitors identified in this table.

(2) Maximum ESR at 100 kHz, 25°C.

(3) Standard capacitance values

7.3.4 Output Capacitors

表7-1 lists the TPSM53603 minimum output capacitance. The effects of DC bias and temperature variation must

be considered when using ceramic capacitance. For ceramic capacitors, the package size, voltage rating, and

dielectric material contribute to differences between the standard rated value and the actual effective value of the

capacitance.

When adding additional capacitance above C_OUT(min), the capacitance can be ceramic type, low-ESR polymer

type, or a combination of the two. See 表7-3 for a preferred list of output capacitors by vendor.

表7-3. Recommended Output Capacitors

CAPACITOR CHARACTERISTICS

VENDOR⁽¹⁾

SERIES

PART NUMBER

ESR⁽²⁾

(mΩ)

VOLTAGE RATING

(V)

CAPACITANCE ⁽²⁾

(µF)

TDK

X5R

X7R

C3225X5R0J476K

6.3

Murata

GCM32ER70J476KE19L

GRM21BR61A476ME15L

C3216X5R1A476M160AB

GRM32ER71A476KE15L

GRM32ER61C476K

C3225X5R0J107M

GRM32ER60J107M

GRM32ER61A107M

C1210C107M4PAC7800

6TPE100MI

Murata

X5R

TDK

X5R

Murata

X7R

Murata

X5R

TDK

X5R

6.3

100

150

220

330

470

Murata

X5R

Murata

X5R

Kemet

X5R

Panasonic

POSCAP

6.3

10TPF150ML

6TPF220M9L

6.3

6TPF330M9L

6TPE470MAZU

(1) Capacitor Supplier Verification, RoHS, Lead-free and Material Details

Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process

requirements for any capacitors identified in this table.

(2) Standard capacitance values.

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7.3.5 Output On/Off Enable (EN)

The voltage on the EN pin provides electrical ON/OFF control of the device. This input features precision

thresholds, allowing the use of an external voltage divider to provide a programmable UVLO (see 节 7.3.6).

Applying a voltage of V_EN≥ V_{EN-LDO_H}causes the device to enter standby mode, powering the internal LDO,

but not producing an output voltage. Increasing the EN voltage to V_EN-Hfully enables the device, allowing it to

enter start-up mode and begin the soft-start period. When the EN input is brought below V_EN-Hby V_EN-HYS, the

regulator stops running and enters standby mode. Further decrease in the EN voltage to below V_EN-LDO-L

completely shuts down the device. 图 7-2 shows this behavior. The values for the various EN thresholds can be

found in 节6.5.

V_EN-H

V_EN-Hœ V_EN-HYS

V_EN-LDO-H

V_EN-LDO-L

V5V

VOUT

V_OUT

图7-2. Precision Enable Behavior

The EN pin cannot be open circuit or floating. The simplest way to enable the operation of the TPSM53603 is to

connect the EN pin to VIN directly as shown in 图 7-3. This allows self start-up of the TPSM53603 when VIN is

within the operation range.

If an application requires controlling the EN pin, an external logic signal can be used to drive the EN pin as

shown in 图 7-4. Applications using an open-drain/collector device to interface with this pin require a pullup

resistor to a voltage above the enable threshold.

V_IN

VIN

PGND

图7-4. Typical Enable Control

图7-3. Enabling the Device

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7.3.6 Programmable Undervoltage Lockout (UVLO)

The TPSM53603 implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin

voltage falls below the internal VIN UVLO threshold. The internal VIN UVLO rising threshold is 3.55 V (typical)

with a typical hysteresis of 500 mV.

If an application requires a higher UVLO threshold, a resistor divider can be placed between VIN, the EN pin,

and AGND as shown in 图 7-5. The enable rising threshold (V_EN-H) is 1.23 V (typ) with 100 mV (typ) hysteresis.

表7-4 lists recommended resistor values for R_ENTand R_ENBto adjust the ULVO voltage.

To ensure proper start-up and reduce input current surges, TI recommends to set the UVLO threshold to

approximately 80% to 85% of the minimum expected input voltage.

V_IN

VIN

R_ENT

R_ENB

AGND

图7-5. Adjustable UVLO

表7-4. Resistor Values for Adjusting UVLO

VIN UVLO (V)

R_ENT(kΩ)

6.5

100

23.7

100

14.3

100

9.09

100

6.65

100

5.23

100

4.32

R_ENB(kΩ)

7.3.7 Power Good (PGOOD)

The TPSM53603 has a built-in power-good signal (PGOOD) which indicates whether the output voltage is within

its regulation range. The PGOOD pin is an open-drain output that requires a pullup resistor to a nominal voltage

source of 18 V or less. The internal 5-V LDO output (V5V pin) can be used as the pullup voltage source. A

typical pullup resistor value is between 10 kΩ and 100 kΩ. The maximum recommended PGOOD sink current

is 3 mA.

Once the output voltage rises above 94% of the set voltage, the PGOOD pin rises to the pullup voltage level.

The PGOOD pin is pulled low when the output voltage drops lower than 92% or rises higher than 107% of the

nominal set voltage. See 图7-6 for typical power-good thresholds.

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V_FB

107%

105%

94%

92%

PGOOD

High

Low

图7-6. Power-good Flag

7.3.8 Light Load Operation

In light load conditions, the device turns on the high-side MOSFET until the inductor current reaches a controlled

minimum value of approximately 1 A. As the input voltage decreases, reducing the voltage headroom between

V_INand V_OUT, the amount of time required to reach this minimum current increases. During this time, additional

energy flows from V_INto V_OUT, resulting in increased output voltage ripple. To eliminate this behavior, the EN

UVLO function must be used to maintain at least 1 V of headroom above V_OUT. Alternatively, additional output

capacitance can be added to reduce the output voltage ripple in applications that operate at light loads with very

low V_INto V_OUTheadroom.

7.3.9 Voltage Dropout

Voltage dropout is the difference between the input voltage and output voltage that is required to maintain output

voltage regulation while providing the rated output current.

To ensure the TPSM53603 maintains output voltage regulation over the operating temperature range, the

minimum V_INis 3.8 V or (V_OUT+ 1 V), whichever is greater.

The TPSM53603 operates in a frequency foldback mode when the dropout voltage is less than the

recommendation above. Frequency foldback reduces the switching frequency to allow the output voltage to

maintain regulation as input voltage decreases. At light load, the TPSM53603 operates in PFM mode, which is a

reduced frequency operation. See 节 7.4.2 for more information on PFM mode. 图 7-7 through 图 7-12 show

typical dropout voltage and frequency foldback curves for 3.3 V, 5 V, and 7 V outputs at T_A= 25°C.

Note

As ambient temperature increases, dropout voltage and frequency foldback occur at higher input

voltage.

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3.6

1500

1400

1300

1200

1100

1000

900

I_OUT

2 A

3 A

3.5

3.4

3.3

3.2

3.1

0 A

1.5 A

3 A

2.9

2.8

2.7

2.6

2.5

2.4

2.3

800

700

600

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

3.5

3.6

3.7

3.8

3.9

4.1

4.2

4.3

Input Voltage (V)

D041

Input Voltage (V)

D044

V_OUT= 3.3 V

图7-7. Voltage Dropout

图7-8. Frequency Foldback

5.2

5.1

1500

1400

1300

1200

1100

1000

900

I_OUT

2 A

3 A

0 A

1.5 A

3 A

4.9

4.8

4.7

4.6

4.5

4.4

4.3

4.2

4.1

800

700

3.9

600

3.8

5.4

5.5

5.6

5.7

5.8

5.9

4.5

4.6

4.7

4.8

4.9

5.1

5.2

5.3

5.4

5.5

5.6

Input Voltage (V)

D045

Input Voltage (V)

D042

V_OUT= 5 V

图7-10. Frequency Foldback

图7-9. Voltage Dropout

7.2

7.1

1500

1400

1300

1200

1100

1000

900

I_OUT

2 A

3 A

0 A

1.5 A

3 A

6.9

6.8

6.7

6.6

6.5

6.4

6.3

6.2

6.1

800

5.9

5.8

5.7

700

600

7.6

7.65

7.7

7.75

7.8

7.85

7.9

7.95

6.5

6.6

6.7

6.8

6.9

7.1

7.2

7.3

7.4

7.5

7.6

7.7

Input Voltage (V)

D046

Input Voltage (V)

D043

V_OUT= 7 V

图7-12. Frequency Foldback

图7-11. Voltage Dropout

7.3.10 Overcurrent Protection (OCP)

The TPSM53603 is protected from overcurrent conditions. Cycle-by-cycle current limit is used for overloads

while hiccup mode is used for short circuits. Hiccup mode is activated if a fault condition persists on the output.

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Hiccup mode reduces power dissipation under severe overcurrent conditions and prevents overheating and

potential damage to the device. In hiccup mode, the regulator is shut down and kept off for 94 ms typical before

the TPSM53603 tries to start again. If overcurrent or short-circuit fault condition still exist, hiccup repeats until the

fault condition is removed. Once the fault is removed, the module automatically recovers with a normal soft-start

power up.

The typical current limit threshold for the TPSM53603 varies slightly as a function of input voltage and output

voltage. 图7-13 shows the typical current limit threshold for several output voltages over the input voltage range.

5.1

4.8

4.5

4.2

3.9

3.6

V_OUT

1 V

1.8 V

3.3

3.3 V

5 V

7 V

3.0

Input Voltage (V)

D024

图7-13. Current Limit Threshold

7.3.11 Thermal Shutdown

The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds

165°C typically. The device reinitiates the power-up sequence when the junction temperature drops below 148°C

typically.

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7.4 Device Functional Modes

7.4.1 Active Mode

The TPSM53603 is in active mode when VIN is above the turnon threshold and the EN pin voltage is above the

EN high threshold. The most direct way to enable the TPSM53603 is to connect the EN pin to VIN. This allows

self start-up of the TPSM53603 when the input voltage is in the operation range of 3.8 V to 36 V. Connecting a

resistor divider between VIN, EN, and AGND adjusts the UVLO to delay the turn on until V_INis closer to its

regulated voltage.

7.4.2 Auto Mode

In auto mode, the device moves between Pulse-Width Modulation (PWM) and Pulse-Frequency Modulation

(PFM) as the load changes. At light loads, the regulator operates in PFM mode. At higher loads, the mode

changes to PWM mode. The typical load current for which the device moves from PFM to PWM can be found in

图 7-14 and 图 7-15. The output current at which the device changes modes depends on the input voltage and

the output voltage. For output currents above the curve, the device is in PWM mode. If the curve is a solid line,

the PWM switching frequency is 1.4 MHz nominal. If the curve is a dashed line, the PWM switching frequency is

reduced due to the minimum on-time of the internal controller to maintain output voltage regulation. For currents

below the curves, the device is in PFM mode. For applications where the switching frequency must be known for

a given condition, the above mentioned effects must be carefully tested before the design is finalized.

In PWM mode, the regulator operates at a constant frequency using PWM to regulate the output voltage. While

operating in this mode, the output voltage is regulated by switching at a constant frequency and modulating the

duty cycle to control the power to the load. This provides excellent line and load regulation and low output

voltage ripple.

In PFM mode, the high-side MOSFET is turned on in a burst of one or more pulses to provide energy to the load.

The duration of the burst and the actual switching frequency depends on the input voltage, output voltage, and

load current. The frequency of these bursts is adjusted to regulate the output while diode emulation is used to

maximize efficiency. This mode provides high light-load efficiency by reducing the amount of input supply current

required to regulate the output voltage at small loads. However, in this mode, expect larger output voltage ripple

and variable switching frequency.

图7-15. PFM/PWM Thresholds (1 V and 1.8 V)

图7-14. PFM/PWM Thresholds (3.3 V, 5 V, and 7 V)

7.4.3 Shutdown Mode

The EN pin provides electrical ON and OFF control for the TPSM53603. When the EN pin voltage is below the

EN low threshold, the device is in shutdown mode. In shutdown mode, the standby current is 5 μA typical.

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8 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

8.1 Application Information

The TPSM53603 is a synchronous, step-down, DC/DC power module. It is used to convert a higher DC voltage

to a lower DC voltage with a maximum output current of 3 A. The TPSM53603 can be configured in a negative

output voltage, inverting buck-boost (IBB) topology. For more details, see the Negative Output Voltage using the

TPSM53602/3/4 application note. The following design procedure can be used to select components for the

TPSM53603. Alternately, the WEBENCH^®software can be used to generate complete designs. When

generating a design, the WEBENCH^®software uses an iterative design procedure and accesses comprehensive

databases of components. See www.ti.com for more details.

8.2 Typical Application

The TPSM53603 only requires a few external components to convert from a wide input voltage supply range to a

wide range of output voltages. 图8-1 shows a basic TPSM53603 schematic for a typical design.

V5V

100 kO

V_IN= 24 V

PGOOD

VOUT

VIN

V_OUT= 5 V

10 µF

50 V

10 µF

50 V

TPSM53603

10 kO

47 µF

10 V

47 µF

10 V

100 kO

PGND

AGND

2.49 kO

图8-1. TPSM53603 Typical Schematic

8.2.1 Design Requirements

For this design example, use the parameters listed in 表 8-1 as the input parameters and follow the design

procedures in 节8.2.2.

表8-1. Design Example Parameters

DESIGN PARAMETER

VALUE

24 V typical

5 V

Input voltage V_IN

Output voltage V_OUT

Output current rating

3 A

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8.2.2 Detailed Design Procedure

8.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the TPSM53603 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

8.2.2.2 Output Voltage Setpoint

The output voltage of the TPSM53603 device is externally adjustable using a resistor divider. The recommended

value of R_FBTis 10 kΩ. The value for R_FBBcan be selected from 表7-1 or calculated using 方程式2:

(kꢀ)

R_FBB

(V_OUTœ 1)

(2)

For the desired output voltage of 5 V, the formula yields a value of 2.5 kΩ. Choose the closest available value of

2.49 kΩfor R_FBB

8.2.2.3 Input Capacitors

The TPSM53603 requires a minimum input capacitance of 20 µF (or 2 × 10 μF) ceramic type. High-quality

ceramic type X5R or X7R capacitors with sufficient voltage rating are recommended. An additional 47 µF of non-

ceramic capacitance is recommended for applications with transient load requirements. The voltage rating of the

input capacitors must be greater than the maximum input voltage.

For this design example, two 10-µF, 50-V, ceramic capacitors are used.

8.2.2.4 Output Capacitor Selection

The TPSM53603 requires a minimum amount of output capacitance for proper operation. The minimum amount

of required output varies depending on the output voltage. See 表7-1 for the required output capacitance.

For this design example, two 47-µF, 10-V, ceramic capacitors are used.

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8.2.3 Application Curves

V_IN

V_OUT

PGOOD

V_IN= 24 V

V_OUT= 5 V

C_OUT= 2 × 47 µF

V_IN= 24 V

V_OUT= 5 V

C_OUT= 2 × 47 µF

图8-3. Enable Turn-OFF

图8-2. Enable Turn-ON

V_OUT

I_OUT

V_IN= 24 V

V_OUT= 5 V

C_OUT= 2 × 47 µF

I_OUT= 0.75 A to 2.25 A

Slew rate: 1 A/µs

图8-4. Transient Response

9 Power Supply Recommendations

The TPSM53603 is designed to operate from an input voltage supply range between 3.8 V and 36 V. This input

supply must be well-regulated and able to withstand maximum input current and maintain a stable voltage. The

resistance of the input supply rail must be low enough that an input current transient does not cause a high

enough drop at the TPSM53603 supply voltage that can cause a false UVLO fault triggering and system reset.

If the input supply is located more than a few centimeters from the TPSM53603, additional bulk capacitance can

be required in addition to the ceramic bypass capacitors. The typical amount of bulk capacitance is a 47-µF

electrolytic capacitor.

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10 Layout

The performance of any switching power supply depends as much upon the layout of the PCB as the component

selection. The following guidelines help users design a PCB with the best power conversion performance,

optimal thermal performance, and minimized generation of unwanted EMI.

10.1 Layout Guidelines

To achieve optimal electrical and thermal performance, an optimized PCB layout is required. 图 10-1 through 图

10-3 show a typical PCB layout. The following are some considerations for an optimized layout.

• Use large copper areas for power planes (VIN, VOUT, and PGND) to minimize conduction loss and thermal

stress.

• Place ceramic input and output capacitors close to the device pins to minimize high frequency noise.

• Locate additional output capacitors between the ceramic capacitor and the load.

• Connect AGND to PGND at a single point.

• Place R_FBTand R_FBBas close as possible to the FB pin.

• Use multiple vias to connect the power planes to internal layers.

• Download the EVM Design Files for fast board design

10.2 Layout Examples

图10-1. Typical Top-Layer Layout

图10-2. Typical Layer-2 Layout

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图10-3. Typical PGND Layer

10.3 Theta JA versus PCB Area

The amount of PCB copper affects the thermal performance of the device. 图 10-4 shows the effects of copper

area on the junction-to-ambient thermal resistance (R_θJA) of the TPSM53603. The junction-to-ambient thermal

resistance is plotted for a 4-layer PCB with PCB area from 30 cm²to 80 cm².

To determine the required copper area for an application:

1. Determine the maximum power dissipation of the device in the application by referencing the power

dissipation graphs in 节6.6 through 节6.9.

2. Calculate the maximum R_θJAusing 方程式3 and the maximum ambient temperature of the application.

(

125èC - T_A(max))

R_qJA

(èC / W)

D(max)

(3)

3. Reference 图10-4 to determine the minimum required PCB area for the application conditions.

4-layer PCB

PCB Area (cm²)

D047

图10-4. R_θJAversus PCB Area (per Layer)

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10.4 Package Specifications

TPSM53603

VALUE

UNIT

Weight

429

Flammability

Meets UL 94 V-O

MTBF Calculated Reliability

Per Bellcore TR-332, 50% stress, T_A= 40°C, ground benign

89.3

MHrs

10.5 EMI

The TPSM53603 is compliant with EN55011 Class-B radiated emissions. 图 10-5 and 图 10-6 show typical

examples of radiated emissions plots for the TPSM53603. The graphs include the plots of the antenna in the

horizontal and vertical positions.

EMI plots were measured using the standard TPSM53603EVM with no input filter.

图10-5. Radiated Emissions 24-V Input, 5-V Output, 3-A Load

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图10-6. Radiated Emissions 12-V Input, 5-V Output, 3-A Load

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11 Device and Documentation Support

11.1 Device Support

11.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此

类产品或服务单独或与任何TI 产品或服务一起的表示或认可。

11.1.2 Development Support

11.1.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the TPSM53603 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

11.2 Documentation Support

11.2.1 Related Documentation

For related documentation see the following:

• Texas Instruments, Negative Output Voltage using the TPSM53602/3/4 application report

11.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.4 支持资源

TI E2E^™中文支持论坛是工程师的重要参考资料，可直接从专家处获得快速、经过验证的解答和设计帮助。搜索

现有解答或提出自己的问题，获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的使用条款。

11.5 Trademarks

HotRod^™and TI E2E^™are trademarks of Texas Instruments.

are registered trademarks of Texas Instruments.

所有商标均为其各自所有者的财产。

11.6 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

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11.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

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14-Sep-2021

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPSM53603RDAR

ACTIVE

B3QFN

RDA

1000 RoHS & Green

NIPDAU

Level-3-245C-168 HR

-40 to 125

TPSM53603

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Sep-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPSM53603RDAR

B3QFN

RDA

1000

330.0

16.4

5.28

5.78

4.28

8.0

16.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Sep-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

B3QFN RDA 15

SPQ

Length (mm) Width (mm) Height (mm)

336.0 336.0 48.0

TPSM53603RDAR

1000

Pack Materials-Page 2

PACKAGE OUTLINE

RDA0015A

B3QFN - 4.1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

5.1

4.9

PIN 1 INDEX AREA

5.6

5.4

4.1 MAX

0.08 C

SEATING PLANE

2.5 0.05

PKG

0.45

0.25

0.1

1.5 0.05

10X

C A B

1.3

1.1

(0.16) TYP

0.05

2X 0.725

2.6 TYP

1.43

PKG

4.6 0.05

2.5 0.05

8X 0.65

2X 0.975

0.6

0.4

0.6

0.4

10X

0.1

C A B

1.3

1.1

0.05

PIN 1 ID

4224086/C 03/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

RDA0015A

B3QFN - 4.1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(2.5)

(1.5)

4X (1.4)

PKG

4X (0.5)

2X (0.975)

10X (0.7)

10X (0.35)

(4.6)

PKG

(1)

TYP

(2.5)

2X (1.43)

8X (0.65)

2X (0.725)

(R0.05) TYP

(1) TYP

(

0.2) VIA

TYP

2X (4)

(4.7)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 16X

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

EXPOSED

METAL

EXPOSED

METAL

SOLDER MASK

OPENING

METAL EDGE

METAL UNDER

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DEFINED

SOLDER MASK DETAILS

4224086/C 03/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

RDA0015A

B3QFN - 4.1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

PKG

4X (1.35)

4X (0.6)

4X (0.45)

(1.15)

2X (0.975)

10X (0.65)

10X (0.3)

PKG

4X (0.475)

(0.95)

(0.65)

2X (1.43)

8X (0.65)

4X (1.675)

2X (0.725)

(R0.05) TYP

4X (0.425)

4X (0.625)

2X (4)

(4.7)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 15:

56% PRINTED SOLDER COVERAGE BY AREA

SCALE: 16X

4224086/C 03/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

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TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TPSM53603 [TI]

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