TPSM5601R5H [TI]

TPSM5601R5Hx, 60-V Input, 1-V to 16-V Output, 1.5-A Power Module in Enhanced HotRodâ¢ QFN Package;


型号：	TPSM5601R5H
厂家：	TEXAS INSTRUMENTS
描述：	TPSM5601R5Hx, 60-V Input, 1-V to 16-V Output, 1.5-A Power Module in Enhanced HotRodâ¢ QFN Package
文件：	总29页 (文件大小：1208K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPSM5601R5H, TPSM5601R5HE

TPSM5601_SR_L5_VH_SF,_IT₄P_–S_DEM_C5_E6_M0_B1_ER_R5₂H₀₂E₀

SLVSFI4 – DECEMBER 2020

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TPSM5601R5Hx, 60-V Input, 1-V to 16-V Output, 1.5-A Power Module in Enhanced

HotRod™ QFN Package

1 Features

3 Description

•

5-mm × 5.5-mm × 4-mm Enhanced HotRod^™QFN

– Excellent thermal performance: up to 18-W

output power at 85°C, no airflow

– Standard footprint: single large thermal pad and

all pins accessible from perimeter

Designed for reliable and rugged applications

– Wide input voltage range: 4.2 V to 60 V

– Input voltage transient protection up to 66 V

– Operating junction range: –40°C to +125°C

– EXT-suffix junction range: –55°C to +125°C

Fixed 1-MHz switching frequency

The TPSM5601R5Hx power module is a highly

integrated 1.5-A power solution that combines a 60-V

input, step-down DC/DC converter with power

MOSFETs, a shielded inductor, and passives in a

thermally enhanced QFN package. The 5-mm x 5.5-

mm x 4-mm, 15-pin QFN package uses Enhanced

HotRod QFN technology for enhanced thermal

performance, small footprint, and low EMI. The

package footprint has all pins accessible from the

perimeter and a single large thermal pad for simple

layout and easy handling in manufacturing.

•

The TPSM5601R5Hx is a compact, easy-to-use

power module with a wide adjustable output voltage

range of 1.0V to 16V. The total solution requires as

few as four external components and eliminates the

loop compensation and magnetics part selection from

the design process. The full feature set includes

power good, programmable UVLO, prebias start-up,

over current and temperature protections, making the

TPSM5601R5Hx an excellent device for powering a

wide range of applications. Space-constrained

applications benefit from the 5-mm × 5.5-mm

package. Additionally, the TPSM5601R5HEXT offers

extended low temperature operation of -55°C and the

TPSM5601R5HS offers frequency spread-spectrum

operation.

FPWM mode of operation

Optimized for ultra-low EMI requirements

– Integrated shielded inductor and high-frequency

bypass capacitors

– Meets EN55011 EMI standards

– Spread spectrum option reduces emissions

26-µA non-switching quiescent current

Monotonic start-up into prebiased output

No loop-compensation or bootstrap components

Precision enable and input UVLO with hysteresis

Thermal shutdown protection with hysteresis

Create a custom regulator design using

WEBENCH^®Power Designer

•

2 Applications

Device Information

PART NUMBER

TPSM5601R5H

TPSM5601R5HE

PACKAGE⁽¹⁾

BODY SIZE (NOM)

•

Field transmitters and sensors, PLC modules

Thermostats, video surveillance, HVAC systems

AC and servo drives, rotary encoders

Industrial transport, asset tracking

QFN (15)

5.0 mm × 5.5 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Negative output applications

100

V_OUT= 12 V

V_IN= 24 V

V_IN= 48 V

V_IN= 60 V

0.3

0.6 0.9

Output Current (A)

1.2

1.5

Typical Efficiency, V_OUT= 12 V

Typical Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

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intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change

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Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Device Comparison Table...............................................2

6 Pin Configuration and Functions...................................3

7 Specifications.................................................................. 4

7.1 Absolute Maximum Ratings ....................................... 4

7.2 ESD Ratings .............................................................. 4

7.3 Recommended Operating Conditions ........................5

7.4 Thermal Information ...................................................5

7.5 Electrical Characteristics ............................................6

7.6 Typical Characteristics (VIN = 12 V)........................... 8

7.7 Typical Characteristics (VIN = 24 V)........................... 9

7.8 Typical Characteristics (VIN = 48 V)......................... 10

7.9 Typical Characteristics (VIN = 60 V)......................... 11

8 Detailed Description......................................................12

8.1 Overview...................................................................12

8.2 Functional Block Diagram.........................................12

8.3 Feature Description...................................................13

8.4 Device Functional Modes..........................................16

9 Applications and Implementation................................17

9.1 Application Information............................................. 17

9.2 Typical Application.................................................... 17

10 Power Supply Recommendations..............................19

11 Layout...........................................................................20

11.1 Layout Guidelines................................................... 20

11.2 Layout Example...................................................... 20

12 Device and Documentation Support..........................22

12.1 Device Support....................................................... 22

12.2 Documentation Support.......................................... 22

12.3 Receiving Notification of Documentation Updates..22

12.4 Support Resources................................................. 22

12.5 Trademarks.............................................................22

12.6 Electrostatic Discharge Caution..............................23

12.7 Glossary..................................................................23

13 Mechanical, Packaging, and Orderable

Information.................................................................... 23

4 Revision History

DATE

REVISION

NOTES

December 2020

Initial Release

5 Device Comparison Table

DEVICE

DESCRIPTION

TPSM5601R5H

60-V input voltage, 1-V to 16-V output voltage, 1.5-A power module, fixed 1-MHz switching, operating

junction temperature range: –40°C to +125°C

TPSM5601R5HEXT

TPSM5601R5HS

Same as TPSM5601R5H, but with extended junction temperature range: –55°C to +125°C

Same as TPSM5601R5H, but with spread spectrum operation

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6 Pin Configuration and Functions

VIN

PGOOD

V5V

PGND

AGND

DNC

VOUT

Figure 6-1. 15-Pin QFN RDA Package (Top View)

Table 6-1. Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NO.

NAME

Analog ground. Zero voltage reference for internal references and logic. All electrical parameters are

measured with respect to this pin. This pin must be connected to PGND at a single point. See

Section 11.2 for a recommended layout.

AGND

—

Do not connect. Do not connect these pins to ground, to another DNC pin, or to any other voltage. These

pins are connected to internal circuitry. Each pin must be soldered to an isolated pad.

DNC

Enable pin. This pin turns the converter on when pulled high and turns off the converter when pulled low.

This pin can be connected directly to VIN. Do not float. This pin can be used to set the input

undervoltage lockout with two resistors. See Section 8.3.4.

Feedback input. Connect the mid-point of the feedback resistor divider to this pin. Connect the upper

resistor (R_FBT) of the feedback divider to V_OUTat the desired point of regulation. Connect the lower

resistor (R_FBB) of the feedback divider to AGND.

3, 6, 13

Not connected. These pins are not connected to any circuitry within the module. It is recommended that

these pins be connected to the PGND plane on the application board to enhance shielding and thermal

performance.

—

Power ground. This is the return current path for the power stage of the device. Connect this pad to the

input supply return, load return, and capacitors associated with the VIN and VOUT pins. See Section 11.2

for a recommended layout.

PGND

Power-good pin. Open-drain output that asserts low if the feedback voltage is not within the specified

window thresholds. A 10-kΩ to 100-kΩ pullup resistor is required and can be tied to the V5V pin or other

DC voltage less than 18 V. If not used, this pin can be left open or connected to PGND.

PGOOD

VIN

Switch node. Do not place any external component on this pin or connect to any signal.

Input supply voltage. Connect the input supply to these pins. Connect input capacitors between these

pins and PGND in close proximity to the device.

1, 14

Output voltage. These pins are connected to the internal output inductor. Connect these pins to the

output load and connect external output capacitors between these pins and PGND.

7, 8

VOUT

V5V

Internal 5-V LDO output. Supplies internal control circuits. Do not connect to external loads. This pin can

be used as logic supply for PGOOD pin.

(1) G = Ground, I = Input, O = Output

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7 Specifications

7.1 Absolute Maximum Ratings

Over the operating ambient temperature range⁽¹⁾

PARAMETER

MIN

–0.3

MAX

UNIT

VIN to PGND

EN to AGND⁽²⁾

V_IN+ 0.3

Input voltage

PGOOD to AGND⁽²⁾

FB to AGND

5.5

AGND to PGND

VOUT to PGND⁽²⁾

VCC to AGND

0.3

Output voltage

5.5

Non-EXT suffix device

EXT suffix device

–40

–55

125

150

245

°C

Operating IC junction

temperature, T_J

(3)

Storage temperature, T_stg

Peak reflow case temperature

Maximum number or reflows allowed

Mechanical vibration

Mechanical shock

Mil-STD-883H, Method 2007.3, 1 msec, 1/2 sine, mounted

Mil-STD-883H, Method 2002.5, 20 to 2000Hz

TBD

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any conditions beyond those indicated in Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The voltage on this pin must not exceed the voltage on the VIN pin by more than 0.3 V

(3) The ambient temperature is the air temperature of the surrounding environment. The junction temperature is the temperature of the

internal power IC when the device is powered. Operating below the maximum ambient temperature, as shown in the safe operating

area (SOA) curves in the typical characteristics sections, ensures that the maximum junction temperature of any component inside the

module is never exceeded.

7.2 ESD Ratings

VALUE

±500

UNIT

Human-body model (HBM)⁽¹⁾

V_(ESD)

Electrostatic discharge

Charged-device model (CDM)⁽²⁾

±1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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7.3 Recommended Operating Conditions

Over operating ambient temperature range (unless otherwise noted) ⁽¹⁾

MIN

4.2

MAX

UNIT

Input voltage, V_IN

Output voltage, V_OUT

Output current, I_OUT

16 ⁽³⁾

1.5

(2)

EN voltage, V_EN

V_IN

(2)

PGOOD pullup voltage, V_PGOOD

Non-EXT suffix device

Operating ambient temperature, T_A

–40

–55

105

°C

EXT suffix device

(1) Recommended operating conditions indicate conditions for which the device is intended to be functional, but do not ensure specific

performance limits. For ensured specifications, see Section 7.5.

(2) The voltage on this pin must not exceed the voltage on the VIN pin by more than 0.3 V.

(3) The recommended maximum output voltage varies depending input voltage.

7.4 Thermal Information

TPSM5601R5Hx

THERMAL METRIC⁽¹⁾

RDA (QFN)

15 PINS

23.9

UNIT

Nat Conv

100 LFM

200 LFM

°C/W

°C

R_θJA

Junction-to-ambient thermal resistance ⁽²⁾

21.8

20.1

ψ_JT

ψ_JB

Junction-to-top characterization parameter ⁽³⁾

Junction-to-board characterization parameter ⁽⁴⁾

Thermal shutdown temperature

3.6

15.3

170

T_SHDN

Recovery temperature

158

°C

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics app-note.

(2) The junction-to-ambient thermal resistance, R_θJA, applies to devices soldered directly to a 6.35 cm x 8.25 cm, four-layer PCB with 2

oz. copper. Additional airflow and PCB copper area reduces R_θJA. See Section 11.2.1 for more information.

(3) The junction-to-top board characterization parameter, ψ_JT, estimates the junction temperature, T_J, of a device in a real system, using a

procedure described in JESD51-2A (section 6 and 7). T_J= ψ_JT× Pdis + T_T; where Pdis is the power dissipated in the device and T_Tis

the temperature of the top of the device.

(4) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature, T_J, of a device in a real system, using a

procedure described in JESD51-2A (sections 6 and 7). T_J= ψ_JB× Pdis + T_B; where Pdis is the power dissipated in the device and T_B

is the temperature of the board 1mm from the device.

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7.5 Electrical Characteristics

Limits apply over T_A= –40°C to +105°C (EXT suffix device; T_A= –55°C to +105°C), V_IN= 24 V, V_OUT= 3.3 V, I_OUT= 1.5 A,

(unless otherwise noted); Minimum and maximum limits are specified through production test or by design. Typical values

represent the most likely parametric norm and are provided for reference only.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INPUT VOLTAGE (V_IN)

Input voltage range

V_INturn on

Over I_OUTrange

4.2 ⁽¹⁾

V_IN

V_INincreasing, I_OUT= 0 A, V_EN= V_IN

V_INdecreasing, I_OUT= 0 A, V_EN= V_IN

V_EN= 0 V, I_OUT= 0 A

3.8

3.3

V_INturn off

I_SHDN

Shutdown supply current

µA

INTERNAL LDO (V_CC

)

Internal LDO output voltage

appearing at the VCC pin

VCC

6 V ≤ V_IN≤ 60 V

4.75

5.25

FEEDBACK

Feedback voltage⁽²⁾

Load regulation

I_OUT= 0 A

0.985

1.015

T_A= +25°C, 0 A ≤ I_OUT≤ 1.5 A

0.057

V_FB

T_A= +25°C, I_OUT= 0 A, 6 V ≤ V_IN

60 V

≤

Line regulation

0.024

0.2

I_FB

Current into FB pin

FB = 1 V

CURRENT

I_OUT

Output current

T_A= 25ºC

1.5

I_OUT

Over-current threshold

V_OUT= 3.3 V, T_A= 25ºC

1.9

0.4

FB pin voltage required to trip

short-circuit hiccup mode

V_HC

t_HC

Time between current-limit hiccup

burst

ENABLE (EN PIN)

EN input level required to turn on

internal LDO

V_EN-VCC-H

V_EN-VCC-L

V_EN-H

Rising threshold

Falling threshold

Rising threshold

1.14

1.30

EN input level required to turn off

internal LDO

0.3

EN input level required to start

switching

1.157

1.231

V_EN-HYS

I_LKG-EN

Hysteresis below V_EN-H

Hysteresis below V_EN-H; falling

V_EN= 3.3 V

110

0.2

Enable input leakage current

POWER GOOD (PGOOD PIN)

V_PG-HIGH-UPV_OUTrising (fault)

V_PG-HIGH-DNV_OUTfalling (good)

% of FB voltage

V_EN= 0 V

107%

105%

R_PG

Power-good flag R_DSON

Ω

Minimum input voltage for proper

PGOOD function

V_IN-PG

I_PG= 50 µA, EN = 0 V

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7.5 Electrical Characteristics (continued)

Limits apply over T_A= –40°C to +105°C (EXT suffix device; T_A= –55°C to +105°C), V_IN= 24 V, V_OUT= 3.3 V, I_OUT= 1.5 A,

(unless otherwise noted); Minimum and maximum limits are specified through production test or by design. Typical values

represent the most likely parametric norm and are provided for reference only.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

PERFORMANCE

V_OUT= 3.3 V, I_OUT= 0.75 A, T_A

25ºC

Efficiency

V_OUT= 5.0 V, I_OUT= 0.75 A, T_A

25ºC

SOFT START

t_SS

Internal soft-start time

4.5

1⁽³⁾

SWITCHING FREQUENCY

ƒ_SWSwitching frequency

I_OUT= 0.75 A, T_A= 25ºC

0.85

1.15

MHz

(1) The recommended minimum V_INis 4.2 V or (VOUT + 600 mV), whichever is greater.

(2) The overall output voltage tolerance will be affected by the tolerance of the external R_FBTand R_FBBresistors.

(3) The typical switching frequency of this device will change based on operating conditions. See the Switching Frequency section for

more information.

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7.6 Typical Characteristics (VIN = 12 V)

T_A= 25°C, unless otherwise noted.

100

1.2

V_OUT

5.0 V

3.3 V

2.5 V

1.8 V

1.2 V

0.8

0.6

0.4

0.2

V_OUT

5.0 V

3.3 V

2.5 V

1.8 V

1.2 V

0.3

0.6 0.9

Output Current (A)

1.2

1.5

0.3

0.6 0.9

Output Current (A)

1.2

1.5

Figure 7-1. Efficiency

Figure 7-2. Power Dissipation

115

V_OUT

15 V

105

12 V

9 V

5 V

3.3 V

Airflow

200LFM

100LFM

Nat conv

0.3

0.6 0.9

Output Current (A)

1.2

1.5

0.25

0.5

0.75

Output Current (A)

1.25

1.5

C_OUT= 2x 47 µF, 25 V, ceramic

Device soldered to a 63.5 mm × 82.5 mm, 4-layer PCB

Figure 7-3. Output Voltage Ripple

Figure 7-4. Safe Operating Area (V_OUT= 1.2 V)

115

105

Airflow

400LFM

200LFM

400LFM

200LFM

100LFM

Nat conv

100LFM

Nat conv

0.25

0.5

0.75

Output Current (A)

1.25

1.5

0.25

0.5

0.75

Output Current (A)

1.25

1.5

Device soldered to a 63.5 mm × 82.5 mm, 4-layer PCB

Figure 7-5. Safe Operating Area (V_OUT= 3.3 V)

Figure 7-6. Safe Operating Area (V_OUT= 5.0 V)

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7.7 Typical Characteristics (VIN = 24 V)

T_A= 25°C, unless otherwise noted.

100

1.6

1.4

1.2

V_OUT

15 V

12 V

9 V

5 V

3.3 V

2.5 V

1.8 V

0.8

0.6

0.4

0.2

V_OUT

15 V

12 V

9 V

5 V

3.3 V

2.5 V

1.8 V

0.3

0.6 0.9

Output Current (A)

1.2

1.5

0.3

0.6 0.9

Output Current (A)

1.2

1.5

Figure 7-7. Efficiency

Figure 7-8. Power Dissipation

115

V_OUT

15 V

105

12 V

9 V

5 V

3.3 V

2.5 V

1.8 V

Airflow

400LFM

200LFM

100LFM

Nat conv

0.3

0.6 0.9

Output Current (A)

1.2

1.5

0.25

0.5

0.75

Output Current (A)

1.25

1.5

C_OUT= 2x 47 µF, 25 V, ceramic

Device soldered to a 63.5 mm × 82.5 mm, 4-layer PCB

Figure 7-9. Output Voltage Ripple

Figure 7-10. Safe Operating Area (V_OUT= 1.8 V)

115

105

Airflow

400LFM

200LFM

400LFM

200LFM

100LFM

Nat conv

100LFM

Nat conv

0.25

0.5

0.75

Output Current (A)

1.25

1.5

0.25

0.5

0.75

Output Current (A)

1.25

1.5

Device soldered to a 63.5 mm × 82.5 mm, 4-layer PCB

Figure 7-11. Safe Operating Area (V_OUT= 5.0 V)

Figure 7-12. Safe Operating Area (V_OUT= 12 V)

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7.8 Typical Characteristics (VIN = 48 V)

T_A= 25°C, unless otherwise noted.

100

2.4

2.2

V_OUT

15 V

12 V

9 V

5 V

1.8

1.6

1.4

1.2

3.3 V

V_OUT

15 V

12 V

9 V

5 V

3.3 V

0.8

0.6

0.3

0.6 0.9

Output Current (A)

1.2

1.5

0.3

0.6 0.9

Output Current (A)

1.2

1.5

Figure 7-13. Efficiency

Figure 7-14. Power Dissipation

115

V_OUT

15 V

105

12 V

9 V

5 V

3.3 V

Airflow

400LFM

200LFM

100LFM

Nat conv

0.3

0.6 0.9

Output Current (A)

1.2

1.5

0.25

0.5

0.75

Output Current (A)

1.25

1.5

C_OUT= 2x 47 µF, 25 V, ceramic

Device soldered to a 63.5 mm × 82.5 mm, 4-layer PCB

Figure 7-15. Output Voltage Ripple

Figure 7-16. Safe Operating Area (V_OUT= 5.0 V)

115

105

Airflow

400LFM

200LFM

400LFM

200LFM

100LFM

Nat conv

100LFM

Nat conv

0.25

0.5

0.75

Output Current (A)

1.25

1.5

0.25

0.5

0.75

Output Current (A)

1.25

1.5

Device soldered to a 63.5 mm × 82.5 mm, 4-layer PCB

Figure 7-17. Safe Operating Area (V_OUT= 12 V)

Figure 7-18. Safe Operating Area (V_OUT= 15 V)

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7.9 Typical Characteristics (VIN = 60 V)

T_A= 25°C, unless otherwise noted.

100

2.8

2.6

2.4

2.2

V_OUT

15 V

12 V

9 V

5 V

3.3 V

1.8

1.6

1.4

1.2

V_OUT

15 V

12 V

9 V

5 V

3.3 V

0.8

0.3

0.6 0.9

Output Current (A)

1.2

1.5

0.3

0.6 0.9

Output Current (A)

1.2

1.5

Figure 7-19. Efficiency

Figure 7-20. Power Dissipation

115

V_OUT

15 V

105

12 V

9 V

5 V

3.3 V

Airflow

400LFM

200LFM

100LFM

Nat conv

0.3

0.6 0.9

Output Current (A)

1.2

1.5

0.25

0.5

0.75

Output Current (A)

1.25

1.5

C_OUT= 2x 47 µF, 25 V, ceramic

Device soldered to a 63.5 mm × 82.5 mm, 4-layer PCB

Figure 7-21. Output Voltage Ripple

Figure 7-22. Safe Operating Area (V_OUT= 5.0 V)

115

105

Airflow

400LFM

200LFM

400LFM

200LFM

100LFM

Nat conv

100LFM

Nat conv

0.25

0.5

0.75

Output Current (A)

1.25

1.5

0.25

0.5

0.75

Output Current (A)

1.25

1.5

Device soldered to a 63.5 mm × 82.5 mm, 4-layer PCB

Figure 7-23. Safe Operating Area (V_OUT= 12 V)

Figure 7-24. Safe Operating Area (V_OUT= 15 V)

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8 Detailed Description

8.1 Overview

The TPSM5601R5Hx converter is an easy-to-use, synchronous buck, DC-DC power module that operates from

a 4.2-V to 60-V supply voltage. The device is intended for step-down conversions from 5-V, 12-V, 24-V, and 48-V

unregulated, semi-regulated or fully-regulated supply rails. With integrated power controller, inductor, and

MOSFETs, the TPSM5601R5Hx delivers up to 1.5-A DC load current, with high efficiency and ultra-low input

quiescent current, in a very small solution size. Although designed for simple implementation, this device offers

flexibility to optimize its usage according to the target application. Control-loop compensation is not required,

reducing design time and external component count.

The TPSM5601R5Hx incorporates several features for comprehensive system requirements, including an open-

drain Power Good circuit for power-rail sequencing and fault reporting, monotonic start-up into prebiased loads,

precision enable with customizable hysteresis for programmable line undervoltage lockout (UVLO), along with

overcurrrent and thermal shutdown with automatic recovery. Additionally, the TPSM5601R5HxS offers frequency

spread-spectrum operation. These features enable a flexible and easy-to-use platform for a wide range of

applications. The pin arrangement is designed for simple PCB layout, requiring as few as four external

components.

8.2 Functional Block Diagram

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8.3 Feature Description

8.3.1 Adjustable Output Voltage (FB)

The TPSM5601R5Hx has an adjustable output voltage range of 1.0 V to 16 V. Setting the output voltage

requires two resistors, R_FBTand R_FBB(see Figure 8-1). Connect R_FBTbetween VOUT, at the regulation point,

and the FB pin. Connect R_FBBbetween the FB pin and AGND (pin 10). The recommended value of R_FBTis 10

kΩ. The value for R_FBBcan be calculated using Equation 1.

1.0

R_FBB

× R_FBT

1.0

V_OUT

(1)

VOUT

R_FBT

10 kꢀ

R_FBB

AGND

Figure 8-1. FB Resistor Divider

Table 8-1. Standard R_FBBValues

VOUT (V)

1.0

R_FBB(kΩ) ⁽¹⁾

VOUT (V)

3.3

R_FBB(kΩ) ⁽¹⁾

4.32

open

49.9

20.0

12.4

10.0

6.65

4.99

1.2

5.0

2.49

1.5

7.5

1.54

1.8

1.10

2.0

0.909

0.715

0.665

2.5

3.0

(1) R_FBT= 10 kΩ

Selecting R_FBTvalue of 10 kΩ is recommended for most applications. A larger R_FBTconsumes less DC current,

which is mandatory if light-load efficiency is critical. However, R_FBTlarger than 1 MΩ is not recommended as the

feedback path becomes more susceptible to noise. High feedback resistance generally requires more careful

layout of the feedback path. It is important to keep the feedback trace as short as possible while keeping the

feedback trace away from the noisy area of the PCB. For more layout recommendations, see Section 11.

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8.3.2 Minimum Input Capacitance

The TPSM5601R5Hx requires a minimum input capacitance of 9.4 μF (2 × 4.7 μF) of ceramic type. High-quality,

ceramic-type X5R or X7R capacitors with sufficient voltage rating are required. Place the input capacitors, as

close as possible to both VIN pins of the device, between VIN and PGND as shown in Section 11.1. Applications

with transient load requirements can benefit from adding additional bulk capacitance to the input as well.

8.3.3 Minimum Output Capacitance

The TPSM5601R5Hx requires a minimum amount of ceramic output capacitance depending on the output

voltage setting. The amount of required output capacitance is shown in Figure 8-2 and is the amount of effective

capacitance. The effects of DC bias and temperature variation must be considered when using ceramic

capacitance. For ceramic capacitors, the package size, voltage rating, and dielectric material contributes to

differences between the standard rated value and the actual effective value of the capacitance. When adding

additional capacitance above the minimum, the capacitance can be ceramic type, low-ESR polymer type, or a

combination of the two.

275

250

225

200

175

150

125

100

10 11 12 13 14 15 16

Output Voltage (V)

Figure 8-2. Minimum Required Output Capacitance

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8.3.4 Precision Enable (EN), Undervoltage Lockout (UVLO), and Hysteresis (HYS)

The EN pin provides precision ON and OFF control for the TPSM5601R5Hx. Once the EN pin voltage exceeds

the threshold voltage, the device starts operation. The simplest way to enable the device is to connect EN

directly to VIN. This allows the device to start up when V_INis within its valid operating range. An external logic

signal can also be used to drive the EN input to toggle the output on and off and for system sequencing or

protection. This input must not be allowed to float.

The TPSM5601R5Hx implements internal undervoltage lockout (UVLO) circuitry on the VIN pin. The device is

disabled when the VIN pin voltage is below the internal VIN UVLO threshold.

If an application requires a higher UVLO threshold, the EN input supports adjustable UVLO by connecting a

resistor divider from VIN to the EN pin. Applying a voltage of ≥ 1.14 V causes the device to enter standby mode,

powering the internal LDO, but not producing an output voltage. Increasing the EN voltage to 1.231 V (typ.) fully

enables the device, allowing it to enter start-up mode and starting the soft-start period. When the EN input is

brought below 1.121 V (110 mV hysteresis), the regulator stops running and enters standby mode. Further

decrease in the EN voltage to below 0.3 V completely shuts down the device.

The TPSM5601R5Hx utilizes a reference-based soft start that prevents output voltage overshoots and large

inrush currents as the regulator is starting up. The rise time of the output voltage is about 4 ms.

8.3.5 Power Good (PGOOD)

The TPSM5601R5Hx provides a PGOOD signal to indicate when the output voltage is within regulation. Use the

PGOOD signal for output monitoring, fault protection, or start-up sequencing of downstream converters. PGOOD

is an open-drain output that requires a pullup resistor to a DC supply not greater than 18 V. V5V or VOUT can be

used as the pullup voltage source. Typical range of pullup resistance is 10 kΩ to 100 kΩ. If necessary, use a

resistor divider to decrease the voltage from a higher voltage pullup rail. If this function is not needed, the

PGOOD pin must be grounded.

When the output voltage exceeds 95% (rising) or decreases below 105% (falling) of the setpoint, the internal

PGOOD switch turns off and PGOOD can be pulled high by the external pullup. If the FB voltage falls below 93%

or rises above 107% of the setpoint, the internal PGOOD switch turns on, and PGOOD is pulled low to indicate

that the output voltage is out of regulation.

Note that during initial power up, a delay of about 4 ms (typical) is inserted from the time that EN is asserted to

the time that the power-good flag goes high. This delay only occurs during start-up and is not encountered

during normal operation of the power-good function.

8.3.6 Overcurrent Protection (OCP)

The TPSM5601R5Hx is protected from overcurrent conditions using cycle-by-cycle current limiting for overload

conditions and hiccup mode for short circuits. The current is compared every switching cycle to the current limit

threshold. During an overcurrent condition, the output voltage decreases.

8.3.7 Thermal Shutdown

Thermal shutdown is an integrated self-protection used to limit junction temperature and prevent damage related

to overheating. Thermal shutdown turns off the device when the junction temperature exceeds 170°C (typ.) to

prevent further power dissipation and temperature rise. Junction temperature decreases after shutdown, and the

TPSM5601R5Hx restarts when the junction temperature falls to 158°C (typ.).

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8.4 Device Functional Modes

8.4.1 Active Mode

The TPSM5601R5Hx is in active mode when VIN is above the turn-ON threshold and the EN pin voltage is

above the EN high threshold. Connect the EN pin to VIN to allow the device to start up when a valid input

voltage is applied. This allows self start-up of the TPSM5601R5Hx when the input voltage is in the operation

range of 4.2 V to 60 V. Connecting a resistor divider between VIN, EN, and AGND adjusts the UVLO to delay the

turn on until VIN is closer to its regulated voltage.

8.4.2 Standby Mode

Start-up and shut-down are controlled by the EN input. This input features precision thresholds, allowing the use

of an external voltage divider to provide an adjustable input UVLO. Applying a voltage of ≥ 1.14 causes the

device to enter standby mode, powering the internal LDO, but not producing an output voltage. Increasing the

EN voltage to 1.231 V (typ.) fully enables the device, allowing it to enter start-up mode and starting the soft-start

period. When the EN input is brought below 1.121 V (110 mV hysteresis), the regulator stops running and enters

standby mode. Further decrease in the EN voltage to below 0.3 V completely shuts down the device.

8.4.3 Shutdown Mode

The EN pin provides ON and OFF control for the TPSM5601R5Hx. When V_ENis below the EN low threshold, the

device is in shutdown mode. Both the internal LDO and the switching regulator are off. The quiescent current in

shutdown mode drops to 5 µA at V_IN= 24 V.

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9 Applications and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

9.1 Application Information

The TPSM5601R5Hx only requires a few external components to convert from a wide range of supply voltages

to a fixed output voltage. To expedite and streamline the process of designing of a TPSM5601R5Hx,

WEBENCH^®online software is available to generate complete designs, leveraging iterative design procedures

and access to comprehensive component databases. The following section describes the design procedure to

configure the TPSM5601R5Hx power module.

As mentioned previously, the TPSM5601R5Hx also integrates several optional features to meet system design

requirements, including precision enable, UVLO, and PGOOD indicator. The application circuit detailed below

shows TPSM5601R5Hx configuration options suitable for several application use cases. Refer to the

TPSM5601R5HxEVM user's guide for more detail.

9.2 Typical Application

Figure 9-1 shows the schematic diagram of a 24-V input, 5-V output, 1.5-A converter.

V5V

TPSM5601R5H

100 kO

V_IN= 24 V

PGOOD

VOUT

VIN

V_OUT= 5 V

4.7 µF

100 V

4.7 µF

100 V

10 kO

47 µF

10 V

47 µF

10 V

PGND

AGND

2.49 kO

Figure 9-1. TPSM5601R5Hx Typical Schematic

9.2.1 Design Requirements

For this design example, use the parameters listed in Table 9-1 as the input parameters and follow the design

procedures in Section 9.2.2.

Table 9-1. Design Example Parameters

DESIGN PARAMETER

VALUE

24 V typical

5 V

Input voltage V_IN

Output voltage V_OUT

Output current rating

1.5 A

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9.2.2 Detailed Design Procedure

9.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the TPSM5601R5Hx device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

•

Run electrical simulations to see important waveforms and circuit performance.

Run thermal simulations to understand board thermal performance.

Export customized schematic and layout into popular CAD formats.

Print PDF reports for the design, and share the design with colleagues.

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

9.2.2.2 Output Voltage Setpoint

The output voltage of the TPSM5601R5Hx device is externally adjustable using a resistor divider. The

recommended value of R_FBTis 10 kΩ. The value for R_FBBcan be selected from Table 8-1 or calculated using

Equation 2:

1.0

R_FBB

× R_FBT

1.0

V_OUT

(2)

For the desired output voltage of 5 V, the formula yields a value of 2.5 kΩ. Choose the closest available standard

value of 2.49 kΩ for R_FBB

9.2.2.3 Input Capacitors

The TPSM5601R5Hx requires a minimum input capacitance of 2x 4.7-µF ceramic type. High-quality ceramic

type X5R or X7R capacitors with sufficient voltage rating are recommended. The voltage rating of input

capacitors must be greater than the maximum input voltage.

For this design, 2x 4.7-µF, 100-V ceramic capacitors are selected.

9.2.2.4 Output Capacitor Selection

The TPSM5601R5Hx requires a minimum amount of output capacitance for proper operation. The minimum

amount of required output varies depending on the output voltage. See Figure 8-2 for the required output

capacitance. Additional output capacitance can be added to reduce ripple voltage or for applications with

transient load requirements.

For this design example, 2x 47-µF, 10-V, ceramic capacitors are used.

9.2.2.5 Power Good Signal

Applications requiring a power good signal to indicate that the output voltage is present and in regulation must

use a pull-up resistor between the PGOOD pin and a valid voltage source.

For this design a 100-kΩ resistor is placed between the PGOOD pin and the V5V pin (the internal 5-V LDO

output).

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9.2.2.6 Application Curves

V_IN= 24 V

V_OUT= 5 V

I_OUT= 1.5 A

V_IN= 24 V

V_OUT= 5 V

I_OUT= 1.5 A

Figure 9-2. Start-up Waveforms

Figure 9-3. Enable Shut-down Waveforms

Figure 9-4. Output Ripple Waveform

Figure 9-5. Transient Response Waveform

10 Power Supply Recommendations

The TPSM5601R5Hx is designed to operate from an input voltage supply range between 4.2 V and 60 V. This

input supply must be able to provide the maximum input current and maintain a voltage above the set UVLO

voltage. Ensure that the resistance of the input supply rail is low enough that an input current transient does not

cause a high enough drop at the TPSM5601R5Hx supply rail to cause a false UVLO fault triggering and system

reset. If the input supply is located more than a few inches from the TPSM5601R5Hx, additional bulk

capacitance can be required in addition to the ceramic input capacitance. A 47-μF electrolytic capacitor is a

typical choice for this function, whereby the capacitor ESR provides a level of damping against input filter

resonances. A typical ESR of 0.5 Ω provides enough damping for most input circuit configurations.

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11 Layout

The performance of any switching power supply depends as much upon the layout of the PCB as the component

selection. Use the following guidelines to design a PCB with the best power conversion performance, optimal

thermal performance, and minimal generation of unwanted EMI.

11.1 Layout Guidelines

To achieve optimal electrical and thermal performance, an optimized PCB layout is required. Figure 11-1 and

Figure 11-2 show a typical PCB layout. Some considerations for an optimized layout are:

•

Use large copper areas for power planes (VIN, VOUT, and PGND) to minimize conduction loss and thermal

stress.

•

Connect all PGND pins together using copper plane.

Connect AGND pin to the PGND copper at a single point near the pin.

Place ceramic input and output capacitors close to the device pins to minimize high frequency noise.

Locate additional output capacitors between the ceramic capacitor and the load.

Place R_FBTand R_FBBas close as possible to their respective pins.

Use multiple vias to connect the power planes to internal layers.

11.2 Layout Example

Figure 11-2. Typical Top-Layer

Figure 11-1. Typical Layout

Figure 11-4. Typical PGND-Layer

Figure 11-3. Typical Mid-Layer

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11.2.1 Theta JA versus PCB Area

The amount of PCB copper as well as airflow effects the thermal performance of the device. Figure 11-5 shows

the effects of copper area and airflow on the junction-to-ambient thermal resistance (R _θJA) of the

TPSM5601R5Hx. The junction-to-ambient thermal resistance versus PCB area is plotted for a 4-layer PCB.

To determine the required copper area for an application:

1. Determine the maximum power dissipation of the device in the application by referencing the power

dissipation graphs in the Typical Characteristics.

2. Calculate the maximum θ_JAusing Equation 3 and the maximum ambient temperature of the application.

(125˘C œ T_A(max)

)

ꢀ_JA

(˘C/W)

P_D(max)

(3)

3. Reference Figure 11-5 to determine the minimum required PCB area for the application conditions.

Nat Conv

100 LFM

200 LFM

PCB Area (cm²)

Figure 11-5. θ_JAvs PCB Area

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12 Device and Documentation Support

12.1 Device Support

12.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.1.2 Development Support

For development support, see the following:

•

For TI's reference design library, visit TI Designs.

To view a related device of this product, see the TPSM5601R5Hx.

12.1.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the TPSM5601R5H device with WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

•

Run electrical simulations to see important waveforms and circuit performance.

Run thermal simulations to understand board thermal performance.

Export customized schematic and layout into popular CAD formats.

Print PDF reports for the design, and share the design with colleagues.

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

12.2 Documentation Support

12.2.1 Related Documentation

For related documentation, see the following:

•

Texas Instruments, TPSM5601R5HxEVM User's Guide

Texas Instruments, Using the TPSM5601R5Hx in an Inverting Buck-Boost Topology Application Report

Texas Instruments, Using New Thermal Metrics Application Report

Texas Instruments, Semiconductor and IC Package Thermal Metrics Application Report

12.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

12.4 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.5 Trademarks

HotRod^™and TI E2E^™are trademarks of Texas Instruments.

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WEBENCH^®is a registered trademark of Texas Instruments.

is a registered trademark of Texas Instruments.

All trademarks are the property of their respective owners.

12.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.7 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this datasheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

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12-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

PTPSM5601R5HEXTRDA

PTPSM5601R5HRDAR

TPSM5601R5HEXTRDAR

TPSM5601R5HRDAR

ACTIVE

B3QFN

RDA

1000 RoHS (In work)

& Non-Green

Call TI

-55 to 125

-40 to 125

-55 to 125

-40 to 125

ACTIVE

PREVIEW

RDA

1000 RoHS (In work)

& Non-Green

Call TI

RDA

1000 RoHS (In work)

& Non-Green

RDA

1000 RoHS (In work)

& Non-Green

TPSM5601R5HSRDAR

RDA

1000 RoHS (In work)

& Non-Green

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

12-Dec-2020

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE OUTLINE

RDA0015A

B3QFN - 4.1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

5.1

4.9

PIN 1 INDEX AREA

5.6

5.4

4.1 MAX

0.08 C

SEATING PLANE

2.5 0.05

PKG

0.45

0.25

0.1

1.5 0.05

10X

C A B

1.3

1.1

(0.16) TYP

0.05

2X 0.725

2.6 TYP

1.43

PKG

4.6 0.05

2.5 0.05

8X 0.65

2X 0.975

0.6

0.4

0.6

0.4

10X

0.1

C A B

1.3

1.1

0.05

PIN 1 ID

4224086/C 03/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

RDA0015A

B3QFN - 4.1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(2.5)

(1.5)

4X (1.4)

PKG

4X (0.5)

2X (0.975)

10X (0.7)

10X (0.35)

(4.6)

PKG

(1)

TYP

(2.5)

2X (1.43)

8X (0.65)

2X (0.725)

(R0.05) TYP

(1) TYP

(

0.2) VIA

TYP

2X (4)

(4.7)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 16X

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

EXPOSED

METAL

EXPOSED

METAL

SOLDER MASK

OPENING

METAL EDGE

METAL UNDER

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DEFINED

SOLDER MASK DETAILS

4224086/C 03/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

RDA0015A

B3QFN - 4.1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

PKG

4X (1.35)

4X (0.6)

4X (0.45)

(1.15)

2X (0.975)

10X (0.65)

10X (0.3)

PKG

4X (0.475)

(0.95)

(0.65)

2X (1.43)

8X (0.65)

4X (1.675)

2X (0.725)

(R0.05) TYP

4X (0.425)

4X (0.625)

2X (4)

(4.7)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 15:

56% PRINTED SOLDER COVERAGE BY AREA

SCALE: 16X

4224086/C 03/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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