TPSM63606RDLR [TI]
TPSM63606 High-Density, 3-V to 36-V Input, 1-V to 16-V Output, 6-A Power Module With Enhanced HotRod⢠QFN Package;型号: | TPSM63606RDLR |
厂家: | TEXAS INSTRUMENTS |
描述: | TPSM63606 High-Density, 3-V to 36-V Input, 1-V to 16-V Output, 6-A Power Module With Enhanced HotRod⢠QFN Package |
文件: | 总38页 (文件大小:2211K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TPSM63606
SLVSGB4 – OCTOBER 2021
TPSM63606 High-Density, 3-V to 36-V Input, 1-V to 16-V Output, 6-A Power Module
With Enhanced HotRod™ QFN Package
1 Features
3 Description
•
Versatile synchronous buck DC/DC module
– Integrated MOSFETs, inductor, and controller
– Wide input voltage range of 3 V to 36 V
– Adjustable output voltage from 1 V to 16 V
– 5.0-mm × 5.5-mm × 4-mm overmolded package
– –40°C to 105°C ambient temperature range
– Frequency adjustable from 200 kHz to 2.2 MHz
using the RT pin or an external SYNC signal
– Negative output voltage capability
The TPSM63606 synchronous buck power module
is a highly integrated 36-V, 6-A DC/DC solution that
combines power MOSFETs, a shielded inductor, and
passives in an Enhanced HotRod™ QFN package.
The module has pins for VIN and VOUT located at the
corners of the package for optimized input and output
capacitor layout placement. Four larger thermal pads
beneath the module enable a simple layout and easy
handling in manufacturing.
•
•
Ultra-high efficiency across the full load range
– 95%+ peak efficiency
With an output voltage from 1 V to 16 V, the
TPSM63606 is designed to quickly and easily
implement a low-EMI design in a small PCB footprint.
The total solution requires as few as four external
components and eliminates the magnetics and
compensation part selection from the design process.
– External bias option for improved efficiency
– Shutdown quiescent current of 0.6 µA (typical)
Ultra-low conducted and radiated EMI signatures
– Low-noise package with dual input paths and
integrated capacitors reduces switch ringing
– Spread-spectrum modulation (S suffix)
– Resistor-adjustable switch-node slew rate
– Constant-frequency FPWM mode of operation
– Meets CISPR 11 and 32 class B emissions
Suitable for scalable power supplies
– Pin compatible with the TPSM63604 (36 V, 4 A)
Inherent protection features for robust design
– Precision enable input and open-drain PGOOD
indicator for sequencing, control, and VIN UVLO
– Overcurrent and thermal shutdown protections
Create a custom design using the TPSM63606
with the WEBENCH® Power Designer
Although designed for small size and simplicity
in space-constrained applications, the TPSM63606
module offers many features for robust performance:
precision enable with hysteresis for adjustable input-
voltage UVLO, resistor-programmable switch node
slew rate and spread spectrum option for improved
EMI, integrated VCC, bootstrap and input capacitors
for increased reliability and higher density, constant
switching frequency over the full load current range,
•
•
and
a PGOOD indicator for sequencing, fault
protection, and output voltage monitoring.
•
Device Information
PART NUMBER(1)
PACKAGE
BODY SIZE (NOM)
2 Applications
TPSM63606
B3QFN (20)
5.0 mm × 5.5 mm
•
•
•
Test and measurement, aerospace and defense
Factory automation and control
Buck and inverting buck-boost power supplies
TPSM63606S
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
100
VIN = 3 V...36 V
VIN1
CBOOT
VIN2
CIN
95
RBOOT
PGND
90
TPSM63606
VOUT = 5 V
VLDOIN
EN/SYNC
IOUT(max) = 6 A
85
VCC
VOUT1
VOUT2
RPG
80
RFBT
COUT
PG
RT
FB
VIN = 12 V
VIN = 24 V
VIN = 36 V
75
70
RFBB
RRT
AGND
0
1
2
3
4
5
6
* VOUT enters dropout
if VIN < 5.8 V
Output Current (A)
Typical Efficiency, VOUT = 5 V, FSW = 1 MHz
Typical Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change
without notice.
TPSM63606
SLVSGB4 – OCTOBER 2021
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings ....................................... 6
7.2 ESD Ratings .............................................................. 6
7.3 Recommended Operating Conditions ........................6
7.4 Thermal Information ...................................................7
7.5 Electrical Characteristics ............................................7
7.6 Typical Characteristics................................................9
7.7 Typical Characteristics (VIN = 12 V)..........................10
7.8 Typical Characteristics (VIN = 24 V).......................... 11
8 Detailed Description......................................................12
8.1 Overview...................................................................12
8.2 Functional Block Diagram.........................................12
8.3 Feature Description...................................................13
8.4 Device Functional Modes..........................................19
9 Applications and Implementation................................20
9.1 Application Information............................................. 20
9.2 Typical Applications.................................................. 20
10 Power Supply Recommendations..............................28
11 Layout...........................................................................29
11.1 Layout Guidelines................................................... 29
11.2 Layout Example...................................................... 30
12 Device and Documentation Support..........................32
12.1 Device Support....................................................... 32
12.2 Documentation Support.......................................... 33
12.3 Receiving Notification of Documentation Updates..33
12.4 Support Resources................................................. 33
12.5 Trademarks.............................................................33
12.6 Electrostatic Discharge Caution..............................33
12.7 Glossary..................................................................33
13 Mechanical, Packaging, and Orderable
Information.................................................................... 33
4 Revision History
DATE
REVISION
NOTES
October 2021
*
Advance Information initial release
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5 Device Comparison Table
ORDERABLE PART RATED OUTPUT
JUNCTION
TEMPERATURE RANGE SPECTRUM
SPREAD
SLEW-RATE
CONTROL
EXTERNAL
SYNC
DEVICE
NUMBER
CURRENT
TPSM63602
TPSM63603
TPSM63603S
TPSM63603E
TPSM63604
TPSM63606
TPSM63606S
TPSM63606E
TPSM63602RDHR
TPSM63603RDHR
TPSM63603SRDHR
TPSM63603EXTRDHR
TPSM63604RDLR
TPSM63606RDLR
TPSM63606SRDLR
TPSM63606EXTRDLR
2 A
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–55°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–55°C to 125°C
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
3 A
Yes
3 A
Yes
Yes
No
Yes
3 A
Yes
4 A
Yes
6 A
No
Yes
6 A
Yes
Yes
Yes
6 A
Yes
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6 Pin Configuration and Functions
1
16
VIN1
VIN2
17
PGND
SW
CBOOT
RBOOT
VLDOIN
AGND
2
3
4
5
6
7
15
14
13
12
11
10
NC
EN/SYNC
PG
18
PGND
RT
19
PGND
AGND
FB
VCC
20
PGND
8
9
VOUT1
VOUT2
Figure 6-1. 20-Pin QFN RDL Package (Top View)
Table 6-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NO.
NAME
Input supply voltage. Connect the input supply to these pins. Connect input capacitors between these
pins and PGND in close proximity to the device.
1, 16
VIN1, VIN2
SW
P
Switch node. Do not place any external component on this pin or connect to any signal. The amount of
copper placed on this pin must be kept to a minimum to prevent issues with noise and EMI.
2
3
O
Bootstrap pin for the internal high-side gate driver. A 100-nF bootstrap capacitor is internally connected
from this pin to SW within the module to provide the bootstrap voltage. CBOOT is brought out to use
in conjunction with RBOOT to effectively lower the value of the internal series bootstrap resistance to
adjust the switch-node slew rate, if necessary.
CBOOT
RBOOT
VLDOIN
I/O
I/O
External bootstrap resistor connection. Internal to the device, a 100-Ω bootstrap resistor is connected
between RBOOT and CBOOT. RBOOT is brought out to use in conjunction with CBOOT to effectively
lower the value of the internal series bootstrap resistance to adjust the switch-node slew rate, if
necessary.
4
Input bias voltage. Input to the internal LDO that supplies the internal control circuits. Connect to an
output voltage point to improve efficiency. Connect an optional high-quality 0.1-μF to 1-μF capacitor from
this pin to ground for improved noise immunity. If the output voltage is above 12 V, connect this pin to
ground.
5
P
Analog ground. Zero-voltage reference for internal references and logic. All electrical parameters are
measured with respect to this pin. These pins must be connected to PGND. See Section 11.2 for a
recommended layout.
6, 11
AGND
VCC
G
Internal LDO output. Used as a supply to the internal control circuits. Do not connect to any external
loads. A 1-μF capacitor internally connects from VCC to AGND.
7
O
P
VOUT1,
VOUT2
Output voltage. These pins are connected to the internal buck inductor. Connect these pins to the output
load and connect external output capacitors between these pins and PGND.
8, 9
Feedback input. Connect the midpoint of the feedback resistor divider to this pin. Connect the upper
resistor (RFBT) of the feedback divider to VOUT at the desired point of regulation. Connect the lower
resistor (RFBB) of the feedback divider to AGND. Do not leave open or connect to ground.
10
12
13
FB
RT
PG
I
I
Frequency setting pin used to set the switching frequency between 200 kHz and 2.2 MHz by placing an
external resistor from RT to AGND. Do not leave open or connect to ground.
Open-drain power-good monitor output that asserts low if the FB voltage is not within the specified
window thresholds. A 10-kΩ to 100-kΩ pullup resistor to a suitable voltage is required . If not used, PG
can be left open or connected to GND.
O
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Table 6-1. Pin Functions (continued)
PIN
TYPE(1)
DESCRIPTION
NO.
14
NAME
Precision enable input pin. High = on, Low = off. Can be connected to VIN. Precision enable allows
the pin to be used as an adjustable input voltage UVLO. It also functions as the synchronization input
pin. Used to synchronize the device switching frequency to a system clock. Triggers on the rising edge
of an external clock. A capacitor can be used to AC couple the synchronization signal to this pin. The
module can be turned off by using an open-drain/collector device to connect this pin to AGND. Connect
an external resistor divider between this pin, VIN and AGND to create an external UVLO.
EN/SYNC
I
15
NC
—
G
No connection. Tie to GND or leave open.
Power ground. This is the return current path for the power stage of the device. Connect these pads to
the input supply return, the load return, and the capacitors associated with the VIN and VOUT pins. See
Section 11.2 for a recommended layout.
17, 18,
19, 20
PGND
(1) P = Power, G = Ground, I = Input, O = Output
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7 Specifications
7.1 Absolute Maximum Ratings
Limits apply over TJ = –40°C to 150°C (unless otherwise noted). (1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
0
MAX
42
UNIT
V
VIN1, VIN2 to AGND, PGND
RBOOT to SW
5.5
5.5
16
V
CBOOT to SW
V
VLDOIN to AGND, PGND
V
Input voltage
EN/SYNC to AGND, PGND
RT to AGND, PGND
FB to AGND, PGND
PG to AGND, PGND
PGND to AGND
42
V
5.5
16
V
V
20
V
–1
2
V
VCC to AGND, PGND
SW to AGND, PGND(2)
VOUT1, VOUT2 to AGND, PGND
PG
–0.3
–0.3
–0.3
–
5.5
42
V
Output voltage
V
16
V
Input current
10
mA
°C
°C
°C
°C
TJ
Junction temperature
Ambient temperature
Storage temperature
–40
–40
–55
150
125
150
245
3
TA
Tstg
Peak reflow case temperature
Maximum number of reflows allowed
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) A voltage of 2 V below PGND and 2 V above VIN can appear on this pin for ≤ 200 ns with a duty cycle of ≤ 0.01%.
7.2 ESD Ratings
VALUE
±1500
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Limits apply over TJ = –40°C to 125°C (unless otherwise noted).
MIN
NOM
MAX
36
UNIT
V
Input voltage
Input voltage
Output voltage
Output current
Frequency
Input current
Output voltage
TJ
VIN (input voltage range after start-up)
3
VLDOIN
12.5
16
V
VOUT(1)
1
0
V
IOUT(2)
6
A
FSW set by RT or SYNC
200
2200
2
kHz
mA
V
PG
PG
16
Operating junction temperature
Operating ambient temperature
–40
–40
125
105
°C
°C
TA
(1) Under no conditions should the output voltage be allowed to fall below zero volts.
(2) Maximum continuous DC current may be derated when operating with high switching frequency and/or high ambient temperature.
Refer to the Typical Characteristics section for details.
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7.4 Thermal Information
TPSM63606
RDL (QFN)
20 PINS
22.6
THERMAL METRIC(1)
UNIT
RθJA
RθJA
ψJT
Junction-to-ambient thermal resistance (TPSM63606 EVM)
Junction-to-ambient thermal resistance (2)
°C/W
°C/W
°C/W
°C/W
33.1
Junction-to-top characterization parameter (3)
Junction-to-board characterization parameter (4)
1
ψJB
12.3
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) The junction-to-ambient thermal resistance, RθJA, applies to devices soldered directly to a 75-mm × 75-mm four-layer PCB with 2 oz.
copper and natural convection cooling. Additional airflow and PCB copper area reduces RθJA
.
(3) The junction-to-top board characterization parameter, ψJT, estimates the junction temperature, TJ, of a device in a real system, using a
procedure described in JESD51-2A (section 6 and 7). TJ = ψJT × PDIS + TT; where PDIS is the power dissipated in the device and TT is
the temperature of the top of the device.
(4) The junction-to-board characterization parameter, ψJB, estimates the junction temperature, TJ, of a device in a real system, using a
procedure described in JESD51-2A (sections 6 and 7). TJ = ψJB × PDIS + TB; where PDIS is the power dissipated in the device and TB is
the temperature of the board 1mm from the device.
7.5 Electrical Characteristics
Limits apply over TJ = –40°C to 125°C, VIN = 24 V, VOUT = 3.3 V, VLDOIN = 5 V, FSW = 800 kHz (unless otherwise noted).
Minimum and maximum limits are specified through production test or by design. Typical values represent the most likely
parametric norm and are provided for reference only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE
Needed to start up (over the IOUT range)
Once operating (over the IOUT range)
3.95
3
36
36
V
V
V
VIN
Input operating voltage range
Hysteresis(1)
VIN_HYS
ENABLE
VEN_RISE
VEN_FALL
VEN_HYS
VEN_WAKE
tEN
1
EN voltage rising threshold
EN voltage falling threshold
EN voltage hysteresis
1.161
1.263
0.91
1.365
0.404
V
V
0.303
0.4
0.353
V
EN wake-up threshold
V
EN high to start of switching delay(1)
0.7
ms
VCC INTERNAL LDO
3.4 V ≤ VVLDOIN ≤ 12.5 V
VVLDOIN = 3.1 V, nonswitching
VVLDOIN < 3.1 V(1)
3.3
3.1
3.6
3.6
1.1
V
V
V
V
V
VCC
Internal LDO VCC output voltage
VCC_UVLO
VCC UVLO rising threshold
VIN < 3.6 V(2)
VCC_UVLO_HYS VCC UVLO hysteresis(2)
Hysteresis below VCC_UVLO
FEEDBACK
VOUT
VFB
Adjustable output voltage range
Feedback voltage
Over the IOUT range
TA = 25°C, IOUT = 0 A
1
16
V
V
1.0
10
Over the VIN range, VOUT = 1 V, IOUT = 0
A, FSW = 200 kHz
VFB_ACC
Feedback voltage accuracy
Input current into FB
–1%
+1%
IFB
VFB = 1 V
nA
CURRENT
IOUT
Output current
TA = 25°C
0
6
A
A
A
A
A
IOCL
Output overcurrent (DC) limit threshold
High-side switch current limit
Low-side switch current limit
Negative current limit
8.3
9.3
7.1
–3
IL_HS
Duty cycle approaches 0%
IL_LS
IL_NEG
Ratio of FB voltage to in-regulation FB voltage to
enter hiccup
VHICCUP
Not during soft start
40%
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Limits apply over TJ = –40°C to 125°C, VIN = 24 V, VOUT = 3.3 V, VLDOIN = 5 V, FSW = 800 kHz (unless otherwise noted).
Minimum and maximum limits are specified through production test or by design. Typical values represent the most likely
parametric norm and are provided for reference only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Short circuit wait time ("hiccup" time before soft start)
tW
80
ms
(1)
SOFT START
tSS
Time from first SW pulse to VFB at 90%
VIN ≥ 4.2 V
VIN ≥ 4.2 V
3.5
9.5
5
7
ms
ms
Time from first SW pulse to release of FPWM lockout
if output not in regulation(1)
tSS2
13
17
POWER GOOD
PGOV
PG upper threshold – rising
% of VOUT setting
105%
92%
107%
94%
110%
PGUV
PG upper threshold – falling
% of VOUT setting
96.5%
PGHYS
PG upper threshold hysteresis (rising and falling)
Input voltage for valid PG output
Low level PG function output voltage
Delay time to PG high signal
% of VOUT setting
1.3%
VIN_PG_VALID
VPG_LOW
tPG_FLT_RISE
tPG_FLT_FALL
46 μA pull-up, VEN/SYNC = 0 V
2 mA pullup to PG pin, VEN/SYNC = 0 V
1.0
1.5
V
V
0.4
2.5
2.0
ms
µs
Glitch filter time constant for PG function
120
SWITCHING FREQUENCY
fSW_RANGE Switching frequency range by RT or SYNC
fSW_RT1
200
180
2200
220
kHz
kHz
kHz
Default switching frequency by RRT
Default switching frequency by RRT
RRT = 66.5 kΩ
RRT = 5.76 kΩ
200
fSW_RT2
1980
2200
2420
Frequency span of spread spectrum operation –
largest deviation from center frequency
fS_SS
fPSS
Spread spectrum active (TPSM63606S)
Spread spectrum active, fSW = 2.1 MHz
2%
Spread spectrum pattern frequency(1)
1.5
Hz
SYNCHRONIZATION
VEN_SYNC Edge amplitude necessary to sync using EN/SYNC
tB
Rise/fall time < 30 ns
2.4
28
V
Blanking of EN after rising or falling edges(1)
4
µs
Enable sync signal hold time after edge for edge
recognition(1)
tSYNC_EDGE
POWER STAGE
tON_MIN
100
ns
VOUT = 1 V, IOUT = 1 A, RBOOT shorted to
CBOOT
Minimum ON pulse width(1)
Maximum ON pulse width(1)
Minimum OFF pulse width
55
9
ns
µs
ns
tON_MAX
VIN = 4 V, IOUT = 1 A, RBOOT shorted to
CBOOT
tOFF_MIN
65
85
THERMAL SHUTDOWN
TSHD
Thermal shutdown threshold (1)
Thermal shutdown hysteresis (1)
Temperature rising
158
168
10
180
°C
°C
TSHD-HYS
PERFORMANCE
η1
η2
Efficiency
Efficiency
VOUT = 3.3 V, IOUT = 6 A, TA = 25°C
VOUT = 5 V, IOUT = 6 A, TA = 25°C
88.6%
91.3%
(1) Parameter specified by design, statistical analysis and production testing of correlated parameters. Not production tested.
(2) Production tested with VIN = 3 V.
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7.6 Typical Characteristics
VIN = 24 V, unless otherwise specified.
1.01
1.005
1
4
TJ = -40C
TJ = 25C
TJ = 125C
3
2
1
0
0.995
0.99
-50
-25
0
25
50
75
100
125
Junction Temperature (°C)
0
6
12
18
24
30
36
Input Voltage (V)
Note
VEN/SYNC = 0 V
Figure 7-1. Shutdown Supply Current
Figure 7-2. Feedback Voltage
70
70
60
50
40
30
20
10
60
50
40
30
20
10
0
High-side MOSFET
Low-side MOSFET
200 400 600 800 1000 1200 1400 1600 1800 2000 2200
Frequency (kHz)
-50
-25
0
25
50
75
100
125
Junction Temperature (°C)
Figure 7-3. Switching Frequency Set by RT
Resistor
Figure 7-4. High-Side and Low-Side MOSFET
RDS(on)
1.4
1.2
1
115
110
105
100
95
0.8
0.6
90
0.4
OV Tripping
OV Recovery
UV Recovery
UV Tripping
VEN Rising
VEN Falling
VEN_WAKE Rising
VEN_WAKE Falling
85
0.2
80
-50
0
-50
-25
0
25
50
75
100 125
-25
0
25
50
75
100
125
Junction Temperature (°C)
Junction Temperature (°C)
Figure 7-6. Power-Good (PG) Thresholds
Figure 7-5. Enable Thresholds
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7.7 Typical Characteristics (VIN = 12 V)
Unless otherwise indicated, TA = 25°C, VLDOIN is tied to VOUT (except for VOUT = 2.5 V), and the module
is soldered to a 76-mm × 63-mm, 4-layer PCB. The SOA curves are taken with TJ(max) = 125°C and TA(max)
105°C. Refer to Section 9.2 for circuit designs.
=
100
95
90
85
80
75
3
2.5
2
7.5 V, 1.5 MHz
5.0 V, 1 MHz
3.3 V, 750 kHz
2.5 V, 500 kHz
1.5
1
7.5 V, 1.5 MHz
5.0 V, 1 MHz
3.3 V, 750 kHz
2.5 V, 500 kHz
0.5
0
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Output Current (A)
Output Current (A)
Figure 7-7. Efficiency
Figure 7-8. Power Dissipation
120
100
80
120
100
80
60
60
0 LFM
0 LFM
40
40
100 LFM
200 LFM
400 LFM
100 LFM
200 LFM
400 LFM
20
20
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Output Current (A)
Output Current (A)
Figure 7-9. Safe Operating Area
(VOUT = 2.5 V, FSW = 500 kHz)
Figure 7-10. Safe Operating Area
(VOUT = 3.3 V, FSW = 750 kHz)
120
100
80
60
0 LFM
40
100 LFM
200 LFM
400 LFM
20
0
1
2
3
4
5
6
Output Current (A)
Figure 7-11. Safe Operating Area
(VOUT = 5 V, FSW = 1 MHz)
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7.8 Typical Characteristics (VIN = 24 V)
Unless otherwise indicated, TA = 25°C, VLDOIN is tied to VOUT (except for VOUT = 2.5 V), and the module
is soldered to a 76-mm × 63-mm, 4-layer PCB. The SOA curves are taken with TJ(max) = 125°C and TA(max)
105°C. Refer to Section 9.2 for circuit designs.
=
100
95
90
85
80
75
4
3.5
3
12 V, 2 MHz
7.5 V, 1.5 MHz
5 V, 1 MHz
3.3 V, 750 kHz
2.5
2
1.5
1
12 V, 2 MHz
7.5 V, 1.5 MHz
5.0 V, 1 MHz
3.3 V, 750 kHz
0.5
0
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Output Current (A)
Output Current (A)
Figure 7-12. Efficiency
Figure 7-13. Power Dissipation
120
100
80
120
100
80
60
60
0 LFM
0 LFM
40
40
100 LFM
200 LFM
400 LFM
100 LFM
200 LFM
400 LFM
20
20
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Output Current (A)
Output Current (A)
Figure 7-14. Safe Operating Area
(VOUT = 2.5 V, FSW = 500 kHz)
Figure 7-15. Safe Operating Area
(VOUT = 3.3 V, FSW = 750 kHz)
120
100
80
120
100
80
60
60
0 LFM
0 LFM
40
40
100 LFM
200 LFM
400 LFM
100 LFM
200 LFM
400 LFM
20
20
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Output Current (A)
Output Current (A)
Figure 7-16. Safe Operating Area
(VOUT = 5 V, FSW = 1 MHz)
Figure 7-17. Safe Operating Area
(VOUT = 12 V, FSW = 2 MHz)
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8 Detailed Description
8.1 Overview
The TPSM63606 is an easy-to-use, synchronous buck DC/DC power module designed for a wide variety of
applications where reliability, small solution size, and low EMI signature are of paramount importance. With
integrated power MOSFETs, a buck inductor, and PWM controller, the TPSM63606 operates over an input
voltage range of 3 V to 36 V with transients as high as 42 V. The module delivers up to 6-A DC load current with
high conversion efficiency and ultra-low input quiescent current in a very small solution footprint. Control loop
compensation is not required, reducing design time and external component count.
With a programmable switching frequency from 200 kHz to 2.2 MHz using its RT pin or an external clock signal,
the TPSM63606 incorporates specific features to improve EMI performance in noise-sensitive applications:
•
•
An optimized package and pinout design enables a shielded switch-node layout that mitigates radiated EMI
Parallel input and output paths with symmetrical capacitor layouts minimize parasitic inductance, switch-
voltage ringing, and radiated field coupling
•
•
•
Pseudo-random spread spectrum (PRSS) modulation in the TPSM63606S reduces peak emissions
Clock synchronization and FPWM mode enable constant switching frequency across the load current range
Integrated power MOSFETs with enhanced gate drive control enable low-noise PWM switching
Together, these features significantly reduce EMI filtering requirements, while helping to meet CISPR 11 and
CISPR 32 class B EMI limits for conducted and radiated emissions.
The TPSM63606 module also includes inherent protection features for robust system requirements:
•
•
An open-drain PGOOD indicator for power-rail sequencing and fault reporting
Precision enable input with hysteresis, providing
– Programmable line undervoltage lockout (UVLO)
– Remote ON/OFF capability
•
•
•
Internally fixed output-voltage soft start with monotonic startup into prebiased loads
Hiccup-mode overcurrent protection with cycle-by-cycle peak and valley current limits
Thermal shutdown with automatic recovery.
Leveraging a pin arrangement designed for simple layout that requires only a few external components, the
TPSM63606 is specified to maximum ambient and junction temperatures of 105°C and 125°C, respectively.
8.2 Functional Block Diagram
VLDOIN
VCC
Optional
external bias
(from VOUT)
RT
LDO bias
subregulator
VIN
Oscillator
RRT
UVLO
SYNC
detect
VIN = 3 V to 36 V
OTP
VIN1, VIN2
RENT
Shutdown
logic
Precision
enable for
VIN UVLO
EN/SYNC
PG
Enable
logic
RBOOT
CBOOT
100
RENB
OCP
PGOOD
indicator
PGOOD
logic
CIN
SW
Power
stage
and
control
logic
2.2 µH
VOUT = 1 V to 16 V
IOUT(max) = 6 A
COUT
RFBT
VOUT1, VOUT2
FB
To VOUT
sense point
UVLO
OTP
OCP
EN
Soft start
+
RFBB
Comp
VREF
PGND
AGND
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8.3 Feature Description
8.3.1 Input Voltage Range (VIN1, VIN2)
With a steady-state input voltage range from 3 V to 36 V, the TPSM63606 module is intended for step-down
conversions from typical 12-V, 24-V, and 28-V input supply rails. The schematic circuit in Figure 8-1 shows all the
necessary components to implement a TPSM63606-based buck regulator using a single input supply.
VIN = 3 V to 36 V
Precision enable
for VIN UVLO
VIN1
VIN2
CIN1
CIN2
PGND
PGND
Synchronization
(200 kHz to 2.2 MHz)
RENT
TPSM63606
CSYNC
Optional
external bias
SYNC
VOUT = 1 V to 16 V
IOUT(max) = 6 A
EN/SYNC
VLDOIN
VOUT
VOUT1
VOUT2
optional
RENB
VCC
RPG
COUT
CBOOT
RBOOT
FB
PG
RT
RFBT
PGOOD
indicator
AGND
RFBB
RRT
Figure 8-1. TPSM63606 Schematic Diagram with Input Voltage Operating Range of 3 V to 36 V
The minimum input voltage required for start-up is 3.95 V. Take extra care to make sure that the voltage at the
VIN pins of the module (VIN1 and VIN2) does not exceed the absolute maximum voltage rating of 42 V during
line or load transient events. Voltage ringing at the VIN pins that exceeds the absolute maximum ratings can
damage the IC.
8.3.2 Adjustable Output Voltage (FB)
The TPSM63606 has an adjustable output voltage range from 1 V up to a maximum of 16 V or slightly less than
VIN, whichever is lower. Setting the output voltage requires two feedback resistors, designated as RFBT and RFBB
in Figure 8-1. The reference voltage at the FB pin is set at 1 V with a feedback system accuracy over the full
junction temperature range of ±1%. The junction temperature range for the device is –40°C to 125°C.
Calculate the value for RFBT using Equation 1 based on a recommended value for RFBB of 10 kΩ.
(1)
Table 8-1 lists the standard resistor values for several output voltages and the recommended switching
frequency range to maintain reasonable peak-to-peak inductor ripple curernt. This table also includes the
minimum required output capacitance for each output voltage setting to maintain stability. The capacitances
as listed represent effective values for ceramic capacitors derated for DC bias voltage and temperature.
Furthermore, place a feedforward capacitor, CFF, in parallel with RFBT to increase the phase margin when the
output capacitance is close to the minimum recommended value.
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CFF (pF)
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Table 8-1. Standard RFBT Values, Recommended FSW Range and Minimum COUT
VOUT RFBT (kΩ) SUGGESTED FSW COUT(min) (µF)
(V)
VOUT RFBT (kΩ) SUGGESTED FSW COUT(min) (µF)
CFF (pF)
(1)
(1)
RANGE (kHz)
300 to 500
400 to 600
500 to 700
650 to 900
700 to 950
(EFFECTIVE)
(V)
RANGE (MHz)
0.8 to 1.2
1.2 to 1.6
1.6 to 2.0
1.7 to 2.2
1.8 to 2.2
(EFFECTIVE)
1
Short
2
300
200
120
65
—
—
5
40.2
64.9
90.9
110
25
20
15
10
8
22
15
—
—
—
1.2
1.8
2.5
3.3
7.5
10
12
15
8.06
15
100
68
23.2
40
47
140
(1) RFBB = 10 kΩ.
Note that higher feedback resistances consume less DC current. However, an upper RFBT resistor value higher
than 1 MΩ renders the feedback path more susceptible to noise. Higher feedback resistances generally require
more careful layout of the feedback path. It is important to locate the feedback resistors close to the FB and
AGND pins, keeping the feedback trace as short as possible (and away from noisy areas of the PCB). See
Section 11.2 guidelines for more detail.
8.3.3 Input Capacitors
Input capacitors are necessary to limit the input ripple voltage to the module due to switching-frequency AC
currents. TI recommends using ceramic capacitors to provide low impedance and high RMS current rating over
a wide temperature range. Equation 2 gives the input capacitor RMS current. The highest input capacitor RMS
current occurs at D = 0.5, at which point the RMS current rating of the capacitors should be greater than half the
output current.
DIL2
12
≈
’
D∂ IOUT2 ∂ 1-D +
∆
÷
÷
◊
ICIN,rms
=
(
)
∆
«
(2)
where
D = VOUT / VIN is the module duty cycle.
•
Ideally, the DC and AC components of input current to the buck stage are provided by the input voltage source
and the input capacitors, respectively. Neglecting inductor ripple current, the input capacitors source current of
amplitude (IOUT – IIN) during the D interval and sink IIN during the 1 – D interval. Thus, the input capacitors
conduct a square-wave current of peak-to-peak amplitude equal to the output current. The resultant capacitive
component of AC ripple voltage is a triangular waveform. Together with the ESR-related ripple component,
Equation 3 gives the peak-to-peak ripple voltage amplitude:
IOUT ∂D ∂ 1- D
(
)
+ IOUT ∂RESR
DV
=
IN
FSW ∂CIN
(3)
(4)
Equation 4 gives the input capacitance required for a particular load current:
D∂ 1-D ∂I
(
)
OUT
CIN
í
FSW ∂ DVIN -RESR ∂IOUT
where
ΔVIN is the input voltage ripple specification.
•
The TPSM63606 requires a minimum of two 10-µF ceramic input capacitors, preferable with X7R or X7S
dielectric and in 1206 or 1210 footprint. Additional capacitance can be required for applications to meet
conducted EMI specifications, such as CISPR 11 or CISPR 32.
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Table 8-2 includes a preferred list of capacitors by vendor. To minimize the parasitic inductance in the switching
loops, position the ceramic input capacitors in a symmetrical layout close to the VIN1 and VIN2 pins and connect
the capacitor return terminals to the PGND pins using a copper ground plane under the module.
Table 8-2. Recommended Ceramic Input Capacitors
VENDOR(1)
TDK
DIELECTRIC
X7R
PART NUMBER
CASE SIZE
CAPACITANCE (µF)(2)
RATED VOLTAGE (V)
C3216X7R1H106K160AC
GCM32EC71H106KA03K
12105C106MAT2A
1206
10
10
10
10
50
50
50
50
Murata
AVX
X7S
1210
X7R
1210
Murata
X7R
GRM32ER71H106KA12L
1210
(1) Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process
requirements for any capacitors identified in this table. See the Third-Party Products Disclaimer.
(2) Nameplate capacitance values (the effective values are lower based on the applied DC voltage and temperature).
As discussed in Section 10, an electrolytic bulk capacitance (68 µF to 100 µF) provides low-frequency filtering
and parallel damping to mitigate the effects of input parasitic inductance resonating with the low-ESR, high-Q
ceramic input capacitors.
8.3.4 Output Capacitors
Table 8-1 lists the TPSM63606 minimum amount of required output capacitance. The effects of DC bias and
temperature variation must be considered when using ceramic capacitance. For ceramic capacitors in particular,
the package size, voltage rating, and dielectric material contribute to differences between the standard rated
value and the actual effective value of the capacitance.
When including additional capacitance above COUT(min), the capacitance can be ceramic type, low-ESR polymer
type, or a combination of the two. See Table 8-3 for a preferred list of output capacitors by vendor.
Table 8-3. Recommended Ceramic Output Capacitors
VENDOR(1)
Murata
DIELECTRIC
X7R
PART NUMBER
CASE SIZE CAPACITANCE (µF)(2)
VOLTAGE (V)
GRM31CZ71C226ME15L
C3225X7R1C226M250AC
GRM32ER71C226KEA8K
C3216X6S1E226M160AC
12103C226KAT4A
1206
1210
1210
1206
1210
1210
1210
1210
1210
1206
1206
1210
22
22
16
16
16
25
25
25
10
10
16
4
TDK
X7R
Murata
TDK
X7R
22
X6S
22
AVX
X7R
22
Murata
AVX
X7R
GRM32ER71E226ME15L
1210ZC476MAT2A
22
X7R
47
Murata
Murata
TDK
X7R
GRM32ER71A476ME15L
GRM32EC81C476ME15L
C3216X6S0G107M160AC
GRM31CD80J107MEA8L
GRM32EC70J107ME15L
47
X6S
47
X6S
100
100
100
Murata
Murata
X6T
6.3
6.3
X7S
(1) Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process
requirements for any capacitors identified in the table. See the Third-Party Products Disclaimer.
(2) Nameplate capacitance values (the effective values are lower based on the applied DC voltage and temperature).
8.3.5 Switching Frequency (RT)
Connect a resistor, designated as RRT in Figure 8-1, between RT and AGND to set the swiching frequency within
the range of 200 kHz to 2.2 MHz. Use Equation 5 or refer to Figure 7-3 to calculate RRT for a desired frequency.
(5)
Refer to Table 8-1 or use the simplified expression in Equation 6 to find a switching frequency that sets an
inductor ripple current of 25% to 40% of the 6-A module current rating at nominal input voltage:
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(6)
where
•
VIN(nom) and VOUT are the nominal input voltage (typically 12 V or 24 V) and output voltage of the application,
respectively.
Note that a resistor value outside of the recommended range can cause the module to shut down. This prevents
unintended operation if the RT pin is shorted to ground or left open. Do not apply a pulsed signal to this pin to
force synchronization. Refer to Section 8.3.7 if clock synchronization is required.
8.3.6 Precision Enable and Input Voltage UVLO (EN/SYNC)
The EN/SYNC pin provides precision ON and OFF control for the TPSM63606. Once the EN/SYNC pin voltage
exceeds the rising threshold and VIN is above its minimum turn-on threshold, the device starts operation. The
simplest way to enable the TPSM63606 is to connect EN/SYNC directly to VIN. This allows the TPSM63606
to start up when VIN is within its valid operating range. However, many applications benefit from the use of an
enable divider network as shown in Figure 8-1, which establishes a precision input undervoltage lockout (UVLO).
This can be used for sequencing, to prevent re-triggering the device when used with long input cables, or to
reduce the occurrence of deep discharge of a battery power source. An external logic signal can also be used to
drive the enable input to toggle the output on and off and for system sequencing or protection.
Calculate RENB using Equation 7:
(7)
where
•
•
•
A typical value for RENT is 100 kΩ.
VEN_RISE is enable rising threshold voltage of 1.263 V (typical).
VIN(on) is the desired start-up input voltage.
Note
The EN/SYNC pin can also be used as an external clock synchronization input. See Section 8.3.7 for
additonal information. A blanking time of 4 µs to 28 µs is applied to the enable logic after a clock edge
is detected. To effectively disable the output, the EN/SYNC input must stay low for longer than 28 µs.
Any logic change within the blanking time is ignored. A blanking time is not applied when the device is
in shutdown mode.
8.3.7 Frequency Synchronization (EN/SYNC)
Synchronize the internal oscillator of the TPSM63606 by AC coupling a positive clock edge to EN/SYNC, as
shown in Figure 8-1. The synchronization frequency range is 200 kHz to 2.2 MHz.
It is recommended to keep the parallel combination value of RENT and RENB in the 100-kΩ range. RENT is
required for synchronization, but RENB can be left open. The external clock must be off before start-up to allow
proper start-up sequencing. After a valid synchronization signal is applied for 2048 cycles, the clock frequency
changes to that of the applied signal.
Referring to Figure 8-2, the AC-coupled voltage edge at the EN/SYNC pin must exceed the SYNC amplitude
threshold, VEN_SYNC, of 2.4 V to trip the internal synchronization pulse detector. In addition, the minimum EN/
SYNC rising and falling pulse durations must be longer than the SYNC signal hold time, tSYNC_EDGE, of 100 ns
and shorter than the minimum blanking time, tB. Use a 3.3-V or higher amplitude pulse signal coupled through a
1-nF capacitor, designated as CSYNC in Figure 8-1.
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VEN/SYNC
tSYNC_EDGE
VEN_SYNC
t
0
tSYNC_EDGE
Figure 8-2. Typical SYNC Waveform
8.3.8 Spread Spectrum
The TPSM63606S includes pseudo-random spread spectrum (PRSS) modulation that provides a ±2% spread
of the switching frequency and its harmonics. PRSS spreads the switching energy smoothly across higher-
frequency bands, improving both conducted and radiated EMI performance, but is low enough to limit unwanted
subharmonic emissions below the switching frequency.
The TPSM63606S uses a cycle-to-cycle frequency hopping method based on a linear feedback shift register
(LFSR). This intelligent pseudo-random generator limits cycle-to-cycle frequency changes to optimize output
ripple. The pseudo-random pattern repeats at less than 1.5 Hz, which is below the audio band. Spread spectrum
is disabled when the module is synchronized to an external clock or when the switching frequency decreases to
maintain regulation when operating in or close to dropout.
8.3.9 Power Good Monitor (PG)
The TPSM63606 provides a power-good status signal to indicate when the output voltage is within a regulation
window of 94% to 107%. The PG voltage goes low when the feedback (FB) voltage is outside of the specified
PGOOD thresholds (see Figure 7-6). This can occur during current limit and thermal shutdown, as well as when
disabled and during start-up.
PG is an open-drain output, requiring an external pullup resistor to a DC supply, such as VCC or VOUT. To
limit current supplied by VCC, the recommended range of pullup resistance is 20 kΩ to 100 kΩ. A 120-µs
deglitch filter prevents false flag operation for short excursions of the output voltage, such as during line and
load transients. When EN/SYNC is pulled low, PG is forced low and remains remains valid as long as the input
voltage is above 1 V (typical). Use the PG signal for start-up sequencing of downstream regulators, as shown in
Figure 8-3, or for fault protection and output monitoring.
VIN(on) = 13.9 V
VIN(off) = 10 V
VOUT2 = 3.3 V
VOUT1 = 5 V
RUV1
1 M
RFB3
PG 13
PG 13
RPG
RFB1
40.2 k
23.2 k
100 k
14
EN/SYNC
14
EN/SYNC
RUV2
FB
10
FB
10
1 V
1 V
100 k
RFB4
10 k
RFB2
10 k
Regulator #1
Regulator #2
Start-up based on
input voltage UVLO
Sequential start-up
based on PG
Figure 8-3. TPSM63606 Sequencing Implementation Using PG and EN/SYNC
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8.3.10 Adjustable Switch-Node Slew Rate (RBOOT, CBOOT)
Adjust the switch-node slew rate of the TPSM63606 to slow the switch-node voltage rise time and improve EMI
performance at high frequencies. However, slowing the rise time decreases efficiency. Care must be taken to
balance the improved EMI versus the decreased efficiency.
Internal to the module, a bootstrap resistor of 100 Ω connects between the RBOOT and CBOOT pins as shown
in Figure 8-4. Leaving these pins open incorporates the 100-Ω resistor in the bootstrap circuit, slowing the switch
voltage slew rate and optimizing EMI. However, if improved EMI is not required, connect RBOOT to CBOOT to
short the internal resistor, thus resulting in highest efficiency. Place a resistor across RBOOT and CBOOT to
allow adjustment of the internal resistance to balance EMI and efficiency performance.
VCC
7
CVCC
4
3
2
RBOOT
CBOOT
1 µF
RBOOT
100
Power
MOSFET
gate drivers
CBOOT
100 nF
SW
Figure 8-4. Internal BOOT Resistor
8.3.11 Bias Supply Regulator (VCC, VLDOIN)
VCC is the output of the internal LDO subregulator used to supply the control circuits of the TPSM63606. The
nominal VCC voltage is 3.3 V. The VLDOIN pin is the input to the internal LDO. Connect this input to VOUT to
provide the lowest possible input supply current. If the VLDOIN voltage is less than 3.1 V, VIN1 and VIN2 directly
power the internal LDO.
To prevent unsafe operation, VCC has UVLO protection that prevents switching if the internal voltage is too low.
See VCC_UVLO and VCC_UVLO_HYS in the Electrical Characteristics.
VCC must not be used to the power external circuitry. Connect a high-quality, 1-μF capacitor from VCC to GND
close to the device pins. Do not load VCC or short it to ground. VLDOIN is an optional input to the internal LDO.
Connect an optional high quality 0.1-µF to 1-µF capacitor from VLDOIN to AGND for improved noise immunity.
The LDO provides the VCC voltage from one of two inputs: VIN or VLDOIN. When VLDOIN is tied to ground
or below 3.1 V, the LDO derives power from VIN. The LDO input becomes VLDOIN when VLDOIN is tied to a
voltage above 3.1 V. The VLDOIN voltage must not exceed both VIN and 12.5 V.
Equation 8 specifies the LDO power loss reduction as:
PLDO-LOSS = ILDO × (VIN-LDO – VVCC
)
(8)
The VLDOIN input provides an option to supply the LDO with a lower voltage than VIN, thus minimizing the LDO
input voltage relative to VCC and reducing power loss. For example, if the LDO current is 10 mA at 1 MHz with
VIN = 24 V and VOUT = 5 V, the LDO power loss with VLDOIN tied to ground is 10 mA × (24 V – 3.3 V) = 207
mW, while the loss with VLDOIN tied to VOUT is equal to 10 mA × (5 V – 3.3 V) = 17 mW – a reduction of 190
mW.
Figure 8-5 and Figure 8-6 show typical efficiency plots with and without VLDOIN connected to VOUT.
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100
100
95
90
85
80
75
70
95
90
85
80
75
VVLDOIN = VOUT
VVLDOIN = GND
VVLDOIN = VOUT
VVLDOIN = GND
70
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Output Current (A)
Output Current (A)
VIN = 24 V
VOUT = 5 V
FSW = 1 MHz
VIN = 36 V
VOUT = 5 V
FSW = 1 MHz
Figure 8-5. Efficiency Increase With External Bias Figure 8-6. Efficiency Increase With External Bias
8.3.12 Overcurrent Protection (OCP)
The TPSM63606 is protected from overcurrent conditions using cycle-by-cycle current limiting of the peak
inductor current. The current is compared every switching cycle to the current limit threshold. During an
overcurrent condition, the output voltage decreases.
The TPSM63606 employs hiccup overcurrent protection if there is an extreme overload. In hiccup mode,
the TPSM63606 module is shut down and kept off for 80 ms (typical) before a restart is attempted. If an
overcurrent or short-circuit fault condition still exists, hiccup repeats until the fault condition is removed. Hiccup
mode reduces power dissipation under severe overcurrent conditions, thus preventing overheating and potential
damage to the device. Once the fault is removed, the module automatically recovers and returns to normal
operation.
8.3.13 Thermal Shutdown
Thermal shutdown is an integrated self-protection used to limit junction temperature and prevent damage related
to overheating. Thermal shutdown turns off the device when the junction temperature exceeds 168°C (typical) to
prevent further power dissipation and temperature rise. Junction temperature decreases after shutdown, and the
TPSM63606 attempts to restart when the junction temperature falls to 158°C (typical).
8.4 Device Functional Modes
8.4.1 Shutdown Mode
The EN/SYNC pin provides ON and OFF control for the TPSM63606. When VEN/SYNC is below approximately
0.4 V, the device is in shutdown mode. Both the internal LDO and the switching regulator are off. The quiescent
current in shutdown mode drops to 0.6 µA (typical). The TPSM63606 also employs internal undervoltage
protection. If the input voltage is below its UV threshold, the regulator remains off.
8.4.2 Standby Mode
The internal LDO for the VCC bias supply has a lower enable threshold than the regulator itself. When VEN/SYNC
is above 1.1 V (maximum) and below the precision enable threshold of 1.263 V (typical), the internal LDO is on
and regulating. The precision enable circuitry is turned on once the internal VCC is above its UVLO threshold.
The switching action and voltage regulation are not enabled until VEN/SYNC rises above the precision enable
threshold.
8.4.3 Active Mode
The TPSM63606 is in active mode when VVCC and VEN/SYNC are above their relevant thresholds and no fault
conditions are present. The simplest way to enable operation is to connect EN/SYNC to VIN, which allows self
start-up when the applied input voltage exceeds the minimum start-up voltage.
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9 Applications and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The TPSM63606 synchronous buck module requires only a few external components to convert from a wide
range of supply voltages to a fixed output voltage at an output current up to of 6 A. To expedite and streamline
the process of designing of a TPSM63606-based regulator, a comprehensive TPSM63606 quickstart calculator
is available by download to assist the system designer with component selection for a given application.
9.2 Typical Applications
For the circuit schematic, bill of materials, PCB layout files, and test results of a TPSM63606-powered
implementation, see the TPSM63606 EVM.
9.2.1 Design 1 – High-Efficiency 6-A Synchronous Buck Regulator for Industrial Applications
Figure 9-1 shows the schematic diagram of a 5-V, 6-A buck regulator with a switching frequency of 1 MHz.
In this example, the target half-load and full-load efficiencies are 93.5% and 91.4%, respectively, based on a
nominal input voltage of 24 V that ranges from 9 V to 36 V. A resistor RRT of 13 kΩ sets the free-running
switching frequency at 1 MHz. An optional SYNC input signal allows adjustment of the switching frequency from
700 kHz to 1.4 MHz for this specific application.
VIN = 9 V to 36 V
VIN(on) = 6 V
VIN(off) = 4.3 V
VIN1
VIN2
CIN1
10
CIN2
10
F
F
PGND
PGND
RENT
Optional
synchronization
374 k
TPSM63606
CSYNC
Optional
external bias
VOUT = 5 V
IOUT(max) = 6 A
SYNC
EN/SYNC
VLDOIN
VOUT1
VOUT2
1 nF
VCC
RENB
optional
RPG
100 k
100 k
COUT
CFF
22 pF
RFBT
CBOOT
RBOOT
FB
2 ꢀ 47
F
PG
RT
40.2 k
PGOOD
indicator
RRT
RFBB
10 k
AGND
13 k
Figure 9-1. Circuit Schematic
9.2.1.1 Design Requirements
Table 9-1 shows the intended input, output, and performance parameters for this application example. Note
that if the input voltage decreases below approximately 5.8 V, the regulator operates in dropout with the output
voltage below its 5-V setpoint.
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Table 9-1. Design Parameters
DESIGN PARAMETER
VALUE
Input voltage range
Input voltage UVLO turn on, off
Output voltage
9 V to 36 V
6 V, 4.3 V
5 V
Maximum output current
Switching frequency
6 A
1 MHz
±1%
Output voltage regulation
Module shutdown current
< 1 µA
Table 9-2 gives the selected buck module power-stage components with availability from multiple vendors. This
design uses an all-ceramic output capacitor implementation.
Table 9-2. List of Materials for Application Circuit 1
REFERENCE
DESIGNATOR
QTY
SPECIFICATION
MANUFACTURER(1)
PART NUMBER
Taiyo Yuden
TDK
UMJ325KB7106KMHT
CNA6P1X7R1H106K
GCM32EC71H106KA03
CGA6P3X7S1H106M
GRM32ER70J476ME20K
12106C476MAT2A
10 µF, 50 V, X7R, 1210, ceramic
CIN1, CIN2
2
Murata
TDK
10 µF, 50 V, X7S, 1210, ceramic
47 µF, 6.3 V, X7R, 1210, ceramic
47 µF, 10 V, X7R, 1210, ceramic
Murata
AVX
COUT1, COUT2
2
1
Murata
AVX
GRM32ER71A476ME15L
1210ZC476MAT2A
100 µF, 6.3 V, X7S, 1210, ceramic
TDK
GRM32EC70J107ME15L
TPSM63606RDLR
U1
TPSM63606 36-V, 6-A synchronous buck module
Texas Instruments
(1) See the Third-Party Products Disclaimer.
More generally, the TPSM63606 module is designed to operate with a wide range of external components
and system parameters. However, the integrated loop compensation is optimized for a certain range of output
capacitance.
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPSM63606 module with WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance.
Run thermal simulations to understand board thermal performance.
Export customized schematic and layout into popular CAD formats.
Print PDF reports for the design, and share the design with colleagues.
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
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9.2.1.2.2 Output Voltage Setpoint
The output voltage of a TPSM63606 module is externally adjustable using a resistor divider. A recommended
value for RFBB of 10 kΩ establishes a divider current of 0.1 mA. Select the value for RFBT from Table 8-1 or
calculate using Equation 9:
(9)
Choose the closest standard value of 40.2 kΩ for RFBT
.
9.2.1.2.3 Switching Frequency Selection
Connect a 13-kΩ resistor from RT to AGND to set a switching frequency of 1 MHz, which is ideal for an output of
5 V as it establishes an inductor peak-to-peak ripple current in the range of 20% to 40% of the 6-A rated output
current at a nominal input voltage of 24 V.
9.2.1.2.4 Input Capacitor Selection
The TPSM63606 requires a minimum input capacitance of 2 × 10-µF ceramic, preferably with X7R dielectric.
The voltage rating of input capacitors must be greater than the maximum input voltage. For this design, select
two 10-µF, X7R, 50-V, 1210 case size, ceramic capacitors connected from VIN1 and VIN2 to PGND as close as
possible to the module. See Figure 11-2 for recommneded layout placement.
9.2.1.2.5 Output Capacitor Selection
The TPSM63606 requires a minimum of 25 µF of effective output capacitance for proper operation at an output
voltage of 5 V. Use high-quality ceramic type capacitors with sufficient voltage and temperature rating. If needed,
connect additional output capacitance to reduce ripple voltage or for applications with specific load transient
requirements.
For this design example, use two 47-µF, 6.3-V or 10-V, X7R, 1210, ceramic capacitors connected close to the
module from the VOUT1 and VOUT2 pins to PGND. The total effective capacitance at 5 V is approximately
52 µF and 38 µF at 25°C and –40°C, respectively.
9.2.1.2.6 Other Connections
Short RBOOT to CBOOT and connect VLDOIN to the 5-V output for best efficiency. To increase phase margin
when using an output capacitance close to the minimum recommende in Table 8-1, use a feedforward capacitor,
designated as CFF in Figure 9-1, across the upper feedback resistor. Based on the feedback resistor values in
this application, a capacitor of 22 pF sets a zero-pole pair at 180 kHz and 900 kHz, respectively.
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9.2.1.3 Application Curves
Unless otherwise indicated, VIN = 24 V, VOUT = 5 V, IOUT = 6 A (0.83-Ω resistive load), and FSW = 1 MHz.
100
95
90
85
80
75
70
5.05
5.025
5
4.975
4.95
VIN = 12 V
VIN = 24 V
VIN = 36 V
VIN = 12 V
VIN = 24 V
VIN = 36 V
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Output Current (A)
Output Current (A)
Figure 9-3. Load Regulation
Figure 9-2. Efficiency
EN 2 V/DIV
VIN 5 V/DIV
VOUT 5 V/DIV
PG 5 V/DIV
VOUT 5 V/DIV
PG 5 V/DIV
4 ms/DIV
4 ms/DIV
Figure 9-5. Enable ON and OFF, VIN = 12 V
Figure 9-4. Startup, VIN Stepped to 12 V
IOUT 2 A/DIV
IOUT 2 A/DIV
VOUT 0.1 V/DIV
VOUT 0.1 V/DIV
80 ꢀs/DIV
80 ꢀs/DIV
Figure 9-6. Load Transient, 3 A to 6 A, 1 A/µs
Figure 9-7. Load Transient, 0 A to 3 A, 1 A/µs
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QP detector
QP detector
AVG detector
AVG detector
Figure 9-9. CISPR 32 Class B Conducted
Emissions: VIN = 24 V
Figure 9-8. CISPR 32 Class B Conducted
Emissions: VIN = 12 V
QPK detector
QPK detector
Figure 9-10. CISPR 32 Class B Radiated
Emissions: Horizontal Polarization
Figure 9-11. CISPR 32 Class B Radiated
Emissions: Vertical Polarization
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9.2.2 Design 2 – Inverting Buck-Boost Regulator with –12-V Output
Figure 9-12 shows the schematic diagram of an inverting buck-boost (IBB) regulator with an output of –12 V at
–2.5 A and a switching frequency of 2 MHz. In this example, the target half-load and full-load efficiencies are
91.5% and 90.5%, respectively, based on a nominal input voltage of 12 V that ranges from 9 V to 24 V.
VIN+
U1
CIN3
10
VIN1
VIN2
VIN = 9 V to 24 V
VIN–
VIN(on) = 8.9 V
F
CIN1
10
CIN2
10
F
F
PGND
PGND
RENT
604 k
–VOUT
–VOUT
TPSM63606
Optional
external bias
Precision
enable for
VIN UVLO
EN/SYNC
VLDOIN
VOUT+
VOUT1
VOUT2
VCC
RENB
100 k
VOUT = –12 V
IOUT(max) = –2.5 A
COUT
CBOOT
RBOOT
FB
RFBT
2 ꢀ 22
F
PG
RT
110 k
–VOUT
VOUT–
–VOUT
RRT
6.34 k
RFBB
10 k
AGND
–VOUT
Figure 9-12. Circuit Schematic
9.2.2.1 Design Requirements
Table 9-3 shows the intended input, output, and performance parameters for this application example. With an
IBB topology, the module sees a total current of IIN + |–IOUT|, which is highest at minimum input voltage.
Table 9-3. Design Parameters
DESIGN PARAMETER
Input voltage range
Input voltage UVLO turn on
Output voltage
VALUE
9 V to 24 V
8.9 V
–12 V
Full-load current
–2.5 A
2 MHz
±1%
Switching frequency
Output voltage regulation
Table 9-4 gives the selected buck module power-stage components with availability from multiple vendors. This
design uses an all-ceramic output capacitor implementation.
Table 9-4. List of Materials for Application Circuit 2
REF DES
QTY
SPECIFICATION
10 µF, 50 V, X7R, 1210, ceramic
22 µF, 16 V, X7R, 1206, ceramic
22 µF, 25 V, X7R, 1210, ceramic
MANUFACTURER(1)
PART NUMBER
C1210C106K5RACTU
CNA6P1X7R1H106K
GRM31CZ71C226ME15L
GRM32ER71E226ME15L
12103C226KAT4A
Kemet
CIN1, CIN2, CIN3
3
TDK
Murata
Murata
COUT1, COUT2
2
1
AVX
47 µF, 16 V, X6S, 1210, ceramic
Murata
GRM32EC81C476ME15L
TPSM63606RDLR
U1
TPSM63606 36-V, 6-A synchronous buck module
Texas Instruments
(1) See the Third-Party Products Disclaimer.
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9.2.2.2 Detailed Design Procedure
9.2.2.2.1 Output Voltage Setpoint
For an output voltage of –12 V, choose upper and lower feedback resistance of 110 kΩ and 10 kΩ, respectively,
using Equation 1 or from Table 8-1.
9.2.2.2.2 IBB Maximum Output Current
The achievable output current with an IBB topology using the TPSM63606 is IOUT(max) = ILDC(max) × (1 – D),
where ILDC(max) = 6 A is the rated current of the module and D = |VOUT| / (VIN + |VOUT|) is the module duty cycle.
Figure 9-13 shows the maximum IBB output current as a function of input voltage for output voltages of –5 V and
–12 V.
9.2.2.2.3 Switching Frequency Selection
Connect a 6.34-kΩ resistor from RT to AGND to set a switching frequency of 2 MHz, which is ideal for an output
of –12 V as it establishes an inductor peak-to-peak ripple current of approximately 40% of the 6-A rated module
current at the nominal input voltage of 12 V.
9.2.2.2.4 Input Capacitor Selection
Use two 10-µF, 50-V, X7R-dielectric ceramic capacitors in 1210 case size connected symmetrically from the
VIN1 and VIN2 pins to PGND as close as possible to the module. More specifically, these capacitors appear
from the drain of the internal high-side MOSFET to the source of the low-side MOSFET, effectively connecting
from the positive input voltage to the negative output voltage terminals.
The sum of the input and output voltages, VIN + |–VOUT|, is the effective applied voltage across the capacitors.
The total effective capacitance at input voltages of 12 V and 24 V (corresponding to applied voltages of 24 V and
36 V) is approximately 17 µF and 14 µF, respectively. Check the capacitance versus voltage derating curve in
the data sheet of the capacitor vendor.
Use an additional 10-µF, 50-V capacitor directly across the input. This capacitor is designated as CIN3 and
connects across the VIN+ and VIN– terminals as shown in Figure 9-12.
9.2.2.2.5 Output Capacitor Selection
For this IBB design example, use two 22-µF, 25-V, X7R-dielectric ceramic capacitors in 1210 case size
connected symmetrically close to the module from the VOUT1 and VOUT2 pins to PGND. The total effective
capacitance is approximately 16 µF with 12 V DC bias.
9.2.2.2.6 Other Considerations
Short RBOOT to CBOOT and connect VLDOIN to the power stage GND terminal (corresponding to VOUT1,
VOUT2 of the module) for best efficiency.
The right-half-plane zero of an IBB topology is at its lowest freqeuncy at minimum input voltage. However, it
does not appear at low frequency for a –12-V output and thus has minimal effect on the loop response for this
application.
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9.2.2.3 Application Curves
Unless otherwise indicated, VIN = 12 V, VOUT = –12 V, and FSW = 2 MHz.
6
5
4
3
2
1
0
95
90
85
80
75
70
65
VIN = 12 V
VIN = 24 V
VOUT = -5 V
VOUT = -12 V
0
0.5
1
1.5
2
2.5
0
3
6
9
12
15
18
21
24
27
30
Output Current (A)
Input Voltage (V)
Figure 9-14. Efficiency
Figure 9-13. IBB Maximum Output Current
-11.9
-11.95
-12
IOUT 2 A/DIV
-12.05
VOUT 0.1 V/DIV
VIN = 12 V
VIN = 24 V
-12.1
0
0.5
1
1.5
2 2.5
80 ꢀs/DIV
Output Current (A)
Figure 9-15. Load Regulation
Figure 9-16. Load Transient, 0 A to 2.5 A
IOUT 2 A/DIV
VOUT 0.1 V/DIV
80 ꢀs/DIV
Figure 9-17. Load Transient, 1.25 A to 2.5 A
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10 Power Supply Recommendations
The TPSM63606 buck module is designed to operate over a wide input voltage range of 3 V to 36 V. The
characteristics of the input supply must be compatible with the Absolute Maximum Ratings and Recommended
Operating Conditions in this data sheet. In addition, the input supply must be capable of delivering the required
input current to the loaded regulator circuit. Estimate the average input current with Equation 10.
VOUT ∂IOUT
IIN
=
V ∂ h
IN
(10)
where
•
η is the efficiency.
If the module is connected to an input supply through long wires or PCB traces with a large impedance, take
special care to achieve stable performance. The parasitic inductance and resistance of the input cables can
have an adverse affect on module operation. More specifically, the parasitic inductance in combination with the
low-ESR ceramic input capacitors form an underdamped resonant circuit, possibly resulting in instability and/or
voltage transients each time the input supply is cycled ON and OFF. The parasitic resistance causes the input
voltage to dip during a load transient. If the module is operating close to the minimum input voltage, this dip can
cause false UVLO triggering and a system reset.
The best way to solve such issues is to reduce the distance from the input supply to the module and use an
electrolytic input capacitor in parallel with the ceramics. The moderate ESR of the electrolytic capacitor helps
damp the input resonant circuit and reduce any overshoot or undershoot at the input. A capacitance in the range
of 47 μF to 100 μF is usually sufficient to provide input parallel damping and helps hold the input voltage steady
during large load transients. A typical ESR of 0.1 Ω to 0.4 Ω provides enough damping for most input circuit
configurations.
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11 Layout
Proper PCB design and layout is important in high-current, fast-switching module circuits (with high internal
voltage and current slew rates) to achieve reliable device operation and design robustness. Furthermore, the
EMI performance of the module depends to a large extent on PCB layout.
11.1 Layout Guidelines
The following list summarizes the essential guidelines for PCB layout and component placement to optimze
DC/DC module performance, including thermals and EMI signature. Figure 11-1 and Figure 11-2 show a
recommended PCB layout for the TPSM63606 with optimized placement and routing of the power-stage and
small-signal components.
1. Place input capacitors as close as possible to the VIN pins. Note the dual and symmetrical arrangement of
the input capacitors based on the VIN1 and VIN2 pins located on each side of the module package. The
high-freqeuency currents are split in two and effectively flow in opposing directions such that the related
magnetic fields contributions cancel each other, leading to improved EMI performance.
•
•
•
Use low-ESR 1206 or 1210 ceramic capacitors with X7R or X7S dielectric. The module has integrated
dual 0402 input capacitors for high-frequency bypass.
Ground return paths for the input capacitors should consist of localized top-side planes that connect to
the PGND pads under the module.
Even though the VIN pins are connected internally, use a wide polygon plane on a lower PCB layer to
connect these pins together and to the input supply.
2. Place output capacitors as close as possible to the VOUT pins. A similar dual and symmetrical arrangement
of the output capacitors enables magnetic field cancellation and EMI mitigation.
•
Ground return paths for the output capacitors should consist of localized top-side planes that connect to
the PGND pads under the module.
•
Even though the VOUT pins are connected internally, use a wide polygon plane on a lower PCB layer to
connect these pins together and to the load, thus reducing conduction loss and thermal stress.
3. Keep the FB trace as short as possible by placing the feedback resistors close to the FB pin. Reduce noise
sensitivity of the output voltage feedback path by placing the resistor divider close to the FB pin, rather than
close to the load. FB is the input to the voltage-loop error anplifier and represents a high-impedance node
sensitive to noise. Route a trace from the upper feedback resistor to the required point of output voltage
regulation.
4. Use a solid ground plane on the PCB layer directly below the top layer with the module. This plane acts as
a noise shield by minimizing the magnetic fields associated with the currents in the switching loops. Connect
AGND pins 6 and 11 directly to PGND pin 19 under the module.
5. Provide enough PCB area for proper heatsinking. Use sufficient copper area to acheive a low thermal
impedance commensurate with the maximum load current and ambient temperature conditions. Provide
adequate heatsinking for the TPSM63606 to keep the junction temperature below 150°C. For operation at
full rated load, the top-side ground plane is an important heat-dissipating area. Use an array of heat-sinking
vias to connect the exposed pads (PGND) of the package to the PCB ground plane. If the PCB has multiple
copper layers, connect these thermal vias to inner-layer ground planes. Make the top and bottom PCB layers
preferably with two-ounce copper thickness (and no less than one ounce).
11.1.1 Thermal Design and Layout
For a DC/DC module to be useful over a particular temperature range, the package must allow for the efficient
removal of the heat produced while keeping the junction temperature within rated limits. The TPSM63606
module is available in a small 5.5-mm × 5-mm 20-pin QFN (RDL) package to cover a range of application
requirements. The Thermal Information table summarizes the thermal metrics of this package with related detail
provided by the Semiconductor and IC Package Thermal Metrics Application Report.
The 20-pin QFN package offers a means of removing heat through the exposed thermal pads at the base of
the package. This allows a significant improvement in heatsinking, and it becomes imperative that the PCB
is designed with thermal lands, thermal vias, and one or more ground planes to complete the heat removal
subsystem. The exposed pads of the TPSM63606 are soldered to the ground-connected copper lands on the
PCB directly underneath the device package, reducing the thermal resistance to a very low value.
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Preferably, use a four-layer board with 2-oz copper thickness for all layers to provide low impedance, proper
shielding and lower thermal resistance. Numerous vias with a 0.3-mm diameter connected from the thermal
lands to the internal and solder-side ground planes are vital to promote heat transfer. In a multi-layer PCB
stack-up, a solid ground plane is typically placed on the PCB layer below the power-stage components. Not only
does this provide a plane for the power-stage currents to flow, but it also represents a thermally conductive path
away from the heat-generating device.
11.2 Layout Example
Figure 11-1. Typical Layout
Place the feedback
components close to the FB pin
Legend
Top layer copper
EN
Layer-2 GND plane
RT
VIN
VIN
VOUT
Input
capacitor
Top solder
Output
capacitor
FB
Position the input
capacitors very close
to the VIN pins
Place an array of
PGND vias close to the
IC for heat spreading
PGND
Input
capacitor
Output
capacitor
VOUT
Place thermal vias at the
VOUT pins for heat spreading
Figure 11-2. Typical Top Layer Design
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11.2.1 Package Specifications
Table 11-1. Package Specifications Table
TPSM63606
VALUE
UNIT
Flammability
Meets UL 94 V-0
MTBF calculated reliability
Per Bellcore TR-332, 50% stress, TA = 40°C, ground benign
2580
MHrs
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.1.2 Development Support
With an input operating voltage from 3 V to 36 V and rated output current from 2 A to 6 A, the TPSM63602/3/4/6
family of synchronous buck power modules specified in Table 12-1 provides flexibility, scalability and optimized
solution size for a range of applications. These modules enable DC/DC solutions with high density, low EMI
and increased flexibility. Available EMI mitigation features include pseudo-random spread spectrum (PRSS),
RBOOT-configured switch-node slew rate control, and integrated input bypass capacitors. All modules are rated
for an ambient temperature up to 105°C.
Table 12-1. Synchronous Buck DC/DC Power Module Family
DC/DC MODULE
TPSM63602
TPSM63603
TPSM63604
TPSM63606
RATED IOUT PACKAGE
DIMENSIONS
FEATURES
EMI MITIGATION
2 A
B0QFN (30)
3 A
6.0 × 4.0 × 1.8 mm
PRSS, RBOOT, integrated
input, VCC and BOOT
capacitors
RT adjustable FSW
external synchronization
,
4 A
B3QFN (20)
6 A
5.5 × 5.0 × 4.0 mm
For development support see the following:
•
•
•
•
•
•
•
•
•
TPSM63606 Quickstart Calculator
TPSM63606 Simulation Models
TPSM63606 and TPSM63606S EVM User's Guide
TPSM63606 Altium Layout Design Files
For TI's reference design library, visit the TI Reference Design library.
For TI's WEBENCH Design Environment, visit the WEBENCH® Design Center.
To design a low-EMI power supply, review TI's comprehensive EMI Training Series.
To design an inverting buck-boost (IBB) regulator, visit DC/DC inverting buck-boost modules.
TI Reference Designs:
– Multiple Output Power Solution For Kintex 7 Application
– Arria V Power Reference Design
– Altera Cyclone V SoC Power Supply Reference Design
– Space-optimized DC/DC Inverting Power Module Reference Design With Minimal BOM Count
– 3- To 11.5-VIN, –5-VOUT, 1.5-A Inverting Power Module Reference Design For Small, Low-noise Systems
Technical Articles:
– Powering Medical Imaging Applications With DC/DC Buck Converters
– How To Create A Programmable Output Inverting Buck-boost Regulator
To view a related device of this product, see the LM61460 36-V, 6-A synchronous buck converter.
•
•
12.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPSM63606 module with WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
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•
•
•
•
Run electrical simulations to see important waveforms and circuit performance.
Run thermal simulations to understand board thermal performance.
Export customized schematic and layout into popular CAD formats.
Print PDF reports for the design, and share the design with colleagues.
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation, see the following:
•
•
Texas Instruments, Innovative DC/DC Power Modules selection guide
Texas Instruments, Enabling Small, Cool and Quiet Power Modules with Enhanced HotRod™ QFN Package
Technology white paper
•
•
•
•
•
•
•
•
•
Texas Instruments, Benefits and Trade-offs of Various Power-Module Package Options white paper
Texas Instruments, Simplify Low EMI Design with Power Modules white paper
Texas Instruments, Power Modules for Lab Instrumentation white paper
Texas Instruments, An Engineer's Guide To EMI In DC/DC Regulators e-book
Texas Instruments, Soldering Considerations for Power Modules application report
Texas Instruments, Practical Thermal Design With DC/DC Power Modules application report
Texas Instruments, Using New Thermal Metrics application report
Texas Instruments, AN-2020 Thermal Design By Insight, Not Hindsight application report
Texas Instruments, Using the TPSM53602/3/4 for Negative Output Inverting Buck-Boost Applications
application report
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
HotRod™ and TI E2E™ are trademarks of Texas Instruments.
WEBENCH® are registered trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this datasheet, refer to the left-hand navigation.
Copyright © 2021 Texas Instruments Incorporated
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TPSM63606
SLVSGB4 – OCTOBER 2021
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PACKAGE OUTLINE
B3QFN - 4.1 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RDL0020A
5.1
4.9
A
B
5.6
5.4
PIN 1 INDEX AREA
4.1
3.9
C
SEATING PLANE
0.08
C
1.63
1.53
4X
1.3
1.1
4X
(0.20) TYP
PKG
(0.2) TYP
8
9
0.92
0.82
0.875
20
4X
0.35
0.15
0.1
12X
1.275
PKG
19
18
C
A B
0.05
C
2X (0.537)
2X (1.612)
10X 0.5
17
16
1
0.925
0.6
0.4
4X
0.8
0.1
C
A B
12X
0.6
PIN 1 ID
(OPTIONAL)
0.05
C
4226416/B 04/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
B3QFN - 4.1 mm max height
RDL0020A
PLASTIC QUAD FLAT PACK- NO LEAD
PKG
4X (1.4)
(Ø0.2) VIA
TYP
4X (0.5)
(0.5) TYP
16
1
2X (0.925)
17
10X (0.25)
(1.075) TYP
18
PKG
2X (0.538)
10X (0.50)
19
4X (0.875)
20
10X (0.9)
2X (0.875)
8
9
(R0.05) TYP
4X (1.58)
(4)
(4.5)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
0.05 MAX
ALL AROUND
0.05 MAX
ALL AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL EDGE
SOLDER MASK
DEFINED
NON- SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4226416/B 04/2021
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
B3QFN - 4.1 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RDL0020A
PKG
4X (1.35)
4X (0.45)
16
1
2X (0.925)
17
10X (0.2)
(1.075) TYP
18
PKG
2X (0.538)
10X (0.5)
19
4X (0.825)
10X (0.85)
20
2X (0.875)
8
9
4X (1.53)
(4)
(R0.05) TYP
(4.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17,18, 19 & 20 :
91% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X
4226416/B 04/2021
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OPTION ADDENDUM
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12-Oct-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PTPSM63606RDLR
ACTIVE
B3QFN
RDL
20
3000
TBD
Call TI
Call TI
-40 to 125
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
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TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
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