TPSM82813SSIL [TI]
TPSM8281x 2.75-V to 6-V Adjustable-Frequency Step-Down Converter with Integrated Inductor;
| 型号： | TPSM82813SSIL |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TPSM8281x 2.75-V to 6-V Adjustable-Frequency Step-Down Converter with Integrated Inductor |
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| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPSM82810, TPSM82813
SLUSDN6 –SEPTEMBER 2019
TPSM8281x 2.75-V to 6-V Adjustable-Frequency Step-Down Converter with Integrated
Inductor
1 Features
3 Description
TPSM8281x is a family of pin-to-pin 3-A and 4-A high
efficiency and easy to use synchronous step-down
DC/DC converters. They are based on a peak current
mode control topology. They are designed for
Telecommunication, Test and Measurement and
Medical applications with high power density and
ease of use requirements. Low resistive switches
allow up to 4-A continuous output current at high
ambient temperature. The switching frequency is
externally adjustable from 1.8 MHz to 4 MHz and can
also be synchronized to an external clock in the same
frequency range. In PWM/PFM mode, TPSM8281x
automatically enters Power Save Mode at light loads
to maintain high efficiency across the whole load
range. TPSM8281x provides a 1% output voltage
accuracy in PWM mode which helps design a power
supply with high output voltage accuracy. The SS/TR
pin allows setting the start-up time or forming tracking
of the output voltage to an external source. This
allows external sequencing of different supply rails
and limiting the inrush current during start-up.
1
•
•
•
•
•
•
•
•
Input voltage range: 2.75 V to 6 V
3-A and 4-A versions
Quiescent current 15-µA typical
Output voltage from 0.6 V to 5.5 V
Output voltage accuracy ±1% (PWM operation)
Adjustable soft-start
Forced PWM or PWM/PFM operation
Adjustable switching frequency of
1.8 MHz to 4 MHz
•
Precise ENABLE input allows
–
–
User-defined undervoltage lockout
Exact sequencing
•
•
•
•
100% duty cycle mode
Active output discharge
Spread spectrum clocking - optional
Power good output with window comparator
The TPSM8281x is available as an adjustable
version, packaged in a 3-mm x 4-mm µSil module
with integrated inductor.
2 Applications
•
•
•
•
•
Macro BTS and cloud RAN
Microwave transmission system and backhaul
Instrumentation
Device Information(1)
PART NUMBER
TPSM82810
PACKAGE
BODY SIZE (NOM)
Patient monitoring and diagnostics
Optical networking
µSil
3-mm x 4-mm
TPSM82813
µSil
3-mm x 4-mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Schematic
Efficiency vs Output Current; VOUT = 3.3 V;
PWM/PFM; fS = 2.25 MHz
TPSM82810
V
IN
2.75 V - 6 V
VOUT
VIN
VOUT
100
95
90
85
80
75
70
65
CIN
22 mF
R1
R2
CFF
EN
FB
COUT
47 mF
MODE/SYNC
R3
COMP/FSET
SS/TR
CSS
PG
GND
60
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
55
50
Copyright © 2019, Texas Instruments Incorporated
100m
1m
10m 100m
Output Current (A)
1
4
D002
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to
change without notice.
TPSM82810, TPSM82813
SLUSDN6 –SEPTEMBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings ............................................................ 5
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information ................................................. 5
7.5 Electrical Characteristics........................................... 5
7.6 Typical Characteristics.............................................. 7
Parameter Measurement Information .................. 8
8.1 Schematic ................................................................. 8
Detailed Description .............................................. 9
9.1 Overview ................................................................... 9
9.2 Functional Block Diagram ......................................... 9
9.3 Feature Description................................................. 10
9.4 Device Functional Modes........................................ 12
10 Application and Implementation........................ 14
10.1 Application Information.......................................... 14
10.2 Typical Application ............................................... 15
10.3 System Examples ................................................. 28
10.4 Do's and Don'ts (Recommended)......................... 30
11 Power Supply Recommendations ..................... 31
12 Layout................................................................... 31
12.1 Layout Guidelines ................................................. 31
12.2 Layout Example .................................................... 31
13 Device and Documentation Support ................. 32
13.1 Device Support...................................................... 32
13.2 Documentation Support ........................................ 32
13.3 Related Links ........................................................ 32
13.4 Receiving Notification of Documentation Updates 32
13.5 Community Resources.......................................... 32
13.6 Trademarks........................................................... 32
13.7 Electrostatic Discharge Caution............................ 32
13.8 Glossary................................................................ 32
8
9
14 Mechanical, Packaging, and Orderable
Information ........................................................... 33
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
REVISION
NOTES
September 2019
*
Advance Information release.
2
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SLUSDN6 –SEPTEMBER 2019
5 Device Comparison Table
DEVICE NUMBER
FEATURES
OUTPUT VOLTAGE
4 A output current
spread spectrum clocking = OFF
TPSM82810SIL
adjustable
4 A output current
spread spectrum clocking = ON
TPSM82810SSIL
TPSM82813SIL
TPSM82813SSIL
adjustable
adjustable
adjustable
3 A output current
spread spectrum clocking = OFF
3 A output current
spread spectrum clocking = ON
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6 Pin Configuration and Functions
µSil Package
14 Pin (µSil)
Top View
TOP VIEW
BOTTOM VIEW
9
10
9
8
7
6
6
7
8
10
FB
FB
GND
GND
GND
GND
14
GND
14
11
13
12
13
12
GND
GND
GND
11
VIN
VIN
VIN
VIN
VIN
VOUT
VOUT
VIN
EN
2
PG
PG
EN
1
3
5
5
3
2
1
4
4
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
2
This is the enable pin of the device. Connect to logic low to disable the device. Pull high to
enable the device. Do not leave this pin unconnected.
EN
I
I
FB
7
Voltage feedback input, connect the resistive output voltage divider to this pin.
Ground pin
GND
6, 10, 13, 14
4
The device runs in PFM/PWM mode when this pin is pulled low. When the pin is pulled high,
the device runs in forced PWM mode. Do not leave this pin unconnected. The mode pin can
also be used to synchronize the device to an external frequency. See the electrical
characteristics for the detailed specification for the digital signal applied to this pin for
external synchronization.
MODE/SYNC
COMP/FSET
I
I
Device compensation and frequency set input. A resistor from this pin to GND defines the
compensation of the control loop as well as the switching frequency if not externally
synchronized. If the pin is tied to GND or VIN, the switching frequency is set to 2.25MHz. Do
not leave this pin unconnected.
9
Open drain power good output. Low impedance when not "power good", high impedance
when "power good". This pin can be left open or tied to GND if not used.
PG
3
8
O
I
Soft-Start / Tracking pin. A capacitor connected from this pin to GND defines the rise time for
the internal reference voltage. The pin can also be used as an input for tracking and
sequencing - see the application section in this data sheet.
SS/TR
VOUT
VIN
5
Output voltage pin. This pin is internally connected to the integrated inductor.
Power supply input. Connect the input capacitor as close as possible between pin VIN and
GND.
1, 11, 12
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
-0.3
-0.3
-0.3
-0.3
-0.3
-40
MAX
6.5
UNIT
V
VIN
VOUT
6.5
V
Pin voltage range(1)
FB
4
V
PG, SS/TR, COMP/FSET
VIN+0.3
6.5
V
Pin voltage range(1)
EN, MODE/SYNC
V
Storage temperature, Tstg
125
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
4
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SLUSDN6 –SEPTEMBER 2019
7.2 ESD Ratings
VALUE
UNIT
(1)
±2000
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
Charged device model (CDM), per JEDEC specification
JESD22- V
V(ESD)
Electrostatic discharge
V
±500
(2)
C101
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
2.75
0.6
27
NOM
MAX
6
UNIT
VIN
Supply voltage range
V
VOUT
COUT
CIN
Output voltage range
5.5
470
V
Effective output capacitance(1)
Effective input capacitance(1)
47
10
µF
µF
kΩ
°C
°C
5
RFSET
TJ
4.5
-40
-40
100
150
125
Operating junction temperature
Operating inductor temperature
Tind
(1) The values given for all the capacitors in the table are effective capacitance, which includes the DC bias effect. Due to the DC bias
effect of ceramic capacitors, the effective capacitance is lower than the nominal value when a voltage is applied. Please check the
manufacturer´s DC bias curves for the effective capacitance vs DC voltage applied. Further restrictions may apply. Please see the
feature description for COMP/FSET about the output capacitance vs compensation setting and output voltage.
7.4 Thermal Information
TPS82810
THERMAL METRIC(1)
µSil
14 PINS
67.5
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-board characterization parameter
°C/W
°C/W
ψJB
19.2
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
over operating junction temperature (TJ = -40 °C to +125 °C) and VIN = 2.7 V to 6 V. Typical values at VIN = 5 V and TJ = 25
°C. (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
EN = high, IOUT= 0 mA, Device not switching,
TJ= 125 °C
IQ
Operating Quiescent Current
21
µA
IQ
Operating Quiescent Current EN = high, IOUT= 0 mA, Device not switching
15
30
18
µA
µA
ISD
Shutdown Current
EN = 0 V, at TJ= 125 °C
EN = 0 V, Nominal value at TJ= 25 °C,
Max value at TJ= 150 °C
ISD
Shutdown Current
1.5
26
µA
Rising Input Voltage
Falling Input Voltage
2.5
2.6
2.5
2.75
2.6
V
V
Undervoltage Lockout
Threshold
VUVLO
2.25
Thermal Shutdown
Temperature
Rising Junction Temperature
170
15
TSD
°C
Thermal Shutdown Hysteresis
CONTROL (EN, SS/TR, PG, MODE)
High Level Input Voltage for
MODE Pin
VIH
1.1
1.8
V
V
Low Level Input Voltage for
MODE Pin
VIL
0.3
4
Frequency Range on MODE
Pin for Synchronization
requires a resistor from COMP/FSET to GND, see
application section
fSYNC
MHz
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Electrical Characteristics (continued)
over operating junction temperature (TJ = -40 °C to +125 °C) and VIN = 2.7 V to 6 V. Typical values at VIN = 5 V and TJ = 25
°C. (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Duty Cycle of
Synchronization Signal at
MODE Pin
40%
50%
60%
Time to Lock to External
Frequency
50
1.1
1.0
µs
V
Input Threshold Voltage for
EN pin; Rising Edge
VIH
VIL
1.06
0.96
1.15
1.05
150
2.5
Input Threshold Voltage for
EN pin; Falling Edge
V
Input Leakage Current for
EN, MODE/SYNC
ILKG
VIH = VIN or VIL= GND
nA
kΩ
V
Resistance from COMP/FSET
to GND for Logic Low
internal frequency setting with f = 2.25 MHz
internal frequency setting with f = 2.25 MHz
0
voltage on COMP/FSET for
logic high
VIN
95%
UVP Power Good Threshold
Voltage; dc Level
Rising (%VFB
)
92%
87%
98%
93%
UVP Power Good Threshold
Voltage; dc Level
Falling (%VFB
)
90%
VTH_PG
OVP Power Good Threshold;
dc Level
Rising (%VFB
)
107%
104%
110%
113%
111%
OVP Power Good Threshold;
dc Level
Falling (%VFB
)
107%
40
Power Good De-glitch Time
for a high level to low level transition on power good
µs
V
Power Good Output Low
Voltage
VOL_PG
IPG = 2 mA
VPG = 5 V
0.07
0.3
ILKG_PG
ISS/TR
Input Leakage Current (PG)
SS/TR Pin Source Current
Tracking Gain
100
2.8
nA
µA
2.1
2.5
1
VFB / VSS/TR for nominal VFB = 0.6 V
Tracking Offset
feedback voltage with VSS/TR = 0 V for nominal VFB = 0.6 V
17
mV
POWER SWITCH
High-Side MOSFET ON-
Resistance
RDS(ON)
RDS(ON)
VIN ≥ 5 V
37
15
60
35
1.5
30
3
mΩ
mΩ
µA
Low-Side MOSFET ON-
Resistance
VIN ≥ 5 V
High-Side MOSFET leakage
current
TJ = 85 °C; VIN = 6 V; V(SW) = 0 V
High-Side MOSFET leakage
current
VIN = 6 V; V(SW) = 0 Vhigh-side MOSFET leakage current
at TJ = 85°C
µA
Low-Side MOSFET leakage
current
TJ = 85 °C; V(SW) = 6 V
µA
Low-Side MOSFET leakage
current
V(SW) = 6 Vlow-side MOSFET leakage current at TJ =
85°C
55
30
80
µA
µA
SW leakage
V(SW) = 0.6 V; current into SW pin
-0.025
100% mode. VIN = 3.3, TJ
85°C
=
RDP
Dropout resistance
50
mΩ
High-Side MOSFET Current
Limit
ILIMH
dc value, for TPSM82810; VIN = 3 V to 6 V
4.8
3.9
5.6
6.55
5.25
A
High-Side MOSFET Current
Limit
ILIMH
ILIMNEG
fS
dc value, for TPSM82813; VIN = 3V to 6 V
dc value
4.5
-1.8
2.25
A
A
Negative Current Limit
PWM Switching Frequency
Range
see the fset function about setting the switching frequency
1.8
2.025
-19%
4
2.475
18%
MHz
PWM Switching Frequency
fS
with COMP/FSET tied to VIN or GND
2.25
MHz
PWM Switching Frequency
Tolerance
using a resistor from COMP/FSET to GND, fs = 1.8 MHz to
< 3 MHz
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Electrical Characteristics (continued)
over operating junction temperature (TJ = -40 °C to +125 °C) and VIN = 2.7 V to 6 V. Typical values at VIN = 5 V and TJ = 25
°C. (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
16%
75
UNIT
PWM Switching Frequency
Tolerance
using a resistor from COMP/FSET to GND, fs = 3 MHz to 4
MHz
-19%
ton,min
Minimum on-time of HS FET
Minimum on-time of LS FET
TJ = -40 °C to 125 °C, VIN = 3.3 V
VIN = 3.3 V
50
30
ns
ns
ton,min
OUTPUT
VFB
Feedback Voltage
0.6
1
V
ILKG_FB
Input Leakage Current (FB)
VFB = 0.6 V
70
nA
VIN ≥ VOUT + 1 V
PWM mode
-1%
-1%
1%
VIN ≥ VOUT + 1 V;
PFM mode;
Co,eff ≥ 22 µF
2%
2.5%
7%
VFB
Feedback Voltage Accuracy
VOUT ≥ 1.5 V
PFM mode;
Co,eff ≥ 47 µF
1 V ≤ VOUT < 1.5 V
-1%
-1%
VIN ≥ VOUT + 1 V;
VSS/TR = 0.3 V
Feedback Voltage Accuracy
with Voltage Tracking
VFB
PWM mode
Load Regulation
PWM mode operation
0.05
0.02
%/A
%/V
Ω
Line Regulation
PWM mode operation, IOUT= 1 A, VIN ≥ VOUT + 1 V
Output Discharge Resistance
50
IOUT = 0 mA, Time from EN=high to start switching; VIN
applied already
tdelay
tdelay
tramp
Start-up Delay Time
135
100
200
150
450
µs
IOUT = 0 mA, Time from EN=high to start switching; VIN
applied already; VIN ≥ 3.1 V
Start-up Delay Time
420
200
IOUT = 0 mA, Time from first switching pulse until 95% of
nominal output voltage; device not in current limit
Ramp time; SS/TR Pin Open
µs
7.6 Typical Characteristics
80
50
VIN = 2.7V
VIN = 3.3V
VIN = 4.0V
VIN = 5.0V
VIN = 6.0V
VIN = 2.7V
76
72
68
64
60
56
52
48
44
40
36
32
28
24
20
46
42
38
34
30
26
22
18
14
10
VIN = 3.3V
VIN = 4.0V
VIN = 5.0V
VIN = 6.0V
-40
25 85
Junction Temperature (°C)
125
150
-40
25 85
Junction Temperature (°C)
125
150
D002
D002
Figure 1. Rds(on) of High Side Switch
Figure 2. Rds(on) of Low Side Switch
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8 Parameter Measurement Information
8.1 Schematic
V
TPSM82810
VOUT
IN
2.75 V - 6 V
VOUT
VIN
CIN
22 mF
R1
CFF
EN
FB
COUT
MODE/SYNC
R2
3 x 22 mF
R3
COMP/FSET
SS/TR
CSS
PG
GND
Copyright © 2019, Texas Instruments Incorporated
Figure 3. Measurement Setup for TPSM82810 and TPSM82813
Table 1. List of Components
(1)
Reference
IC
Description
TPSM82810 or TPSM82813
22 µF / 10 V; GRM21BD71A226ME44
3 x 22 µF / 10 V; GRM21BD71A226ME44
10 nF (equal to 1ms start-up ramp); GCM155R71H103KA55D
8,06 kΩ
Manufacturer
Texas Instruments
CIN
Murata
Murata
any
COUT
CSS
RCF
CFF
any
10 pF
any
R1
Depending on VOUT
any
R2
Depending on VOUT
any
R3
100kΩ
any
(1) See the Third-party Products Disclaimer
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9 Detailed Description
9.1 Overview
The TPSM8281x synchronous switch mode DC/DC converters modules are based on a peak current mode
control topology. The control loop is internally compensated. In order to optimize the bandwidth of the control
loop to the wide range of output capacitance that can be used with TPSM8281x, one of 3 internal compensation
settings can be selected. See COMP/FSET. The compensation setting is selected either by a resistor from
COMP/FSET to GND, or by the logic state of this pin. The regulation network achieves fast and stable operation
with small external components and low ESR ceramic output capacitors. The device can be operated without
feed forward capacitor on the output voltage divider, however using a typically 10 pF feed forward capacitor
improves transient response.
The devices support forced fixed frequency PWM operation with the MODE pin tied to a logic high level. The
frequency is defined as either 2.25 MHz internally fixed when COMP/FSET is tied to GND or VIN or in a range of
1.8 MHz to 4 MHz defined by a resistor from COMP/FSET to GND. Alternatively, the devices can be
synchronized to an external clock signal in a range from 1.8 MHz to 4 MHz, applied to the MODE pin with no
need for additional passive components. External synchronization is only possible if a resistor from COMP/FSET
to GND is used. If COMP/FSET is directly tied to GND or VIN, TPSM8281x can not be synchronized externally.
An internal PLL allows to change from internal clock to external clock during operation. The synchronization to
the external clock is done on a falling edge of the clock applied at MODE to the rising edge on the SW pin. This
allows a roughly 180° phase shift when the SW pin is used to generate the synchronization signal for a second
converter. When the MODE pin is set to a logic low level, the device operates in power save mode (PFM) at low
output current and automatically transfers to fixed frequency PWM mode at higher output current. In PFM mode,
the switching frequency decreases linearly based on the load to sustain high efficiency down to very low output
current.
9.2 Functional Block Diagram
VIN
VOUT
Bias
Regulator
Gate Drive and Control
Ipeak
Izero
EN
MODE
gm
GND
FB
Oscillator
PG
Device
Control
+
-
Bandgap
SS/TR
Thermal
COMP/FSET
Shutdown
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9.3 Feature Description
9.3.1 Precise Enable
The voltage applied at the Enable pin of the TPSM8281x is compared to a fixed threshold of 1.1 V for a rising
voltage. This allows to drive the pin by a slowly changing voltage and enables the use of an external RC network
to achieve a power-up delay.
The Precise Enable input provides a user programmable undervoltage lockout by adding a resistor divider to the
input of the Enable pin.
The enable input threshold for a falling edge is typically 100 mV lower than the rising edge threshold. The
TPSM8281x starts operation when the rising threshold is exceeded. For proper operation, the EN pin must be
terminated and must not be left floating. Pulling the EN pin low forces the device into shutdown, with a shutdown
current of typically 1 μA. In this mode, the internal high side and low side MOSFETs are turned off and the entire
internal control circuitry is switched off.
9.3.2 COMP/FSET
This pin allows to set two different parameters independently:
•
•
internal compensation settings for the control loop (3 settings available)
the switching frequency in PWM mode from 1.8 MHz to 4 MHz
A resistor from COMP/FSET to GND changes the compensation as well as the switching frequency. The change
in compensation allows to adapt the device to different values of output capacitance. The resistor should be
placed close to the pin to keep the parasitic capacitance on the pin to a minimum. The compensation setting is
sampled at start-up of the converter, so a change in the resistor during operation only has an effect on the
switching frequency but not on the compensation.
In order to save external components, the pin can also be directly tied to VIN or GND to set a pre-defined
switching frequency / compensation. Do not leave the pin floating.
The switching frequency has to be selected based on the input voltage and the output voltage to meet the
specifications for the minimum on-time and minimum off-time.
Example: VIN = 5 V, VOUT = 1 V --> duty cycle (DC) = 1 V / 5 V = 0.2
•
•
with ton = DC * T --> ton,min = 1/fs,max * DC
--> fs,max = 1/ton,min * DC = 1/0.075 µs * 0.2 = 2.67 MHz
The compensation range has to be chosen based on the minimum capacitance used. The capacitance can be
increased from the minimum value as given in Table 2 up to the maximum of 470 µF in all of the 3 compensation
ranges. If the capacitance of an output changes during operation, e.g. when load switches are used to connect or
disconnect parts of the circuitry, the compensation has to be chosen for the minimum capacitance on the output.
With large output capacitance, the compensation should be done based on that large capacitance to get the best
load transient response. Compensating for large output capacitance but placing less capacitance on the output
may lead to instability.
The switching frequency for the different compensation setting is determined by the following equations.
For compensation (comp) setting 1:
Space
18MHz ×kW
RCF(kW) =
fS(MHz)
(1)
For compensation (comp) setting 2:
Space
60MHz ×kW
RCF(kW) =
fS(MHz)
(2)
Space
For compensation (comp) setting 3:
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Feature Description (continued)
Space
180MHz ×kW
RCF(kW) =
fS(MHz)
(3)
Table 2. Switching Frequency and Compensation for TPSM82810 (4 A) and TPSM82813 (3 A)
Minimum Output
Capacitance
Minimum Output
Capacitance
Minimum Output
Capacitance
Compensation
RCF
Switching Frequency
for VOUT < 1 V
for 1 V ≤ VOUT < 3.3 V
for VOUT ≥ 3.3 V
for smallest output
capacitance
(comp setting 1)
1.8 MHz (10 kΩ) ... 4 MHz (4.5 kΩ)
10 kΩ ... 4.5 kΩ
33 kΩ ... 15 kΩ
100 kΩ ... 45 kΩ
tied to GND
53 µF
100 µF
200 µF
53 µF
32 µF
60 µF
27 µF
50 µF
according to Equation 1
for medium output
capacitance
(comp setting 2)
1.8 MHz (33 kΩ) ... 4 MHz (15 kΩ)
according to
for large output
capacitance
(comp setting 3)
1.8 MHz (100 kΩ) ... 4 MHz (45 kΩ)
120 µF
32 µF
100 µF
27 µF
according to Equation 3
for smallest output
capacitance
(comp setting 1)
internally fixed 2.25 MHz
internally fixed 2.25 MHz
for large output
capacitance
tied to VIN
200 µF
120 µF
100 µF
(comp setting 3)
Refer to Output Capacitor for further details on the output capacitance required depending on the output voltage.
A too high resistor value for RCF is decoded as "tied to VIN", a value below the lowest range as "tied to GND".
The minimum output capacitance in Table 2 and is for capacitors close to the output of the device. If the
capacitance is distributed, a lower compensation setting may be required.
9.3.3 MODE / SYNC
When MODE/SYNC is set low, the device operates in PWM or PFM mode depending on the output current. The
MODE/SYNC pin allows to force PWM mode when set high. The pin also allows to apply an external clock in a
frequency range from 1.8 MHz to 4 MHz for external synchronization. Similar to COMP/FSET, the specifications
for the minimum on-time and minimum off-time has to be observed when setting the external frequency. For use
with external synchronization on the MODE/SYNC pin, the internal switching frequency should be set by RCF to a
similar value than the externally applied clock. This ensures that, if the external clock fails, the switching
frequency stays in the same range and the compensation settings are still valid. When there is no resistor from
COMP/FSET to GND but the pin is pulled high or low, external synchronization is not possible.
9.3.4 Spread Spectrum Clocking (SSC); optional
The device offers spread spectrum clocking as an option. For the devices that have SSC enabled, the switching
frequency is randomly changed in PWM mode when the internal clock is used. The frequency variation is
typically between the nominal switching frequency and up to 288kHz above the nominal switching frequency.
When the device is externally synchronized by applying a clock signal to the MODE/SYNC pin, TPSM8281x
follows the external clock and the internal spread spectrum block is turned off. SSC is also disabled during soft-
start.
9.3.5 Undervoltage Lockout (UVLO)
If the input voltage drops, the undervoltage lockout prevents mis-operation of the device by switching off both the
power FETs. The device is fully operational for voltages above the rising UVLO threshold and turns off if the
input voltage trips below the threshold for a falling supply voltage.
9.3.6 Power Good Output (PG)
Power good is an open drain output driven by a window comparator. PG is held low when the device is disabled,
in undervoltage lockout and thermal shutdown. When the output voltage is in regulation hence, within the window
defined in the electrical characteristics, the output is high impedance.
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Table 3. PG Status
EN
X
Device Status
VIN < 2 V
PG State
undefined
low
low
VIN ≥ 2 V
2 V ≤ VIN ≤ UVLO OR in thermal shutdown OR VOUT not in
high
high
low
regulation
VOUT in regulation
high impedance
9.3.7 Thermal Shutdown
The junction temperature (TJ) of the device is monitored by an internal temperature sensor. If TJ exceeds 170 °C
(typ), the device goes into thermal shutdown. Both the high-side and low-side power FETs are turned off and PG
goes low. When TJ decreases below the hysteresis amount of typically 15 °C, the converter resumes normal
operation, beginning with Soft-Start. During a PFM pause, the thermal shutdown is not active. After a PFM
pause, the device needs up to 9 µs to detect a too high junction temperature. If the PFM burst is shorter than this
delay, the device will not detect a too high junction temperature.
9.4 Device Functional Modes
9.4.1 Pulse Width Modulation (PWM) Operation
TPSM8281x has two operating modes: Forced PWM mode is discussed in this section and PWM/PFM as
discussed in Power Save Mode Operation (PWM/PFM)
With the MODE/SYNC pin set to high, TPSM8281x operates with pulse width modulation in continuous
conduction mode (CCM). The switching frequency is either defined by a resistor from the COMP pin to GND or
by an external clock signal applied to the MODE/SYNC pin. With an external clock applied to MODE/SYNC,
TPSM8281x follows the frequency applied to the pin. The frequency needs to be in a range TPSM8281x can
operate at, taking the minimum on-time into account.
9.4.2 Power Save Mode Operation (PWM/PFM)
When the MODE/SYNC pin is low, power save mode is allowed. The device operates in PWM mode as long as
the output current is higher than half of the inductor´s ripple current. To maintain high efficiency at light loads, the
device enters power save mode at the boundary to discontinuous conduction mode (DCM). This happens if the
output current becomes smaller than half of the inductor´s ripple current.
In power save mode the switching frequency decreases linearly with the load current maintaining high efficiency.
9.4.3 100% Duty-Cycle Operation
The duty cycle of a buck converter operated in PWM mode is given as D=VOUT/VIN. The duty cycle increases
as the input voltage comes close to the output voltage and the off-time gets smaller. When the minimum off-time
of typically 30 ns is reached, TPSM8281x skips switching cycles while it approaches 100% mode. In 100%
mode, it keeps the high-side switch on continuously. The high side switch stays turned on as long as the output
voltage is below the target. In 100% mode, the low side switch is turned off. The maximum dropout voltage in
100% mode is the product of the on-resistance of the high side switch plus the series resistance of the inductor
and the load current.
9.4.4 Current Limit and Short Circuit Protection
The TPSM8281x is protected against overload and short circuit events. If the inductor current exceeds the
current limit ILIMH, the high side switch is turned off and the low side switch is turned on to ramp down the
inductor current. The high side switch turns on again only if the current in the low side switch has decreased
below the low side current limit. Due to internal propagation delay, the actual current can exceed the static
current limit. The dynamic current limit is given as:
V
L
Ipeak(typ) = ILIMH
+
×tPD
(4)
where:
ILIMH is the static current limit as specified in the electrical characteristics
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Device Functional Modes (continued)
L is the effective inductance at the peak current (typical 470nH)
VL is the voltage across the inductor (VIN - VOUT) and
tPD is the internal propagation delay of typically 50 ns.
The current limit can exceed static values, especially if the input voltage is high and very small inductances are
used. The dynamic high side switch peak current can be calculated as follows:
V
IN -VOUT
Ipeak(typ) = ILIMH
+
×50ns
(5)
9.4.5 Output Discharge
The purpose of the discharge function is to ensure a defined down-ramp of the output voltage when the device is
being disabled but also to keep the output voltage close to 0 V when the device is off. The output discharge
feature is only active once TPSM8281x has been enabled at least once since the supply voltage was applied.
The discharge function is enabled as soon as the device is disabled, in thermal shutdown or in undervoltage
lockout. The minimum supply voltage required for the discharge function to remain active typically is 2 V. Output
discharge is not activated during a current limit or fold-back current limit event.
9.4.6 Soft Start / Tracking (SS/TR)
The internal Soft-Start circuitry controls the output voltage slope during startup. This avoids excessive inrush
current and ensures a controlled output voltage rise time. It also prevents unwanted voltage drops from high
impedance power sources or batteries. When EN is set high to start operation, the device starts switching after a
delay of about 200 μs then the internal reference and hence VOUT rises with a slope controlled by an external
capacitor connected to the SS/TR pin.
Leaving the SS/TR pin un-connected provides the fastest startup ramp with 150 µs typically. A capacitor
connected from SS/TR to GND is charged with 2.5 µA by an internal current source during soft start until it
reaches the reference voltage of 0.6 V. The capacitance required to set a certain ramp-time (tramp) therefore is:
(6)
If the device is set to shutdown (EN = GND), undervoltage lockout or thermal shutdown, an internal resistor pulls
the SS/TR pin to GND to ensure a proper low level. Returning from those states causes a new startup sequence.
A voltage applied at SS/TR can be used to track a master voltage. The output voltage follows this voltage in both
directions up and down in forced PWM mode. In PFM mode, the output voltage decreases based on the load
current. The SS/TR pin must not be connected to the SS/TR pin of other devices. An external voltage applied on
SS/TR is internally clamped to the feedback voltage (0.6 V). It is recommended to set the target for the external
voltage on SS/TR slightly above the feedback voltage. Given the tolerances of the resistor divider R5 and R6 on
SS/TR, this makes sure the device "switches" to the internal reference voltage when the power-up sequencing is
finished. See Figure 65.
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
10.1.1 Programming the Output Voltage
The output voltage of the TPSM8281x is adjustable. It can be programmed for output voltages from 0.6 V to 5.5
V, using a resistor divider from VOUT to GND. The voltage at the FB pin is regulated to 600 mV. The value of
the output voltage is set by the selection of the resistor divider from Equation 7. It is recommended to choose
resistor values which allow a current of at least 2 µA, meaning the value of R2 should not exceed 400 kΩ. Lower
resistor values are recommended for highest accuracy and most robust design.
V
OUT
æ
ö
R1
= R
-1
FB
2 × ç
è
÷
V
ø
(7)
10.1.2 External Component Selection
10.1.3 Capacitor Selection
10.1.3.1 Input Capacitor
For most applications, 22 µF nominal is sufficient and is recommended. The input capacitor buffers the input
voltage for transient events and also decouples the converter from the supply. A low ESR multilayer ceramic
capacitor (MLCC) is recommended for best filtering and should be placed between VIN and GND as close as
possible to those pins.
10.1.3.2 Output Capacitor
The architecture of the TPSM8281x allows the use of tiny ceramic output capacitors with low equivalent series
resistance (ESR). These capacitors provide low output voltage ripple and are recommended. To keep its low
resistance up to high frequencies and to get narrow capacitance variation with temperature, it is recommended to
use dielectric X7R, X7T or equivalent. Using a higher value has advantages like smaller voltage ripple and a
tighter DC output accuracy in power save mode. By changing the device compensation with a resistor from
COMP/FSET to GND, the device can be compensated in 3 steps based on the minimum capacitance used on
the output. The maximum capacitance is 470 µF in any of the compensation settings.
The minimum capacitance required on the output depends on the compensation setting as well as on the current
rating of the device. TPSM82810 and TPSM82813 require a minimum output capacitance of 27 µF while the
lower current versions TPSM82812 and TPSM82811 require 15 µF at minimum. The required output capacitance
also changes with the output voltage.
For output voltages below 1 V, the minimum increases linearly from 32 µF at 1 V to 53 µF at 0.6 V for
TPSM8281x with the compensation setting for smallest output capacitance. Other compensation ranges are
equivalent. See Table 2 for details.
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10.2 Typical Application
V
TPSM82810
VOUT
IN
2.75 V - 6 V
VOUT
VIN
CIN
22 mF
R1
CFF
EN
FB
COUT
MODE/SYNC
R2
3 x 22 mF
R3
COMP/FSET
SS/TR
CSS
PG
GND
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Figure 4. Typical Application
10.2.1 Design Requirements
The design guidelines provide a component selection to operate the device within the recommended operating
conditions.
10.2.2 Detailed Design Procedure
V
OUT
æ
ö
R1
= R
-1
FB
2 × ç
è
÷
V
ø
(8)
With VFB = 0.6 V:
Table 4. Setting the Output Voltage
Nominal Output Voltage VOUT
R1
R2
CFF
Exact Output Voltage
0.8 V
1.0 V
1.1 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
16.9 kΩ
20 kΩ
51 kΩ
30 kΩ
47 kΩ
68 kΩ
51 kΩ
40.2 kΩ
15 kΩ
19.6 kΩ
10 pF
10 pF
10 pF
10 pF
10 pF
10 pF
10 pF
10 pF
0.7988 V
1.0 V
39.2 kΩ
68 kΩ
1.101 V
1.2 V
76.8 kΩ
80.6 kΩ
47.5 kΩ
88.7 kΩ
1.5 V
1.8 V
2.5 V
3.314 V
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10.2.3 Application Curves
All plots have been taken with a nominal switching frequency of 2.25 MHz when set to PWM mode, unless
otherwise noted. The BOM is according to Table 1
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
100m
1m
10m
Output Current (A)
100m
1
4
0
0
0
1
2
Output Current (A)
3
4
D002
D002
VOUT = 3.3 V
PFM
TA = 25 °C
VOUT = 3.3 V
PWM
TA = 25 °C
Figure 5. Efficiency vs Output Current
Figure 6. Efficiency vs Output Current
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
60
VIN = 2.7 V
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
100m
1m
10m 100m
Output Current (A)
1
4
1
2
Output Current (A)
3
4
D002
D002
VOUT = 1.8 V
PFM
TA = 25 °C
VOUT = 1.8 V
PWM
TA = 25 °C
Figure 7. Efficiency vs Output Current
Figure 8. Efficiency vs Output Current
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
100m
1m
10m 100m
Output Current (A)
1
4
1
2
Output Current (A)
3
4
D002
D006
VOUT = 1.2 V
PFM
TA = 25 °C
VOUT = 1.2 V
PWM
TA = 25 °C
Figure 9. Efficiency vs Output Current
Figure 10. Efficiency vs Output Current
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100
95
90
85
80
75
70
65
60
55
50
45
100
95
90
85
80
75
70
65
60
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
40
100m
1m
10m 100m
Output Current (A)
1
4
0
1
2
Output Current (A)
3
4
D002
D002
VOUT = 1.0 V
PFM
TA = 25 °C
VOUT = 1.0 V
PWM
TA = 25 °C
Figure 11. Efficiency vs Output Current
Figure 12. Efficiency vs Output Current
90
85
80
75
70
65
60
55
50
90
85
80
75
70
65
60
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
100m
1m
10m 100m
Output Current (A)
1
4
0
1
2
Output Current (A)
3
4
D002
D002
VOUT = 0.6 V
PFM
TA = 25 °C
VOUT = 0.6 V
PWM
TA = 25 °C
Figure 13. Efficiency vs Output Current
Figure 14. Efficiency vs Output Current
3.32
3.315
3.31
3.32
3.315
3.31
3.305
3.3
3.305
3.3
3.295
3.29
3.295
3.29
3.285
3.28
3.285
3.28
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
3.275
3.27
3.275
3.27
100m
1m
10m 100m
Output Current (A)
1
4
100m
1m
10m 100m
Output Current (A)
1
4
D002
D002
VOUT = 3.3 V
PFM
TA = 25 °C
VOUT = 3.3 V
PWM
TA = 25 °C
Figure 15. Output Voltage vs Output Current
Figure 16. Output Voltage vs Output Current
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1.82
1.816
1.812
1.808
1.804
1.8
1.82
1.816
1.812
1.808
1.804
1.8
1.796
1.796
1.792
1.788
1.784
1.78
1.792
1.788
1.784
1.78
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
100m
1m
10m 100m
Output Current (A)
1
4
100m
1m
10m 100m
Output Current (A)
1
4
D002
D002
VOUT = 1.8 V
PFM
TA = 25 °C
VOUT = 1.8 V
PWM
TA = 25 °C
Figure 17. Output Voltage vs Output Current
Figure 18. Output Voltage vs Output Current
1.2125
1.21
1.2125
1.21
1.2075
1.205
1.2025
1.2
1.2075
1.205
1.2025
1.2
1.1975
1.195
1.1925
1.19
1.1975
1.195
1.1925
1.19
VIN = 2.7 V
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
1.1875
1.1875
100m
1m
10m 100m
Output Current (A)
1
4
100m
1m
10m 100m
Output Current (A)
1
4
D002
D002
VOUT = 1.2 V
PFM
TA = 25 °C
VOUT = 1.2 V
PWM
TA = 25 °C
Figure 19. Output Voltage vs Output Current
Figure 20. Output Voltage vs Output Current
1.01
1.008
1.006
1.004
1.002
1
1.01
1.008
1.006
1.004
1.002
1
0.998
0.996
0.994
0.992
0.99
0.998
0.996
0.994
0.992
0.99
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
100m
1m
10m 100m
Output Current (A)
1
4
100m
1m
10m 100m
Output Current (A)
1
4
D002
D002
VOUT = 1.0 V
PFM
TA = 25 °C
VOUT = 1.0 V
PWM
TA = 25 °C
Figure 21. Output Voltage vs Output Current
Figure 22. Output Voltage vs Output Current
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0.606
0.6045
0.603
0.6015
0.6
0.606
0.6045
0.603
0.6015
0.6
0.5985
0.597
0.5955
0.594
0.5985
0.597
0.5955
0.594
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
100m
1m
10m 100m
Output Current (A)
1
4
100m
1m
10m 100m
Output Current (A)
1
4
D002
D002
VOUT = 0.6 V
PFM
TA = 25 °C
VOUT = 0.6 V
PWM
TA = 25 °C
Figure 23. Output Voltage vs Output Current
Figure 24. Output Voltage vs Output Current
VOUT = 3.3 V
VIN = 5.0 V
PFM
TA = 25 °C
VOUT = 3.3 V
VIN = 5.0 V
PWM
TA = 25 °C
IOUT = 0.4 A to 3.6 A to 0.4 A
IOUT = 0.4 A to 3.6 A to 0.4 A
Figure 25. Load Transient Response
Figure 26. Load Transient Response
VOUT = 1.8 V
VIN = 5.0 V
PWM
TA = 25 °C
VOUT = 1.8 V
VIN = 5.0 V
PFM
TA = 25 °C
IOUT = 0.4 A to 3.6 A to 0.4 A
IOUT = 0.4 A to 3.6 A to 0.4 A
Figure 28. Load Transient Response
Figure 27. Load Transient Response
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VOUT = 1.2 V
VIN = 5.0 V
PFM
TA = 25 °C
VOUT = 1.2 V
VIN = 5.0 V
PWM
TA = 25 °C
IOUT = 0.4 A to 3.6 A to 0.4 A
IOUT = 0.4 A to 3.6 A to 0.4 A
Figure 29. Load Transient Response
Figure 30. Load Transient Response
VOUT = 1.0 V
VIN = 5.0 V
PFM
TA = 25 °C
VOUT = 1.0 V
VIN = 5.0 V
PWM
TA = 25 °C
IOUT = 0.4 A to 3.6 A to 0.4 A
IOUT = 0.4 A to 3.6 A to 0.4 A
Figure 31. Load Transient Response
Figure 32. Load Transient Response
VOUT = 0.6 V
VIN = 3.3 V
PWM
TA = 25 °C
VOUT = 0.6 V
VIN = 3.3 V
PFM
TA = 25 °C
IOUT = 0.4 A to 3.6 A to 0.4 A
IOUT = 0.4 A to 3.6 A to 0.4 A
Figure 34. Load Transient Response
Figure 33. Load Transient Response
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VOUT = 3.3 V
IOUT = 0.5 A
PFM
TA = 25 °C
VOUT = 3.3 V
IOUT = 4 A
PWM
TA = 25 °C
VIN = 4.5 V to 5.5 V to 4.5 V
VIN = 4.5 V to 5.5 V to 4.5 V
Figure 35. Line Transient Response
Figure 36. Line Transient Response
VOUT = 1.8 V
IOUT = 0.5 A
PFM
TA = 25 °C
VOUT = 1.8 V
IOUT = 4 A
PWM
TA = 25 °C
VIN = 4.5 V to 5.5 V to 4.5 V
VIN = 4.5 V to 5.5 V to 4.5 V
Figure 37. Line Transient Response
Figure 38. Line Transient Response
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VOUT = 1.2 V
IOUT = 0.5 A
PFM
TA = 25 °C
VOUT = 1.2 V
IOUT = 4 A
PWM
TA = 25 °C
VIN = 4.5 V to 5.5 V to 4.5 V
VIN = 4.5 V to 5.5 V to 4.5 V
Figure 39. Line Transient Response
Figure 40. Line Transient Response
VOUT = 1.0 V
IOUT = 0.5 A
PFM
TA = 25 °C
VOUT = 1.0 V
IOUT = 4 A
PWM
TA = 25 °C
VIN = 4.5 V to 5.5 V to 4.5 V
VIN = 4.5 V to 5.5 V to 4.5 V
Figure 41. Line Transient Response
Figure 42. Line Transient Response
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VOUT = 0.6 V
IOUT = 0.5 A
PFM
TA = 25 °C
VOUT = 0.6 V
IOUT = 4 A
PWM
TA = 25 °C
VIN = 3.0 V to 3.6 V to 3.0 V
VIN = 3.0 V to 3.6 V to 3.0 V
Figure 43. Line Transient Response
Figure 44. Line Transient Response
VOUT = 3.3 V
IOUT = 0.5 A
PFM
TA = 25 °C
VOUT = 3.3 V
IOUT = 4 A
PWM
TA = 25 °C
VIN = 5.0 V
BW = 20 MHz
VIN = 5.0 V
BW = 20 MHz
Figure 45. Output Voltage Ripple
Figure 46. Output Voltage Ripple
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VOUT = 1.8 V
IOUT = 0.5 A
PFM
TA = 25 °C
VOUT = 1.8 V
IOUT = 4 A
PWM
TA = 25 °C
VIN = 5.0 V
BW = 20 MHz
VIN = 5.0 V
BW = 20 MHz
Figure 47. Output Voltage Ripple
Figure 48. Output Voltage Ripple
VOUT = 1.2 V
IOUT = 0.5 A
PFM
TA = 25 °C
VOUT = 1.2 V
IOUT = 4 A
PWM
TA = 25 °C
VIN = 5.0 V
BW = 20 MHz
VIN = 5.0 V
BW = 20 MHz
Figure 49. Output Voltage Ripple
Figure 50. Output Voltage Ripple
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VOUT = 1.0 V
IOUT = 0.5 A
PFM
TA = 25 °C
VOUT = 1.0 V
IOUT = 4 A
PWM
TA = 25 °C
VIN = 5.0 V
BW = 20 MHz
VIN = 5.0 V
BW = 20 MHz
Figure 51. Output Voltage Ripple
Figure 52. Output Voltage Ripple
VOUT = 0.6 V
IOUT = 0.5 A
PFM
TA = 25 °C
VOUT = 0.6 V
IOUT = 4 A
PWM
TA = 25 °C
VIN = 3.3 V
BW = 20 MHz
VIN = 3.3 V
BW = 20 MHz
Figure 53. Output Voltage Ripple
Figure 54. Output Voltage Ripple
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VOUT = 3.3 V
IOUT = 4 A
PWM
TA = 25 °C
VOUT = 1.8 V
IOUT = 4 A
PWM
TA = 25 °C
VIN = 5 V
CSS = 4.7 nF
VIN = 5 V
CSS = 4.7 nF
Figure 55. Start-Up Timing
Figure 56. Start-Up Timing
VOUT = 1.2 V
IOUT = 4 A
PWM
TA = 25 °C
VOUT = 1.0 V
IOUT = 4 A
PWM
TA = 25 °C
VIN = 5 V
CSS = 4.7 nF
VIN = 5 V
CSS = 4.7 nF
Figure 57. Start-Up Timing
Figure 58. Start-Up Timing
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4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
Vin = 5.0 V
-20
VOUT = 3.3 V
-40
0
20
40
60
80
100 120 140
Ambient Temperature (°C)
D002
PWM
CSS = 4.7 nF
VOUT = 0.6 V
IOUT = 4 A
PWM
TA = 25 °C
Figure 60. Output Current Derating vs Ambient
Temperature
VIN = 3.3 V
CSS = 4.7 nF
Figure 59. Start-Up Timing
4.5
4
4.5
4
3.5
3
3.5
3
2.5
2
2.5
2
1.5
1
1.5
1
Vin = 3.3 V
Vin = 5.0 V
Vin = 3.3 V
Vin = 5.0 V
0.5
0.5
0
0
-40
-20
0
20
Ambient Temperature (°C)
40
60
80
100 120 140
-40
-20
0
20
Ambient Temperature (°C)
40
60
80
100 120 140
D002
D002
VOUT = 1.8 V
PWM
CSS = 4.7 nF
VOUT = 1.2 V
PWM
CSS = 4.7 nF
Figure 61. Output Current Derating vs Ambient
Temperature
Figure 62. Output Current Derating vs Ambient
Temperature
4.5
4
4.5
4
3.5
3
3.5
3
2.5
2
2.5
2
1.5
1
1.5
1
Vin = 3.3 V
Vin = 5.0 V
0.5
0.5
Vin = 3.3 V
0
0
-40
-20
0
20
Ambient Temperature (°C)
40
60
80
100 120 140
-40
-20
0
20
Ambient Temperature (°C)
40
60
80
100 120 140
D002
D002
VOUT = 1.0 V
PWM
CSS = 4.7 nF
VOUT = 0.6 V
PWM
CSS = 4.7 nF
Figure 63. Output Current Derating vs Ambient
Temperature
Figure 64. Output Current Derating vs Ambient
Temperature
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10.3 System Examples
10.3.1 Voltage Tracking
TPSM8281x follows the voltage applied to the SS/TR pin. A voltage ramp on SS/TR to 0.6 V ramps the output
voltage according to the 0.6 V feedback voltage.
Tracking the 3.3 V of device 1 such that both rails reach their target voltage at the same time, requires a resistor
divider on SS/TR of device 2 equal to the output voltage divider of device 1. The output current of 2.5 µA on the
SS/TR pin causes an offset voltage on the resistor divider formed by R5 and R6. The equivalent resistance of R5
// R6 should therefore be kept below 15 kΩ. The current from SS/TR causes a slightly higher voltage across R6
than 0.6 V, which is desired because device 2 switches to its internal reference as soon as the voltage at SS/TR
is higher than 0.6V.
In case both devices need to run in forced PWM mode, it is recommended to tie the MODE pin of device 2 to the
output voltage or the power good signal of device 1, the master device. TPSM8281x do have a duty cycle
limitation defined by the minimum on-time. For tracking down to low output voltages, device 2 can not follow
once the minimum duty cycle is reached. Enabling PFM mode while tracking is in progress, allows to ramp down
the output voltage close to 0 V.
Device 1 (master)
TPSM82810
V
IN
2.75 V - 6 V
3.3 V
VIN
VOUT
10 pF
C
IN
22 mF
EN
FB
COUT
47 mF
MODE/SYNC
EN
COMP/FSET
SS/TR
4.7 nF
PG
GND
Device 2 (slave)
TPSM82810
1.8 V
VIN
VOUT
10 pF
CIN
22 mF
EN
FB
R5
COUT
MODE/SYNC
47 mF
COMP/FSET
SS/TR
PG
R6
GND
Copyright© 2019, Texas InstrumentsIncorporated
Figure 65. Schematic for Output Voltage Tracking
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System Examples (continued)
Figure 66. Scope Plot for Output Voltage Tracking
10.3.2 Synchronizing to an external Clock
TPSM8281x can be externally synchronized by applying an external clock on the MODE/SYNC pin. There is no
need for any additional circuitry as long as the input signal meets the requirements given in the electrical
specifications. The clock can be applied / removed during operation, allowing to switch from an extertnally
defined fixed frequency to power-save mode or to internal fixed frequency operation. The value of the RCF
resistor should be choosen such that the internally defined frequency and the externally applied frequency are
close to each other. This ensures a smooth transition from internal to external frequency and vice versa.
TPSM82810
V
IN
2.75 V - 6 V
VOUT
VIN
VOUT
CIN
22 mF
R1
R2
CFF
EN
FB
COUT
47 mF
MODE/SYNC
R3
COMP/FSET
SS/TR
fext
CSS
PG
GND
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Figure 67. Schematic using External Synchronization
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System Examples (continued)
VIN = 5 V
RCF = 8.06 kΩ
IOUT = 0.1 A
VIN = 5 V
RCF = 8.06 kΩ
IOUT = 1 A
VOUT = 1.8 V
fEXT = 2.5 MHz
VOUT = 1.8 V
fEXT = 2.5 MHz
Figure 68. Switching from External Syncronization to
Power-Save Mode (PFM)
Figure 69. Switching from External Synchronizaion to
Internal Fixed Frequency
10.4 Do's and Don'ts (Recommended)
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11 Power Supply Recommendations
The TPSM8281x device family has no special requirements for its input power supply. The input power supply´s
output current needs to be rated according to the supply voltage, output voltage and output current of the
TPSM8281x.
12 Layout
12.1 Layout Guidelines
A proper layout is critical for the operation of a switched mode power supply, even more at high switching
frequencies. Therefore the PCB layout of the TPSM8281x demands careful attention to ensure operation and to
get the performance specified. A poor layout can lead to issues like poor regulation (both line and load), stability
and accuracy weaknesses, increased EMI radiation and noise sensitivity.
See Layout Example for the recommended layout of the TPSM82810, which is designed for common external
ground connections. The input capacitor should be placed as close as possible between the VIN and GND pin.
Provide low inductive and resistive paths for loops with high di/dt. Therefore paths conducting the switched load
current should be as short and wide as possible. Provide low capacitive paths (with respect to all other nodes) for
wires with high dv/dt. Therefore, the input and output capacitance should be placed as close as possible to the
IC pins and parallel wiring over long distances as well as narrow traces should be avoided. Loops which conduct
an alternating current should outline an area as small as possible, as this area is proportional to the energy
radiated.
Sensitive nodes like FB need to be connected with short wires and not nearby high dv/dt signals (for example
SW). As they carry information about the output voltage, they should be connected as close as possible to the
actual output voltage (at the output capacitor). The capacitor on the SS/TR pin as well as the FB resistors, R1
and R2, should be kept close to the IC and connect directly to those pins and the system ground plane.
The package uses the pins for power dissipation. Thermal vias on the VIN, GND and SW pins help to spread the
heat into the pcb.
The recommended layout is implemented on the EVM and shown in its User's Guide, TPSM82810EVM-xxx
Evaluation Module.
12.2 Layout Example
VOUT
VIN
R1
CFF
GND
Figure 70. Example Layout
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13 Device and Documentation Support
13.1 Device Support
13.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.2 Documentation Support
13.2.1 Related Documentation
For related documentation see the following:
•
TPSM82810EVM-015 Evaluation Module, SLVUBG0
13.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 5. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
ORDER NOW
TPSM82810
TPSM82813
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
13.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.5 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.6 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
SIL0014B
MicroSiPTM - 2.4 mm max height
S
C
A
L
E
3
.
0
0
0
MICRO SYSTEM IN PACKAGE
A
B
3
PIN 1 INDEX
AREA
(3.2)
4
PICK AREA
NOTE 3
(2.5)
2.4 MAX
C
0.08 C
2X 1.8
1.22
1.18
4X
4X 0.3 0.1
10X (0.05)
6
5
4X (0.075)
0.57
0.53
2X 3.175
6X
12
13
14
SYMM
4X 0.8 0.1
2X 1.3
2X 1.15
11
4X 0.65
0.27
0.23
6X
10
1
0.1
C A B
PIN 1 ID
(OPTIONAL)
SYMM
0.05
C
0.845
0.805
4X
0.1
C A B
C
2X 0.9
0.05
4225112/A 07/2019
MicroSiP is a trademark of Texas Instruments
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Pick and place nozzle 1.3 mm or smaller recommended.
4. The package thermal pads must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
SIL0014B
MicroSiPTM - 2.4 mm max height
MICRO SYSTEM IN PACKAGE
2X (2)
PKG
COPPER KEEP-OUT AREA
METAL UNDER
SOLDER MASK
TYP
(0.05) TYP
(0.3)
SOLDER MASK
OPENING
TYP
10
1
4X (0.45)
6X (0.75)
(3.25)
6X (0.25)
11
12
14
4X (0.575)
4X (0.8)
PKG
2X (3.35)
13
4X (0.65)
(R0.05) TYP
5
4X (1)
6
SEE DETAILS
4X (1.4)
(0.3)
4X (0.3)
(2.65)
LAND PATTERN EXAMPLE
SCALE:20X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
PADS 1, 5, 6, 10 AND 11 - 14
SOLDER MASK DETAILS
NOT TO SCALE
4225112/A 07/2019
NOTES: (continued)
5. This package is designed to be soldered to thermal pads on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
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EXAMPLE STENCIL DESIGN
SIL0014B
MicroSiPTM - 2.4 mm max height
MICRO SYSTEM IN PACKAGE
2X (2)
4X (0.45)
(R0.1) TYP
SYMM
1
10
6X (0.75)
6X (0.25)
11
12
4X (0.575)
2X (3.35)
14
13
SYMM
6X (0.65)
4X (0.8)
4X (1)
6
5
4X (1.4)
4X (0.3)
(2.65)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:25X
4225112/A 07/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OPTION ADDENDUM
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23-Sep-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPSM82810SILR
TPSM82810SSILR
TPSM82813SILR
TPSM82813SSILR
XPSM82810SILT
PREVIEW
PREVIEW
PREVIEW
PREVIEW
ACTIVE
uSiP
uSiP
uSiP
uSiP
uSiP
SIL
SIL
SIL
SIL
SIL
14
14
14
14
14
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
ENEPIG
ENEPIG
ENEPIG
ENEPIG
ENEPIG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
FG
GC
GD
HF
X
3000
Green (RoHS
& no Sb/Br)
TPSM8281X
XPSM82813SILT
ACTIVE
uSiP
SIL
14
3000
Green (RoHS
& no Sb/Br)
ENEPIG
Level-2-260C-1 YEAR
-40 to 125
I
P
TPSM8281X
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Sep-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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Addendum-Page 2
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