TPSM82864A [TI]
具有集成电感器、采用 3.5mm x 4mm QFN 封装的 2.4V 至 5.5V 输入、4A 薄型降压电源模块;
| 型号： | TPSM82864A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有集成电感器、采用 3.5mm x 4mm QFN 封装的 2.4V 至 5.5V 输入、4A 薄型降压电源模块 电感器 电源电路 |
| 文件： | 总35页 (文件大小：2966K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPSM82864A, TPSM82866A
ZHCSMK6B –SEPTEMBER 2021 –REVISED NOVEMBER 2022
TPSM82864A/TPSM82866A 具有集成电感器、采用3.5mm × 4.0mm 薄超模压塑料
QFN 封装的2.4V 至5.5V 输入、4A/6A 降压电源模块
1 特性
3 说明
• 效率高达96%
• 优异的热性能
• 符合CISPR-11 B 类标准
• 1% 的输出电压精度
• 可实现快速瞬态响应的DCS-Control 拓扑
• 1.4mm 或1.8mm 超薄型QFN 封装
• 输入电压范围为2.4V 至5.5V
• 同一器件型号可提供：
– 可调输出电压：0.6V 至VIN
– 13 个集成式固定输出电压选项
• 具有窗口比较器的电源正常状态指示器
• 2.4MHz 开关频率
• 强制PWM 或省电模式
• 4µA 工作静态电流
• 输出电压放电
• 100% 占空比模式
• 断续短路保护
• 热关断
TPSM8286xA 器件系列包含4A 和6A 降压转换器电源
模块，该电源模块经优化可实现小解决方案尺寸和高效
率。该电源模块集成了同步降压转换器和电感器，可简
化设计、减少外部元件并节省印刷电路板 (PCB) 面
积。该器件采用紧凑的薄型封装，适用于通过标准表面
贴装设备进行自动组装。
通过 DCS-Control 架构可实现严格的输出电压精度
（即使与小型输出电容搭配工作时也是如此），以及出
色的负载瞬态性能。该转换器在中高负载条件下以
PWM 模式运行，并在轻负载时自动进入省电模式运
行，从而在整个负载电流范围内保持高效率。此类器件
还可强制进入PWM 模式运行，以实现超小的输出电压
纹波。
器件的EN 和PG 引脚支持顺序配置，可带来灵活的系
统设计。集成的软启动功能降低了输入电源需要提供的
浪涌电流。过热保护和断续短路保护功能使得该解决方
案稳健且可靠。
• –40°C 至125°C 工作温度范围
• 间距为0.5mm 的3.5mm × 4.0mm QFN 封装
• 35mm2 解决方案尺寸
器件信息
封装尺寸（标
称值）
封装(1)
器件型号
输出电流
TPSM82864A
TPSM82866A
4A
6A
RDJ 或RDM
（B0QFN，
23）
2 应用
3.50mm ×
4.00mm
• 适用于FPGA、CPU、ASIC 的内核电源
• 光学模块
• 医疗成像
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 工业运输
• 工厂自动化和控制
• 航天和国防
100
95
90
85
80
75
70
65
VIN
VOUT
1.8 V
2.4 V to 5.5 V
VIN
EN
VOUT
VOS
C2
C1
22 µF
2 × 22 µF or
1 × 47 µF
R3
FB
VSET/
MODE
VPG
60
VOUT = 0.6V
PG
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
55
50
45
40
R4
133 kΩ
FPWM
PSM
AGND PGND
100u
1m
10m
100m
1
6
Output Current (A)
典型应用原理图- 固定输出电压选项
TPSM82866AA0HRDMR –效率与输出电流间的关系
曲线；VIN = 5.0V
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSEF1
TPSM82864A, TPSM82866A
ZHCSMK6B –SEPTEMBER 2021 –REVISED NOVEMBER 2022
www.ti.com.cn
Table of Contents
8.4 Device Functional Modes..........................................12
9 Application and Implementation..................................14
9.1 Application Information............................................. 14
9.2 Typical Application.................................................... 14
9.3 Power Supply Recommendations.............................21
9.4 Layout....................................................................... 21
10 Device and Documentation Support..........................24
10.1 Device Support....................................................... 24
10.2 Documentation Support.......................................... 24
10.3 接收文档更新通知................................................... 24
10.4 支持资源..................................................................24
10.5 Trademarks.............................................................24
10.6 Electrostatic Discharge Caution..............................24
10.7 术语表..................................................................... 24
11 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Options................................................................ 3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information....................................................5
7.5 Electrical Characteristics.............................................6
7.6 Typical Characteristics................................................7
8 Detailed Description........................................................8
8.1 Overview.....................................................................8
8.2 Functional Block Diagram...........................................8
8.3 Feature Description.....................................................8
Information.................................................................... 24
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (December 2021) to Revision B (November 2022)
Page
• Added TPSM8286xAA0HRDM to the data sheet............................................................................................... 3
Changes from Revision * (September 2021) to Revision A (December 2021)
Page
• 将文档状态从“预告信息”更改为“量产数据”................................................................................................ 1
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5 Device Options
ORDERABLE PART NUMBER
DEVICE HEIGHT
OUTPUT CURRENT
TPSM82864AA0SRDJR
1.4 mm
4 A
TPSM82864AA0HRDMR
TPSM82866AA0SRDJR
TPSM82866AA0HRDMR
1.8 mm
1.4 mm
1.8 mm
6 A
6 Pin Configuration and Functions
TOP VIEW
BOTTOM VIEW
7
8
9
10
11
12
12
11
10
9
8
7
VOUT
VOUT
VOUT
VOUT
VOS
SW
SW
PGND
VOUT
13
6
5
4
3
2
13
6
5
4
3
2
PGND
PGND
PGND
VSET/MODE
PG
VOUT
Exposed
Thermal
Pad
23
Exposed
Thermal
Pad
23
14
15
16
17
14
PGND
VOUT
15
PGND
VOUT
16
VSET/MODE
PG
VOS
17
FB
FB
EN
AGND
EN
AGND
18
19
20
21
22
1
1
22
21
20
19
18
图6-1. TPSM82864A, TPSM82866A - QFN (23 Pin)
表6-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
AGND
18
1
P
I
Analog ground pin. Must be connected to a common GND plane.
Device enable pin. To enable the device, this pin must be pulled high. Pulling this pin low
disables the device. Do not leave floating.
EN
FB
Voltage feedback input. Connect the output voltage resistor divider to this pin. When using a
fixed output voltage, connect directly to VOUT.
17
2
I
Power-good open-drain output pin. The pullup resistor can be connected to voltages up to 5.5 V.
If unused, leave this pin floating. This pin is pulled to GND when the device is in shutdown.
PG
O
P
4, 5, 6, 8, 9,
10, 11, 19, 20
PGND
Power ground pin. Must be connected to common GND plane.
SW
VIN
7
21, 22
O
P
I
Switch pin of the power stage. This pin can be left floating.
Power supply input voltage pin
VOS
VOUT
16
Output voltage sense pin. This pin must be directly connected to the output capacitor.
Output voltage pin
12, 13, 14, 15
P
Connecting a resistor to GND selects one of the fixed output voltages. Tying the pin high or low
selects an adjustable output voltage. After the device has started up, the pin operates as a
MODE input. Applying a high level selects forced PWM mode operation and a low level selects
power save mode operation.
VSET/MODE
3
I
Exposed
Thermal Pad
Internally connected to PGND. Must be soldered to achieve appropriate power dissipation and
mechanical reliability. Must be connected to common GND plane.
23
P
(1) I = Input, O = Output, P = Power
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7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1)
MIN
–0.3
–0.3
–2.5
MAX
UNIT
VIN, EN, VOS, FB, PG, VSET/MODE
6
VIN + 0.3
10
Voltage(2)
SW (DC), VOUT
V
SW (AC, less than 10ns)(3)
Sink current at PG
ISINK_PG
TJ
2
mA
°C
Junction temperature
Storage temperature
125
–40
–40
Tstg
125
°C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltage values are with respect to network ground terminal.
(3) While switching.
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
2.4
NOM
MAX
5.5
VIN
10
4
UNIT
V
VIN
Supply Voltage Range
VOUT
tF_VIN
Output Voltage Range
0.6
V
Falling transition time at VIN (1)
Output current, TPSM82864A
Output current, TPSM82866A
mV/µs
IOUT
A
6
Nominal resistance range for external voltage selection resistor (E96
resistor series)
10
249
1%
kΩ
RVSET
External voltage selection resistor tolerance
External voltage selection resistor temperature coefficient
Junction temperature
±200 ppm/°C
125 °C
TJ
–40
(1) The falling slew rate of VIN should be limited if VIN goes below VUVLO (see Power Supply Recommendations).
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7.4 Thermal Information
TPSM8286x
23 PINS
THERMAL METRIC(1)
UNIT
RDM
JEDEC 51-5
RDJ
JEDEC 51-5
RDJ
EVM
RDM
EVM
RθJA
Junction-to-ambient thermal resistance
43.2
42.5
14.9
6.8
43.3
34.3
10.8
3.6
25.4
n/a(2)
n/a(2)
2.4
25.9
n/a(2)
n/a(2)
3.7
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
RθJB
ΨJT
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
14.8
10.7
10.9
12.7
ΨJB
(1) For more information about thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
(2) Not applicable to an EVM.
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7.5 Electrical Characteristics
TJ = -40 °C to 125 °C, and VIN = 2.4 V to 5.5 V. Typical values are at TJ = 25 °C and VIN = 5 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
SUPPLY
IQ_VIN
Quiescent current into VIN pin
Quiescent current into VOS pin
Shutdown current
EN = High, no load, device not switching
4
8
10
µA
µA
EN = High, no load, device not switching,
VVOS = 1.8 V
IQ_VOS
ISD
VUVLO
0.24
2.3
2.2
150
20
1
2.4
2.3
µA
V
EN = Low, TJ = -40℃to 85℃
VIN rising
2.2
2.1
Under voltage lock out threshold
VIN falling
V
Thermal shutdown threshold
Thermal shutdown hysteresis
TJ rising
°C
°C
TJSD
TJ falling
LOGIC INTERFACE
High-level input threshold voltage at EN
and VSET/MODE
VIH
1.0
V
Low-level input threshold voltage at
EN and VSET/MODE
VIL
0.4
0.1
V
IEN,LKG
Input leakage current into EN pin
0.01
µA
START-UP, POWER GOOD
Time from EN high to device starts switching with
a 249-kΩ resistor connected between VSET/
MODE and GND
tDelay
tRamp
Enable delay time
420
650 1100
µs
Output voltage ramp time
Time from device starts switching to power good
VFB referenced to VFB(nominal)
VFB referenced to VFB(nominal)
Isink = 1 mA
0.8
85
1
91
1.5
96
ms
%
VPG(low) Power good lower threshold
VPG(high) Power good upper threshold
103
111
120
0.4
0.1
%
VPG,OL
Low-level output voltage
Input leakage current into PG pin
Power good delay
V
IPG,LKG
tPG,DLY
VPG = 5.0 V
0.01
34
µA
µs
Rising and falling edges
OUTPUT
Fixed voltage operation, FPWM, no load, TJ =
0°C to 85°C
1
%
–1
VOUT
Output voltage accuracy
Fixed voltage operation, FPWM, no load
Adjustable voltage operation
2
606
0.4
%
mV
µA
–2
VFB
Feedback voltage
594
600
0.01
3.5
IFB,LKG
RDIS
Input leakage into FB pin
Output discharge resistor at VOS pin
Load regulation
Adjustable voltage operation, VFB = 0.6 V
Ω
VOUT = 1.2 V, FPWM
0.04
%/A
POWER SWITCH
TPSM8286xAA0SRDJ
100% mode. VIN = 3.3 V, TJ = 25°C
28
24
35
mΩ
mΩ
RDP
Dropout resistance
TPSM8286xAA0HRDM
100% mode. VIN = 3.3 V, TJ = 25°C
TPSM82864A
TPSM82866A
TPSM82864A
TPSM82866A
5
7
5.5
7.9
4.5
6.5
-3
6
A
A
High-side FET forward current limit
Low-side FET forward current limit
8.5
ILIM
A
A
Low-side FET negative current limit
PWM switching frequency
A
fSW
IOUT = 1 A, VOUT = 1.2 V
2.4
MHz
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7.6 Typical Characteristics
10
9
1.5
1.3
1.1
0.9
0.7
0.5
0.3
0.1
TJ = -40°C
TJ = -40°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
TJ
TJ
=
=
25°C
85°C
TJ = 125°C
8
7
6
5
4
3
2.4
2.8
3.2
3.6
4
4.4
4.8
5.2 5.5
2.4
2.8
3.2
3.6
4
4.4
4.8
5.2 5.5
Input Voltage (V)
Input Voltage (V)
图7-2. Shutdown Current ISD
图7-1. Quiescent Current into VIN IQ_VIN
10
50
45
40
35
30
25
20
15
TJ = -40°C
TJ
TJ
TJ
=
=
=
-40°C
25°C
85°C
TJ
TJ
=
=
25°C
85°C
9
8
7
6
5
4
3
2
TJ = 125°C
TJ = 125°C
2.4
2.8
3.2
3.6
4
4.4
4.8
5.2 5.5
2.4
2.8
3.2
3.6
4
4.4
4.8
5.2 5.5
Input Voltage (V)
Input Voltage (V)
TPSM8286xAA0SRDJ
图7-3. Output Discharge Resistance RDIS
图7-4. Dropout Resistance RDP
50
45
40
35
30
25
20
15
T
T
J = -40°C
J = 25°C
TJ = 85°C
TJ = 125°C
2.4
2.8
3.2
3.6
4
4.4
4.8
5.2 5.5
Input Voltage (V)
TPSM8286xAA0HRDM
图7-5. Dropout Resistance RDP
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8 Detailed Description
8.1 Overview
The TPSM8286xA synchronous step-down converter power module is based on DCS-Control (Direct Control
with Seamless transition into power save mode). This is an advanced regulation topology that combines the
advantages of hysteretic, voltage, and current mode control. The DCS-Control topology operates in PWM (pulse
width modulation) mode for medium-to-heavy load conditions and in PSM (power save mode) at light load
currents. In PWM, the converter operates with its nominal switching frequency of 2.4 MHz, having a controlled
frequency variation over the input voltage range. As the load current decreases, the converter enters power save
mode, reducing the switching frequency and minimizing the quiescent current of the IC to achieve high efficiency
over the entire load current range. DCS-Control supports both operation modes using a single building block
and, therefore, has a seamless transition from PWM to PSM without effects on the output voltage. The
TPSM8286xA offers excellent DC voltage regulation and load transient regulation, combined with low output
voltage ripple, minimizing interference with RF circuits.
8.2 Functional Block Diagram
PG
VIN
VPG(high)
+
–
EN
Control Logic
UVLO
VFB
PG
delay
Thermal Shutdown
Start-up Ramp
+
–
VPG(low)
VSET/
MODE
VSW
VIN
HS-FET
Forward Current Limit
TON
HICCUP
Direct Control
VSW
and
220 nH
VREF
selection
Compensation
VOUT
SW
Gate
Drive
Modulator
+
EA
_
Comparator
FB
VOS
LS-FET
RDIS
Forward Current Limit
Zero Current Detect
Negative Current Limit
PGND
AGND
8.3 Feature Description
8.3.1 Power Save Mode
As the load current decreases, the device seamlessly enters power save mode (PSM) operation. In PSM, the
converter operates with a reduced switching frequency and a minimum quiescent current to maintain high
efficiency. Power save mode is based on a fixed on-time architecture, as shown in 方程式1.
V
OUT
t
∂416ns
ON
V
IN
(1)
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The switching frequency in PSM is estimated as:
(2)
The load current at which PSM is entered is at one half of the ripple current of the inductor and it can be
estimated as:
(3)
In power save mode, the output voltage rises slightly above the nominal output voltage. This effect is minimized
by increasing the output capacitance.
8.3.2 Forced PWM Mode
After the device has powered up and ramped up VOUT, the VSET/MODE pin acts as a digital input. With a high
level on the VSET/MODE pin, the device enters forced PWM (FPWM) mode and operates with a constant
switching frequency over the entire load range, even at very light loads. This reduces the output voltage ripple
and allows simple filtering of the switching frequency for noise-sensitive applications but lowers efficiency at light
loads.
8.3.3 Optimized Transient Performance from PWM to PSM Operation
For most converters, the load transient response in PWM mode is improved compared to PSM, because the
converter reacts faster on the load step and actively sinks energy on the load release. As an additional feature,
the TPSM8286xA automatically stays in PWM mode for 128 cycles after a heavy load release to bring the output
voltage back to the regulation level faster. After these 128 cycles of PWM mode, it automatically returns to PSM
(if VSET/MODE is low). See 图8-1. Without this optimization, the output voltage overshoot is higher.
VOUT
PSM
FPWM mode for
mode
128 switching cycles
PSM
Device operates in PWM
mode
because of high load current
IOUT
图8-1. Optimized Transient Performance from PWM to PSM
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8.3.4 Low Dropout Operation (100% Duty Cycle)
The device offers a low dropout operation by entering 100% duty cycle mode if the input voltage comes close to
the target output voltage. In this mode, the high-side MOSFET switch is constantly turned on. This is particularly
useful in battery-powered applications to achieve the longest operation time by taking full advantage of the
whole battery voltage range. The minimum input voltage to maintain a minimum output voltage is given by:
VIN (min) = VOUT (min) + IOUT (max) × RDP
(4)
where
• VOUT (min) = Minimum output voltage the load can accept
• IOUT (max) = Maximum output current
• RDP = Resistance from VIN to VOUT (high-side RDS(on) + RDC of the inductor)
8.3.5 Soft Start
After enabling the device, there is a 650-µs enable delay (tDelay) before the device starts switching. The tDelay
time varies with the VSET/MODE resistor used and is longest with a resistance of 249 k or higher. After the
enable delay, an internal soft-start circuit ramps up the output voltage in 1 ms (tRamp). This action avoids
excessive inrush current and creates a smooth output voltage ramp up. This action also prevents excessive
voltage drops of batteries that have a high internal impedance. 图8-2 shows the start-up sequence.
VIN
EN
VOUT
tDelay
tStart-up
tRamp
图8-2. Start-Up Sequence
The device is able to start into a pre-biased output capacitor. The device starts with the applied bias voltage and
ramps the output voltage to its nominal value.
8.3.6 Switch Current Limit and HICCUP Short-Circuit Protection
The switch current limit prevents the device from high inductor current and from drawing excessive current from
the battery or input voltage rail. Excessive current can occur with a heavy load or shorted output circuit condition.
If the inductor current reaches the threshold ILIM, cycle by cycle, the high-side MOSFET is turned off and the low-
side MOSFET is turned on until the inductor current ramps down to the low-side MOSFET current limit.
When the high-side MOSFET current limit is triggered 256 times, the device stops switching. The device then
automatically re-starts with soft start after a typical delay time of 16 ms has passed. The device repeats this
mode until the high load condition disappears. This HICCUP short-circuit protection reduces the current
consumed from the input supply because the device only draws input current approximately 10% of the time
during an overload condition. 图9-29 shows the hiccup short-circuit protection.
The low-side MOSFET also contains a negative current limit to prevent excessive current from flowing back
through the inductor to the input. If the low-side sinking current limit is exceeded, the low-side MOSFET is turned
off. In this scenario, both MOSFETs are off until the start of the next cycle. The negative current limit is only
active in forced PWM mode.
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8.3.7 Undervoltage Lockout
To avoid mis-operation of the device at low input voltages, undervoltage lockout (UVLO) disables the device
when the input voltage is lower than VUVLO. When the input voltage recovers, the device automatically returns to
operation with soft start.
8.3.8 Thermal Shutdown
When the junction temperature exceeds TJSD, the device goes into thermal shutdown, stops switching, and
activates the output voltage discharge. When the device temperature falls below the threshold by the hysteresis,
the device returns to normal operation automatically with soft start.
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8.4 Device Functional Modes
8.4.1 Enable and Disable (EN)
The device is enabled by setting the EN pin to a logic high. Accordingly, shutdown mode is forced if the EN pin is
pulled low. In shutdown mode, the internal power switches as well as the entire control circuitry are turned off. An
internal switch smoothly discharges the output through the VOS pin in shutdown mode. Do not leave the EN pin
floating.
The typical enable threshold value of the EN pin is 0.66 V for rising input signals and the typical shutdown
threshold is 0.52 V for falling input signals.
8.4.2 Output Discharge
The purpose of the output discharge function is to ensure a defined down-ramp of the output voltage when the
device is disabled and to keep the output voltage close to 0 V. The output discharge is active when the EN pin is
set to a logic low and during thermal shutdown. The discharge is active down to an input voltage of 1.6 V
(typical).
8.4.3 Power Good (PG)
The device has an open-drain power-good pin, which is specified to sink up to 2 mA. The power-good output
requires a pullup resistor connected to any voltage rail less than 5.5 V. The PG signal can be used for
sequencing of multiple rails by connecting it to the EN pin of other converters. Leave the PG pin unconnected
when not used. 表8-1 shows the typical PG pin logic.
表8-1. PG Pin Logic
LOGIC STATUS
DEVICE CONDITIONS
HIGH IMPEDANCE
LOW
0.9 × VOUT_NOM ≤VVOUT ≤1.1 × VOUT_NOM
√
Enable
VVOUT < 0.9 × VOUT_NOM or VVOUT > 1.1 × VOUT_NOM
√
√
√
√
Shutdown
EN = low
Thermal shutdown
UVLO
TJ > TJSD
1.8 V < VIN < VUVLO
Power supply removal VIN < 1.8 V
undefined
The PG pin has a 34-μs delay time on the falling edge and a 34-μs delay before PG goes high. See 图8-3.
VPG(high)
VO
VPG(low)
tPG,DLY
tPG,DLY
tPG,DLY
tPG,DLY
tPG,DLY
tPG,DLY
PG
图8-3. Power-Good Transient and Delay Behavior
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8.4.4 Output Voltage and Mode Selection (VSET/MODE)
The TPSM8286xA family devices are configurable as either an adjustable output voltage or a fixed output
voltage, depending on the needs of each individual application. This feature simplifies the logistics during mass
production, as one part number offers several fixed output voltage options as well as an adjustable output
voltage option. During the enable delay (tDelay), the device configuration is set by an external resistor connected
to the VSET/MODE pin through an internal R2D (resistor to digital) converter. This configures the VREF input to
the error amplifier (EA) to be either the VFB voltage (0.6-V typical) or the selected output voltage. 表 8-2 shows
the options.
表8-2. Output Voltage Selection Table
RESISTOR AT VSET/MODE PIN (E96 SERIES, ±1% ACCURACY,
FIXED OR ADJUSTABLE OUTPUT VOLTAGE
200 ppm OR BETTER)
249 k or logic high
205 k
Adjustable (through a resistive divider on the FB pin)
3.30 V
162 k
2.50 V
133 k
1.80 V
105 k
1.50 V
68.1 k
1.35 V
56.2 k
1.20 V
44.2 k
1.10 V
36.5 k
1.05 V
28.7 k
1.00 V
23.7 k
0.95 V
18.7 k
0.90 V
15.4 k
0.85 V
0.80 V
12.1 k
10 k or logic low
Adjustable (through a resistive divider on the FB pin)
The R2D converter has an internal current source, which applies current through the external resistor, and an
internal ADC, which reads back the resulting voltage level. Depending on the detected resistance, the output
voltage is set. After this R2D conversion is finished, the current source is turned off to avoid current flowing
through the external resistor. Make sure that the additional leakage current path is less than 20 nA and the
capacitance is not greater than 30 pF from this pin to GND during R2D conversion, otherwise a false VOUT value
is set. For more details, refer to the Benefits of a Resistor-to-Digital Converter in Ultra-Low Power Supplies
White Paper. When the device is set to a fixed output voltage, the FB pin must be connected to the output
directly. See 图8-4.
VIN
VOUT
2.4 V to 5.5 V
1.8 V
VIN
EN
VOUT
VOS
C2
C1
22 µF
2 × 22 µF or
1 × 47 µF
R3
FB
VSET/
MODE
VPG
PG
R4
133 kΩ
AGND PGND
图8-4. Fixed Output Voltage Application Circuit
After the start-up period (tStart-up), a different operation mode can be selected. When VSET/MODE is set to high,
the device is in forced PWM mode. Otherwise, the device is in power save mode.
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The TPSM8286xA is a synchronous step-down converter power module family. The following section discusses
the selection of the external components to complete the power supply design. The required power inductor is
integrated inside the TPSM8286xA. The integrated shielded inductor has a value of 0.22 µH with a ±20%
tolerance. The TPSM82864A and TPSM82866A are pin-to-pin and BOM-to-BOM compatible. The
TPSM8286xAA0HRDMR devices give a higher efficiency than the TPSM8286xAA0SRDJR devices due to their
increased height. For a given package height (RDM or RDJ), the 4A and 6A version give the same efficiency and
performance and are different only in their rated output current.
9.2 Typical Application
VIN
VOUT
2.4 V to 5.5 V
1.2 V
VIN
EN
VOUT
VOS
C2
C1
22 µF
2 × 22 µF or
1 × 47 µF
R3
R1
R2
FB
VPG
PG
VSET/
MODE
AGND PGND
图9-1. Typical Application
9.2.1 Design Requirements
For this design example, use 表9-1 as the input parameters.
表9-1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage
2.4 V to 5.5 V
1.2 V
Output voltage
Maximum output current
6 A
表9-2 lists the components used for the example.
表9-2. List of Components
REFERENCE
DESCRIPTION
MANUFACTURER(1)
Murata
C1
22 µF, Ceramic capacitor, 6.3 V, X7R, size 0805, GRM21BZ70J226ME44
47 µF, Ceramic capacitor, 6.3 V, X6S, size 0805, JMK212BC6476MG-T
C2
R1
R2
R3
Taiyo Yuden
Depending on the output voltage, Chip resistor, 1/16 W, 1%
100 kΩ, Chip resistor, 1/16 W, 1%
Std
Std
Std
100 kΩ, Chip resistor, 1/16 W, 1%
(1) See the Third-party Products disclaimer.
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9.2.2 Detailed Design Procedure
9.2.2.1 Setting The Output Voltage
With the VSET/MODE pin set high or low, an adjustable output voltage is set by an external resistor divider
according to 方程式5:
≈
∆
«
’
VOUT
VFB
V
OUT
≈
’
R1= R2ì
-1 = R2ì
-1
÷
÷
∆
«
0.6V
◊
◊
(5)
To keep the feedback (FB) net robust from noise, set R2 equal to or lower than 100 kΩ to have at least 6 µA of
current in the voltage divider. Lower values of FB resistors achieve better noise immunity but lower light-load
efficiency, as explained in the Design Considerations for a Resistive Feedback Divider in a DC/DC Converter
Technical Brief.
When a fixed output voltage is selected, connect the FB pin directly to the output. R1 and R2 are not needed, as
V
OUT is set through a resistor on the VSET/MODE pin. Select the recommended resistor value from the list in 表
8-2.
9.2.2.2 Input and Output Capacitor Selection
For the best output and input voltage filtering, low-ESR ceramic capacitors are required. The input capacitor
minimizes input voltage ripple, suppresses input voltage spikes, and provides a stable system rail for the device.
The input capacitor must be placed between VIN and PGND as close as possible to those pins. For most
applications, 22 μF is sufficient, though a larger value reduces input current ripple. The input capacitor plays an
important role in the EMI performance of the system as explained in the Simplify Low EMI Design With Power
Modules White Paper.
The architecture of the device allows the use of tiny ceramic output capacitors with low equivalent series
resistance (ESR). These capacitors provide low output voltage ripple and are recommended. The capacitor
value can range from 2 × 22 µF up to 150 µF. The recommended typical output capacitors are 2 × 22 µF or 1 ×
47 µF with an X5R or better dielectric. Values over 150 µF can degrade the loop stability of the converter.
Ceramic capacitors have a DC-Bias effect, which has a strong influence on the final effective capacitance.
Choose the right capacitor carefully in combination with considering its package size and voltage rating. Make
sure that the effective input capacitance is at least 10 µF and the effective output capacitance is at least 22 µF.
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9.2.3 Application Curves
VIN = 5.0 V, VOUT = 1.2 V, TA = 25°C, BOM = 表 9-2, unless otherwise noted. Solid lines show the FPWM mode and dashed
lines show PSM.
100
95
90
85
80
75
70
65
60
55
50
45
40
100
95
90
85
80
75
70
65
60
55
50
45
40
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
100u
1m
10m
100m
1
6
6
6
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6
6
Output Current (A)
Output Current (A)
TPSM8286xAA0SRDJ
PSM and FPWM
TPSM8286xAA0SRDJ
FPWM
图9-2. Efficiency VIN = 5.0 V and TA = 25°C
图9-3. Efficiency VIN = 5.0 V and TA = 85°C
100
95
90
85
80
75
70
65
60
100
95
90
85
80
75
70
65
60
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
55
50
45
40
55
50
45
40
100u
1m
10m
100m
1
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Output Current (A)
Output Current (A)
TPSM8286xAA0SRDJ
PSM and FPWM
TPSM8286xAA0SRDJ
FPWM
图9-4. Efficiency VIN = 3.3 V and TA = 25°C
图9-5. Efficiency VIN = 3.3 V and TA = 85°C
100
95
90
85
80
75
70
65
60
100
95
90
85
80
75
70
65
60
55
55
VOUT = 0.6V
VOUT = 0.6V
50
45
40
50
45
40
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
100u
1m
10m
100m
1
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Output Current (A)
Output Current (A)
TPSM8286xAA0SRDJ
PSM and FPWM
TPSM8286xAA0SRDJ
FPWM
图9-6. Efficiency VIN = 2.8 V and TA = 25°C
图9-7. Efficiency VIN = 2.8 V and TA = 85°C
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100
95
90
85
80
75
70
65
60
55
50
45
100
95
90
85
80
75
70
65
60
55
50
45
40
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
40
100u
1m
10m
100m
1
6
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
Output Current (A)
Output Current (A)
TPSM8286xAA0HRDM
PSM and FPWM
TPSM8286xAA0HRDM
FPWM
图9-8. Efficiency VIN = 5.0 V and TA = 25°C
图9-9. Efficiency VIN = 5.0 V and TA = 85°C
100
95
90
85
80
75
70
65
60
100
95
90
85
80
75
70
65
60
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
55
50
45
40
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
55
50
45
40
100u
1m
10m
100m
1
6
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
Output Current (A)
Output Current (A)
TPSM8286xAA0HRDM
FPWM
TPSM8286xAA0HRDM
PSM and FPWM
图9-11. Efficiency VIN = 3.3 V and TA = 85°C
图9-10. Efficiency VIN = 3.3 V and TA = 25°C
100
95
90
85
80
75
70
65
60
100
95
90
85
80
75
70
65
60
55
55
VOUT = 0.6V
VOUT = 0.6V
50
45
40
50
45
40
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
100u
1m
10m
100m
1
6
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
Output Current (A)
Output Current (A)
TPSM8286xAA0HRDM
PSM and FPWM
TPSM8286xAA0HRDM
FPWM
图9-12. Efficiency VIN = 2.8 V and TA = 25°C
图9-13. Efficiency VIN = 2.8 V and TA = 85°C
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2
2
1
VOUT = 0.6V
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
1
0
0
-1
-1
10u
100u
1m
10m
100m
1
6
10u
100u
1m
10m
100m
1
6
Output Current (A)
Output Current (A)
TA = 25°C
TA = 25°C
图9-14. Load Regulation VIN = 5.0 V and PSM
图9-15. Load Regulation VIN = 5.0 V and FPWM
2
2
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
1
0
1
0
-1
-1
10u
100u
1m
10m
100m
1
6
10u
100u
1m
10m
100m
1
6
Output Current (A)
Output Current (A)
TA = 25°C
TA = 25°C
图9-16. Load Regulation VIN = 3.3 V and PSM
图9-17. Load Regulation VIN = 3.3 V and FPWM
2
2
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
1
0
1
0
-1
-1
10u
100u
1m
10m
100m
1
6
10u
100u
1m
10m
100m
1
6
Output Current (A)
Output Current (A)
TA = 25°C
TA = 25°C
图9-18. Load Regulation VIN = 2.8 V and PSM
图9-19. Load Regulation VIN = 2.8 V and FPWM
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4
3
4
3
2
2
1
0.7
0.5
1
0.7
0.5
0.3
0.2
0.3
0.2
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
0.1
0.07
0.05
0.1
0.07
0.05
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
0.03
0.03
0.02
10m
0.02
10m
100m
Output Current (A)
1
6
100m
Output Current (A)
1
6
PSM and FPWM
TA = 25°C
PSM and FPWM
TA = 25°C
图9-20. Switching Frequency VIN = 5.0 V
图9-21. Switching Frequency VIN = 3.3 V
VIN
VIN
VOUT
VOUT
VSW
VSW
VIN = 5.0 V
VOUT = 1.2 V
TA = 25°C
VIN = 5.0 V
VOUT = 1.2 V
TA = 25°C
图9-22. FPWM Operation IOUT = 6 A
图9-23. PSM Operation IOUT = 0.1 A
VOUT
VOUT
IOUT
IOUT
VIN = 5.0 V
VOUT = 1.2 V
TA = 25°C
VIN = 5.0 V
VOUT = 1.2 V
TA = 25°C
图9-24. Load Transient FPWM IOUT = 0 A →6 A
图9-25. Load Transient PSM IOUT = 0 A →6 A
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EN
PG
EN
PG
VOUT
VOUT
VSET / MODE
VSET / MODE
IOUT = 6.0 A
IOUT = 0 A
RVSET = 56.2 kΩ
RVSET = 56.2 kΩ
图9-26. Start-Up into Full Load
图9-27. Start-Up with No Load
PG
VOUT
VOUT
IOUT
IOUT
RLOAD = 100 mΩ(during overload)
VIN = 5.0 V
VOUT = 1.2 V
TA = 25°C
图9-29. HICCUP Short-Circuit Protection
图9-28. Load Sweep IOUT = 20 mA →6 A
7
7
VOUT = 0.6V
VOUT = 0.6V
6.5
6.5
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
6
6
5.5
5
5.5
5
4.5
4
4.5
4
3.5
3
3.5
3
2.5
2
2.5
2
1.5
1.5
1
1
75
80
85
90
95
100 105 110 115 120
75
80
85
90
95
100 105 110 115 120
Ambient Temperature (°C)
Ambient Temperature (°C)
R
θJA = 25.4°C/W
TJmax = 125°C
R
θJA = 25.4°C/W TJmax = 125°C
图9-30. Safe Operating Area VIN = 5.0-V
图9-31. Safe Operating Area VIN = 3.3-V
TPSM82866AA0HRDMR
TPSM82866AA0HRDMR
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7
6.5
6
7
6.5
6
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
5.5
5
5.5
5
4.5
4
4.5
4
3.5
3
3.5
3
2.5
2
2.5
2
1.5
1.5
1
1
75
80
85
90
95
100 105 110 115 120
75
80
85
90
95
100 105 110 115 120
Ambient Temperature (°C)
Ambient Temperature (°C)
R
θJA = 25.4°C/W
TJmax = 125°C
R
θJA = 25.4°C/W
TJmax = 125°C
图9-32. Safe Operating Area VIN = 5.0-V
图9-33. Safe Operating Area VIN = 3.3-V
TPSM82866AA0SRDJR
TPSM82866AA0SRDJR
9.3 Power Supply Recommendations
The device is designed to operate from an input voltage supply range from 2.4 V to 5.5 V. The average input
current of the TPSM8286xA is calculated as:
(6)
Make sure that the input power supply has a sufficient current rating for the application. The power supply must
avoid a fast ramp down. The falling ramp speed must be slower than 10 mV/μs if the input voltage drops below
VUVLO
.
9.4 Layout
9.4.1 Layout Guidelines
A proper layout is critical for the operation of any switched mode power supply, especially at high switching
frequencies. Therefore, the PCB layout of the TPSM8286xA demands careful attention to ensure best
performance. A poor layout can lead to issues like the following:
• Bad line and load regulation
• Instability
• Increased EMI radiation
• Noise sensitivity
Refer to the Five Steps to a Great PCB Layout for a Step-Down Converter Technical Brief for a detailed
discussion of general best practices. The following are specific recommendations for the TPSM8286xA:
• Place the input capacitor as close as possible to the VIN and PGND pins of the device. This placement is the
most critical component placement. Route the input capacitor directly to the VIN and PGND pins avoiding
vias.
• Place the output capacitor close to the VOUT and PGND pins and route it directly avoiding vias.
• Place the FB resistors R1 and R2 close to the FB and AGND pins and place R4 close to the VSET/MODE pin
to minimize noise pickup.
• The sense traces connected to the VOS pin is a signal trace. Take special care to avoid noise being induced.
Keep the trace away from SW.
• To improve thermal performance, use GND vias under the exposed thermal pad. Directly connect the AGND
and PGND pins to the exposed thermal pad with copper on the top PCB layer.
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• Refer to 图9-34 for an example of component placement, routing, and thermal design.
• The recommended land pattern for the TPSM8286xA is shown at the end of this data sheet. For best
manufacturing results, create the pads as solder mask defined (SMD) when some pins (such as VIN, VOUT,
and PGND) are connected to large copper planes. Using SMD pads keeps each pad the same size and
avoids solder pulling the device during reflow.
9.4.2 Layout Example
R1
R2
VOUT
GND
U1
AGND
PGND
PGND
VIN
PGND
PGND
PGND
PGND
GND
VIN
EN
SW
VIN
35 mm²
Total Solution Size
R4
图9-34. Layout Example
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9.4.2.1 Thermal Considerations
The TPSM8286xA power module temperature must be kept less than the maximum rating of 125°C. The
following are three basic approaches for enhancing thermal performance:
• Improve the power dissipation capability of the PCB design.
• Improve the thermal coupling of the component to the PCB.
• Introduce airflow into the system.
To estimate the approximate module temperature of the TPSM8286xA, apply the typical efficiency stated in this
data sheet to the desired application condition to compute the power dissipation of the module. Then, calculate
the module temperature rise by multiplying the power dissipation by its thermal resistance. Using this method to
compute the maximum device temperature, the Safe Operating Area (SOA) graphs demonstrate the required
derating in maximum output current at high ambient temperatures. For more details on how to use the thermal
parameters in real applications, see the Thermal Characteristics of Linear and Logic Packages Using JEDEC
PCB Designs Application Report and Semiconductor and IC Package Thermal Metrics Application Report.
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TPSM82864A, TPSM82866A
ZHCSMK6B –SEPTEMBER 2021 –REVISED NOVEMBER 2022
www.ti.com.cn
10 Device and Documentation Support
10.1 Device Support
10.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
10.2 Documentation Support
10.2.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs
Application Report
• Texas Instruments, Semiconductor and IC Package Thermal Metrics Application Report
• Texas Instruments, Benefits of a Resistor-to-Digital Converter in Ultra-Low Power Supplies White Paper
• Texas Instruments, Design Considerations for a Resistive Feedback Divider in a DC/DC Converter Technical
Brief
• Texas Instruments, Simplify Low EMI Design With Power Modules White Paper
10.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
10.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
8-Dec-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPSM82864AA0HRDMR
TPSM82864AA0SRDJR
TPSM82866AA0HRDMR
TPSM82866AA0SRDJR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
B0QFN
B0QFN
B0QFN
B0QFN
RDM
RDJ
RDM
RDJ
23
23
23
23
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
TM864AA0H
Samples
Samples
Samples
Samples
NIPDAU
NIPDAU
NIPDAU
TM864AA0S
TM866AA0H
TM866AA0S
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
8-Dec-2022
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Dec-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPSM82864AA0HRDMR B0QFN
TPSM82864AA0SRDJR B0QFN
TPSM82866AA0HRDMR B0QFN
TPSM82866AA0SRDJR B0QFN
RDM
RDJ
RDM
RDJ
23
23
23
23
3000
3000
3000
3000
330.0
330.0
330.0
330.0
17.6
17.6
17.6
17.6
3.8
3.8
3.8
3.8
4.3
4.3
4.3
4.3
2.0
2.0
2.0
2.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Dec-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPSM82864AA0HRDMR
TPSM82864AA0SRDJR
TPSM82866AA0HRDMR
TPSM82866AA0SRDJR
B0QFN
B0QFN
B0QFN
B0QFN
RDM
RDJ
RDM
RDJ
23
23
23
23
3000
3000
3000
3000
336.0
336.0
336.0
336.0
336.0
336.0
336.0
336.0
48.0
48.0
48.0
48.0
Pack Materials-Page 2
PACKAGE OUTLINE
B0QFN - 1.85 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RDM0023A
3.6
3.4
B
A
4.1
3.9
PIN 1 INDEX AREA
1.85
1.75
C
SEATING PLANE
(0.10) TYP
0.01
0.00
2X 2.5
0.08
C
(0.20) TYP
1.6±0.1
8X (0.125)
8X (0.05)
12
7
2X (0.3)
0.6
0.4
(0.125) TYP
18X
23
1.8±0.1
PKG
2X (0.3)
2X 3
℄
2X (0.45)
26X (0.15)
18X
0.3
0.2
2X (0.9)
0.1
C
A
B
0.05
C
1
18
PIN 1 ID
22
0.55
0.45
8X
SYMM
22X 0.5
℄
0.1
C
A B
0.05
C
4226712/D 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
B0QFN - 1.85 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RDM0023A
2X (2.5)
SYMM
℄
26X (0.25)
8X (0.5)
22X (0.5)
(0.55)
22
18
1
18X (0.7)
(0.35)
2X (0.3)
(0.95)
PKG
(3.65)
2X (3)
(1.8)
℄
23
7
(R0.05) TYP
(Ø0.2) TYP
12
(1.6)
(3.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
0.05 MAX
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
NON- SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4226712/D 03/2023
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
B0QFN - 1.85 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RDM0023A
2X (2.5)
26X (0.25)
8X (0.5)
SYMM
℄
22X (0.5)
22
18
1
18X (0.7)
PKG
(3.65)
2X (3)
℄
23
(1.63)
(0.3)
7
(R0.05) TYP
12
(1.47)
(3.2)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD:
83% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X
4226712/D 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
B0QFN - 1.45 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RDJ0023A
3.6
3.4
B
A
4.1
3.9
PIN 1 INDEX AREA
1.45
1.35
C
SEATING PLANE
0.01
0.00
0.08
C
(0.10) TYP
(0.20) TYP
2X 2.5
1.6±0.1
8X (0.125)
8X (0.05)
12
7
2X (0.3)
0.6
0.4
(0.125) TYP
18X
23
1.8±0.1
PKG
2X (0.3)
2X 3
℄
2X (0.45)
26X (0.15)
18X
0.3
0.2
2X (0.9)
0.1
C
A
B
0.05
C
1
18
PIN 1 ID
22
0.55
0.45
8X
SYMM
22X 0.5
℄
0.1
C
A B
0.05
C
4226407/D 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
B0QFN - 1.45 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RDJ0023A
2X (2.5)
SYMM
℄
26X (0.25)
8X (0.5)
22X (0.5)
(0.55)
22
18
1
18X (0.7)
(0.35)
2X (0.3)
(0.95)
PKG
(3.65)
2X (3)
(1.8)
℄
23
7
(R0.05) TYP
(Ø0.2) TYP
12
(1.6)
(3.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
0.05 MAX
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
NON- SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4226407/D 03/2023
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
B0QFN - 1.45 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RDJ0023A
2X (2.5)
26X (0.25)
8X (0.5)
SYMM
℄
22X (0.5)
22
18
1
18X (0.7)
PKG
(3.65)
2X (3)
℄
23
(1.63)
(0.3)
7
(R0.05) TYP
12
(1.47)
(3.2)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD:
83% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X
4226407/D 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
相关型号：
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TI
TPSM82866AA0HRDMR
具有集成电感器、采用 3.5mm x 4mm QFN 封装的 2.4V 至 5.5V 输入、6A 薄型降压电源模块 | RDM | 23 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPSM82866AA0SRDJR
具有集成电感器、采用 3.5mm x 4mm QFN 封装的 2.4V 至 5.5V 输入、6A 薄型降压电源模块 | RDJ | 23 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPSM82901
具有集成电感器的 3V 至 17V、1A 高效率、低 IQ 同步降压转换器模块Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPSM82901SISR
具有集成电感器的 3V 至 17V、1A 高效率、低 IQ 同步降压转换器模块 | SIS | 11 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPSM82902
具有集成电感器的 3V 至 17V、2A 高效率、低 IQ 同步降压转换器模块Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPSM82902SISR
具有集成电感器的 3V 至 17V、2A 高效率、低 IQ 同步降压转换器模块 | SIS | 11 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPSM82903
具有集成电感器的 3V 至 17V、3A 高效率、低 IQ 同步降压转换器模块Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPSM82903SISR
具有集成电感器的 3V 至 17V、3A 高效率、低 IQ 同步降压转换器模块 | SIS | 11 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPSM82913
17-V VIN, 3-A low-noise and low-ripple buck module with integrated ferrite bead filter compensationWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
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