TPSM82913 [TI]
17-V VIN, 3-A low-noise and low-ripple buck module with integrated ferrite bead filter compensation;
| 型号： | TPSM82913 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 17-V VIN, 3-A low-noise and low-ripple buck module with integrated ferrite bead filter compensation |
| 文件： | 总38页 (文件大小：4533K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPSM82913, TPSM82913E
ZHCSOW9B –OCTOBER 2022 –REVISED MAY 2023
TPSM8291x 具有集成式铁氧体磁珠滤波器补偿的3V 至17V、2A/3A 低噪声和低
纹波降压电源模块
1 特性
3 说明
• 低输出噪声< 20µVRMS
TPSM8291x 器件是一系列高效、低噪声和低纹波电流
模式同步降压电源模块。这些器件非常适合通常使用
LDO 实现后置稳压的噪声敏感型应用，例如高速
ADC、时钟和抖动清除器、串行器、解串器和雷达应
用。
（100Hz 至100kHz）
• 采用铁氧体磁珠后，低输出电压纹波< 10µVRMS
• 大于65dB 的高PSRR（高达100kHz）
• 2.2MHz 或1MHz 定频峰值电流模式控制
• 可与外部时钟同步（可选）
• 集成环路补偿支持铁氧体磁珠，适用于具有30dB
衰减的二阶L-C 滤波器（可选）
• 展频调制（可选）
• 3.0V 至17V 输入电压范围
• 0.8V 至5.5V 输出电压范围
• 57mΩ/20mΩRDSon
这些器件在 2.2MHz 或 1MHz 的固定开关频率下工
作，并可与外部时钟同步。
为了进一步减小输出电压纹波，器件集成了环路补偿，
可与可选的第二级铁氧体磁珠 L-C 滤波器一起工作。
该功能可将输出电压纹波降至10µVRMS 以下。
通过使用 NR/SS 引脚上的集成电容器对内部电压基准
进行滤波来实现类似于低噪声 LDO 的低频噪声水平。
可以在模块中添加一个外部电容器以进行额外的滤波。
• 输出电压精度为±1%
• 精密使能输入可实现
– 用户定义的欠压锁定
– 准确排序
• 可调节软启动
• 电源正常状态输出
• 输出放电（可选）
• -40°C 至125°C 的结温范围
可选展频调制方案扩展了更宽范围内的直流/直流开关
频率，从而降低了混合毛刺。
器件信息
封装尺寸（标称
值）
封装(1)
器件名称
输出电流
TPSM82912(2)
2A
– -ET 版本为–55°C 至125°C
• 使用TPSM8291x 并借助WEBENCH® Power
Designer 创建定制设计
RDU
（QFN，
28）
4.50 mm × 5.50
mm × 1.80 mm
TPSM82913、
TPSM82913E
3A
2 应用
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
(2) 产品预发布。
• 电信基础设施
• 测试和测量
• 航天和国防（雷达、航空电子设备）
• 医疗
10 nH
10
Vin
12 V
5
Vout
3.3 V / 3 A
VIN
OUT
2
1
0.5
3x
22 µF
CIN
10 µF
EN/SYNC
S-CONF
NR/SS
22 µF
15.4 k
4.87 k
FB
0.2
0.1
0.05
PG
PGND
0.02
0.01
CNRSS = open, 19.6 VRMS
CNRSS = 220 nF, 17 VRMS
CNRSS = 470 nF, 16.6 VRMS
CNRSS = 2.2 F, 16.3 VRMS
0.005
0.002
0.001
典型应用
0.0005
1x101
1x102
1x103
1x104
1x105
1x1063x106
Frequency (Hz)
输出噪声与频率间的关系
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSGJ4
TPSM82913, TPSM82913E
ZHCSOW9B –OCTOBER 2022 –REVISED MAY 2023
www.ti.com.cn
Table of Contents
7.4 Device Functional Modes..........................................19
8 Application and Implementation..................................21
8.1 Application Information............................................. 21
8.2 Typical Applications.................................................. 21
8.3 Power Supply Recommendations.............................28
8.4 Layout....................................................................... 28
9 Device and Documentation Support............................31
9.1 Device Support......................................................... 31
9.2 Documentation Support............................................ 31
9.3 接收文档更新通知..................................................... 31
9.4 支持资源....................................................................31
9.5 Trademarks...............................................................31
9.6 静电放电警告............................................................ 32
9.7 术语表....................................................................... 32
10 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics................................................7
7 Detailed Description......................................................15
7.1 Overview...................................................................15
7.2 Functional Block Diagram.........................................15
7.3 Feature Description...................................................16
Information.................................................................... 32
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (December 2022) to Revision B (May 2023)
Page
• 从器件信息 表中删除了 TPSM82912-ET............................................................................................................1
• 在器件信息 表中将TPSM82913-ET 更新为TPSM82913E 并删除了预发布状态.............................................. 1
• Added -ET temp range in the Electrical Characteristics table............................................................................ 4
Changes from Revision * (October 2022) to Revision A (December 2022)
Page
• 将数据表状态从“预告信息”更改为“混合量产”............................................................................................ 1
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSGJ4
2
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5 Pin Configuration and Functions
图5-1. 28-Pin QFN RDU Package (Top View)
表5-1. Pin Functions
PIN
NAME
VIN
I/O
DESCRIPTION
NO.
18
I
Power supply input voltage pin
Power ground connection
1, 2, 3, 5,
6, 7, 8, 9,
16, 17, PGND
25, 26,
28
10, 11,
12, 13,
VOUT
14, 15,
O
Output connection. Connect recommended output capacitance from VOUT to PGND.
27
4
SW
PG
NC Switch pin of the power stage. Do not connect, leave floating.
Open-drain power-good output. This pin is pulled to GND when VOUT is below the power-good threshold. It requires a pull-up
19
O
resistor to output a logic high. It can be left open or tied to GND if not used.
20
21
22
23
PSNS
NR/SS
FB
I
Power sense ground. Connect directly to the ground plane.
O
I
A capacitor connected to this pin sets the soft-start time and low frequency noise level of the device.
Feedback pin of the device
S-CONF
O
Smart Configuration pin. This pin configures the operation modes of the device. See 表7-1.
Enable/Disable pin including threshold-comparator. Connect to logic low to disable the device. Pull high to enable the device.
This pin has an internal pull-down resistor of typically 500 kΩwhen the device is disabled. Apply a clock to this pin to
synchronize the device.
24
EN/SYNC
I
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Product Folder Links: TPSM82913 TPSM82913E
English Data Sheet: SLVSGJ4
TPSM82913, TPSM82913E
ZHCSOW9B –OCTOBER 2022 –REVISED MAY 2023
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–2.5
–0.3
–0.3
MAX
18
UNIT
V
VIN, EN/SYNC, PG, S-CONF
SW (DC)
VIN + 0.3
21
V
Voltage(2)
SW (AC, less than 10ns)(3)
VOUT, FB, NR/SS
PSNS
V
6
V
0.3
V
Sink Current
PG
10
mA
°C
°C
TJ
Junction temperature, -ET versions only
Storage temperature
125
125
–55
–65
Tstg
Mechanical
shock
Mil-STD-883D, Method 2002.3, 1 msec, 1/2 sine, mounted
Mil-STD-883D, Method 2007.2, 20 to 2000 Hz
1500
20
G
G
Mechanical
vibration
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltage values are with respect to the network ground terminal
(3) While switching
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001,
all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per ANSI/ESDA/JEDEC
JS-002, all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
3.0
0.8
5
NOM
MAX
17
UNIT
VIN
VOUT
CIN
COUT
Lf
Input voltage
V
V
Output voltage
5.5
Effective input capacitance
Effective output capacitance
Effective filter inductance
Effective filter capacitance
10
47
10
40
µF
µF
nH
µF
µF
A
40
0
80
50
Cf
20
40
0
160
200
3
COUT + Cf Effective total output capacitance, including first and second L-C filter
IOUT
IOUT
Output current for TPSM82913
Output current for TPSM82912
Junction temperature
0
2
A
(1)
TJ
TJ
125
125
°C
°C
–40
–55
(1)
Junction temperature, -ET versions only
(1) Operating lifetime is derated at junction temperatures above 125°C.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSGJ4
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6.4 Thermal Information
TPSM8291x
THERMAL METRIC(1)
RDU 30-pin QFN
JEDEC 51-7 PCB TPSM8291xEVM-213
UNIT
RθJA
RθJC(top)
RθJB
ΨJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
31.3
22.4
7.2
30.2
°C/W
°C/W
°C/W
°C/W
°C/W
n/a (2)
n/a (2)
-3.0 (3)
9.0
Junction-to-top characterization parameter
Junction-to-board characterization parameter
-4.9 (3)
7.1
YJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Not applicable to an EVM
(3) This is a negative value because the case temperature is higher than the die junction temperature due to the integrated inductor
having the highest power dissipation in the module.
6.5 Electrical Characteristics
Over recommended input voltage range, TJ = -40 ℃to 125 ℃, (TJ = -55 ℃to 125 ℃for -ET parts). Typical values are at Vin
= 12 V andTJ = 25 ℃(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
EN = High, no load, device switching, fsw
= 1 MHz
IQ
Quiescent current
5
mA
ISD
Shutdown current
EN = GND
VIN rising
VIN rising
0.3
70
3.0
µA
V
VUVLO
VUVLO
VHYS
Under voltage lockout
2.85
2.92
Under voltage lockout
3.04
V
Under voltage lockout hysteresis
Thermal shutdown threshold
Thermal shutdown hysteresis
200
170
20
mV
°C
°C
TJ rising
TJ falling
TJSD
CONTROL and INTERFACE
High-level input-threshold voltage at EN/
SYNC
VH_EN
0.97
0.87
1.1
1.01
0.9
1.04
0.93
V
V
V
V
Low-level input-threshold voltage at EN/
SYNC
VL_EN
High-level input-threshold clock signal on
EN/SYNC
VH_SYNC
VL_SYNC
EN/SYNC = clock
EN/SYNC = clock
Low-level input-threshold clock signal on
EN/SYNC
0.4
IEN,LKG
RPD
Input leakage current into EN/SYNC
Pull-down resistor on EN/SYNC
EN/SYNC = GND or VIN
EN/SYNC = Low
5
160
nA
330
500
kΩ
Time from EN/SYNC high to device starts
switching, RS-CONF = 80.6 kΩ
tdelay
Enable delay time
1
ms
µA
%
INR/SS
NR/SS source current
67.5
-4
75
82.5
+4
RS-CONF tolerance for all settings
according to 表7-1
RS-CONF S-CONF resistor step range accuracy
Maximum capacitance connected to S-
CONF pin
CS-CONF
30
pF
VPG
Power good threshold
VFB rising, referenced to VFB nominal
VFB falling, referenced to VFB nominal
ISINK = 1 mA
93
88
95
90
98
93
%
%
V
VPG
Power good threshold
VPG,OL
IPG,LKG
Low-level output voltage at PG pin
Input leakage current into PG pin
0.4
500
VPG = 5 V
5
nA
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English Data Sheet: SLVSGJ4
TPSM82913, TPSM82913E
ZHCSOW9B –OCTOBER 2022 –REVISED MAY 2023
www.ti.com.cn
6.5 Electrical Characteristics (continued)
Over recommended input voltage range, TJ = -40 ℃to 125 ℃, (TJ = -55 ℃to 125 ℃for -ET parts). Typical values are at Vin
= 12 V andTJ = 25 ℃(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPG,DLY
OUTPUT
ton
Power good delay time
VFB falling
8
µs
Minimum on-time
35
50
0.8
1
70
60
ns
ns
V
VIN ≥5 V, Iout = 1 A
VIN ≥5 V, Iout = 1 A
–40℃≤TJ ≤125℃
VFB = 0.8 V
toff
Minimum off-time
VFB
Feedback regulation accuracy
Input leakage current into FB
0.792
0.808
70
IFB,LKG
nA
VIN = 12 V, 1.2 VOUT, 1 A, CNR/SS = 220
nF, fsw = 1 MHz, CFF = open, COUT = 3 x
22 µF, f ≤100 kHz
PSRR
VNRMS
VNRMS
Vopp
Power supply rejection ratio
Output voltage RMS noise
Output voltage RMS noise
Output ripple voltage at fSW
Output ripple voltage at fSW
65
27.4
13.3
9
dB
VIN = 12 V, BW = 100 Hz to 100 kHz, CNR/
SS = 220 nF, fSW = 1 MHz, VOUT = 1.2 V,
CFF = open, COUT = 3 x 22 µF
µVRMS
µVRMS
µVRMS
µVRMS
VIN = 5 V, BW = 100 Hz to 100 kHz, CNR/
SS = 220 nF, fSW = 2.2 MHz, VOUT = 1.2 V,
CFF = open, COUT = 3 x 22 µF
VIN = 12 V, fSW = 1 MHz, VOUT = 1.2 V,
COUT = 3 x 22 µF, Lf = 10 nH, Cf = 2 x 22
µF
VIN = 5 V, fSW = 2.2 MHz, VOUT = 1.2V,
COUT = 3 x 22 µF, Lf = 10 nH, Cf = 2 x 22
uF
Vopp
< 3
EN/SYNC = GND, VOUT = 1.2 V, VIN ≥5
V. See 节6.6 for plot.
RDIS
Output discharge resistance
Output discharge resistance
7
Ω
Ω
EN/SYNC = GND, VOUT = 5 V, VIN ≥5 V.
See 节6.6 for plot.
RDIS
32
fSW
Switching frequency
2.2-MHz setting
2.2-MHz setting
1-MHz setting
1-MHz setting
1.98
1.9
2.2
2.2
1
2.42
2.42
1.18
1.2
MHz
MHz
MHz
MHz
%
fSW
Synchronization range
Switching frequency
fSW
0.9
fSW
Synchronization range
Synchronization duty cycle
0.86
45
1
DSYNC
55
Phase delay from EN/SYNC rising edge
to SW rising edge
tsync_delay Synchronization phase delay
90
ns
ISWpeak
ISWpeak
Peak switch current limit
Peak switch current limit
TPSM82912(1)
TPSM82913
TPSM82912(1)
TPSM82913
2.9
3.7
3.5
4.3
4.0
5.1
A
A
ISWvalley Valley switch current limit
ISWvalley Valley switch current limit
Inegvalley Negative valley current limit
3.4
A
4.2
A
-1.39
57
-0.96
95
A
High-side FET on-resistance
RDS(ON)
VIN ≥5 V
VIN ≥5 V
mΩ
mΩ
Low-side FET on-resistance
20
39
(1) Preview information
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English Data Sheet: SLVSGJ4
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6.6 Typical Characteristics
VIN = 12 V, VOUT = 1.2 V, TA = 25°C, BOM = 表8-1, (unless otherwise noted)
450
400
350
300
250
200
150
100
50
Spread Spectrum Modulation
OFF
Random
0
0x100
2x107
4x107
6x107
8x107
1x108
Frequency (Hz)
BW = 10 kHz
2.2 μH, 1 MHz
1 s/div
12 V to 1.2 V, 1 A
First L-C Only
2.2 μH, 1 MHz
12 V to 1.2 V, 1 A
First L-C Only
图6-1. VOUT Ripple After the First L-C Filter
图6-2. VOUT Ripple FFT After the First L-C Filter
20
Spread Spectrum Modulation
18
16
14
12
10
8
OFF
Random
6
4
2
0
0x100
2x107
4x107
6x107
8x107
1x108
Frequency (Hz)
BW = 10 kHz
2.2 μH, 1 MHz
1 s/div
12 V to 1.2 V, 1 A
First and second L-C
2.2 μH, 1 MHz
12 V to 1.2 V, 1 A
First and second L-C
图6-3. VOUT Ripple After the Second L-C Filter
图6-4. VOUT Ripple FFT After the Second L-C Filter
650
Spread Spectrum Modulation
600
OFF
Random
550
500
450
400
350
300
250
200
150
100
50
0
0x100
2x107
4x107
6x107
8x107
1x108
Frequency (Hz)
BW = 10 kHz
2.2 μH, 1 MHz
1 s/div
12 V to 1.8 V, 1 A
First L-C Only
2.2 μH, 1 MHz
12 V to 1.8 V, 1 A
First L-C Only
图6-5. VOUT Ripple After the First L-C Filter
图6-6. VOUT Ripple FFT After the First L-C Filter
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English Data Sheet: SLVSGJ4
TPSM82913, TPSM82913E
ZHCSOW9B –OCTOBER 2022 –REVISED MAY 2023
www.ti.com.cn
6.6 Typical Characteristics (continued)
VIN = 12 V, VOUT = 1.2 V, TA = 25°C, BOM = 表8-1, (unless otherwise noted)
20
18
16
14
12
10
8
Spread Spectrum Modulation
OFF
Random
6
4
2
0
0x100
2x107
4x107
6x107
8x107
1x108
Frequency (Hz)
BW = 10 kHz
2.2 μH, 1 MHz
1 s/div
12 V to 1.8 V, 1 A
First and second L-C
2.2 μH, 1 MHz
12 V to 1.8 V, 1 A
First and second L-C
图6-7. VOUT Ripple After the Second L-C Filter
图6-8. VOUT Ripple FFT After the Second L-C Filter
400
Spread Spectrum Modulation
360
OFF
Random
320
280
240
200
160
120
80
40
0
0x100
2x107
4x107
6x107
8x107
1x108
Frequency (Hz)
1 s/div
2.2 μH, 2.2 MHz
图6-9. VOUT Ripple After the First L-C Filter
BW = 10 kHz
12 V to 3.3 V, 1 A
First L-C Only
12 V to 3.3 V, 1 A
First L-C Only
2.2 μH, 2.2 MHz
图6-10. VOUT Ripple FFT After the First L-C Filter
20
Spread Spectrum Modulation
18
OFF
Random
16
14
12
10
8
6
4
2
0
0x100
2x107
4x107
6x107
8x107
1x108
Frequency (Hz)
1 s/div
BW = 10 kHz
12 V to 3.3 V, 1 A
First and second L-C
2.2 μH, 2.2 MHz
12 V to 3.3 V, 1 A
First and second L-C
2.2 μH, 2.2 MHz
图6-11. VOUT Ripple After the Second L-C Filter
图6-12. VOUT Ripple FFT After the Second L-C Filter
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English Data Sheet: SLVSGJ4
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ZHCSOW9B –OCTOBER 2022 –REVISED MAY 2023
www.ti.com.cn
6.6 Typical Characteristics (continued)
VIN = 12 V, VOUT = 1.2 V, TA = 25°C, BOM = 表8-1, (unless otherwise noted)
200
180
160
140
120
100
80
Spread Spectrum Modulation
OFF
Random
60
40
20
0
0x100
2x107
4x107
6x107
8x107
1x108
Frequency (Hz)
1 s/div
BW = 10 kHz
5 V to 1.2 V, 1 A
First L-C Only
2.2 μH, 2.2 MHz
5 V to 1.2 V, 1 A
First L-C Only
2.2 μH, 2.2 MHz
图6-13. VOUT Ripple After the First L-C Filter
图6-14. VOUT Ripple FFT After the First L-C Filter
20
Spread Spectrum Modulation
18
OFF
Random
16
14
12
10
8
6
4
2
0
0x100
2x107
4x107
6x107
8x107
1x108
Frequency (Hz)
1 s/div
2.2 μH, 2.2 MHz
图6-15. VOUT Ripple after the Second L-C Filter
BW = 10 kHz
5 V to 1.2 V, 1 A
First and second L-C
5 V to 1.2 V, 1 A
First and second L-C
2.2 μH, 2.2 MHz
图6-16. VOUT Ripple FFT After the Second L-C Filter
200
Spread Spectrum Modulation
180
OFF
Random
160
140
120
100
80
60
40
20
0
0x100
2x107
4x107
6x107
8x107
1x108
Frequency (Hz)
1 s/div
2.2 μH, 2.2 MHz
图6-17. VOUT Ripple After the First L-C Filter
BW = 10 kHz
5 V to 1.8 V, 1 A
First L-C Only
5 V to 1.8 V, 1 A
First L-C Only
2.2 μH, 2.2 MHz
图6-18. VOUT Ripple FFT After the First L-C Filter
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6.6 Typical Characteristics (continued)
VIN = 12 V, VOUT = 1.2 V, TA = 25°C, BOM = 表8-1, (unless otherwise noted)
20
18
16
14
12
10
8
Spread Spectrum Modulation
OFF
Random
6
4
2
0
0x100
2x107
4x107
6x107
8x107
1x108
Frequency (Hz)
1 s/div
BW = 10 kHz
5 V to 1.8 V, 1 A
First and second L-C
2.2 μH, 2.2 MHz
5 V to 1.8 V, 1 A
First and second L-C
2.2 μH, 2.2 MHz
图6-19. VOUT Ripple After the Second L-C Filter
图6-20. VOUT Ripple FFT After the Second L-C Filter
200
Spread Spectrum Modulation
180
OFF
Random
160
140
120
100
80
60
40
20
0
0x100
2x107
4x107
6x107
8x107
1x108
Frequency (Hz)
1 s/div
2.2 μH, 2.2 MHz
图6-21. VOUT Ripple After the First L-C Filter
BW = 10 kHz
5 V to 3.3 V, 1 A
First L-C Only
5 V to 3.3 V, 1 A
First L-C Only
2.2 μH, 2.2 MHz
图6-22. VOUT Ripple FFT After the First L-C Filter
20
Spread Spectrum Modulation
18
OFF
Random
16
14
12
10
8
6
4
2
0
0x100
2x107
4x107
6x107
8x107
1x108
Frequency (Hz)
1 s/div
2.2 μH, 2.2 MHz
BW = 10 kHz
5 V to 3.3 V, 1 A
First and second L-C
5 V to 3.3 V, 1 A
First and second L-C
2.2 μH, 2.2 MHz
图6-23. VOUT Ripple After the Second L-C Filter
图6-24. VOUT Ripple FFT After the Second L-C Filter
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6.6 Typical Characteristics (continued)
VIN = 12 V, VOUT = 1.2 V, TA = 25°C, BOM = 表8-1, (unless otherwise noted)
6 V to 1.2 V, 1 A
BW = 50 Hz
12 V to 1.2 V, 2 A
BW = 10 kHz
2.2 μH, 1 MHz
2.2 μH, 1 MHz
S-CONF = OFF, Triangular, Random
S-CONF = OFF, Triangular, Random
图6-25. Spread Spectrum FFT - 50-Hz BW
图6-26. Spread Spectrum FFT - 10-kH BW
10
5
10
5
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
CNRSS = open, 25.8 VRMS
CNRSS = 220 nF, 27.4 VRMS
CNRSS = 470 nF, 27.3 VRMS
CNRSS = 2.2 F, 25 VRMS
CNRSS = open, 27.5 VRMS
CNRSS = 220 nF, 25.7 VRMS
CNRSS = 470 nF, 25.9 VRMS
CNRSS = 2.2 F, 25.9 VRMS
0.005
0.005
0.002
0.001
0.002
0.001
0.0005
0.0005
1x101
1x102
1x103
1x104
1x105
1x1063x106
1x101
1x102
1x103
1x104
1x105
1x1063x106
Frequency (Hz)
Frequency (Hz)
12 V to 1.2 V
1 MHz
After ferrite bead filter
12 V to 1.8 V
1 MHz
After ferrite bead filter
NR/SS = Open, 220 nF, 470 nF, 2.2 μF, BW = 100 Hz to 100 kHz
图6-27. Output Noise Density vs Frequency
NR/SS = Open, 220 nF, 470 nF, 2.2 μF, BW = 100 Hz to 100 kHz
图6-28. Output Noise Density vs Frequency
10
5
10
5
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
CNRSS = open, 13.8 VRMS
CNRSS = 220 nF, 13.3 VRMS
CNRSS = 470 nF, 13.2 VRMS
CNRSS = 2.2 F, 13.2 VRMS
0.005
CNRSS = open, 19.6 VRMS
CNRSS = 220 nF, 17 VRMS
CNRSS = 470 nF, 16.6 VRMS
CNRSS = 2.2 F, 16.3 VRMS
0.005
0.002
0.001
0.002
0.001
0.0005
0.0005
1x101
1x102
1x103
1x104
1x105
1x1063x106
1x101
1x102
1x103
1x104
1x105
1x1063x106
Frequency (Hz)
Frequency (Hz)
5 V to 1.2 V
2.2 MHz
After ferrite bead filter
12 V to 3.3 V
2.2 MHz
After ferrite bead filter
NR/SS = Open, 220 nF, 470 nF, 2.2 μF, BW = 100 Hz to 100 kHz
图6-30. Output Noise Density vs Frequency
NR/SS = Open, 220 nF, 470 nF, 2.2 μF, BW = 100 Hz to 100 kHz
图6-29. Output Noise Density vs Frequency
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6.6 Typical Characteristics (continued)
VIN = 12 V, VOUT = 1.2 V, TA = 25°C, BOM = 表8-1, (unless otherwise noted)
10
5
10
5
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
CNRSS = open, 15.3 VRMS
CNRSS = 220 nF, 14.3 VRMS
CNRSS = 470 nF, 14.3 VRMS
CNRSS = 2.2 F, 14.2 VRMS
CNRSS = open, 19.1 VRMS
CNRSS = 220 nF, 16.6 VRMS
CNRSS = 470 nF, 16.1 VRMS
CNRSS = 2.2 F, 15.9 VRMS
0.005
0.005
0.002
0.001
0.002
0.001
0.0005
0.0005
1x101
1x102
1x103
1x104
1x105
1x1063x106
1x101
1x102
1x103
1x104
1x105
1x1063x106
Frequency (Hz)
Frequency (Hz)
5 V to 1.8 V
2.2 MHz
After ferrite bead filter
5 V to 3.3 V
2.2 MHz
After ferrite bead filter
NR/SS = Open, 220 nF, 470 nF, 2.2 μF, BW = 100 Hz to 100 kHz
图6-31. Output Noise Density vs Frequency
NR/SS = Open, 220 nF, 470 nF, 2.2 μF, BW = 100 Hz to 100 kHz
图6-32. Output Noise Density vs Frequency
120
120
110
100
90
80
70
60
50
40
30
20
110
100
90
80
70
60
50
40
30
20
12Vin 1.2Vout 1A
12Vin 1.2Vout 2A
12Vin 1.2Vout 3A
12Vin 1.8Vout 1A
12Vin 1.8Vout 2A
12Vin 1.8Vout 3A
1x101
1x102
1x103
1x104
1x105
1x101
1x102
1x103
1x104
1x105
Frequency (Hz)
Frequency (Hz)
12 V to 1.2 V
1 A, 2 A, 3 A
12 V to 1.8 V
1 A, 2 A, 3 A
2.2 μH, 1 MHz
2.2 μH, 1 MHz
After ferrite bead filter
After ferrite bead filter
图6-33. PSRR vs Frequency
图6-34. PSRR vs Frequency
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6.6 Typical Characteristics (continued)
VIN = 12 V, VOUT = 1.2 V, TA = 25°C, BOM = 表8-1, (unless otherwise noted)
120
110
100
90
80
70
60
50
40
12Vin 3.3Vout 1A
12Vin 3.3Vout 2A
30
12Vin 3.3Vout 3A
20
1x101
1x102
1x103
1x104
1x105
Frequency (Hz)
VIN = 5 V
12 V to 3.3 V
1 A, 2 A, 3 A
2.2 μH, 2.2 MHz
After ferrite bead
filter
图6-36. High-Side RDS(ON) vs Junction Temperature
图6-35. PSRR vs Frequency
1 MHz, 2 A
VIN = 5 V
图6-38. FB Pin Voltage Error vs Input Voltage
图6-37. Low-Side RDS(ON) vs Junction Temperature
5 VIN to 0.8 VOUT
1 MHz
12 VIN
1 MHz
图6-39. Output Voltage Error vs Load
图6-40. Oscillator Frequency vs Temperature
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6.6 Typical Characteristics (continued)
VIN = 12 V, VOUT = 1.2 V, TA = 25°C, BOM = 表8-1, (unless otherwise noted)
12 VIN
2.2 MHz
VIN: 3 V, 5 V, 12 V
图6-41. Oscillator Frequency vs Temperature
图6-42. Shutdown Current vs Temperature
VIN: 12 V
25°C
图6-43. Output Discharge Resistance vs Output Voltage
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7 Detailed Description
7.1 Overview
The TPSM8291x low-noise, low-ripple synchronous buck converter module is a fixed frequency current mode
converter module. The converter module has a filtered internal reference to achieve a low-noise output similar to
low-noise LDOs. The converter module achieves lower output voltage ripple by using a switching frequency of
either 2.2 MHz or 1 MHz and an integrated 2.2-μH inductor. The output voltage ripple can be further reduced by
adding a small second stage L-C filter to the output. This can be a ferrite bead or a small inductor, followed by an
output capacitor. Internal compensation maintains stability with an external filter inductor up to 50 nH. To avoid
voltage drops across this second stage filter, the device regulates the output voltage after the filter. The
TPSM8291x family supports an optional spread spectrum modulation. For example, when powering ADCs,
spread spectrum modulation reduces the mixing spurs. Switching frequency, spread spectrum modulation, and
output discharge are set using the S-CONF pin.
7.2 Functional Block Diagram
PG
VIN
High Side
Current Sense
+
VPG
VFB
t
Slope
Compensation
Undervoltage
lockout
+
EN/SYNC
G
t
1.0V
Thermal shutdown
Clock
Detector
MUX
MOSFET Driver
Anti Shoot Through
2.2 µH
EN/SYNC
Converter Control Logic
VOUT
1MHz/2.2MHz
MODE
MODE
Spread Spectrum
Modulation
Low Side
Current Sense
PGND
VIN
Comparator
FB
2nd stage filter
compensation
t
GM
Start-up readout
ADC
+
S-CONF
Register
Selection
VIN
MODE
S-CONF
GM Amplifier
Iss
Softstart
Rf
RDIS
VREF
0.8V
Output voltage
MODE
discharge
logic
220 nF
PSNS
NR/SS
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7.3 Feature Description
7.3.1 Smart Config (S-CONF)
This S-CONF pin configures the device based on the resistor value. This pin is read after EN/SYNC goes high.
The device configuration cannot be changed during operation. The S-CONF value is re-read if EN is pulled
below 200 mV or if VIN falls below UVLO. 表7-1 shows the configuration options of the following:
• Switching frequency
• Spread spectrum modulation
• Output discharge
• Synchronization
表7-1. S-CONF Device Configuration Modes
SWITCHING
FREQUENCY
OUTPUT
DISCHARGE
S-CONF
SPREAD SPECTRUM
SYNCHRONIZATION
VIN
2.2 MHz
1 MHz
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
Discharge On
ON
No
GND
No
2.2 MHz
2.2MHz
2.2 MHz
1 MHz
OFF
1.9 MHz to 2.42 MHz
4.87 kΩ
6.04kΩ
7.5 kΩ
9.31 kΩ
11.5kΩ
14.3 kΩ
Triangle
Random
OFF
No
No
0.9 MHz to 1.2 MHz
1 MHz
Triangle
Random
No
No
1 MHz
2.2 MHz
1 MHz
OFF
OFF
No
18.2 kΩ
22.1 kΩ
27.4 kΩ
34 kΩ
ON
No
2.2 MHz
2.2 MHz
2.2 MHz
1 MHz
OFF
ON
1.9 MHz to 2.42 MHz
Triangle
Random
OFF
ON
No
ON
No
42.2 kΩ
52.3 kΩ
64.9kΩ
80.6 kΩ
ON
0.9 MHz to 1.2 MHz
1 MHz
Triangle
Random
ON
No
No
1 MHz
ON
7.3.2 Device Enable (EN/SYNC)
The device is enabled by pulling the EN/SYNC pin high and has an accurate rising threshold voltage of typically
1.01 V. After the device is enabled, the operation mode is set by the configuration of the S-CONF pin. This
occurs during the device start-up delay time tdelay. After tdelay expires, the internal soft-start circuitry ramps up the
output voltage over the soft-start time set by the CNR/SS capacitor. The start-up delay time tdelay varies depending
on the selected S-CONF value. the time is shortest with smaller S-CONF resistors.
The EN/SYNC pin has an active pulldown resistor RPD. This resistor prevents an uncontrolled start-up of the
device, in case the EN/SYNC pin cannot be driven to a low level. The pulldown resistor is disconnected after
start-up. With EN set to a low level, the device enters shutdown and the pulldown resistor is activated again.
7.3.3 Device Synchronization (EN/SYNC)
The EN/SYNC pin is also used for device synchronization. After a clock signal is applied to this pin, the device is
enabled and reads the configuration of the S-CONF pin. The external clock frequency must be within the clock
synchronization frequency range set by the S-CONF pin. When the clock signal changes from a clock to a static
high, then the device switches from external clock to internal clock. To shutdown the device when using an
external clock, EN/SYNC must go low for at least 10 µs.
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The clock signal can be a logic signal with a logic level as specified in the electrical table, and can be applied
directly to the EN/SYNC pin. External logic, such as an AND gate, can be used to combine separate enable and
clock inputs, as shown in 图7-1.
EN
EN/SYNC
CLK
图7-1. Synchronization with Separate Enable Signal (Optional)
7.3.4 Spread Spectrum Modulation
Using the S-CONF pin enables or disables spread spectrum modulation. DC/DC converters generate an output
voltage ripple at the switching frequency. When powering ADCs or an analog front end (AFE), the switching
frequency generates high frequency mixing spurs as well as a low frequency spur in the output frequency
spectrum. Using the optional second stage L-C filter reduces the ripple of the converter and spurs by up to 30
dB.
The device has integrated two different spread spectrum modulation (SSM) schemes that are selected by the
resistor connected to the S-CONF pin according to 表 7-1. It is possible to select random or triangle modulation
to spread the switching frequency over a larger frequency range. The triangular SSM is modulated based on the
switching frequency, and results in 1.9-kHz for 1-MHz switching frequency and 4.3-kHz for 2.2-MHz switching
frequency. The modulation spread is ±10% of the device switching frequency. This SSM provides high
attenuation when the receiver bandwidth is less than the modulation frequency, typically the case for systems
using Fast Fourier Transforms (FFT) post processing as in high speed ADC applications. For applications
sensitive to noise at the modulation frequency, random SSM is used. Using a random spread spectrum
modulation also reduces the spurs in the output spectrum as shown in 图 6-2. The random SSM operates with
the same frequency spread and modulation period as the triangular SSM. The randomized modulation uses a
Fibonacci Linear-Feedback Shift Register (LFSR) so that every tone is generated once during the pseudo-
random generation period. The frequency spreading is shown in 图 7-2.The attenuation using random or triangle
SSM is shown in 图6-26.
fSW
Unmodulated
(single tone)
Spectral envelope of
triangular modulation
(+/- 10% fSW
)
Spectral envelope of
random modulation
(+/- 10% fSW
)
fMOD
Triangular
(single tone)
Increased noise floor
with random modulation
图7-2. Spread Spectrum Modulation
7.3.5 Output Discharge
Output discharge is enabled or disabled, depending on the S-CONF setting. With output discharge enabled, the
output voltage is pulled low by a discharge resistor RDIS of typically 7 Ω. The output discharge function is
enabled during thermal shutdown, UVLO, or when EN/SYNC is pulled low.
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7.3.6 Undervoltage Lockout (UVLO)
To avoid misoperation of the device at low input voltages, the device is enabled after the input voltage is above
the undervoltage lockout threshold. The device is disabled after the input voltage falls below the undervoltage
threshold.
7.3.7 Power-Good Output
The device has a power-good output. The PG pin goes high impedance once the FB pin voltage is above 95% of
the nominal voltage, and is driven low after the voltage falls below typically 90% of the nominal voltage. 表 7-2
shows the typical PG pin logic. The PG pin is an open-drain output and is specified to sink up to 10 mA. The
power-good output requires a pullup resistor connecting to any voltage rail less than 18 V. The PG signal can be
used for sequencing of multiple rails by connecting to the EN pin of other converters. If not used, the PG pin can
be left floating or connected to GND. PG has a deglitch time of typically 8 μs before going low.
表7-2. Power Good Pin Logic
PG LOGIC STATUS
DEVICE STATE
HIGH IMPEDANCE
LOW
VFB ≥VPG
√
Enabled (EN/SYNC = High)
VFB < VPG after tPG
√
√
Shutdown (EN/SYNC = Low)
UVLO
0.7 V < VIN < VUVLO
TJ > TJSD
√
√
Thermal Shutdown
Power Supply Removal
VIN < 0.7 V
√
7.3.8 Noise Reduction and Soft-Start Capacitor (NR/SS)
A capacitor connected to this pin reduces the low frequency noise of the converter and sets the soft-start time.
The larger the capacitor, the lower the noise and the longer the start-up time of the converter. The module has
an internal 220-nF capacitor connected to the NR/SS pin. If no external capacitor is connected to the NR/SS pin,
the default start-up time is 2.35 ms, although longer start-up times and additional noise reduction can be
achieved with additional capacitance connected to the NR/SS pin. The maximum NR/SS cap is 3.3 µF for a
start-up time of 35 ms.During soft start with a light load, the device skips switching pulses as needed to not
discharge the output voltage. The device can start into a pre-biased output voltage.
The device achieves low noise by adding an R-C filter to the reference voltage, as shown in Functional Block
Diagram. During start-up, the NR/SS capacitor is charged with a constant current of 75 µA (typical) to 0.8 V.
Larger NR/SS capacitors provide for lower low frequency noise, as shown in 图6-29.
7.3.9 Current Limit and Short-Circuit Protection
The device is protected against short circuits and overcurrent. The switch current limit prevents the device from
high inductor current and from drawing excessive current from the input voltage rail. Excessive current can occur
with a shorted, saturated inductor or a heavy load, shorted output circuit condition. If the inductor current reaches
the threshold ISWpeak, the high-side MOSFET is turned off and the low-side MOSFET is turned on to ramp down
the inductor current. The high-side MOSFET is turned on again only when the low-side current is below the low-
side sourcing current limit ISWvalley
.
Due to internal propagation delay, the actual current can exceed the static current limit, especially if the input
voltage is high and very small inductances are used. The dynamic current limit is calculated as follows:
V
L
≈
’
Ipeak(typ) = ISWpeak
+
ìtPD
∆
«
÷
◊
L
(1)
where
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• ISWpeak is the static current limit, specified in Electrical Characteristics
• L is the inductance (2.2 μH for the TPSM8291x)
• VL is the voltage across the inductor (VIN –VOUT)
• tPD is the internal propagation delay, typically 50 ns
The low-side MOSFET also contains a negative current limit to prevent excessive current from flowing back
through the inductor to the input. This can happen during light load conditions or a pre-biased output condition. If
the low-side sinking current limit is exceeded, the low-side MOSFET is turned off. In this scenario, both
MOSFETs are off until the start of the next cycle.
7.3.10 Thermal Shutdown
The device goes into thermal shutdown after the junction temperature exceeds typically 170°C with a 20°C
hysteresis.
7.4 Device Functional Modes
7.4.1 Fixed Frequency Pulse Width Modulation
To minimize output voltage ripple, the device operates in fixed frequency PWM operation down to no load. The
switching frequency of 1 MHz or 2.2 MHz is selected using the S-CONF pin.
7.4.2 Low Duty Cycle Operation
For high input voltages or low output voltages, the 70-ns minimum on-time limits the maximum input to output
voltage difference and the switching frequency selected. When the minimum on-time is reached, the output
voltage rises above the regulation point. Refer to 表8-2 for detailed design recommendations.
7.4.3 High Duty Cycle Operation (100% Duty Cycle)
The device offers a low input-to-output voltage differential by entering 100% duty cycle mode. In this mode, the
high-side MOSFET switch is constantly turned on. The minimum input voltage to maintain output voltage
regulation, depending on the load current and the output voltage level, is calculated as:
V
IN(min) =VOUT(min) + IOUT ì(RDS(ON) + R
L
)
(2)
where
• VOUT(min) is the minimum output voltage the load can accept
• IOUT is the output current
• RDS(ON) is the RDS(ON) of the high-side MOSFET
• RL is the DC resistance of the inductor used,
76 mΩfor the TPSM8291x
To maintain fixed frequency switching, the device requires a minimum off-time of 50 ns (typical), 60 ns
(maximum). If this limit is reached during a switching pulse, the device skips switching pulses to maintain output
voltage regulation. If the input voltage decreases further, the device enters 100% mode.
7.4.4 Second Stage L-C Filter Compensation (Optional)
Most low-noise and low-ripple applications use a ferrite bead and bypass capacitor before the load. Using a
second L-C filter is especially useful for low-noise and low-ripple applications with constant load current such as
ADCs, DACs, and Jitter Cleaner. The second stage L-C filter is optional, and the device can be used without this
filter. Without the filter, the device has a low output voltage noise of typically 16.6 μVRMS shown in 图 6-29 with
an output voltage ripple of 280 μVRMS shown in 图 6-10. The second stage L-C filter attenuates the output
voltage ripple by another approximately 30 dB shown in 图 6-12. To improve load regulation, the device can
remote sense the output voltage after the second stage L-C filter and is internally compensated for the additional
double pole generated by the L-C filter.
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To keep the second stage L-C filter as small as possible, the internal compensation is optimized for a 10-nH to
50-nH inductance. A small ferrite bead or even a PCB trace provides sufficient inductance for output voltage
ripple filtering. See 节8.2.2.2.3 for details.
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8 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The family of devices are optimized for low noise and low output voltage ripple.
8.2 Typical Applications
Lf
10 nH
Vin
12 V
Vo
1.2 V / 3 A
VIN
OUT
COUT
3x
22 µF
CIN
2 x 10 µF
EN/SYNC
S-CONF
NR/SS
Cf
2 x 22µF
R1
2.43 k
FB
PG
R2
4.87 k
PGND
图8-1. Typical Schematic
表8-1 shows the list of components for the application curves in 节8.2.3, unless otherwise noted.
表8-1. List of Components
REFERENCE
PART NUMBER
DESCRIPTION
MANUFACTURER(1)
Low-noise and low-ripple buck
module
TPSM82913
TPSM82913
Texas Instruments
Ceramic capacitors: 2 × 10 µF ±10%
25-V ceramic capacitor X7S 0805
CIN
C2012X7S1E106K125AC
TDK
Ceramic capacitors: 3 × 22 µF, 10 V,
±20%, X7S, 0805
COUT
Lf
C2012X7S1A226M125AC
BLE18PS080SN1
TDK
MuRata
TDK
Ferrite Bead
Ceramic capacitor: 2 × 22 µF, 10 V,
±20%, X7S, 0805
Cf
C2012X7S1A226M125AC
CNR/SS, CFF
R1, R2
Optional, not shown
Ceramic capacitor
Resistor
Standard
Standard
(1) See the Third-Party Products Disclaimer
8.2.1 Design Requirements
The external components have to fulfill the needs of the application, but also meet the stability criteria of the
control loop of the device. The device is optimized to work within a range of external components, and can be
optimized for the following:
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• Efficiency
• Output ripple
• Component count
• Lowest noise
Typical applications that have input voltages of ≤6 V use a 2.2-MHz switching frequency. Applications that have
input voltages > 6 V can be optimized for efficiency using a 1-MHz switching frequency. In this case, the output
voltage ripple doubles, which is typically acceptable when powering high speed ADCs. Optimization for powering
clock and PLL circuits that need a 3.3-V output use a 2.2-MHz switching frequency, minimizing output voltage
ripple and low frequency noise.
For the application cases that are not found in 表 8-2, there are two methods to design the TPSM8291x circuit.
节8.2.2.1 uses Webench to design the circuit automatically or the calculations in 节8.2.2.2 can be used instead.
表8-2. Typical Single L-C Filter Design Recommendations
DESIGN GOAL
VIN
VOUT
FSW
OUTPUT CAPACITORS 3
≤2.0 V(1)
Typical
12 V(1)
1 MHz
3 × 22 µF, 10 V, 0805
Higher efficiency (with
higher ripple and noise)
12 V
12 V
1 MHz
3 × 22 µF, 10 V, 0805
3 × 22 µF, 10 V, 0805
2.0 V < VOUT ≤3.3 V
2.6 V ≤VOUT ≤3.3 V
Low ripple, noise PLL and
Clock Supply
2.2 MHz
Typical
Typical
12 V
5 V
> 3.3 V
2.2 MHz
2.2 MHz
3 × 22 µF, 10 V, 0805
≤3.3 V
1 × 47 µF, 1210 and 2 ×
22 µF, 10 V, 0805
Typical
5 V
> 3.3 V
2.2 MHz
(1) The maximum input to output voltage difference is limited by the device maximum minimum on-time of 70 ns. This is especially
important for input voltages above 12 V or output voltages below 1 V. See 节8.2.2.2.1.
(2) For output capacitor part numbers, see 表8-4.
The second stage L-C filter is optional, as the device can be used without this filter to achieve below 20-μVRMS
noise typically. A second stage filter is added to provide additional attenuation of the output voltage ripple. The
output voltage is sensed after the second L-C filter by connecting the FB resistors to the second stage L-C filter
capacitor. This action provides remote sense, minimizing output voltage drop due to the ferrite bead. Refer to 表
8-3 for second stage L-C filter recommendations based on the output voltage.
表8-3. Second Stage L-C (Ferrite Bead) Filter Design Recommendations
VOUT (V)
FERRITE BEAD IMPEDANCE (AT 100 MHZ)(2)
OUTPUT CAPACITORS (1)
2 × 22 µF, 10 V, 0805
3 × 22 µF, 10 V, 0805
≤3.3 V
8 Ωto 20 Ω
8 Ωto 20 Ω
> 3.3 V
(1) For output capacitor part numbers, see 表8-4.
(2) For second stage L-C filter part numbers, see 表8-5.
8.2.2 Detailed Design Procedure
If the specific design is not found in the 表 8-2 section, TI recommends WEBENCH® to generate the design.
Alternatively, the manual design procedure in External Component Selection can be followed.
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPSM8291x device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost.
3. Open the advanced tab to optimize for output voltage ripple.
4. After in a TPSM8291x design, enable the second stage L-C filter and change other settings from the drop-
down on the left.
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The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 External Component Selection
8.2.2.2.1 Switching Frequency Selection
The switching frequency can be chosen to optimize efficiency (1 MHz) or ripple, noise (2.2 MHz). Using the 2.2-
MHz setting increases the gain of the feedback loop and can result in lower output noise. However, additional
considerations for minimum on-time and duty cycle must also be considered. First, calculate the duty cycle using
方程式 3. Higher efficiency results in a shorter on-time, so a conservative approach is to use a higher efficiency
than expected in the application.
V
OUT
D =
VIN
ì
h
(3)
where
• ηis the estimated efficiency (use the value from the efficiency curves or 0.9 as an conservative assumption)
Then, calculate the on-time with both 1 MHz and 2.2 MHz using 方程式 4. The on-time must always remain
above the minimum on-time of 70 ns. Use the maximum input voltage and maximum efficiency to determine the
minimum duty cycle, Dmin. Use the maximum switching frequency for fSW
.
D
min
=
SW _ max
tON _ min
f
(4)
then
• If tON_min min < 70 ns with 2.2 MHz, use 1 MHz.
• If tON_min min < 70 ns with 1 MHz, reduce the maximum input voltage.
• If tON_min min ≥70 ns for both cases, use 1 MHz for highest efficiency, or 2.2 MHz for lowest noise and
ripple.
8.2.2.2.2 Output Capacitor Selection
The effective output capacitance can range from 40 μF (minimum) up to 200 μF (maximum) for a single L-C
system design. When using a second L-C filter, the first L-C filter must have output capacitance between 40 μF
and 80 μF, the second stage L-C filter (if used) must have at least 20 μF of capacitance, and the total
capacitance for both L-C filters must be less than 200 μF. Load transient testing and measuring the bode plot
are good ways to verify stability.
TI recommends ceramic capacitors (X5R or X7R). Ceramic capacitors have a DC-Bias effect, which has a strong
influence on the final effective capacitance. Choose the right capacitor carefully in combination with considering
its package size and voltage rating. The ESR and ESL of the output capacitor are also important considerations
in selecting the output capacitors for low noise applications. Smaller package sizes typically have lower ESL and
ESR. 0805 or smaller packages are recommended, as long as they provide the required capacitance and
voltage rating for stable operation. 表8-4 lists recommended output capacitors.
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PACKAGE
表8-4. Recommended Output Capacitors
CAPACITOR TYPE
Bulk Capacitor
CAPACITOR VALUE
MANUFACTURER
TDK C2012X7S1A226M125AC
Murata GRM32ER71A476ME15L
VOLTAGE (V)
10
10
0805
1210
22 μF, X7S
Bulk Capacitor
47 μF, X7R
8.2.2.2.3 Ferrite Bead Selection for Second L-C Filter
Using a ferrite bead for the second stage L-C filter minimizes the external component count because most of the
noise sensitive circuits use a RF bead for high frequency attenuation as a default component at their inputs.
Select a ferrite bead with sufficiently high inductance at full load, and with low DC resistance (below 10 mΩ) to
keep the converter efficiency as high as possible. The ferrite bead inductance decreases with increased load
current. Therefore, the ferrite bead must have a current rating much higher than the desired load current.
The recommendation is to choose a ferrite bead with an impedance of 8 Ω to 20 Ω at 100 MHz. Refer to 表 8-5
for possible ferrite beads.
表8-5. Recommended Ferrite Beads
INDUCTANCE AT
100 MHz
(CALCULATED)
IMPEDANCE AT
100 MHZ
CURRENT
RATING
PART NUMBER
MANUFACTURER
SIZE
DC RESISTANCE
BLE18PS080SN1
74279221100
7427922808
MuRata
0603
13.5 nH
5 A
8.5 Ω
10 Ω
8 Ω
4 mΩ
3 mΩ
5 mΩ
Wurth Elektronik
Wurth Electronik
1206
0603
15.9 nH
12.7 nH
10.5 A
9.5 A
The internal compensation has been designed to be stable with up to 50 nH of inductance in the second stage
filter. To achieve low ripple, the second L-C filter requires only 5-nH to 10-nH inductance. The inductance can be
estimated from the ferrite bead impedance specification at 100 MHz, with the assumption that the inductance is
similar at the selected converter switching frequency of 1 MHz or 2.2 MHz, and can be verified through tools
available on some manufacturer websites. The inductance of a ferrite bead is calculated using 方程式5:
Z
L =
2ìp ì f
(5)
where
• Z is the impedance of the ferrite bead in ohms at the specified frequency (usually 100 MHz)
• f is the specified frequency (usually 100 MHz)
8.2.2.2.4 Input Capacitor Selection
For the best output and input voltage filtering, Ti recommends X5R or X7R ceramic capacitors. The input bulk
capacitor minimizes input voltage ripple, suppresses input voltage spikes, and provides a stable system rail for
the device. TI recommends a 10-μF or larger input capacitor. Having two in parallel further improves the input
voltage ripple filtering, minimizing noise coupling into adjacent circuits. The voltage rating of the cap must also
be taken into consideration, and must provide the required 5-μF minimum effective capacitance after DC bias
derating.
In addition to the bulk input cap, a smaller cap must be placed directly from the VIN pin to the PGND pin to
minimize input loop parasitic inductance, thereby minimizing the high frequency noise of the device. The input
cap placement affects the output noise, so care must be taken in placing both the bulk cap and bypass caps. 表
8-6 lists recommended input capacitors.
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表8-6. Recommended Input Capacitors
INPUT CAP TYPE
CAPACITOR VALUE
MANUFACTURER
VOLTAGE RATING (V)
25
25
PACKAGE SIZE
TDK
Bulk Cap
0805
0402
10 μF, X7S
C2012X7S1E106K125AC
Murata
GRM155R71E222KA01D
Bypass Cap
2.2 nF, X7R
8.2.2.2.5 Setting the Output Voltage
Choose resistors R1 and R2 to set the output voltage within a range of 0.8 V to 5.5 V, according to 方程式 6. To
keep the feedback network robust from noise, and to reduce the self-generated noise of resistors, set R2 equal
to or lower than 5 kΩ. Lower values of FB resistors achieve better noise immunity, and lower light load
efficiency, as explained in the Design Considerations for a Resistive Feedback Divider in a DC/DC Converter
technical brief.
æ
ç
è
ö
VOUT
VFB
V
OUT
æ
ö
R1 = R2 ´
-1 = R2 ´
- 1
÷
÷
ç
0.8V
è
ø
ø
(6)
A feedforward capacitor (CFF) is not required for proper operation, but can further improve output noise.
However, care must be taken in choosing the CFF, because the power-good (PG) function can not be valid with a
large CFF during start-up, and can cause spurious triggering of the PG pin during a large load transient. Refer to
the Pros and Cons Using a Feedforward Capacitor with a Low Dropout Regulator application report for a
discussion of the pros and cons of using a feedforward capacitor.
8.2.2.2.6 NR/SS Capacitor Selection
As described in 节 7.3.8, the NR/SS cap affects both the total noise and the soft-start time. When no NR/SS cap
is connected, there is a default 2.35-ms soft-start time. The recommended value for a 5-ms soft-start time and
good noise performance is 220 nF, as there is an internal 220 nF capacitor already in the module. The maximum
NR/SS cap is 3.3 μF for a start-up time of 35 ms. Values greater than 1 μF have minimal improvement in noise
performance. Use 方程式 7 and 方程式 8 to calculate the soft-start time based on desired soft-start time or the
chosen capacitor value. Note that the CNRSS in the equation below is the combination of the internal 220 nF cap
and any external cap from the CNRSS pin to GND.
C
× 0.8
NRSS
I
tss s =
(7)
(8)
NRSS
I
× t
ss
NRSS
0.8
C
F =
NRSS
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8.2.3 Application Curves
VIN=12 V, VOUT=1.2 V, TA=25°C, BOM = 表8-1, (unless otherwise noted)
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
60
55
50
5 Vin
12 Vin
17 Vin
5 Vin
12 Vin
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
3
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
3
Output Current (A)
Output Current (A)
0.8 Vout
1st L-C Only
1.2 Vout
1st L-C Only
2.2 μH, 1 MHz
2.2 μH, 1 MHz
图8-2. Efficiency vs Load Current
图8-3. Efficiency vs Load Current
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
60
55
50
5 Vin
12 Vin
17 Vin
5 Vin
12 Vin
17 Vin
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
Output Current (A)
3
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
Output Current (A)
3
3.3 Vout
1st L-C Only
2.2 μH, 2.2 MHz
1.8 Vout
1st L-C Only
2.2 μH, 1 MHz
图8-5. Efficiency vs Load Current
图8-4. Efficiency vs Load Current
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
60
55
50
12 Vin
17 Vin
5 Vin
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
Output Current (A)
3
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
Output Current (A)
3
5 Vout
1st L-C Only
1.2 Vout
1st L-C Only
2.2 μH, 2.2 MHz
2.2 μH, 2.2 MHz
图8-6. Efficiency vs Load Current
图8-7. Efficiency vs Load Current
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100
95
90
85
80
75
70
65
60
55
12 V to 1.2 V
1 MHz
1st L-C Only
5 Vin
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
300 mA to 3 A to 300 mA
50
0
3
图8-9. Load Transient
Output Current (A)
1.8 Vout
1st L-C Only
2.2 μH, 2.2 MHz
图8-8. Efficiency vs Load Current
12 V to 1.2 V
1 MHz
After 2nd L-C
12 V to 1.8 V
1 MHz
1st L-C Only
300 mA to 3 A to 300 mA
300 mA to 3 A to 300 mA
图8-10. Load Transient
图8-11. Load Transient
12 V to 1.8 V
1 MHz
After 2nd L-C
12 V to 3.3 V
2.2 MHz
1st L-C Only
300 mA to 3 A to 300 mA
300 mA to 3 A to 300 mA
图8-12. Load Transient
图8-13. Load Transient
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12 V to 3.3 V
2.2 MHz
After 2nd L-C
300 mA to 3 A to 300 mA
图8-14. Load Transient
8.3 Power Supply Recommendations
The power supply to the TPSM8291x must have a current rating according to the supply voltage, output voltage,
and output current of the TPSM8291x.
8.4 Layout
8.4.1 Layout Guidelines
A proper layout is critical for the operation of any switched mode power supply, especially at high switching
frequencies. Therefore, the PCB layout of the TPSM8291x demands careful attention to ensure best
performance. A poor layout can lead to issues like bad line and load regulation, instability, increased EMI
radiation, and noise sensitivity. Refer to the Five Steps to a Great PCB Layout for a Step-Down Converter
technical brief for a detailed discussion of general best practices. Specific recommendations for the device are
listed below.
• The TPSM8291x has an integrated input capacitor. However, placement of the input capacitors must be
placed as close as possible to the VIN and PGND pins of the device. Route the input capacitors directly to
the VIN and PGND pins avoiding vias.
• Place the output capacitor ground close to the PGND pin and route it directly avoiding vias.
• Sensitive traces, such as the connections to the NR/SS and FB pins must be connected with short traces and
be routed away from any noise source.
• Connect the PSNS pin directly to the system GND plane with a via.
• The SW pin must not be connected and must be left floating. If the pin is soldered to PCB copper, the pour
needs to be as small as possible with no inner layer connections. The pin is provided for probing the internal
SW only, and not to be connected to any external component, as shown on the EVM.
• Place the second L-C filter, Lf and Cf, near the load to reduce any radiated coupling around the second L-C
filter
• Place the FB resistors, R1 and R2, close to the FB pin and route the VOUT connection from R1 to the load as
a remote sense trace. If a second L-C filter is used, this connection must be made after Lf.
• The recommended layout is implemented on the EVM and shown in the EVM user's guide.
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8.4.2 Layout Example
VIN
CNRSS
GND
CIN
Text Here
R2
R1
Cff
RSCONF
COUT
VOUT
Text Here
GND
图8-15. Recommended Layout for Single L-C Filter
备注
For a single L-C configuration, the feedback sense is placed near the VOUT capacitors. For a second
L-C filter design, the feedback sense is placed near the load after the VOUT_FILT capacitors.
VIN
GND
CIN
Text Here
CNRSS
R2
R1
VOUT_FILT
Cff
RSCONF
COUT
VOUT
Lf
Cf
Text Here
Text Here
GND
图8-16. Recommended Layout for Design with Second L-C Filter
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备注
The ferrite bead can be placed closer to the device as long as it is placed > 8 mm from the device.
This placement avoids capacitive and electromagnetic coupling to the output of the ferrite bead. If the
ferrite bead is placed < 8 mm, the filtering effect of the ferrite bead is greatly reduced. If the ferrite
bead is routed through a via to the back side of the board, ensure adequate ground plane between the
layers if the ferrite bead is in this area.
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9 Device and Documentation Support
9.1 Device Support
9.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
9.1.2 Development Support
9.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPSM8291x device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost.
3. Open the advanced tab to optimize for output voltage ripple.
4. Once in a TPSM8291x design, you can enable the second stage L-C filter and change other settings from
the drop-down on the left.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2 Documentation Support
9.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Design Considerations for a Resistive Feedback Divider in a DC/DC Converter technical
brief
• Texas Instruments, Five Steps to a Great PCB Layout for a Step-Down Converter technical brief
• Texas Instruments, Pros and Cons Using a Feedforward Capacitor with a Low Dropout Regulator application
report
9.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
9.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
9.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: TPSM82913 TPSM82913E
English Data Sheet: SLVSGJ4
TPSM82913, TPSM82913E
ZHCSOW9B –OCTOBER 2022 –REVISED MAY 2023
www.ti.com.cn
9.6 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
9.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSGJ4
32
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Product Folder Links: TPSM82913 TPSM82913E
PACKAGE OPTION ADDENDUM
www.ti.com
30-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PTPSM82913RDUR
TPSM82913RDUR
ACTIVE
ACTIVE
ACTIVE
B0QFN
B0QFN
B0QFN
RDU
RDU
RDU
28
28
28
1500 RoHS & Green
1500 RoHS & Green
1500 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-55 to 125
PTPSM2913
Samples
Samples
Samples
NIPDAU
NIPDAU
TPSM82913
82913-ET
TPSM82913RDUR-ET
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Jun-2023
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OUTLINE
RDU0028A
B0QFN - 1.9 mm max height
S
C
A
L
E
2
.
5
0
0
PLASTIC QUAD FLATPACK - NO LEAD
4.6
4.4
A
B
PIN 1 INDEX AREA
5.6
5.4
0.01
0.00
(0.095) TYP
A
30.000
DETAIL A
TYPICAL
SEE DETAIL A
1.9
1.7
C
SEATING PLANE
0.08 C
4X (0.725)
4X 1.15 0.1
0.65
0.55
0.775
0.675
4X
8X
0.8
0.7
(0.125) TYP
4X
0.1
C A B
C
13
7
0.05
4X 0.65
26
25
27
2X 1.65 0.1
2X (0.975)
2X (0.725)
SYMM
28
2X 3
2X 1.15 0.1
0.3
16X
0.2
12X 0.5
0.1
C A B
C
19
1
0.05
0.6
0.4
24
20X
SYMM
(R0.125) TYP
(0.15) TYP
8X 0.5
4X 0.65
2X 2
4228418/B 02/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RDU0028A
B0QFN - 1.9 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(R0.1) TYP
ALL INSIDE CORNERS
24
(2.6)
19
(R0.05) TYP
ALL OUTSIDE CORNERS
1
2X (2.15)
20X (0.7)
2X (1.5)
4X (0.325)
4X (1.05)
2X (1)
28
25
26
2X (0.725)
2X (0.5)
4X (0.4)
2X (1.15)
PKG
0.000
4X (0.475)
2X (0.5)
32X (0.25)
2X (0.975)
2X (1)
27
2X (1.65)
2X (1.5)
4X (1.475)
2X (2.15)
(2.6)
4X (0.6)
7
4X (0.925)
13
4X
(0.6)
4X
(0.925)
(
0.2) TYP
VIA
4X
(1.15)
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4228418/B 02/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RDU0028A
B0QFN - 1.9 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(R0.1) TYP
ALL INSIDE CORNERS
24
(2.6)
19
(R0.05) TYP
ALL OUTSIDE CORNERS
1
2X (2.15)
4X (0.325)
20X (0.7)
2X (1.5)
2X (1)
25
26
28
2X (0.725)
2X (0.5)
2X (1.08)
SYMM
0.000
32X (0.25)
2X (0.5)
2X (0.975)
2X (1)
27
2X (1.51)
2X (1.5)
2X (2.15)
(2.6)
4X (0.6)
7
4X (0.925)
13
4X
4X
(1.08)
(0.6)
4X
(0.925)
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 15X
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
PADS 25 & 28: 89%
PADS 26 & 27: 86%
4228418/B 02/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
相关型号：
TPSM82913RDUR
17-V VIN, 3-A low-noise and low-ripple buck module with integrated ferrite bead filter compensation | RDU | 28 | -40 to 125
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